JP6788401B2 - comparator - Google Patents

Description

The present invention relates to a comparator, and particularly relates to a comparator having improved high-speed response characteristics, voltage dependence, and the like.

With the diversification of electronic devices, it is ideal that the comparator has a wide common-mode input voltage and good high-speed response to the input, and it can be used in a wide range of power supply voltages. It is hoped that various characteristics such as response characteristics will not change. From this point of view, various circuit configurations of comparators capable of applying in-phase input voltage from negative power supply voltage to positive power supply voltage have been proposed and put into practical use (see, for example, Patent Document 1 and the like).

An example of a circuit configuration of such a conventional comparator is shown in FIG. 8, and the conventional circuit will be described below with reference to the same figure.
This comparator includes a first differential pair DEF1 composed of transistors M1 and M2 and a second constant current source CS2, and a first differential pair DEF1 composed of transistors M3 and M4 and a first constant current source CS1. The differential pair DEF2 of 2 is roughly divided into a folded cascode circuit CAS configured by using the transistors M5 to M8 and an output stage PA by the output transistor M9.

In this comparator, NMOSFETs (N-channel MOS field effect transistors) are used for the transistors M1 and M2 that form the first differential pair DEF1, and the transistors M3 and M4 that form the second differential pair DEF2 are used for the transistors M3 and M4. PMOSFETs (P-channel MOS field effect transistors) are used respectively.
The fold-out cascode circuit CAS has a function of connecting the first differential pair DEF1 and the second differential pair DEF2, and the transistors M5 and M6 have PMOSFETs and the transistors M7 and M8 have NMOSFETs, respectively. It is used.
Further, an N MOSFET is used for the output transistor M9.

The response characteristics of the conventional comparator having the above-described configuration are required as described below.
First, the response characteristic to be described below is that the propagation delay time when the output voltage of the comparator is changed to High from Low, the propagation delay time, in the following description, the gate potential V _M9 of the transistor M9 It is assumed that the fluctuation time of is the main.

First, the main node potentials of the circuit when the output voltage is Low, that is, when the output voltage is a value close to the negative power supply voltage, are as follows.
First, the potential of the inverting input terminal INM is higher than the potential of the non-inverting input terminal INP, so that more current from the constant current source CS1 flows toward the transistor M4 than at the transistor M3 of the second differential pair DEF2. The voltage drop at the fourth resistor R4 increases.

Therefore, the gate-source voltage difference Vgs _M8 of the transistor _M8 is smaller than the gate-source potential difference Vgs _{M7 of} the transistor M7. Since the potential difference Vgs _M8 between the gate and the source is small, the drain potential of the transistor M8 rises, and the gate potential Vg _M9 of the transistor M9 rises accordingly.

On the other hand, in the first differential pair DEF1, the current of the second constant current source CS2 flows more in the transistor M1 than in the transistor M2, the voltage drop in the first resistor R1 increases, and the first is The voltage drop in the resistor R2 of 2 is reduced.
As a result, the voltage difference Vgs _M6 between the gate and source of the transistor M6 becomes large, the drain potential of the transistor M6 rises, and the gate potential Vg _M9 of the transistor M9 rises.

As the gate potential Vg _M9 of the transistor M9 rises, the potential of the output terminal OUT of the comparator, which is the drain potential of the transistor M9, becomes Low.
As described above, the potential difference between the gate and the source of the transistor M8 Vgs _M8 is small, but when this Vgs _M8 is smaller than the threshold voltage Vth _{M8 of} the transistor M8, that is, the drain current of the transistor M8 hardly flows. In this case, the gate potential Vg _M9 of the transistor M9 has substantially the same potential as the positive power supply voltage VDD.

On the other hand, in the transistor M6, the potential difference Vgs _M6 between the gate and the source has a large value such that the drain current _IM6 flows, but as described above, the gate potential Vg _M9 of the transistor _M9 is substantially equal to the positive power supply voltage VDD. When it becomes a value, the potential difference Vds _M6 between the drain and the source of the transistor M6 becomes zero, and the drain current I _M6 of the transistor M6 does not flow.
Therefore, when the output voltage of the comparator is Low, the gate potential Vg _M9 of the output transistor M9 becomes substantially the positive power supply voltage VDD.

Here, if the gate potential of the transistor M9 when the output voltage is Low is defined as Vg _M9L , Vg _M9L is represented by the following equation 1.

Vg _M9L ≒ VDD ・ ・ ・ Equation 1

Next, the operation when the output voltage of the comparator changes from Low to High, that is, the operation when the output voltage changes from a substantially negative power supply potential to a substantially positive power supply potential will be described.
In such a state, the potential of the non-inverting input terminal INP is higher than the potential of the inverting input terminal INM, so that the current from the constant current source CS1 is higher in the transistor M3 than in the transistor M4 of the second differential pair DEF2. A large amount of current flows, and the voltage drop at the third resistor R3 increases.

Therefore, the gate-source voltage difference Vgs _M8 of the transistor _M8 becomes larger than the gate-source potential difference Vgs _{M7 of} the transistor M7. Since the potential difference Vgs _M8 between the gate and the source is large, a drain current flows through the transistor M8, the drain potential of the transistor M8 decreases, and the gate potential Vg _M9 of the transistor M9 decreases accordingly.

At this time, the electric charge charged in the parasitic capacitance Cc between the gate of the transistor M9 and the negative power supply voltage VSS becomes a current Icx and is discharged, and a part of the electric charge becomes a drain current of the transistor M8.

On the other hand, in the first differential pair DEF1, a larger current of the second constant current source CS2 flows in the transistor M2 than in the transistor M1, and the voltage drop in the second resistor R2 increases. The notation "R2" shall be used as the resistance value of the second resistor as necessary in the following description.

The current flowing through the second resistor R2 is determined by the potential difference Vgs _M6 between the reference voltage Vref applied to the gates of the transistors M5 and M6 and the gate source of the transistor M6, and the voltage drop in the second resistor R2. relationship between the current I _M6 and the reference voltage Vref of the second resistor resistance value R2 and the transistor M6 is expressed by equation 2 below.

_{R2 × (I M2 + I M6} ) + (2 × I M6 × L P / k'P × W P) 1/2 + Vth M6 = VDD -Vref ··· Formula 2

Note _{that, I M2,} the drain _{current, I M6} of the transistor M2, the drain current of the transistor M6 of the 6, _k'P is the gate oxide capacitance mobility and per unit area of the transistor M6 product, W _P, the gate width of the transistor M6, _{L P} is the gate length, Vth _M6 transistor M6 is the threshold voltage of the transistor M6.

Under such a relationship, the magnitude of the current _IM6 , which is a part of the current flowing through the second resistor R2, is determined.
The drain current I _M6 flows through the sixth transistor M6, but the Vgs _M6 has a low value due to the voltage drop caused by the second resistor R2. Therefore, in the sixth transistor M6, the potential difference between the drain and the source becomes large, and the current _IM6 flows, and as a result, the gate potential Vgs _M9 of the ninth transistor M9 decreases.

The operation of the first and second differential pairs DEF1 and DEF2 when the output voltage changes from Low to High has been described above, but in the end, the gate potential Vg _M9 of the transistor M9 drops, and the drain current in the transistor M9. Stops flowing, and the output voltage of the comparator becomes High. Therefore, the gate potential Vg _M9 of the transistor M9 when the output voltage becomes High drops to the threshold voltage Vth _M9 of the transistor M9.

Here, if the gate voltage of the transistor M9 when the output voltage is High is defined as Vg _M9H , Vg _M9H is expressed by the following equation 3.

Vg _M9H = Vth _M9 ... Equation 3

Therefore, the gate voltage change amount ΔVg _M9 of the transistor M9 when the output voltage changes from Low to High is expressed by the following equation 4 using the above equations 1 and 3.

_{ΔVg M9 = Vg M9L -Vg M9H ≒} VDD-Vth M9 ··· formula 4

Further, using this equation 4, the fluctuation time t _LH of the gate potential Vg _M9 when the output voltage changes from Low to High is expressed by the following equation 5.

t _LH = ΔVg _M9 × Cx / Icx = (VDD-Vth _M9 ) × Cx / Icx ・ ・ ・ Equation 5

Here, Cx is the parasitic capacitance between the gate of the transistor M9 and the negative power supply voltage VSS, and Icx is the discharge current of the parasitic capacitance Cx.

Japanese Patent No. 3024579

As described above, it can be said that the response time of the transistor M9 when the output voltage changes from Low to High becomes longer as the positive power supply voltage VDD becomes higher.
Looking at this in terms of the change in propagation time in the comparator, as shown in FIG. 7, it can be confirmed that the higher the positive power supply voltage VDD, the longer the propagation time. That is, the conventional circuit has a problem that the response time deteriorates as the power supply voltage increases, and a comparator having a stable response characteristic without being affected by the power supply voltage is desired.

The present invention has been made in view of the above circumstances, and provides a comparator capable of reliably suppressing the dependence of the response characteristic on the power supply voltage.

In order to achieve the above object of the present invention, the comparator according to the present invention is
An input stage composed of a first differential pair made up of first and second MOS transistors and a second differential pair made up of third and fourth MOS transistors, and the first differential pair. It is provided with a folded cascode circuit capable of outputting the differential output of the differential pair of the above, and an output circuit connected to the output stage of the folded cascode circuit to output an output signal.
In the output stage of the folded cascode circuit, the sixth MOS transistor using the P-channel MOS transistor and the eighth MOS transistor using the N-channel MOS transistor are placed between the positive power supply voltage and the negative power supply voltage. The sixth MOS transistor is connected in series so as to be located on the positive power supply voltage side.
For the sixth MOS transistor that constitutes the output stage of the folded cascode circuit and is connected to the input stage of the output circuit and the potential between the gate and the source rises when the output circuit is in the Low output state. Therefore, a diversion MOS transistor for dividing the current flowing through the sixth MOS transistor is provided.
The diversion MOS transistor includes an output stage of the folded cascode circuit and an input stage of the output circuit so that the current flowing through the sixth MOS transistor of the folded cascode circuit can flow into the negative power supply voltage side. In a comparator provided in series between the mutual connection points of the above and the negative power supply voltage.
A resistor is provided between one end of the flow dividing MOS transistor on the negative power supply voltage side and the negative power supply voltage side, and a resistor forming the second differential pair is used for the resistor. The diversion MOS transistor is provided in series between the output stage of the folded cascode circuit and the input stage of the output circuit and the negative power supply voltage via the resistor.
The third and fourth MOS transistors are P-channel MOS transistors, and the sources of the third and fourth MOS transistors are connected to each other, and a third is connected between the connection point and the positive power supply voltage. The constant current source of 1 is provided, and the negative power supply voltage is applied to the drain of the third MOS transistor via the third resistor and the fourth MOS transistor via the fourth resistor. The gate of the third MOS transistor is the gate of the first MOS transistor using an N-channel MOS transistor, and the gate of the fourth MOS transistor is the gate of the second MOS using an N-channel MOS transistor. While each connected to the gate of the transistor,
The folded cascode circuit has, in addition to the sixth and eighth MOS transistors, a fifth MOS transistor using a P-channel MOS transistor and a seventh MOS transistor using an N-channel MOS transistor. The gates of the fifth and sixth MOS transistors are connected to each other, while the source of the fifth MOS transistor is the drain of the first MOS transistor, and the source of the sixth MOS transistor is the source of the sixth MOS transistor. Each connected to the drain of the second MOS transistor,
In the seventh and eighth MOS transistors, the respective gates and the drain of the seventh MOS transistor are connected to each other, and the drain of the fifth MOS transistor is connected to the fifth MOS transistor. And the drain of the 7th MOS transistor are connected to the gate of the diversion MOS transistor.
The drain of the eighth MOS transistor is connected to the drain of the sixth MOS transistor.
The source of the 7th MOS transistor is connected to the drain of the 3rd MOS transistor, and the source of the 8th transistor is connected to the drain of the 4th MOS transistor.
The resistor constituting the second differential pair provided between one end of the flow dividing MOS transistor on the negative power supply voltage side and the negative power supply voltage side is the fourth resistor or the third resistor. It is a resistor.

According to the present invention, by making it possible to divide the current flowing through the MOS transistor of the folded cascode circuit, it is possible to suppress an unnecessary increase in the gate potential of the output transistor constituting the output circuit, so that the response time of the output transistor can be reduced. The dependence on the power supply voltage can be almost eliminated, the propagation delay time when a high power supply voltage is used is improved, the response characteristics are stable, and a highly reliable comparator can be provided.

It is a circuit diagram which shows the circuit example of the 1st Example of the comparator according to the Embodiment of this invention. It is a circuit diagram which shows the circuit example of the 2nd Example of the comparator according to the Embodiment of this invention. It is a circuit diagram which shows the circuit example of the 3rd Example of the comparator according to the Embodiment of this invention. It is a circuit diagram which shows the circuit example of the 4th Example of the comparator according to the Embodiment of this invention. It is a circuit diagram which shows the circuit example of the 5th Example of the comparator according to the Embodiment of this invention. It is a characteristic diagram which shows the change example of the propagation delay time with respect to the change of the power supply voltage of the comparator in embodiment of this invention together with the characteristic of the conventional circuit. It is a characteristic diagram which shows the change example of the propagation delay time with respect to the change of the power supply voltage of a conventional circuit together with the characteristic of a conventional circuit. It is a circuit diagram which shows the circuit example of the conventional comparator.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 6.
The members, arrangements, etc. described below are not limited to the present invention, and can be variously modified within the scope of the gist of the present invention.
First, the circuit configuration in the first embodiment of the comparator according to the embodiment of the present invention will be described with reference to FIG.
The comparator in the first embodiment is roughly divided into a first differential pair 101, a second differential pair 102, a folded cascode circuit 103, and an output circuit 104. ing.

The first differential pair 101 is a first and second transistor (denoted as “M1” and “M2” in FIG. 1, respectively) 1, 2 and a second constant current source (“CS2” in FIG. 1). ”) 22 is the main component.
In this first embodiment, N MOSFETs (N-channel MOS field effect transistors) are used for the first and second transistors 1 and 2 constituting the first differential pair 101.

The drain of the first transistor 1 is passed through the first resistor (denoted as "R1" in FIG. 1) 31, and the drain of the second transistor 2 is the second resistor (denoted as "R1" in FIG. 1). A second constant current source 22 is connected in series between each source and the negative power supply voltage VSS, while the positive power supply voltage VDD is applied to both of them via the "R2") 32. It is provided.
Further, the gate of the first transistor 1 is referred to as an inverting input terminal (denoted as "INM" in FIG. 1) 41, and the gate of the second transistor 2 is referred to as a non-inverting input terminal (denoted as "INP" in FIG. 1). Notation) 42 are connected to each.

Next, in the second differential pair 102, PMOSFETs (P-channel MOS field effect transistors) are used for the third and fourth transistors 3 and 4, and the third and fourth transistors 3 and 4 are used. The sources are connected to each other, and a first constant current source (denoted as “CS1” in FIG. 1) 21 is connected between the connection point and the positive power supply voltage terminal 43.

Further, the drain of the third transistor 3 is passed through the third resistor (denoted as "R3" in FIG. 1) 33, and the drain of the fourth transistor 4 is the fourth resistor (denoted as "R3" in FIG. 1). In, both are connected to the negative power supply voltage terminal 44 via the “R4”) 34, and the negative power supply voltage VSS is applied.
Further, the gate of the third transistor 3 is connected to the gate of the first transistor 1, and the gate of the fourth transistor 4 is connected to the gate of the second transistor 2.

The folded cascode circuit 103 has a function of connecting the first differential pair 101 and the second differential pair 102, and the fifth and sixth transistors 5 and 6 have PMOSFETs, and the seventh and eighth transistors. NMOSFETs are used in the transistors 7 and 8 of the above.
The fifth and sixth transistors 5 and 6 are connected to the reference voltage terminal 45 as well as their respective gates are connected to each other, while the source of the fifth transistor 5 is connected to the drain of the first transistor 1. , The source of the sixth transistor 6 is connected to the drain of the second transistor 2, respectively.

On the other hand, in the seventh and eighth transistors 7 and 8, the respective gates and the drain of the seventh transistor 7 are connected to each other, and are also connected to the drain of the fifth transistor 5.
The drain of the eighth transistor 8 is connected to the drain of the sixth transistor 6.

The source of the seventh transistor 7 is connected to the drain of the third transistor 3, and the source of the eighth transistor 8 is connected to the drain of the fourth transistor 4.
Further, a 101st transistor (denoted as "M101" in FIG. 1) 16 using a MOSFET in which a source is connected to the drain of the 8th transistor 8 and a gate is connected to the drain of the 7th transistor 7 is provided. A negative power supply voltage VSS is applied to the drain.

The output circuit 104 is configured by using a ninth transistor (denoted as “M9” in FIG. 1) 9 which is an NMOSFET, and a third constant is formed between the drain and the positive power supply voltage terminal 43. A current source (denoted as "CS3" in FIG. 1) 23 is provided in series, and an output terminal 46 is connected to the drain.
The source of the ninth transistor 9 is connected to the negative power supply voltage terminal 44 so that the negative power supply voltage VSS is applied, while the gate is the drain of the fifth and eighth transistors 5 and 8. It is connected to.

Next, the response characteristics of the comparator having the above configuration will be described.
The response characteristic described below is the propagation delay time when the output voltage of the comparator changes from Low to High, and this propagation delay time is mainly the fluctuation time of the gate potential Vg _M9 of the ninth transistor 9. It is assumed that
First, the main node potentials of the circuit when the output voltage is Low, that is, when the output voltage is substantially a negative power supply voltage, are as follows.

First, the potential of the inverting input terminal 41 is higher than the potential of the non-inverting input terminal 42, so that the first constant current is directed toward the fourth transistor 4 than the third transistor 3 of the second differential pair 102. More current flows from the source 21 and the voltage drop at the fourth resistor 34 increases.

Then, the gate-source voltage difference Vgs _{M8 of} the eighth transistor 8 becomes smaller than the gate-source potential difference Vgs _{M7 of} the seventh transistor 7.
Since the potential difference Vgs _M8 between the gate and source of the eighth transistor 8 is small, the drain potential of the eighth transistor 8 rises, and the gate potential Vg _M9 of the ninth transistor 9 rises accordingly.

For example, in the conventional comparator shown in FIG. 8 above, as shown in Equation 1 above, the gate potential Vg _M9 of the transistor M9 in the circuit of FIG. 8 rises to the vicinity of the positive power supply voltage VDD. In the comparator according to the embodiment of the above, the increase of the gate potential Vg _M9 of the ninth transistor 9 is suppressed as represented by the following equation 6.

Vg _M9L = R3 × (I _M3 + I _M7 ) + Vgs _M7 + Vgs _M101 ... Equation 6

Here, _IM3 is the drain current of the third transistor 3, _IM7 is the drain current of the seventh transistor 7, Vgs _M7 is the potential difference between the gate and the source of the seventh transistor 7, and Vgs _M101 is. It is a potential difference between the gate and the source of the 101st transistor 16.

Then, the output voltage that describes for the first differential pair 101 operates in a state of Low. In the first differential pair 101, the current of the second constant current source 22 flows more toward the first transistor 1 than by the second transistor 2, and the voltage drop in the first resistor 31 increases. On the other hand, the voltage drop in the second resistor 32 is reduced.

As a result, the potential difference Vgs _M6 between the gate and the source of the sixth transistor 6 becomes large, the drain current flows through the sixth transistor 6, and the drain potential rises. Therefore, the gate potential Vg _M9 of the ninth transistor 9 increases. Rise.
In this case, the gate potential Vg _M9 of the ninth transistor 9 has a value represented by the above equation 6.
At this time, the drain current _IM6 of the sixth transistor 6 flows into the negative power supply voltage VSS side through the 101st transistor 16.

As described above, when the output voltage is Low, the gate potential Vg _M9 of the ninth transistor 9 is represented by the above equation 6, and unlike the conventional circuit as shown in FIG. 8, the present invention is carried out. In the embodiment, the gate-source potential Vgs _M9 of the ninth transistor 9 when the output voltage is Low does not depend on the positive power supply voltage VDD.

Next, the operation when the output voltage of the comparator changes from Low to High, that is, the operation when the output voltage changes from a substantially negative power supply potential to a substantially positive power supply potential will be described.
In such a state, the potential of the non-inverting input terminal 42 is higher than the potential of the inverting input terminal 41, so that the first transistor 3 is directed toward the third transistor 3 rather than the fourth transistor 4 of the second differential pair 102. More current flows from the constant current source 21 and the voltage drop at the third resistor 33 increases.

Therefore, the gate-source voltage difference Vgs _{M8 of} the eighth transistor 8 becomes larger than the gate-source potential difference Vgs _{M7 of} the seventh transistor 7. Since the potential difference Vgs _M8 between the gate and source of the eighth transistor 8 is large, the drain current flows through the eighth transistor 8 and the drain potential decreases accordingly, and the gate of the ninth transistor 9 is accompanied by the drain current. The potential Vg _M9 decreases.

At this time, the electric charge charged in the parasitic capacitance Cc between the gate of the ninth transistor 9 and the negative power supply voltage VSS becomes a current Icx and is discharged, and a part of it is discharged as a drain current of the eighth transistor 8. It becomes.

On the other hand, in the first differential pair 101, a larger amount of current from the second constant current source 22 flows through the second transistor 2 than in the first transistor 1, and the voltage drops in the second resistor 32. Will increase. The notation "R2" shall be used as the resistance value of the second resistor 32 as necessary in the following description.

The current flowing through the second resistor 32 is the reference voltage Vref applied to the gates of the fifth and sixth transistors 5 and 6, the potential difference Vgs _M6 between the gate and source of the sixth transistor 6, and the second. The relationship between the resistance value R2 of the second resistor 32, the current _IM6 of the sixth transistor 6 and the reference voltage Vref is expressed by the following equation 7, which is determined by the voltage drop in the resistor 32.

_{R2 × (I M2 + I M6} ) + (2 × I M6 × L P / k'P × W P) 1/2 + Vth M6 = VDD-Vref ··· Equation 7

Note _{that, I M2,} a second drain current of the transistor _{2, I M6} is the drain current of the transistor 6 of the sixth, _k'P, the gate of the mobility and per unit area of the transistor 6 of the sixth product of oxide capacitance, _{W P} is the gate width of the transistor 6 of the sixth, _{L P,} the gate length of the transistor 6 of the sixth, Vth _M6 is the threshold voltage of the transistor 6 of the sixth.
Under such a relationship, the magnitude of the current _IM6 , which is a part of the current flowing through the second resistor R2, is determined.

A drain current I _M6 flows through the sixth transistor 6, but the Vgs _M6 has a low value due to the voltage drop caused by the second resistor 32. Therefore, in the sixth transistor 6, the potential difference between the drain and the source becomes large, and the current _IM6 flows, whereby the gate potential Vgs _M9 of the ninth transistor 9 decreases.

The operation of the first and second differential pairs 101 and 102 when the output voltage changes from Low to High has been described above, but in the end, the gate potential Vg _M9 of the ninth transistor 9 decreases, and the ninth transistor 9 decreases. The drain current does not flow through the transistor 9 of the comparator 9, and the output voltage of the comparator becomes High. Therefore, the gate potential Vg _M9 of the ninth transistor 9 when the output voltage becomes High drops to the threshold voltage Vth _M9 of the ninth transistor 9.
Here, if the gate voltage of the transistor M9 when the output voltage is High is defined as Vg _M9H , Vg _M9H is expressed by the following equation 8.

Vg _M9H = Vth _M9 ... Equation 8

Therefore, the gate voltage change amount ΔVg _M9 of the ninth transistor 9 when the output voltage changes from Low to High is expressed by the following equation 9 using the above equations 6 and 8.

_{ΔVg M9 = Vg M9L -Vg M9H =} R3 × (I M3 + I M7) + Vgs M7 + Vgs M101 -Vth M9 ··· formula 9

Further, using this equation 9, the fluctuation time t _LH of the gate potential Vg _M9 when the output voltage changes from Low to High is expressed by the following equation 10.

_{t LH = ΔVg M9 × Cx /} Icx = {R3 × (I M3 + I M7) + Vgs M7 + Vgs M101 -Vth M9} × Cx / Icx ··· Equation 10

Here, Cx is the parasitic capacitance between the gate of the ninth transistor 9 and the negative power supply voltage VSS, and Icx is the discharge current of the parasitic capacitance Cx.
According to the above equation 10, the response time of the ninth transistor 9 when the output voltage changes from Low to High is different from the response time in the conventional circuit shown in the equation 5 above, and does not depend on the power supply voltage. I can understand that there is.

Therefore, as shown in FIG. 6, the comparator according to the embodiment of the present invention keeps the propagation delay time with respect to the change of the power supply voltage substantially constant, and unlike the conventional case, the dependence of the response characteristic with respect to the power supply voltage is extremely high. It is small and highly stable.

Next, the second embodiment will be described with reference to FIG.
The same components as the components in the circuit shown in FIG. 1 are designated by the same reference numerals, detailed description thereof will be omitted, and the differences will be mainly described below.
In the comparator in the second embodiment, the 102nd transistor (denoted as "M102" in FIG. 2) 17 is described below instead of the 101st transistor 16 in the first embodiment shown in FIG. It is different from the first embodiment in that it is provided so as to do so.

The 102nd transistor 17 is a MOSFET whose source is connected to the drains of the 6th and 8th transistors 6 and 8, while the drain is connected to the source of the 8th transistor 8 and the gate is the 5th and 5th and 8th transistors. It is connected to the drains of the seventh transistors 5 and 7.

The circuit operation in such a configuration is basically the same as that of the first embodiment except for the following points.
That is, in the first embodiment, the current flowing through the 101st transistor 16 flows into the negative power supply voltage VSS side, whereas the current flowing through the 102nd transistor 17 in the second embodiment is. It flows into the fourth resistor 34.

Even in such a circuit operation, the fluctuation time t _LH of the gate potential Vg _M9 of the ninth transistor 9 when the output voltage changes from Low to High is the above equation as in the first embodiment. It is represented by 10.
Therefore, the response time of the ninth transistor 9 when the output voltage changes from Low to High does not depend on the power supply voltage.

As shown in FIG. 6, the comparator in the second embodiment also maintains a substantially constant propagation delay time with respect to a change in the power supply voltage, and unlike the conventional comparator, the dependence of the response characteristic on the power supply voltage is extremely small. , It is highly stable.

Next, a third embodiment will be described with reference to FIG.
The same components as the components in the circuit shown in FIG. 1 are designated by the same reference numerals, detailed description thereof will be omitted, and the differences will be mainly described below.
In the comparator according to the third embodiment, the 103rd transistor (denoted as "M103" in FIG. 3) 18 is described below in place of the 101st transistor 16 in the first embodiment shown in FIG. It is different from the first embodiment in that it is provided so as to do so.

The 103rd transistor 18 is a MOSFET whose source is connected to the drains of the 6th and 8th transistors 6 and 8, while the drain is connected to the source of the 7th transistor 7 and the gates are the 5th and 5th and 8th transistors. It is connected to the drains of the seventh transistors 5 and 7.

The circuit operation in such a configuration is basically the same as that of the first embodiment except for the following points.
That is, in the first embodiment, the current flowing through the 101st transistor 16 flows into the negative power supply voltage VSS side, whereas the current flowing through the 103rd transistor 18 in the third embodiment is It flows into the third resistor 33.

As described above, the inflow destination of the current flowing through the 103rd transistor 18 when the output voltage changes from Low to High is different from that of the first embodiment, but the fluctuation time of the gate potential Vg _M9 of the ninth transistor 9 t _LH is expressed by the following equation 11.

_{t LH = ΔVg M9 × Cx /} Icx = {R3 × (I M3 + I M7 + I M6) + Vgs M7 + Vgs M101 -Vth M9} × Cx / Icx ··· formula 11

After all, also in this third embodiment, it can be understood from the equation 11 that the response time of the ninth transistor 9 when the output voltage changes from Low to High does not depend on the power supply voltage.
Therefore, as shown in FIG. 6, the comparator of the third embodiment also keeps the propagation delay time with respect to the change of the power supply voltage substantially constant, and unlike the conventional case, the dependence of the response characteristic with respect to the power supply voltage is extremely high. It is small and highly stable.

Next, a fourth embodiment will be described with reference to FIG.
The same components as the components in the circuit shown in FIG. 1 are designated by the same reference numerals, detailed description thereof will be omitted, and the differences will be mainly described below.
In the comparator according to the fourth embodiment, the 104th transistor (denoted as "M104" in FIG. 4) 19 is described below instead of the 101st transistor 16 in the first embodiment shown in FIG. It is different from the first embodiment in that it is provided so as to do so.

The 104th transistor 19 is a MOSFET whose source is connected to the drains of the 6th and 8th transistors 6 and 8, while the drain and gate are connected to the drain and gate of the 7th transistor 7. The circuit operation in such a configuration is basically the same as that of the third embodiment, except for the following points.

That is, in the third embodiment, the current flowing through the 103rd transistor 18 flows into the third resistor 33, whereas the current flowing through the 104th transistor 19 in the fourth embodiment flows. , It flows into the seventh transistor 7.
Thus, the fluctuation time t _LH of the gate potential Vg _M9 of the ninth transistor 9 when the output voltage changes from Low to High is expressed by the above equation 11 as in the case of the third embodiment. ..

After all, also in this fourth embodiment, it can be understood from the equation 11 that the response time of the ninth transistor 9 when the output voltage changes from Low to High does not depend on the power supply voltage.
Therefore, as shown in FIG. 6, the comparator of the fourth embodiment also keeps the propagation delay time with respect to the change of the power supply voltage substantially constant, and unlike the conventional case, the dependence of the response characteristic with respect to the power supply voltage is extremely high. It is small and highly stable.

Next, a fifth embodiment will be described with reference to FIG.
The same components as the components in the circuit shown in FIG. 1 are designated by the same reference numerals, detailed description thereof will be omitted, and the differences will be mainly described below.
In the comparator according to the fifth embodiment, the 105th transistor (denoted as "M105" in FIG. 5) 20 is described below in place of the 101st transistor 16 in the first embodiment shown in FIG. It is different from the first embodiment in that it is provided so as to do so.

The 105th transistor 20 is an NMOSFET whose drain and gate are connected to the drains of the 6th and 8th transistors 6 and 8 while the source is connected to the drain and gate of the 7th transistor 7. It has become.
The circuit operation in such a configuration is basically the same as that of the fourth embodiment.
Thus, the fluctuation time t _LH of the gate potential Vg _M9 of the ninth transistor 9 when the output voltage changes from Low to High is expressed by the above equation 11 as in the case of the fourth embodiment. ..

After all, also in this fifth embodiment, it can be understood from the equation 11 that the response time of the ninth transistor 9 when the output voltage changes from Low to High does not depend on the power supply voltage.
Therefore, as shown in FIG. 6, the comparator of the fifth embodiment also keeps the propagation delay time with respect to the change of the power supply voltage substantially constant, and unlike the conventional case, the dependence of the response characteristic with respect to the power supply voltage is extremely high. It is small and highly stable.

Changes in response characteristics to changes in power supply voltage can be reliably suppressed, further stability,
It can be applied to comparators for which reliability is desired.

101 ... 1st differential pair 102 ... 2nd differential pair 103 ... Folded cascode circuit 104 ... Output circuit

Claims (2)

An input stage composed of a first differential pair made up of first and second MOS transistors and a second differential pair made up of third and fourth MOS transistors, and the first differential pair. It is provided with a folded cascode circuit capable of outputting the differential output of the differential pair of the above, and an output circuit connected to the output stage of the folded cascode circuit to output an output signal.
In the output stage of the folded cascode circuit, the sixth MOS transistor using the P-channel MOS transistor and the eighth MOS transistor using the N-channel MOS transistor are placed between the positive power supply voltage and the negative power supply voltage. The sixth MOS transistor is connected in series so as to be located on the positive power supply voltage side.
For the sixth MOS transistor that constitutes the output stage of the folded cascode circuit and is connected to the input stage of the output circuit and the potential between the gate and the source rises when the output circuit is in the Low output state. Therefore, a diversion MOS transistor for dividing the current flowing through the sixth MOS transistor is provided.
The diversion MOS transistor includes an output stage of the folded cascode circuit and an input stage of the output circuit so that the current flowing through the sixth MOS transistor of the folded cascode circuit can flow into the negative power supply voltage side. In a comparator provided in series between the mutual connection points of the above and the negative power supply voltage.
A resistor is provided between one end of the flow dividing MOS transistor on the negative power supply voltage side and the negative power supply voltage side, and a resistor forming the second differential pair is used for the resistor. The diversion MOS transistor is provided in series between the output stage of the folded cascode circuit and the input stage of the output circuit and the negative power supply voltage via the resistor.
The third and fourth MOS transistors are P-channel MOS transistors, and the sources of the third and fourth MOS transistors are connected to each other, and a third is connected between the connection point and the positive power supply voltage. The constant current source of 1 is provided, and the negative power supply voltage is applied to the drain of the third MOS transistor via the third resistor and the fourth MOS transistor via the fourth resistor. The gate of the third MOS transistor is the gate of the first MOS transistor using an N-channel MOS transistor, and the gate of the fourth MOS transistor is the gate of the second MOS using an N-channel MOS transistor. While each connected to the gate of the transistor,
The folded cascode circuit has, in addition to the sixth and eighth MOS transistors, a fifth MOS transistor using a P-channel MOS transistor and a seventh MOS transistor using an N-channel MOS transistor. The gates of the fifth and sixth MOS transistors are connected to each other, while the source of the fifth MOS transistor is the drain of the first MOS transistor, and the source of the sixth MOS transistor is the source of the sixth MOS transistor. Each connected to the drain of the second MOS transistor,
In the seventh and eighth MOS transistors, the respective gates and the drain of the seventh MOS transistor are connected to each other, and the drain of the fifth MOS transistor is connected to the fifth MOS transistor. And the drain of the 7th MOS transistor are connected to the gate of the diversion MOS transistor.
The drain of the eighth MOS transistor is connected to the drain of the sixth MOS transistor.
The source of the 7th MOS transistor is connected to the drain of the 3rd MOS transistor, and the source of the 8th transistor is connected to the drain of the 4th MOS transistor.
The resistor constituting the second differential pair provided between one end of the flow dividing MOS transistor on the negative power supply voltage side and the negative power supply voltage side is the fourth resistor or the third resistor. A comparator characterized by being a resistor. When the diversion MOS transistor is a P-channel MOS transistor, its source is connected to the drains of the sixth and eighth MOS transistors, while the drain and gate of the diversion MOS transistor are the seventh. The seventh MOS transistor is connected in series between the diversion MOS transistor and the third resistor so as to be connected to the drain and gate of the transistor.
When the diversion MOS transistor is an N-channel MOS transistor, its drain and gate are connected to the drains of the sixth and eighth MOS transistors, while the source of the diversion MOS transistor is the seventh. The seventh MOS transistor is connected in series between the diversion MOS transistor and the third resistor so as to be connected to the drain and the gate of the transistor. 1. The comparator according to 1.

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