JP6634117B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  For example, a semiconductor device in which a semiconductor element such as a transistor is sealed with a resin package has been proposed. Patent Literature 1 discloses a semiconductor device including a semiconductor element having three electrodes, three leads connected to these electrodes, and a resin package that covers each of the semiconductor element and a part of the three leads. The three electrodes are formed on the same surface of the semiconductor element. The semiconductor element is joined to one of the three leads. The three electrodes are electrically connected to the three leads through three wires. The resin package covers the entire semiconductor element, all of the three wires, and a part of the three leads. Portions of the three leads protruding from the resin package serve as terminal portions for mounting the semiconductor device.

  In a conventional semiconductor device, a lead on which a semiconductor element is arranged is larger than a semiconductor element in a plan view. The size of the resin package is determined by the large leads. For this reason, large leads hinder miniaturization of the semiconductor device.

  The three wires generally have a loop shape. Therefore, in order to properly cover the three wires, the resin package needs to have an appropriate height. This increases the height of the semiconductor device. At the same time, in order to properly bond the three wires, it is necessary to secure a certain distance between a so-called first bonding portion and a second bonding portion. Further, the terminal portions of the three leads protrude from the resin package. These increase the dimensions of the semiconductor device in plan view. Thus, there is a problem that it is difficult to reduce the size of the semiconductor device.

JP 2012-190936 A

  The present invention has been conceived under the above circumstances, and has as its main object to provide a semiconductor device which can be reduced in size.

  According to a first aspect of the present invention, the semiconductor device includes a semiconductor element, a main lead on which the semiconductor element is arranged, and a resin package that covers the semiconductor element and the main lead. A semiconductor device is provided that is exposed and has a portion that does not overlap the main lead when viewed in the thickness direction of the semiconductor element.

  Preferably, the main lead has a main lead main surface and a main lead back surface facing each other, the semiconductor element is disposed on the main lead main surface, and the main lead back surface is formed of the resin. Exposed from the package.

  Preferably, the main lead includes a main full thickness portion and a main eave portion, the main total thickness portion is a portion extending from the main lead main surface to the main lead back surface, and the main eave portion is the semiconductor eaves portion. It protrudes from the main entire thickness portion in a direction perpendicular to the thickness direction of the element.

  Preferably, the semiconductor element entirely overlaps the main entire thickness portion as viewed in the thickness direction of the semiconductor element.

  Preferably, the semiconductor device further includes a first sub-lead that is electrically connected to the semiconductor element. The first sub-lead is separated from the main lead and is exposed from the resin package.

Preferably, the main eave portion has a main front portion, and the main front portion protrudes from the total main thickness portion toward the first sub-lead.

  Preferably, the main eave portion has a main side portion, and the main side portion projects from the main full thickness portion in a direction perpendicular to a direction in which the main front portion projects. .

  Preferably, the main lead includes a main side connecting portion protruding from the main side portion, and the main side connecting portion has an end face exposed from the resin package.

  Preferably, the main eave portion has a main rear portion, and the main rear portion protrudes from the main full thickness portion in a direction opposite to a direction in which the main front portion protrudes.

  Preferably, the main lead includes a main rear connecting portion protruding from the main rear portion, and the main rear connecting portion has an end face exposed from the resin package.

  Preferably, the main entire thickness portion is entirely surrounded by the main eaves portion when viewed in the thickness direction of the semiconductor element.

  Preferably, the main eave portion entirely overlaps the semiconductor element when viewed in the thickness direction of the semiconductor element.

  Preferably, the semiconductor device further includes a main surface plating layer formed on the main lead and interposed between the semiconductor element and the main lead.

  Preferably, the main surface plating layer overlaps the entire main eave portion.

  Preferably, the semiconductor device further includes a first sub-lead that is electrically connected to the semiconductor element, the first sub-lead is separated from the main lead, and the outer side of the resin package when viewed in a thickness direction of the semiconductor element. And is exposed from the resin package.

  Preferably, the first sub-lead includes a first sub-full thickness portion and a first sub-eave portion, and the first sub-lead has a first sub-lead main surface and a first sub-lead rear surface facing opposite sides. The first sub lead back surface is exposed from the resin package, the first sub total thickness portion is a portion extending from the first sub lead main surface to the first sub lead back surface, The one sub-eave portion protrudes from the first sub-all-thickness portion in a direction perpendicular to the thickness direction of the semiconductor element, and constitutes the first sub-lead main surface.

  Preferably, the first sub-eave portion has a first sub-front portion, and the first sub-front portion projects from the first sub full thickness portion toward the main lead.

  Preferably, the first sub total thickness portion is exposed from the resin package toward the outside of the resin package when viewed in the thickness direction of the semiconductor element.

  Preferably, the first sub-lead includes a first sub-extending portion, extends from the first sub-all-thickness portion in a direction perpendicular to a thickness direction of the semiconductor element, and The first sub-lead forms a back surface, and the first sub-extending portion is exposed from the resin package toward the outside of the resin package when viewed in the thickness direction of the semiconductor element.

  Preferably, the first sub-lead has a main surface of the first sub-lead and a back surface of the first sub-lead facing each other, and the back surface of the first sub-lead is exposed from the resin package.

  Preferably, the resin package has a resin back surface facing in the same direction as the direction of the first sub lead back surface, and the resin back surface is flush with the first sub lead back surface.

  Preferably, the first sub-lead has a first sub-lead end face connected to the back surface of the first sub-lead, and the first sub-lead end face faces a side opposite to a side where the main lead is located. .

  Preferably, the first sub-lead end face is exposed from the resin package.

  Preferably, the resin package has a first resin end face facing in the same direction as the direction of the first sub-lead end face, and the first resin end face is flush with the first sub-lead end face. .

  Preferably, the first sub-lead has a first sub-lead side surface connected to the back surface of the first sub-lead, and the first sub-lead side surface has a direction in which the first sub-lead end surface faces and a thickness of the semiconductor element. In both directions.

  Preferably, the first sub-lead side surface is exposed from the resin package.

  Preferably, the resin package has a first resin side surface facing the same direction as the direction of the first sub-lead side surface, and the first sub-lead side surface is flush with the first resin side surface. .

  Preferably, the semiconductor device further includes a first wire directly connected to the semiconductor element and electrically connecting the semiconductor element and the first auxiliary lead.

  Preferably, the apparatus further includes a first sub-plating layer interposed between the first sub-lead and the first wire.

  Preferably, the semiconductor device further includes a second sub-lead electrically connected to the semiconductor element, wherein the second sub-lead is separated from the main lead and the first sub-lead, and viewed in a thickness direction of the semiconductor element. The resin package is exposed outside the resin package.

  Preferably, the semiconductor device further includes a second wire directly connected to the semiconductor element and electrically connecting the semiconductor element and the second auxiliary lead.

  Preferably, the apparatus further comprises a second sub-plating layer interposed between the second sub-lead and the second wire.

  Preferably, the semiconductor element has a semiconductor layer stacked on each other, a eutectic layer of a semiconductor and a metal, and a single metal layer constituting the back electrode, and the single metal layer is directly bonded to the main lead. Have been.

  Preferably, the eutectic layer is made of a eutectic of Si and Au.

  Preferably, the single metal layer is thinner than the eutectic layer.

  Preferably, the semiconductor device further includes a first wire, wherein the semiconductor element includes a first surface electrode to which the first wire is bonded, and wherein the first surface electrode is configured such that the main surface is viewed in a thickness direction of the semiconductor element. It overlaps the thick part.

  Preferably, the semiconductor device further includes a second wire, wherein the semiconductor element includes a second surface electrode to which the second wire is bonded, and wherein the second surface electrode is configured such that the main surface is viewed in a thickness direction of the semiconductor element. It overlaps the thick part.

  Preferably, further comprising a first wire, a second wire, the semiconductor element, the first surface electrode to which the first wire is joined, and the second surface electrode to which the second wire is joined, And at least one of the first surface electrode and the second surface electrode overlaps the main entire thickness portion in the thickness direction of the semiconductor element.

  According to a second aspect of the present invention, there are a front surface and a back surface facing in opposite directions in the thickness direction, a first surface electrode and a second surface electrode formed on the front surface, and a back electrode formed on the back surface. A semiconductor element, a main pad having a die pad portion to which the back electrode is electrically connected and a main back terminal portion facing the opposite side to the die pad portion, and a first lead connected to the first front electrode via a first wire. A first sub lead having a first wire bonding portion and a first sub back surface terminal portion facing the opposite side to the first wire bonding portion, and a second wire bonding connected to the second front surface electrode via a second wire A second sub-lead having a second sub-backside terminal portion facing the side opposite to the second wire bonding portion, the semiconductor element and the main lead, the first sub-lead, A resin package that covers a part of the second sub-lead and exposes the main back surface terminal portion, the first sub back surface terminal portion, and the second sub back surface terminal portion on the same side, The main lead has a main total thickness portion extending from the die pad portion to the main back surface terminal portion, and a main eave portion protruding from the die pad portion side portion of the main full thickness portion in a direction perpendicular to the thickness direction. Wherein the die pad portion and the semiconductor element overlap both the main total thickness portion and the main eave portion in a thickness direction view, and at least one of the first surface electrode and the second surface electrode. The first wire is bonded to the first bonding portion bonded to the first wire bonding portion via the first bump to the first surface electrode. A second bonding portion connected to the first bonding portion bonded to the second wire bonding portion, and a second bonding portion bonded to the second surface electrode via a second bump. And a semiconductor device.

  Preferably, the first surface electrode is a gate electrode, the second surface electrode is a source electrode, the back electrode is a drain electrode, and the semiconductor element is configured as a transistor. An electrode is more distant from the first sub-lead and the second sub-lead than the second surface electrode.

  Preferably, the first surface electrode overlaps the main entire thickness portion when viewed in the thickness direction, and the second surface electrode overlaps the main eave portion when viewed in the thickness direction.

  Preferably, the first surface electrode overlaps both the main entire thickness portion and the main eave portion in a thickness direction view.

  Preferably, the first bump of the first wire and the second bonding portion of the first wire overlap with both the main entire thickness portion and the main eave portion in a thickness direction view.

  Preferably, the main eave portion has a main front portion protruding from the total main thickness portion toward the first sub lead and the second sub lead.

  Preferably, the main eave portion has a main side portion protruding in a direction perpendicular to a direction in which the main front portion protrudes.

  Preferably, the main lead has a main side connecting portion projecting from the main side portion and having one end surface exposed from the resin package.

  Preferably, the main eave portion has a main rear portion protruding on a side opposite to the main front portion.

  Preferably, the main lead has a main rear connecting portion protruding from the main rear portion and having one end surface exposed from the resin package.

  Preferably, all of the main total thickness portion is surrounded by the main eave portion.

  Preferably, a main surface plating layer is formed on the die pad portion.

  Preferably, the main surface plating layer overlaps all of the main eaves.

  Preferably, the first sub lead is a first sub full thickness portion extending from the first wire bonding portion to the first sub back surface terminal portion and a portion of the first sub full thickness portion on the first wire bonding portion side. A first sub-eave portion protruding in a direction perpendicular to the thickness direction.

  Preferably, the first sub eave portion has a first sub front portion protruding from the first sub full thickness portion toward the main lead.

  Preferably, the first sub eave portion has a first sub side portion protruding in a direction perpendicular to a direction in which the first sub front portion protrudes.

  Preferably, the first sub-lead has a first sub-side connecting portion projecting from the first sub-side portion and having one end surface exposed from the resin package.

  Preferably, the first sub-eave portion has a first sub-rear portion protruding on a side opposite to the first sub-front portion.

  Preferably, the first sub-lead has a first sub-rear connecting portion projecting from the first sub-rear portion and having one end surface exposed from the resin package.

  Preferably, all of the first sub-total thickness portion is surrounded by the first sub-eave portion.

  Preferably, a first sub surface plating layer is formed in the first wire bonding portion.

  Preferably, the first sub surface plating layer overlaps all of the first sub eaves.

  Preferably, the second sub lead is a second sub full thickness portion extending from the second wire bonding portion to the second sub back surface terminal portion, and a portion of the second sub full thickness portion on the side of the second wire bonding portion. A second sub-eave portion protruding in a direction perpendicular to the thickness direction.

  Preferably, the second sub eave portion has a second sub front portion protruding from the second sub full thickness portion toward the main lead.

  Preferably, the second sub eave portion has a second sub side portion protruding in a direction perpendicular to a direction in which the second sub front portion protrudes.

  Preferably, the second sub-lead has a second sub-side connecting portion projecting from the second sub-side portion and having one end surface exposed from the resin package.

  Preferably, the second sub-eave portion has a second sub-rear portion protruding on the opposite side to the second sub-front portion.

  Preferably, the second sub-lead has a second sub-rear connecting portion projecting from the second sub-rear portion and having one end surface exposed from the resin package.

  Preferably, all of the second sub-thick portions are surrounded by the second sub-eave portions.

  Preferably, a second sub surface plating layer is formed in the second wire bonding portion.

  Preferably, the second sub surface plating layer overlaps all of the second sub eaves.

  Preferably, the semiconductor element has a semiconductor layer stacked on each other, a eutectic layer of a semiconductor and a metal, and a single metal layer constituting the back electrode, and the single metal layer is directly bonded to the die pad portion. Have been.

  Preferably, the eutectic layer is made of a eutectic of Si and Au.

  Preferably, the single metal layer is thinner than the eutectic layer.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

FIG. 2 is a perspective view of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1. FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1. FIG. 4 is a sectional view taken along the line IV-IV in FIG. 2. FIG. 5 is a sectional view taken along line VV in FIG. 2. FIG. 2 is a partially enlarged cross-sectional view of the semiconductor device shown in FIG. 1. FIG. 7 is a sectional view taken along line VII-VII in FIG. 2. FIG. 7 is a sectional view taken along the line VIII-VIII in FIG. 2. FIG. 3 is a cross-sectional view taken along line IX-IX in FIG. 2. 2 is an enlarged image showing a second bonding portion of the semiconductor device shown in FIG. FIG. 2 is a cross-sectional view showing one step in a method for manufacturing the semiconductor device shown in FIG. 1. It is a perspective view of a semiconductor device concerning a 2nd embodiment of the present invention. FIG. 13 is a plan view of the semiconductor device shown in FIG. 12. FIG. 2 is an enlarged plan view of a main part showing a semiconductor element of the semiconductor device of FIG. 1. It is a top view of the modification of the semiconductor device of the present invention. FIG. 13 is a perspective view illustrating an example of a semiconductor device according to a third embodiment of the present invention. FIG. 17 is a perspective view illustrating the semiconductor device of FIG. 16. FIG. 17 is a plan view illustrating the semiconductor device of FIG. 16. FIG. 19 is a sectional view taken along the line XIX-XIX in FIG. 18. It is sectional drawing which follows the XX-XX line of FIG. FIG. 17 is an enlarged fragmentary sectional view showing the semiconductor device of FIG. 16; FIG. 19 is a sectional view taken along the line XXII-XXII in FIG. 18. It is sectional drawing which follows the XXIII-XXIII line of FIG. FIG. 19 is a sectional view taken along the line XXIV-XXIV in FIG. 18. FIG. 17 is an enlarged plan view of a principal part showing a semiconductor element of the semiconductor device of FIG. 16. FIG. 17 is a sectional view illustrating an example of a manufacturing process of the semiconductor device in FIG. 16. FIG. 17 is a sectional view illustrating an example of a manufacturing process of the semiconductor device in FIG. 16. FIG. 17 is a sectional view illustrating an example of a manufacturing process of the semiconductor device in FIG. 16. FIG. 17 is a sectional view illustrating an example of a manufacturing process of the semiconductor device in FIG. 16. FIG. 17 is a sectional view illustrating an example of a manufacturing process of the semiconductor device in FIG. 16. FIG. 17 is a sectional view illustrating an example of a manufacturing process of the semiconductor device in FIG. 16. 17 is an enlarged image showing a second bonding portion formed in an example of a manufacturing process of the semiconductor device in FIG. 16. FIG. 17 is an essential part plan view showing a cutting step in an example of a manufacturing step of the semiconductor device in FIG. 16; 17 is an X-ray image showing the semiconductor device of FIG. It is a top view showing an example of a semiconductor device based on a 4th embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.

  A first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a perspective view of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a plan view of the semiconductor device shown in FIG. FIG. 3 is a bottom view of the semiconductor device shown in FIG. FIG. 4 is a sectional view taken along line IV-IV in FIG. FIG. 5 is a sectional view taken along line VV in FIG. FIG. 6 is a partially enlarged sectional view of the semiconductor device shown in FIG. FIG. 7 is a sectional view taken along the line VII-VII in FIG. FIG. 8 is a sectional view taken along line VIII-VIII in FIG. FIG. 9 is a sectional view taken along the line IX-IX in FIG.

  The semiconductor device 101 of the present embodiment includes a semiconductor element 200, a main lead 300, a first sub lead 400, a second sub lead 500, a first wire 600, a second wire 700, and a resin package 800. 1 and 2, the resin package 800 is indicated by a two-dot chain line. The semiconductor device 101 is configured as a so-called relatively small semiconductor device that can be mounted on a surface. As an example of the size of the semiconductor device 101, the dimension in the x direction is about 0.4 to 0.8 mm, the dimension in the y direction is about 0.2 to 0.6 mm, and the dimension z in the thickness direction is 0.3 to 0.3 mm. It is about 4 mm.

  In the present embodiment, the semiconductor element 200 is configured as a so-called transistor. The semiconductor element 200 has a front surface 201 and a back surface 202, and a first front electrode 211, a second front electrode 212, and a back electrode 220 are formed. The front surface 201 and the back surface 202 face in opposite directions in the z direction. To give an example of the size of the semiconductor element 200, the dimension in the x direction is about 300 μm, and the dimension in the y direction is about 300 μm.

  As shown in FIG. 14, the first surface electrode 211 and the second surface electrode 212 are formed on the surface 201, and are configured by a part of the electrode layer 213 made of, for example, an Au plating layer. In the present embodiment, the first surface electrode 211 is a gate electrode, and the second surface electrode 212 is a source electrode. In the present embodiment, in FIG. 14, the first surface electrode 211 is located on the left side in the x direction, and the second surface electrode 212 is located on the right side in the x direction. Further, the first surface electrode 211 is located on the lower side in the y-direction diagram, and the second surface electrode 212 is located on the upper side in the y-direction diagram. The back surface electrode 220 is formed on the back surface 202. In the present embodiment, the back electrode 220 is a drain electrode.

  By removing a part of the electrode layer 231, a removed region 214 is formed. The removal region 214 has a shape surrounding the first surface electrode 211. More specifically, the removal region 214 has a portion extending in parallel with each other along four sides of the semiconductor element 200 and a portion located across a relatively large area to surround the first surface electrode 211. I have. The first surface electrode 211 and the second surface electrode 212 are insulated from each other by the annular removal region 214.

  The area around the second surface electrode 212 is an active area 216. In the active region 216, a MOSFET 217 is formed at a position inside the surface 201 in the z direction. The MOSFET 217 includes a plurality of unit cells 218 arranged in a matrix. Note that the arrangement form of the plurality of unit cells 218 is not limited to a matrix shape, and may be, for example, a stripe shape or a staggered shape.

  In the present embodiment, one second surface electrode 212 is provided as a source electrode. However, the present invention is not limited to this, and a plurality of second surface electrodes 212 may be provided.

  The semiconductor element 200 is arranged on the main lead 300. As shown in FIGS. 2 and 3, in the present embodiment, the semiconductor element 200 has a portion that does not overlap the main lead 300 when viewed in the thickness direction z. That is, in the thickness direction z, the semiconductor element 200 has a portion protruding outside the main lead 300. As will be described in detail later, the main lead 300 is exposed from the resin package 800. The main lead 300 is derived from a lead frame. The main lead 300 is formed by performing patterning such as etching on a metal plate made of Cu, for example.

  As shown in FIG. 4, FIG. 5, etc., the main lead 300 has a main lead main surface 310 and a main lead back surface 320 which face each other. The main lead main surface 310 and the main lead back surface 320 are both flat.

  The main lead main surface 310 faces upward in the thickness direction z. The semiconductor element 200 is arranged on the main lead main surface 310. In the present embodiment, a main surface plating layer 311 is formed on the main lead main surface 310 of the main lead 300. Main surface plating layer 311 is interposed between semiconductor element 200 and main lead 300. The main surface plating layer 311 is formed over the entire area of the main surface 310 of the main lead. Main surface plating layer 311 is made of, for example, Ag having a thickness of about 2 μm.

  In FIG. 3, the main lead back surface 320 is indicated by hatching. The main lead back surface 320 faces downward in the thickness direction z opposite to the main lead main surface 310 and is used for surface mounting the semiconductor device 101. The main lead back surface 320 has a rectangular shape. The main lead back surface 320 entirely overlaps the main lead main surface 310 when viewed in the thickness direction z, and is included in the main lead main surface 310.

  The main lead 300 includes a main total thickness portion 330 and a main eave portion 340.

  The main total thickness portion 330 is a portion extending from the main lead main surface 310 to the main lead back surface 320 in the thickness direction z. In the present embodiment, the entire main thickness portion 330 entirely overlaps the semiconductor element 200 in the thickness direction z. At least one of the first surface electrode 211 and the second surface electrode 212 overlaps the main entire thickness portion 330 in the thickness direction z. In the present embodiment, both the first surface electrode 211 and the second surface electrode 212 overlap the main entire thickness portion 330 in the thickness direction z. That is, the first surface electrode 211 and the second surface electrode 212 are arranged near the center of the semiconductor element 200 when viewed in the thickness direction z. Unlike the present embodiment, only the first surface electrode 211 overlaps the main full thickness portion 330 in the thickness direction z, and the second surface electrode 212 overlaps the main full thickness portion 330 in the thickness direction z. It is not necessary. Similarly, unlike the present embodiment, only the second surface electrode 212 overlaps the main full thickness portion 330 in the thickness direction z, and the first surface electrode 211 overlaps the main full thickness portion 330 in the thickness direction z. It does not have to overlap in. In the present embodiment, the thickness of the main total thickness portion 330 is about 0.9 to 1.1 mm. The main total thickness portion 330 forms the main lead back surface 320.

  The main eaves portion 340 protrudes from the main full thickness portion 330 in a direction perpendicular to the thickness direction z. In the present embodiment, the main eave portion 340 protrudes from the main total thickness portion 330 in the x direction and the y direction perpendicular to the thickness direction z. In this embodiment, the main eave portion 340 further protrudes from the portion of the main total thickness portion 330 on the main lead main surface 310 side in the x direction and the y direction perpendicular to the thickness direction z. The thickness of the main eave portion 340 is, for example, half of the total main thickness portion 330 and is about 0.05 mm. The main eave portion 340 and the main total thickness portion 330 constitute the main lead main surface 310 described above. On the other hand, main eave portion 340 does not constitute main lead back surface 320. The main eave portion 340 surrounds the main entire thickness portion 330 in the thickness direction z. In the present embodiment, the main eaves portion 340 further entirely overlaps the semiconductor element 200 as viewed in the thickness direction z.

  In the present embodiment, the main eave portion 340 has a main front portion 341, a main side portion 342, and a main rear portion 343.

  The main front portion 341 protrudes from the main full thickness portion 330 toward the first sub lead 400. Further, in the present embodiment, the main front portion 341 further projects from the main entire thickness portion 330 toward the second sub-lead 500.

  The main side portion 342 protrudes from the main full thickness portion 330 in a direction perpendicular to the direction in which the main front portion 341 protrudes. More specifically, the main side portion 342 protrudes from the total main thickness portion 330 in the y direction. In the present embodiment, two main side portions 342 are formed. In the present embodiment, the main lead 300 has two main side connecting portions 351. The main side connecting portion 351 extends from the main side portion 342 of the main eave portion 340 and has the same thickness as the main side portion 342. An end surface in the y direction of the main side connection portion 351 is exposed from the resin package 800.

  The main rear portion 343 protrudes from the main full thickness portion 330 in a direction opposite to the direction in which the main front portion 341 protrudes. In the present embodiment, the main lead 300 has a main rear connecting portion 352. The main rear connecting portion 352 extends from the main rear portion 343 of the main eave portion 340, and has the same thickness as the main rear portion 343. The x-direction end face of the main rear connection portion 352 is exposed from the resin package 800.

  As shown in FIG. 6, in the semiconductor element 200, the back electrode 220 is bonded to the main lead main surface 310 (main surface plating layer 311). Specifically, back electrode 220 as a single metal layer is directly bonded to main lead main surface 310 (main surface plating layer 311) by, for example, a thermocompression bonding method. In this thermocompression bonding, no vibration is applied, and only heat and pressure are applied.

  The first sub lead 400 is separated from the main lead 300. Specifically, the first sub-lead 400 is disposed apart from the main lead 300 in the x direction. Further, the first sub lead 400 is separated from the second sub lead 500. The first sub lead 400 is exposed from the resin package 800 to the outside of the resin package 800 when viewed in the thickness direction z. In the present embodiment, the first sub lead 400 is exposed from the resin package 800 in the directions x and y from the resin package 800. The first sub lead 400 is derived from a lead frame. The first sub-lead 400 is formed by performing patterning such as etching on a metal plate made of, for example, Cu.

  The first sub-lead 400 has a first sub-lead main surface 410, a first sub-lead back surface 420, a first sub-lead end surface 481, and a first sub-lead side surface 482. The first sub-lead main surface 410, the first sub-lead back surface 420, the first sub-lead end surface 481, and the first sub-lead side surface 482 are all flat.

  The first sub lead main surface 410 faces upward in the thickness direction z. The first wire 600 is bonded to the first sub lead main surface 410. In the present embodiment, a first sub surface plating layer 411 is formed on the first sub lead main surface 410. The first sub surface plating layer 411 is interposed between the first sub lead main surface 410 and the first wire 600. The first sub surface plating layer 411 is formed over the entire area of the first sub lead main surface 410. The first sub surface plating layer 411 is made of, for example, Ag having a thickness of about 2 μm. In FIG. 1, the halftone is applied to the first sub surface plating layer 411 for convenience of understanding.

  The first sub-lead back surface 420 faces the opposite side to the direction in which the first sub-lead main surface 410 faces. Specifically, the back surface 420 of the first sub lead faces downward in the thickness direction z on the opposite side to the main surface 410 of the first sub lead. The first sub lead back surface 420 is exposed from the resin package 800. The first sub lead back surface 420 is used for surface mounting the semiconductor device 101. In FIG. 3, the first sub lead back surface 420 is indicated by hatching.

  The first sub-lead end face 481 faces the side opposite to the side where the main lead 300 is located. Specifically, the first sub-lead end face 481 faces the right side in FIG. The first sub-lead end surface 481 is connected to the first sub-lead back surface 420. The first sub-lead end surface 481 is exposed from the resin package 800.

  The first sub-lead side surface 482 faces a direction perpendicular to both the direction of the first sub-lead end surface 481 and the thickness direction z of the semiconductor element 200. Specifically, the first sub-lead side surface 482 faces the lower side in FIG. The first sub-lead side surface 482 is connected to the first sub-lead back surface 420. The first sub-lead side surface 482 is exposed from the resin package 800.

  The first sub lead 400 includes a first sub full thickness portion 430 and a first sub eave portion 440.

  The first sub total thickness portion 430 is a portion extending from the first sub lead main surface 410 to the first sub lead back surface 420 in the thickness direction z. In the present embodiment, the thickness of the first sub total thickness portion 430 is about 0.1 mm. The first sub-thick portion 430 forms a first sub-lead main surface 410 and a first sub-lead back surface 420. In the present embodiment, the first sub total thickness portion 430 is exposed from the resin package 800. Therefore, the first sub total thickness portion 430 forms the first sub lead end surface 481 and the first sub lead side surface 482.

  The first sub eaves portion 440 protrudes from the first sub full thickness portion 430 in a direction perpendicular to the thickness direction z. In the present embodiment, the first sub-eave portion 440 protrudes in the x direction and the y direction. The thickness of the first sub-eave portion 440 is, for example, half of the first sub-total thickness portion 430 and is about 0.05 mm. The first sub-eave portion 440 forms a first sub-lead main surface 410. On the other hand, the first sub-eave portion 440 does not constitute the first sub-lead back surface 420.

  In the present embodiment, the first sub-eave portion 440 has a first sub-front portion 441 and a first sub-inner portion 442.

  The first sub front part 441 protrudes from the first sub total thickness part 430 toward the main lead 300. The first sub inner portion 442 protrudes from the first sub full thickness portion 430 toward the second sub lead 500.

  The second sub lead 500 is separated from the main lead 300. Specifically, the second sub-lead 500 is spaced apart from the main lead 300 in the x direction. Further, the second sub-lead 500 is separated from the first sub-lead 400. The second sub-lead 500 is exposed from the resin package 800 outside the resin package 800 when viewed in the thickness direction z. In the present embodiment, the second sub-lead 500 is exposed from the resin package 800 in the directions x and y from the resin package 800. The second sub lead 500 is derived from a lead frame. The second sub-lead 500 is formed by performing patterning such as etching on a metal plate made of, for example, Cu.

  The second sub-lead 500 has a second sub-lead main surface 510, a second sub-lead back surface 520, a second sub-lead end surface 581, and a second sub-lead side surface 582. The second sub-lead main surface 510, the second sub-lead back surface 520, the second sub-lead end surface 581, and the second sub-lead side surface 582 are all flat.

  The second sub lead main surface 510 faces upward in the thickness direction z. The second wire 700 is bonded to the second sub lead main surface 510. In the present embodiment, a second sub surface plating layer 511 is formed on the second sub lead main surface 510. Second sub surface plating layer 511 is interposed between second sub lead main surface 510 and second wire 700. The second sub surface plating layer 511 is formed over the entire area of the second sub lead main surface 510. The second sub surface plating layer 511 is made of, for example, Ag having a thickness of about 2 μm. In FIG. 1, the halftone is applied to the second sub surface plating layer 511 for convenience of understanding.

  The second sub-lead back surface 520 faces the opposite side to the direction in which the second sub-lead main surface 510 faces. Specifically, the second sub-lead back surface 520 faces downward in the thickness direction z on the side opposite to the second sub-lead main surface 510. The second sub lead back surface 520 is exposed from the resin package 800. The second sub lead back surface 520 is used for surface mounting the semiconductor device 101. In FIG. 3, the second sub-lead back surface 520 is indicated by hatching.

  The second sub-lead end surface 581 faces the side opposite to the side where the main lead 300 is located. Specifically, the second sub-lead end face 581 faces the right side in FIG. The second sub-lead end surface 581 is connected to the second sub-lead back surface 520. The second sub-lead end face 581 is exposed from the resin package 800.

  The second sub-lead side surface 582 faces a direction perpendicular to both the direction of the second sub-lead end surface 581 and the thickness direction z of the semiconductor element 200. Specifically, the second sub-lead side surface 582 faces upward in FIG. The second sub-lead side surface 582 is connected to the second sub-lead back surface 520. The second sub-lead side surface 582 is exposed from the resin package 800.

  The second sub lead 500 includes a second sub full thickness portion 530 and a second sub eave portion 540.

  The second sub total thickness portion 530 is a portion extending from the second sub lead main surface 510 to the second sub lead back surface 520 in the thickness direction z. In the present embodiment, the thickness of the second sub total thickness portion 530 is about 0.1 mm. The second sub total thickness portion 530 forms a second sub lead main surface 510 and a second sub lead back surface 520. In the present embodiment, the second sub full thickness portion 530 is exposed from the resin package 800. Therefore, the second sub total thickness portion 530 forms the second sub lead end surface 581 and the second sub lead side surface 582.

  The second sub eaves portion 540 protrudes from the second sub full thickness portion 530 in a direction perpendicular to the thickness direction z. In the present embodiment, the second sub-eave portion 540 protrudes in the x direction and the y direction. The thickness of the second sub-eave portion 540 is, for example, half of the second sub-total thickness portion 530 and is about 0.05 mm. The second sub-eave portion 540 forms a second sub-lead main surface 510. On the other hand, the second sub-eave portion 540 does not constitute the second sub-lead back surface 520.

  In the present embodiment, the second sub-eave portion 540 has a second sub-front portion 541 and a second sub-inner portion 542.

  The second sub front portion 541 protrudes from the second sub full thickness portion 530 toward the main lead 300. The second sub inner portion 542 protrudes from the second sub total thickness portion 530 toward the first sub lead 400.

  The first wire 600 is directly connected to the semiconductor element 200 and makes the semiconductor element 200 and the first sub lead 400 conductive. Specifically, the first wire 600 is bonded to the first surface electrode 211 of the semiconductor element 200 and the first sub surface plating layer 411.

  The first wire 600 has a first bonding part 610 and a second bonding part 620. The first wire 600 is made of Au having a diameter of about 20 μm.

  The first bonding portion 610 is bonded to the first sub surface plating layer 411 and has a crown-shaped mass portion.

  The second bonding portion 620 is bonded to the first surface electrode 211 of the semiconductor device 200 via the first bump 630. The second bonding portion 620 has a tapered shape in which the thickness z in the thickness direction becomes smaller toward the tip.

  The first bump 630 is a portion similar to the above-described lump portion of the first bonding portion 610. In the present embodiment, the volume of the first bump 630 is slightly smaller than the volume of the lump of the first bonding portion 610. The first bump 630 overlaps the main entire thickness portion 330 in the thickness direction z. FIG. 10 shows an enlarged image of the second bonding portion 620 of the semiconductor device shown in FIG.

  The second wire 700 is directly connected to the semiconductor element 200 and makes the semiconductor element 200 and the second sub-lead 500 conductive. Specifically, the second wire 700 is bonded to the second surface electrode 212 of the semiconductor element 200 and the second sub surface plating layer 511.

  The second wire 700 has a first bonding part 710 and a second bonding part 720. The second wire 700 is made of Au having a diameter of about 20 μm.

  The first bonding portion 710 is bonded to the second sub surface plating layer 511 and has a crown-shaped mass portion.

  The second bonding portion 720 is bonded to the second surface electrode 212 of the semiconductor device 200 via the second bump 730. The second bonding portion 720 has a tapered shape in which the thickness in the thickness direction z decreases toward the tip.

  The second bump 730 is a portion similar to the above-described lump portion of the first bonding portion 710. The second bump 730 overlaps the main full thickness portion 330 in the thickness direction z. In the present embodiment, the volume of the second bump 730 is slightly smaller than the volume of the lump of the first bonding portion 710.

  The resin package 800 covers the semiconductor element 200, the main lead 300, the first sub lead 400, the second sub lead 500, the first wire 600, and the second wire 700. The resin package 800 is made of, for example, a black epoxy resin. Further, the resin package 800 places the main lead back surface 320 of the main lead 300, the first sub lead back surface 420 of the first sub lead 400, and the second sub lead back surface 520 of the second sub lead 500 in the thickness direction z downward. It is exposed to the side.

  The resin package 800 has a resin main surface 801, a resin back surface 802, a first resin side surface 803, a second resin side surface 804, a first resin end surface 805, and a second resin end surface 806.

  The resin main surface 801 faces in the same direction as the direction in which the main lead main surface 310 faces. In the present embodiment, the resin main surface 801 is flat.

  The resin back surface 802 faces in the same direction as the direction in which the main lead back surface 320 faces. That is, the resin back surface 802 faces in a direction opposite to the direction in which the resin main surface 801 faces. The resin back surface 802 is flat. The main lead 300, the first sub lead 400, and the second sub lead 500 are exposed from the resin back surface 802. In the present embodiment, the resin back surface 802 is flush with any of the main lead back surface 320, the first sub lead back surface 420, and the second sub lead back surface 520.

  The first resin side surface 803 faces the same direction as the direction of the first sub-lead side surface 482 of the first sub-lead 400. The first resin side surface 803 is flat. The first sub-lead 400 is exposed from the first resin side surface 803. In the present embodiment, the first sub total thickness portion 430 is exposed from the second resin side surface 804. The first resin side surface 803 is flush with the first sub-lead side surface 482. In the present embodiment, the main lead 300 is further exposed on the first resin side surface 803. Specifically, in the first resin side surface 803, the main side connecting portion 351 of the main lead 300 is exposed. The first resin side surface 803 is flush with the end surface of the main side connection portion 351.

  The second resin side surface 804 faces in the same direction as the direction in which the second sub-lead side surface 582 of the second sub-lead 500 faces. The second resin side surface 804 is flat. The second sub-lead 500 is exposed from the second resin side surface 804. The second resin side surface 804 is flush with the second sub-lead side surface 582. In the present embodiment, the second sub total thickness portion 530 is exposed from the second resin side surface 804. In the present embodiment, the main lead 300 is further exposed on the second resin side surface 804. Specifically, in the second resin side surface 804, the main side connecting portion 351 of the main lead 300 is exposed. The second resin side surface 804 is flush with the end surface of the main side connection portion 351.

  The first resin end face 805 faces in the same direction as the direction in which the first sub lead end face 481 of the first sub lead 400 faces. The first resin end surface 805 is flat. The first sub lead 400 is exposed from the first resin end surface 805. The first resin end face 805 is flush with the first sub-lead end face 481. In the present embodiment, the first sub total thickness portion 430 is exposed from the first resin end surface 805. Similarly, the first resin end surface 805 faces the same direction as the direction of the second sub-lead end surface 581 of the second sub-lead 500. The second sub-lead 500 is exposed from the first resin end face 805. The first resin end face 805 is flush with the second sub-lead end face 581. In the present embodiment, the second sub total thickness portion 530 is exposed from the first resin end surface 805.

  The second resin end face 806 faces in a direction opposite to the direction in which the first resin end face 805 faces. The second resin end surface 806 is flat. The main lead 300 is exposed from the second resin end surface 806. In the present embodiment, the main rear connection portion 352 is exposed from the second resin end surface 806. The second resin end surface 806 is flush with the end surface of the main rear connection portion 352.

  The reason why the surface of the resin and the surface of the lead (the main lead 300, the first sub-lead 400, or the second sub-lead 500) are flush is that the lead frame and the This is because the resin member to be the resin package is diced collectively. FIG. 11 is a sectional view of one step in the method for manufacturing the semiconductor device shown in FIG. FIG. 7 shows the vicinity of the first sub lead 400. In this embodiment, the lead and the resin member are diced along the line Ct1 in FIG.

  Next, the operation and effect of the present embodiment will be described.

  In the present embodiment, the semiconductor element 200 has a portion that does not overlap with the main lead 300 when viewed in the thickness direction z of the semiconductor element 200. According to such a configuration, the size of the main lead 300 can be relatively smaller than the size of the semiconductor element 200 when viewed in the thickness direction z. Thus, the size of the resin package 800 as viewed in the thickness direction z is determined not by the main lead 300 but by the semiconductor element 200. Thus, the size of the semiconductor device 101 in the thickness direction z can be reduced.

  In the present embodiment, the main lead 300 includes a main total thickness portion 330 and a main eave portion 340. According to such a configuration, the bonding area between the semiconductor element 200 and the main lead 300 can be increased. Thus, the semiconductor element 200 can be securely joined to the main lead 300.

Then, the second bonding portion 620 of the first wire 600 is bonded to the first surface electrode 211 via the first bump 630, and the second bonding portion 720 of the second wire 700 is bonded to the second surface electrode 212 via the second bump 730. With this configuration, the height in the thickness direction z of the first wire 600 and the second wire 700 can be reduced. This contributes to lowering the height z of the semiconductor device 101 in the thickness direction. Therefore, according to the present embodiment, the size of the semiconductor device 101 can be reduced.

  Since the first surface electrode 211 as a gate electrode is more separated from the first sub lead 400 and the second sub lead 500 than the second surface electrode 212 as a source electrode, the length of the first wire 600 is increased. Can be longer than the second wire 700. The first wire 600 having a longer length can easily increase the bonding strength particularly at the second bonding portion 620. Generally, first surface electrode 211 as a gate electrode is formed on a relatively smooth surface of semiconductor layer 231 via an insulating layer (not shown). It is difficult for such a first surface electrode 211 to relatively improve the bonding strength of wire bonding. On the other hand, the second surface electrode 212 as a source electrode is often connected to a metal portion filled in a plurality of trenches (vertical holes) formed in the semiconductor layer 231. With such a configuration, the second surface electrode 212 can relatively easily improve the bonding strength of wire bonding. Therefore, joining the first wire 600, whose joining strength is easy to increase, to the first surface electrode 211 as a gate electrode, which is relatively concerned with insufficient joining strength, is advantageous for avoiding problems such as wire peeling. .

  The main eave portion 340 has the main front portion 341, so that the bonding strength between the main lead 300 and the resin package 800 can be increased. In addition, it is possible to prevent the main lead back surface 320 and the first sub lead back surface 420 and the second sub lead back surface 520 from being unduly approached while the semiconductor element 200 is brought closer to the first sub lead 400 and the second sub lead 500. can do.

  The main eave portion 340 has the main side portion 342 and the main rear portion 343, so that the bonding strength between the main lead 300 and the resin package 800 can be increased. The configuration in which the main total thickness portion 330 is entirely surrounded by the main eave portion 340 is suitable for increasing the bonding strength between the main lead 300 and the resin package 800.

  The main side connection part 351 and the main rear connection part 352 appropriately hold the main lead 300 in the manufacturing process of the semiconductor device 101. The end surface in the y direction of the main side connecting portion 351 and the end surface in the x direction of the main rear connecting portion 352 are separated from the main lead back surface 320 although exposed from the resin package 800. For this reason, there is little possibility that the solder for surface-mounting the semiconductor device 101 erroneously spreads on the y-direction end surface of the main side connection portion 351 and the x-direction end surface of the main rear connection portion 352.

  By forming the main surface plating layer 311 on the main lead main surface 310, the bonding strength between the back electrode 220 of the semiconductor element 200 and the main lead main surface 310 can be increased. Since the main surface plating layer 311 overlaps all of the main eaves portions 340, the area that can be used as the main lead main surface 310 can be increased.

  Since the first sub-lead 400 has the first sub-eave portion 440, the bonding strength between the first sub-lead 400 and the resin package 800 can be increased. Since the first sub-eave portion 440 has the first sub-front portion 441, the distance between the first sub-lead back surface 420 and the main lead back surface 320 is unduly approached while increasing the bonding strength with the resin package 800. Can be avoided. This is because even when the entire semiconductor device 101 is downsized, the first sub lead back surface 420 and the main lead back surface 320 are bonded to the solder adhering to the first sub lead back surface 420 and to the main lead back surface 320. This means that it is possible to prevent the problem of conduction through the solder.

  Since the first sub-eave portion 440 has the first sub-inner portion 442, the bonding strength between the first sub-lead 400 and the resin package 800 can be increased. Since the first sub-eave portion 440 has the first sub-inner portion 442, the distance between the first sub-lead back surface 420 and the second sub-lead back surface 520 is improper while increasing the bonding strength with the resin package 800. Can be avoided. This is because even when the entire semiconductor device 101 is downsized, the first sub-lead back surface 420 and the second sub-lead back surface 520 are formed by solder adhering to the first sub-lead back surface 420 and the second sub-lead back surface. This means that it is possible to prevent a problem that conduction occurs via the solder adhering to the back surface 520.

  In the present embodiment, the first sub-lead 400 has a first sub-lead end surface 481 connected to the first sub-lead back surface 420. The first sub-lead end surface 481 is exposed from the resin package 800. Therefore, the first sub lead back surface 420 can be made wider. Thereby, the tape 901 (see FIG. 11) used for resin molding for forming the resin package 800 and the first sub-lead back surface 420 can be more firmly joined. Therefore, at the time of resin molding, it is possible to prevent the resin material from entering between the tape 901 and the back surface of the first auxiliary lead 420. Thereby, it is possible to prevent the occurrence of resin burrs on the back surface 420 of the first sub lead. Similarly, a similar effect can be obtained by exposing the first sub-lead side surface 482 from the resin package 800. Further, the effect on the first sub-lead 400 is also caused by the second sub-lead end surface 581 of the second sub-lead 500 being exposed from the resin package 800 and the second sub-lead side surface 582 being exposed. And the same effect as described above.

  By forming the first sub-surface plating layer 411 on the first sub-lead main surface 410, the bonding strength between the first wire 600 and the first sub-lead main surface 410 can be increased.

  Since the second sub-lead 500 has the second sub-eave portion 540, the bonding strength between the second sub-lead 500 and the resin package 800 can be increased. Since the second sub-eave portion 540 has the second sub-front portion 541, the distance between the second sub-lead back surface 520 and the main lead back surface 320 is unduly approached while increasing the bonding strength with the resin package 800. Can be avoided.

  Since the second sub-eave portion 540 has the second sub-inner portion 542, the bonding strength between the second sub-lead 500 and the resin package 800 can be increased. Since the second sub-eave portion 540 has the second sub-inner portion 542, the distance between the second sub-lead back surface 520 and the first sub-lead back surface 420 is incorrect while increasing the bonding strength with the resin package 800. Can be avoided. This is because even when the entire semiconductor device 101 is downsized, the first sub-lead back surface 420 and the second sub-lead back surface 520 are formed by solder adhering to the first sub-lead back surface 420 and the second sub-lead back surface. This means that it is possible to prevent a problem that conduction occurs via the solder adhering to the back surface 520.

  By forming the second sub-surface plating layer 511 on the second sub-lead main surface 510, the bonding strength between the second wire 700 and the second sub-lead main surface 510 can be increased.

  In bonding the semiconductor element 200 and the main lead main surface 310 of the main lead 300, the back electrode 220 made of a single metal layer is directly bonded to the main lead main surface 310, and vibration is applied during the bonding. Absent. With such a configuration, it is not necessary to set a margin area in consideration of vibration in a region of the main lead 300 located around the semiconductor element 200. This is advantageous for miniaturization of the semiconductor device 101.

  A second embodiment of the present invention will be described with reference to FIGS.

  FIG. 12 is a perspective view of a semiconductor device according to the second embodiment of the present invention. FIG. 13 is a plan view of the semiconductor device shown in FIG.

  The semiconductor device 102 shown in these figures differs from the semiconductor device 101 in the shape of the first sub lead 400 and the second sub lead 500. Since the configuration other than those described below is the same as that of the semiconductor device 101, the same reference numerals as in the first embodiment are assigned and the description is omitted.

  In the present embodiment, the first sub-lead 400 includes a first sub-extended portion 460 in addition to the first sub-total thickness portion 430 and the first sub-eave portion 440.

  In the present embodiment, the first sub full thickness portion 430 is not exposed from the resin package 800.

  The first sub-extending portion 460 extends from the first sub-all-thickness portion 430 in a direction perpendicular to the thickness direction z. The thickness of the first sub-extending portion 460 is, for example, half of the first sub-total thickness portion 430, and is about 0.05 mm. The first sub extension 460 constitutes the first sub lead back surface 420. On the other hand, the first sub extension 460 does not constitute the first sub lead main surface 410. The first sub-extending portion 460 is exposed from the resin package 800 toward the outside of the resin package 800 as viewed in the thickness direction z. Specifically, the first sub-extending portion 460 is exposed from the resin package 800 in the directions x and y from the resin package 800. Therefore, the first sub extension 460 forms the first sub lead end face 481 and the first sub lead side face 482.

  In the present embodiment, the first sub-extending portion 460 has a first sub-rear portion 461 and a first sub-side portion 462.

  The first sub rear portion 461 protrudes from the first sub full thickness portion 430 toward the side opposite to the side where the main lead 300 is located. The first sub-rear part 461 forms a first sub-lead end face 481. The first sub side portion 462 protrudes from the first sub full thickness portion 430 toward the side opposite to the side where the second sub lead 500 is located. The first sub side portion 462 constitutes a first sub lead side surface 482.

  In the present embodiment, the second sub overall thickness portion 530 is not exposed from the resin package 800.

  The second sub-extending portion 560 extends from the second sub-all-thickness portion 530 in a direction perpendicular to the thickness direction z. The thickness of the second sub-extending portion 560 is, for example, half of the second sub-all-thickness portion 530, and is about 0.05 mm. The second sub extension 560 forms a second sub lead back surface 520. On the other hand, the second sub extension 560 does not constitute the second sub lead main surface 510. The second sub-extending portion 560 is exposed from the resin package 800 toward the outside of the resin package 800 in the thickness direction z. Specifically, the second sub-extending portion 560 is exposed from the resin package 800 in the directions x and y from the resin package 800. Therefore, the second sub-extending portion 560 forms a second sub-lead end surface 581 and a second sub-lead side surface 582.

  In the present embodiment, the second sub extension 560 has a second sub rear portion 561 and a second sub side portion 562.

  The second sub rear portion 561 protrudes from the second sub full thickness portion 530 toward the side opposite to the side where the main lead 300 is located. The second sub-rear part 561 forms a second sub-lead end face 581. The second sub side portion 562 protrudes from the second sub full thickness portion 530 toward the side opposite to the side where the first sub lead 400 is located. The second sub-side portion 562 forms a second sub-lead side surface 582.

  When manufacturing the semiconductor device 102, the leads and the resin member are diced along the line Ct2 in FIG. 11 used for the description of the semiconductor device 101.

  Next, the operation and effect of the present embodiment will be described.

  According to the present embodiment, in addition to the same functions and effects as described for the semiconductor device 101, the following functions and effects are achieved.

  According to the present embodiment, when cutting the first sub-lead 400 of the lead frame, it is not necessary to dice the first sub-all-thickness portion 430, and it is sufficient to dice a relatively thin portion. The occurrence of burrs is proportional to the thickness of the lead frame to be cut. Therefore, it is possible to suppress the occurrence of metal burrs that can be formed by cutting a portion of the lead frame that is to become the first sub lead 400. Similarly, it is possible to suppress the occurrence of metal burrs that can be formed by cutting a portion of the lead frame that will become the second sub-lead 500.

  Actually, when the main lead 300, the first sub-lead 400, and the second sub-lead 500 are patterned by etching, the boundary between the main total thickness portion 330 and the main eave portion 340 is determined as shown in FIGS. Are not formed and may be curved. Similarly, in the first sub-lead 400, the boundary between the first sub full thickness portion 430 and the first sub eave portion 440, the boundary between the first sub eave portion 440 and the first sub extension portion 460, the second sub lead 500 , The boundary between the second sub-eave portion 540 and the second sub-eave portion 540, the boundary between the second sub-eave portion 540 and the second sub-extend portion 560, and the like can also be curved surfaces. This is because even if the semiconductor devices 101 and 102 have the above-mentioned very small configuration, the above-mentioned curved surface is inevitably formed in the etching process even if the semiconductor devices 101 and 102 have the above-mentioned very small configuration, even though the design shown in FIGS. This is because it may occur.

  FIG. 15 shows a modification of the semiconductor device. As shown in the figure, the positions of the first surface electrode 211 serving as a gate electrode, the second surface electrode 212 serving as a source electrode, the second bonding portions 620 and 720, the first bump 630, and the second bump 730 are determined. 2 is different from the semiconductor device shown in FIG. The description of the semiconductor device shown in FIG. 15 other than those positions is the same as the description of the semiconductor device 101, and thus the description other than the positions is omitted. In FIG. 2, the first surface electrode 211 as the gate electrode is located on the left side of the semiconductor element 200, and the second surface electrode 212 as the source electrode is located on the right side of the semiconductor element 200. In addition, the second bonding portion 620 and the first bump 630 were located on the left side of the second bonding portion 720 and the second bump 730. On the other hand, in FIG. 15, the first surface electrode 211 serving as a gate electrode is located on the right side of the semiconductor element 200, and the second surface electrode 212 serving as a source electrode is located on the left side of the semiconductor element 200. The second bonding portion 620 and the first bump 630 are located on the right side of the second bonding portion 720 and the second bump 730. As described above, the positions of the first surface electrode 211 serving as the gate electrode and the second surface electrode 212 serving as the source electrode can be freely changed in plan view.

  The present invention is not limited to the embodiments described above. The specific configuration of each part of the present invention can be freely changed in various ways. The semiconductor element is not limited to a transistor, and may be, for example, a diode.

  16 to 24 show an example of the semiconductor device according to the third embodiment of the present invention.

  The semiconductor device 101 of this embodiment includes a semiconductor element 200, a main lead 300, a first sub lead 400, a second sub lead 500, a first wire 600, a second wire 700, and a resin package 800. The semiconductor device 101 is configured as a so-called surface-mountable relatively small semiconductor device. For example, the size in the x direction is about 0.8 mm, the dimension in the y direction is about 0.6 mm, and the size in the z direction. The direction dimension is about 0.36 mm. The z direction is the thickness direction of the semiconductor element, the main lead, the first sub lead, and the second sub lead according to the present invention. FIG. 16 is a perspective view of the semiconductor device 101 as viewed from above in the z direction. FIG. 17 is a perspective view of the semiconductor device 101 as viewed from below in the z direction. FIG. 18 is a plan view of the semiconductor device 101. FIG. FIG. 19 is a cross-sectional view in the zx plane along the line XIX-XIX in FIG. FIG. 20 is a cross-sectional view in the zx plane along the line XX-XX in FIG. FIG. 21 is an enlarged cross-sectional view of a main part in a zx plane crossing the semiconductor element 200. FIG. 22 is a cross-sectional view in the yz plane along the line XXII-XXII in FIG. FIG. 23 is a cross-sectional view in the yz plane along the line XXIII-XXIII in FIG. FIG. 24 is a cross-sectional view in the yz plane along the line XXIV-XXIV in FIG.

  In the present embodiment, the semiconductor element 200 is configured as a so-called transistor. The semiconductor element 200 has a front surface 201 and a back surface 202, and a first front electrode 211, a second front electrode 212, and a back electrode 220 are formed. The front surface 201 and the back surface 202 face in opposite directions in the z direction. To give an example of the size of the semiconductor element 200, the dimension in the x direction is about 300 μm, and the dimension in the y direction is about 300 μm.

  As shown in FIG. 25, the first surface electrode 211 and the second surface electrode 212 are formed on the surface 201, and are configured by a part of the electrode layer 213 made of, for example, an Au plating layer. In the present embodiment, the first surface electrode 211 is a gate electrode, and the second surface electrode 212 is a source electrode. In the present embodiment, in FIGS. 18 and 25, the first surface electrode 211 is located on the left side in the x direction, and the second surface electrode 212 is located on the right side in the x direction. Further, the first surface electrode 211 is located on the lower side in the y-direction diagram, and the second surface electrode 212 is located on the upper side in the y-direction diagram. The back surface electrode 220 is formed on the back surface 202. In the present embodiment, the back electrode 220 is a drain electrode.

  By removing a part of the electrode layer 231, a removed region 214 is formed. The removal region 214 has a shape surrounding the first surface electrode 211. More specifically, the removal region 214 has a portion extending in parallel with each other along the four sides of the semiconductor element 200 and a portion located across a relatively large area to surround the first surface electrode 211. I have. The first surface electrode 211 and the second surface electrode 212 are insulated from each other by the annular removal region 214.

  The area around the second surface electrode 212 is an active area 216. In the active region 216, a MOSFET 217 is formed at a position inside the surface 201 in the z direction. The MOSFET 217 includes a plurality of unit cells 218 arranged in a matrix. Note that the arrangement form of the plurality of unit cells 218 is not limited to a matrix shape, and may be, for example, a stripe shape or a staggered shape.

  In the present embodiment, one second surface electrode 212 is provided as a source electrode. However, the present invention is not limited to this, and a plurality of second surface electrodes 212 may be provided.

  FIG. 21 shows the vicinity of the back electrode 220 of the semiconductor element 200. The semiconductor device 200 of the present embodiment has a semiconductor layer 231 and a eutectic layer 232. The semiconductor layer 231 is a layer in which each part functioning as a transistor is formed, and is made of, for example, Si. The eutectic layer 232 is made of a eutectic of a semiconductor and a metal constituting the semiconductor layer 231. In the present embodiment, the eutectic layer 232 is made of a eutectic of Si as a semiconductor and Au as a metal. The eutectic layer 232 is formed by laminating Au layers on the semiconductor layer 231 and then performing an alloying process by heating them. A back electrode 220 is stacked below the eutectic layer 232 in the z direction. The back electrode 220 is formed by forming an Au layer on the eutectic layer 232 by vapor deposition, for example, and is an example of a single metal layer according to the present invention. Eutectic layer 232 has a thickness of, for example, about 1200 nm. The back electrode 220 as a single metal layer has a thickness of, for example, about 600 nm and is thinner than the eutectic layer 232. In the present embodiment, the surface of the eutectic layer 232 that faces downward in the z direction is defined as the back surface 202 of the semiconductor element 200.

  The main lead 300 has a die pad portion 310, a main back surface terminal portion 320, a main total thickness portion 330, and a main eave portion 340. The main lead 300 is formed by performing patterning such as etching on a metal plate made of Cu, for example.

  The die pad portion 310 faces upward in the z direction, and is a portion where the semiconductor element 200 is mounted. In the present embodiment, the die pad 310 has a rectangular shape having a dimension in the x direction of about 0.4 mm and a dimension in the y direction of about 0.5 mm. In the present embodiment, the main surface plating layer 311 is formed on the die pad 310. The main surface plating layer 311 is formed over the entire area of the die pad portion 310. Main surface plating layer 311 is made of, for example, Ag having a thickness of about 2 μm. In FIG. 16, for convenience of understanding, the main surface plating layer 311 is subjected to halftone.

  The main back surface terminal portion 320 faces downward in the z direction on the opposite side to the die pad portion 310, and is used for surface mounting the semiconductor device 101. The main back surface terminal portion 320 has a rectangular shape having a dimension in the x direction of about 0.18 mm and a dimension in the y direction of about 0.48 mm. The main back surface terminal portion 320 entirely overlaps the die pad portion 310 when viewed in the z direction, and is included in the die pad portion 310. In the present embodiment, the main lead 300 is provided with a main back surface plating layer 321. The main backside plating layer 321 is laminated on a portion of the main lead 300 for forming the main backside terminal portion 320, and is made of, for example, Ni, Sn, or an alloy thereof having a thickness of about 0.06 mm. In this embodiment, for the sake of convenience, the lower surface in the z direction of the main back surface plating layer 321 is defined as the main back surface terminal portion 320. For example, in a configuration without the main back surface plating layer 321, the main back surface portion is formed by the above-described Cu portion. The terminal section 320 may be configured.

  The main total thickness portion 330 is a portion extending from the die pad portion 310 to the main back surface terminal portion 320 in the z direction. In the present embodiment, the main total thickness portion 330 refers to a portion made of Cu excluding the main back surface plating layer 321 and has a thickness of about 0.1 mm. The main total thickness portion 330 has a dimension in the x direction of about 0.18 mm and a dimension in the y direction of about 0.48 mm, similarly to the main back surface terminal portion 320.

  The main eave portion 340 protrudes from the portion of the main total thickness portion 330 on the die pad portion 310 side in the x direction and the y direction perpendicular to the z direction. The main eave portion 340 has the upper end surface in the z direction flush with the main full thickness portion 330. In the present embodiment, the main eave portion 340 has a main front portion 341, a main side portion 342, and a main rear portion 343. The thickness of the main eave portion 340 is, for example, half of the total main thickness portion 330 and is about 0.05 mm.

  The main front part 341 protrudes from the main total thickness part 330 toward the first sub lead 400 and the second sub lead 500 in the x direction. In the present embodiment, the main front portion 341 has a rectangular shape having a dimension in the x direction of about 0.21 mm and a dimension in the y direction of about 0.5 mm.

  The main side portion 342 protrudes from the main entire thickness portion 330 in the y direction. In the present embodiment, two main side portions 342 are formed. The main side portion 342 has a dimension in the x direction of about 0.18 mm and a dimension in the y direction of about 0.01 mm. In the present embodiment, the main lead 300 has two main side connecting portions 351. The main side connecting portion 351 extends from the main side portion 342 of the main eave portion 340 and has the same thickness as the main side portion 342. An end surface in the y direction of the main side connection portion 351 is exposed from the resin package 800. The main side connecting portion 351 has a dimension in the x direction of about 0.1 mm and a dimension in the y direction of about 0.04 mm.

  The main rear portion 343 protrudes from the main full thickness portion 330 to the side opposite to the main front portion 341. The main rear portion 343 has a dimension in the x direction of about 0.01 mm and a dimension in the y direction of about 0.5 mm. In the present embodiment, the main lead 300 has two main rear connecting portions 352. The main rear connecting portion 352 extends from the main rear portion 343 of the main eave portion 340, and has the same thickness as the main rear portion 343. The x-direction end face of the main rear connection portion 352 is exposed from the resin package 800. The main rear connection portion 352 has a dimension in the x direction of about 0.04 mm and a dimension in the y direction of about 0.1 mm.

  With the above-described configuration, in the present embodiment, the entire main total thickness portion 330 is surrounded by the main eave portion 340 in the z direction. Also, the upper surface in the z direction of the main total thickness portion 330 and the main eave portion 340 is the die pad portion 310, and the main surface plating layer 311 overlaps all of the main full thickness portion 330 and the main eave portion 340. As shown in FIG. 18, in the semiconductor element 200, about half of the semiconductor element 200 overlaps the main full thickness part 330 in the z direction, and the other half overlaps the main front part 341 of the main eave part 340. I have. The first surface electrode 211 as a gate electrode overlaps with the main entire thickness portion 330, and the second surface electrode 212 as a source electrode overlaps with the main front portion 341 of the main eave portion 340.

  As shown in FIG. 21, in the semiconductor element 200, the back surface electrode 220 is bonded to the die pad portion 310 (main surface plating layer 311). Specifically, back electrode 220 as a single metal layer is directly bonded to die pad portion 310 (main surface plating layer 311) by, for example, a thermocompression bonding method. In this thermocompression bonding, no vibration is applied, and only heat and pressure are applied.

  The first sub lead 400 is spaced apart from the main lead 300 in the x direction, and includes a first wire bonding portion 410, a first sub back surface terminal portion 420, a first sub full thickness portion 430, and a first sub lead portion 430. It has an eave portion 440. The first sub lead 400 is formed by performing patterning such as etching on a metal plate made of, for example, Cu.

  The first wire bonding portion 410 faces upward in the z direction, and is a portion to which the first wire 600 is bonded. In the present embodiment, the first wire bonding portion 410 has a rectangular shape having a dimension in the x direction of about 0.2 mm and a dimension in the y direction of about 0.2 mm. Further, in the present embodiment, the first sub surface plating layer 411 is formed on the first wire bonding portion 410. The first sub surface plating layer 411 is formed over the entire area of the first wire bonding section 410. The first sub surface plating layer 411 is made of, for example, Ag having a thickness of about 2 μm. In FIG. 16, the halftone is applied to the first sub surface plating layer 411 for convenience of understanding.

  The first sub-back surface terminal portion 420 faces downward in the z direction on the opposite side to the first wire bonding portion 410 and is used for surface mounting the semiconductor device 101. The first sub-backside terminal 420 has a rectangular shape with a dimension in the x direction of about 0.18 mm and a dimension in the y direction of about 0.13 mm. The first sub-backside terminal portion 420 entirely overlaps the first wire bonding portion 410 when viewed in the z direction, and is included in the first wire bonding portion 410. In the present embodiment, the first sub lead 400 has a first sub backside plating layer 421 formed thereon. The first sub-backside plating layer 421 is laminated on a portion of the first sub-lead 400 for forming the first sub-backside terminal portion 420, and is, for example, Ni or Sn having a thickness of about 0.06 mm or any of these. Made of alloy. In the present embodiment, for the sake of convenience, the lower surface in the z direction of the first sub-backside plating layer 421 is defined as the first sub-backside terminal portion 420. For example, in a configuration having no first sub-backside plating layer 421, the above-described Cu The first sub-back surface terminal section 420 may be constituted by a portion made of.

  The first sub total thickness portion 430 is a portion extending from the first wire bonding portion 410 to the first sub back surface terminal portion 420 in the z direction. In the present embodiment, the first sub total thickness portion 430 refers to a portion made of Cu excluding the first sub back plating layer 421, and has a thickness of about 0.1 mm. The first sub-thickness portion 430 has a dimension in the x-direction of about 0.18 mm and a dimension in the y-direction of about 0.13 mm, similarly to the first sub-backside terminal section 420.

  The first sub-eave portion 440 protrudes from the portion of the first sub total thickness portion 430 on the first wire bonding portion 410 side in the x direction and the y direction perpendicular to the z direction. The first sub-eave portion 440 has the upper end surface in the z direction flush with the first sub-full thickness portion 430. In the present embodiment, the first sub-eave portion 440 has a first sub-front portion 441, a first sub-side portion 442, and a first sub-rear portion 443. The thickness of the first sub-eave portion 440 is, for example, half of the first sub-total thickness portion 430, and is about 0.05 mm.

  The first sub front part 441 protrudes from the first sub full thickness part 430 toward the main lead 300 in the x direction. In the present embodiment, the first sub front part 441 has a dimension in the x direction of about 0.01 mm and a dimension in the y direction of about 0.2 mm.

  The first sub side portion 442 projects from the first sub full thickness portion 430 in the y direction. In the present embodiment, two first sub side portions 442 are formed. In FIG. 18, the first sub-side portion 442 located in the upper part of the y-direction diagram projects toward the second sub-lead 500, and has a dimension in the x direction of about 0.2 mm and a dimension in the y direction of about 0.06 mm. is there. The first sub-side portion 442 located below in the y-direction diagram has a dimension in the y-direction x direction of about 0.2 mm and a dimension in the y-direction of about 0.01 mm. In the present embodiment, the first sub-lead 400 has the first sub-side connecting portion 451. The first sub-side connecting portion 451 extends downward from the first sub-side portion 442 of the first sub-eave portion 440 in the y direction in FIG. 18 and has the same thickness as the first sub-side portion 442. ing. The end surface in the y direction of the first sub side coupling portion 451 is exposed from the resin package 800. The first sub-side connecting portion 451 has a dimension in the x direction of about 0.1 mm and a dimension in the y direction of about 0.04 mm.

  The first sub rear portion 443 protrudes from the first sub full thickness portion 430 to the side opposite to the first sub front portion 441. The first sub-rear portion 443 has a dimension in the x direction of about 0.01 mm and a dimension in the y direction of about 0.14 mm. In the present embodiment, the first sub lead 400 has a first sub rear connecting portion 452. The first sub-rear connecting portion 452 extends from the first sub-rear portion 443 of the first sub-eave portion 440, and has the same thickness as the first sub-rear portion 443. The x-direction end face of the first sub-rear connecting portion 452 is exposed from the resin package 800. The first sub rear connecting portion 452 has a dimension in the x direction of about 0.04 mm and a dimension in the y direction of about 0.1 mm.

  With the above-described configuration, in the present embodiment, the entire first sub-thick portion 430 is surrounded by the first sub-eave portion 440 in the z direction. Further, the upper surface in the z direction of the first sub total thickness portion 430 and the first sub eave portion 440 is a first wire bonding portion 410, and the first sub surface plating layer 411 is formed by the first sub total thickness portion 430 and It overlaps all of the first sub-eave portions 440.

  The second sub-lead 500 is spaced apart from the main lead 300 in the x-direction at a position aligned with the first sub-lead 400 in the y-direction, and includes a second wire bonding portion 510 and a second sub-back surface terminal portion. 520, a second sub total thickness portion 530 and a second sub eave portion 540. The second sub-lead 500 is formed by performing patterning such as etching on a metal plate made of, for example, Cu.

  The second wire bonding portion 510 faces upward in the z direction, and is a portion where the second wire 700 is bonded. In the present embodiment, the second wire bonding section 510 has a rectangular shape having a dimension in the x direction of about 0.2 mm and a dimension in the y direction of about 0.2 mm. In the present embodiment, the second sub surface plating layer 511 is formed in the second wire bonding portion 510. The second sub surface plating layer 511 is formed over the entire area of the second wire bonding portion 510. The second sub surface plating layer 511 is made of, for example, Ag having a thickness of about 2 μm. In FIG. 16, the halftone is applied to the second sub surface plating layer 511 for convenience of understanding.

  The second sub back surface terminal portion 520 faces downward in the z direction on the opposite side to the second wire bonding portion 510, and is used for surface mounting the semiconductor device 101. The second sub-back surface terminal portion 520 has a rectangular shape having a dimension in the x direction of about 0.18 mm and a dimension in the y direction of about 0.13 mm. The second sub-back surface terminal portion 520 entirely overlaps the second wire bonding portion 510 when viewed in the z direction, and is included in the second wire bonding portion 510. In the present embodiment, the second sub lead 500 is provided with a second sub back plating layer 521. The second sub-rear surface plating layer 521 is laminated on a portion of the second sub-lead 500 for forming the second sub-rear surface terminal portion 520, and for example, Ni or Sn having a thickness of about 0.06 mm, or Ni or Sn thereof. Made of alloy. In the present embodiment, for the sake of convenience, the lower surface in the z-direction of the second sub-backside plating layer 521 is defined as the second sub-backside terminal portion 520. For example, in a configuration having no second sub-backside plating layer 521, the above-described Cu The second sub-back surface terminal portion 520 may be constituted by the portion made of.

  The second sub total thickness portion 530 is a portion extending from the second wire bonding portion 510 to the second sub back surface terminal portion 520 in the z direction. In the present embodiment, the second sub total thickness portion 530 refers to a portion made of Cu excluding the second sub back plating layer 521, and has a thickness of about 0.1 mm. The second sub-all-thickness portion 530 has a dimension in the x-direction of about 0.18 mm and a dimension in the y-direction of about 0.13 mm, like the second sub-backside terminal 520.

  The second sub eaves portion 540 protrudes from the portion of the second sub full thickness portion 530 on the side of the second wire bonding portion 510 in the x direction and the y direction perpendicular to the z direction. The second sub-eave portion 540 has the upper end surface in the z direction flush with the second sub-full thickness portion 530. In the present embodiment, the second sub-eave portion 540 has a second sub-front portion 541, a second sub-side portion 542, and a second sub-rear portion 543. The thickness of the second sub-eave portion 540 is, for example, half of the second sub-total thickness portion 530, and is about 0.05 mm.

  The second sub front portion 541 protrudes from the second sub full thickness portion 530 toward the main lead 300 in the x direction. In the present embodiment, the second sub front portion 541 has a dimension in the x direction of about 0.01 mm and a dimension in the y direction of about 0.2 mm.

  The second sub side portion 542 projects from the second sub full thickness portion 530 in the y direction. In the present embodiment, two second sub side portions 542 are formed. In FIG. 18, the second sub-side portion 542 located in the lower part of the drawing in the y direction projects toward the first sub lead 400 and has a dimension in the x direction of about 0.2 mm and a dimension in the y direction of about 0.06 mm. is there. The second sub lateral portion 542 located in the upper part in the y direction has a dimension in the x direction of about 0.2 mm and a dimension in the y direction of about 0.01 mm. In the present embodiment, the second sub-lead 500 has a second sub-side connecting portion 551. The second sub-side connection portion 551 extends upward from the second sub-side portion 542 of the second sub-eave portion 540 in the y direction in FIG. 18 and has the same thickness as the second sub-side portion 542. ing. The end surface in the y direction of the second sub side coupling portion 551 is exposed from the resin package 800. The second sub-side connecting portion 551 has a dimension in the x direction of about 0.1 mm and a dimension in the y direction of about 0.04 mm.

  The second sub rear portion 543 protrudes from the second sub full thickness portion 530 to the side opposite to the second sub front portion 541. The second sub-rear part 543 has a dimension in the x direction of about 0.01 mm and a dimension in the y direction of about 0.14 mm. In the present embodiment, the second sub-lead 500 has a second sub-rear connecting portion 552. The second sub-rear connecting portion 552 extends from the second sub-rear portion 543 of the second sub-eave portion 540, and has the same thickness as the second sub-rear portion 543. An end surface in the x direction of the second sub-rear connecting portion 552 is exposed from the resin package 800. The second sub-rear connecting portion 552 has a dimension in the x direction of about 0.04 mm and a dimension in the y direction of about 0.1 mm.

  With the above-described configuration, in the present embodiment, the entire second sub-thick portion 530 is surrounded by the second sub-eave portion 540 in the z direction. Further, the upper surface in the z direction of the second sub full thickness portion 530 and the second sub eave portion 540 is a second wire bonding portion 510, and the second sub surface plating layer 511 includes the second sub full thickness portion 530 and The second sub-eave portion 540 is entirely overlapped.

  The first wire 600 is joined to the first surface electrode 211 of the semiconductor element 200 and the first wire bonding portion 410 of the first sub lead 400, and has a first bonding portion 610 and a second bonding portion 620. The first wire 600 is made of Au having a diameter of about 20 μm.

  The first bonding portion 610 is bonded to the first wire bonding portion 410 of the first sub lead 400 and has a crown-shaped mass. The second bonding portion 620 is bonded to the first surface electrode 211 of the semiconductor device 200 via the first bump 630. The second bonding portion 620 has a tapered shape in which the thickness in the z direction decreases toward the tip. The first bump 630 is a portion similar to the above-described lump portion of the first bonding portion 610. In the present embodiment, the volume of the first bump 630 is slightly smaller than the volume of the lump portion of the first bonding portion 610.

  The second wire 700 is joined to the second surface electrode 212 of the semiconductor element 200 and the second wire bonding portion 510 of the second sub lead 500, and has a first bonding portion 710 and a second bonding portion 720. The second wire 700 is made of Au having a diameter of about 20 μm.

  The first bonding portion 710 is bonded to the second wire bonding portion 510 of the second sub lead 500 and has a crown-shaped mass. The second bonding portion 720 is bonded to the second surface electrode 212 of the semiconductor device 200 via the second bump 730. The second bonding portion 720 has a tapered shape in which the thickness in the z direction becomes smaller toward the tip. The second bump 730 is a part similar to the above-mentioned lump part of the first bonding part 710. In the present embodiment, the volume of the second bump 730 is slightly smaller than the volume of the lump portion of the first bonding portion 710.

  The resin package 800 covers the semiconductor element 200 and a part of each of the main lead 300, the first sub lead 400, and the second sub lead 500, and is made of, for example, a black epoxy resin. In the resin package 800, the main back surface terminal portion 320 of the main lead 300, the first sub back surface terminal portion 420 of the first sub lead 400, and the second sub back surface terminal portion 520 of the second sub lead 500 are all connected in the z direction. It is exposed to the lower side. In the present embodiment, the distance between the upper end of the first wire 600 and the second wire 700 in the z direction and the upper end of the resin package 800 in the z direction is about 50 μm.

  Next, an example of a method for manufacturing the semiconductor device 101 will be described below with reference to FIGS.

  26 to 32, the process of bonding the first wire 600 will be mainly described, but the second wire 700 is also bonded by the same process. First, as shown in FIG. 26, the semiconductor element 200 is joined to the main lead 300. At this time, if a lead frame in which a plurality of main leads 300, first sub-leads 400, and second sub-leads 500 are connected is used, manufacturing efficiency can be improved. The capillary Cp is prepared, and the wire 601 is exposed from the tip. The wire 601 is made of Au having a diameter of about 20 μm. Then, a ball is formed on the tip of the wire 601 by generating a spark just above the first surface electrode 211 of the semiconductor element 200.

  Next, as shown in FIG. 27, the ball 602 is joined to the first surface electrode 211 of the semiconductor element 200 by lowering the capillary Cp. Then, the capillary Cp is raised with the wire 601 fixed to the capillary Cp. Thereby, as shown in FIG. 28, the first bump 630 is formed on the first surface electrode 211.

  Next, as shown in FIG. 29, a spark is generated just above the first wire bonding portion 410 of the first sub lead 400, so that the ball 602 is formed again at the tip of the wire 601. Next, as shown in FIG. 30, the ball 602 is joined to the first wire bonding portion 410 of the first sub lead 400 by lowering the capillary Cp.

  Next, while the wire 601 is not fixed to the capillary Cp, the capillary Cp is moved as shown in FIG. Thereby, first, the first bonding portion 610 is formed. In addition, the tip of the capillary Cp is pressed against the first bump 630. At this time, the wire 601 is sandwiched between the capillary Cp and the first bump 630. Further, for example, heat and vibration may be applied through a support (not shown) that holds the main lead 300. Then, the capillary Cp is separated from the semiconductor element 200 with the wire 601 fixed to the capillary Cp. Thereby, a second bonding portion 620 is formed. FIG. 32 is an enlarged image of the second bonding portion 620 and the first bump 630 taken from above in the z direction. As is clearly shown in the figure, a second bonding portion 620 having a slightly widened shape is joined to the first bump 630 having a circular shape in plan view.

  Thereafter, the bonding step of the second wire 700 is performed together with the bonding step of the first wire 600. Also, for example, a black epoxy resin is used to cover the semiconductor element 200, the main lead 300, a part of the first sub lead 400, and a part of the second sub lead 500, and the first wire 600 and the second wire 700. To form a plate-like resin member. FIG. 33 shows the above-described lead frame, semiconductor element 200, first wire 600, and second wire 700, which are covered with the resin member (not shown). Then, the semiconductor device 101 shown in FIGS. 16 to 24 is obtained by cutting the resin member and the lead frame together along the cutting line CL in the drawing.

  Next, the operation of the semiconductor device 101 will be described.

  According to the present embodiment, the die pad portion 310 and the semiconductor element 200 overlap with both the main full thickness portion 330 and the main eave portion 340 in the z direction. Main eave portion 340 exhibits a function of increasing the bonding strength between main lead 300 and resin package 800. The main lead 300 can be prevented from excessively protruding from the semiconductor element 200 while improving the bonding strength. This contributes to reducing the dimension of the semiconductor device 101 as viewed in the z direction. Further, the fact that at least one of the first surface electrode 211 and the second surface electrode 212 overlaps the main eave portion 340 is advantageous in reducing the dimension of the semiconductor device 101 as viewed in the z direction. Then, the second bonding portion 620 of the first wire 600 is bonded to the first surface electrode 211 via the first bump 630, and the second bonding portion 720 of the second wire 700 is bonded to the second surface electrode 212 via the second bump 730. With this configuration, the height of the first wire 600 and the second wire 700 in the z direction can be reduced. This contributes to reducing the height of the semiconductor device 101 in the z direction. Therefore, according to the present embodiment, the size of the semiconductor device 101 can be reduced.

  Since the first surface electrode 211 serving as the gate electrode is more distant from the first sub lead 400 and the second sub lead 500 than the second surface electrode 212 serving as the source electrode, the length of the first wire 600 is increased. Can be made longer than the second wire 700. The first wire 600 having a longer length can easily increase the bonding strength particularly at the second bonding portion 620. Generally, first surface electrode 211 as a gate electrode is formed on a relatively smooth surface of semiconductor layer 231 via an insulating layer (not shown). Such a first surface electrode 211 is unlikely to relatively improve the bonding strength of wire bonding. On the other hand, the second surface electrode 212 as a source electrode is often connected to a metal portion filled in a plurality of trenches (vertical holes) formed in the semiconductor layer 231. With such a configuration, the second surface electrode 212 can relatively easily improve the bonding strength of wire bonding. Therefore, joining the first wire 600, which easily increases the joining strength, to the first surface electrode 211 as the gate electrode, which is relatively concerned with the lack of joining strength, is advantageous for avoiding problems such as wire peeling. .

  Since first surface electrode 211 overlaps main full thickness portion 330 when viewed in the z direction, as shown in FIGS. 27 and 31, first surface electrode 211 as a gate electrode for which there is a concern that bonding strength is relatively insufficient, is shown. , The capillary Cp can be pressed more reliably. On the other hand, by arranging the second surface electrode 212 as a source electrode, which is relatively easy to improve the bonding strength, at a position overlapping the main eave portion 340 in the z direction, the dimension of the semiconductor device 101 in the z direction is reduced. be able to.

  The main eave portion 340 has the main front portion 341 so that the bonding strength between the main lead 300 and the resin package 800 can be increased. In addition, the main back surface terminal portion 320, the first sub back surface terminal portion 420, and the second sub back surface terminal portion 520 are improperly approached while the semiconductor element 200 is brought closer to the first sub lead 400 and the second sub lead 500. That can be avoided.

  The main eave portion 340 has the main side portion 342 and the main rear portion 343, so that the bonding strength between the main lead 300 and the resin package 800 can be increased. The configuration in which the main total thickness portion 330 is entirely surrounded by the main eave portion 340 is suitable for increasing the bonding strength between the main lead 300 and the resin package 800.

  The main side connection part 351 and the main rear connection part 352 appropriately hold the main lead 300 in the manufacturing process of the semiconductor device 101. The end surface in the y direction of the main side connection portion 351 and the end surface in the x direction of the main rear connection portion 352 are exposed from the resin package 800 but are separated from the main back surface terminal portion 320. For this reason, there is little possibility that the solder for surface-mounting the semiconductor device 101 erroneously spreads on the y-direction end surface of the main side connection portion 351 and the x-direction end surface of the main rear connection portion 352.

  Since the main surface plating layer 311 is formed on the die pad 310, the bonding strength between the back electrode 220 of the semiconductor element 200 and the die pad 310 can be increased. Since the main surface plating layer 311 overlaps with all the main eaves portions 340, the area that can be used as the die pad portion 310 can be increased.

  Since the first sub-lead 400 has the first sub-eave portion 440, the bonding strength between the first sub-lead 400 and the resin package 800 can be increased. Since the first sub-eave portion 440 has the first sub-front portion 441, the distance between the first sub-back terminal portion 420 and the main back terminal portion 320 is improper while increasing the bonding strength with the resin package 800. It is possible to avoid approaching.

  Since the first sub-eave portion 440 has the first sub-side portion 442 and the first sub-rear portion 443, the bonding strength between the first sub-lead 400 and the resin package 800 can be increased. The configuration in which the first sub total thickness portion 430 is entirely surrounded by the first sub eaves portion 440 is suitable for increasing the bonding strength between the first sub lead 400 and the resin package 800. Since the first sub-side portion 442 on the second sub-lead 500 side is relatively large, the bonding strength is improved, and the first sub-backside terminal portion 420 and the second sub-backside terminal portion 520 are improper. Can be avoided.

  The first sub side connection portion 451 and the first sub rear connection portion 452 appropriately hold the first sub lead 400 in the manufacturing process of the semiconductor device 101. The y-direction end surface of the first sub-side connection portion 451 and the x-direction end surface of the first sub-rear connection portion 452 are separated from the first sub-rear surface terminal portion 420 although exposed from the resin package 800. For this reason, there is little possibility that solder for surface mounting the semiconductor device 101 erroneously spreads on the y-direction end surface of the first sub-side connection portion 451 and the x-direction end surface of the first sub-rear connection portion 452.

  Since the first sub surface plating layer 411 is formed on the first wire bonding portion 410, the bonding strength between the first wire 600 and the first wire bonding portion 410 can be increased.

  Since the second sub-lead 500 has the second sub-eave portion 540, the bonding strength between the second sub-lead 500 and the resin package 800 can be increased. Since the second sub-eave portion 540 has the second sub-front portion 541, the distance between the second sub-back terminal portion 520 and the main back terminal portion 320 is improper while increasing the bonding strength with the resin package 800. It is possible to avoid approaching.

  Since the second sub-eave portion 540 has the second sub-side portion 542 and the second sub-rear portion 543, the bonding strength between the second sub-lead 500 and the resin package 800 can be increased. The configuration in which the entire second sub-thick portion 530 is surrounded by the second sub-eave portion 540 is suitable for increasing the bonding strength between the second sub-lead 500 and the resin package 800. Since the second sub side portion 542 on the first sub lead 400 side is relatively large, the joining strength is improved, and the second sub back surface terminal portion 520 and the first sub back surface terminal portion 420 are not improper. Can be avoided.

  The second sub-side connection portion 551 and the second sub-rear connection portion 552 appropriately hold the second sub-lead 500 in the manufacturing process of the semiconductor device 101. The y-direction end surface of the second sub-side connection portion 551 and the x-direction end surface of the second sub-rear connection portion 552 are separated from the second sub-rear surface terminal portion 520 although exposed from the resin package 800. For this reason, there is little possibility that the solder for surface mounting the semiconductor device 101 erroneously spreads on the y-direction end surface of the second sub-side connection portion 551 and the x-direction end surface of the second sub-rear connection portion 552.

  By forming the second sub surface plating layer 511 on the second wire bonding portion 510, the bonding strength between the second wire 700 and the second wire bonding portion 510 can be increased.

  In bonding the semiconductor element 200 and the die pad portion 310 of the main lead 300, the back electrode 220 made of a single metal layer is directly bonded to the die pad portion 310, and no vibration is applied during the bonding. With such a configuration, it is not necessary to set a margin area in consideration of vibration in a region of the main lead 300 located around the semiconductor element 200. This is advantageous for miniaturization of the semiconductor device 101.

  FIG. 34 is an X-ray image of the semiconductor device 101. 16, when the main lead 300, the first sub-lead 400, and the second sub-lead 500 are patterned by etching, the boundary between the main full thickness portion 330 and the main eaves portion 340 is as shown in FIG. The clear corners shown in FIG. 24 to FIG. 24 are not formed, but are curved. Similarly, the boundary between the first sub full thickness portion 440 and the first sub eave portion 440 in the first sub lead 400 or the second sub full thickness portion 540 and the second sub eave portion 540 in the second sub lead 500 is formed. The boundary is also a curved surface. This is because even if the semiconductor device 101 has the above-described very small configuration, the above-mentioned curved surface is inevitably generated in the etching process even if the semiconductor device 101 has the above-described design intended for the configurations shown in FIGS. .

  FIG. 35 shows a semiconductor device according to the fourth embodiment of the present invention. In the figure, the same or similar elements as those in the above embodiment are denoted by the same reference numerals as those in the above embodiment.

  In the present embodiment, the first surface electrode 211 overlaps both the main full thickness portion 330 and the main eaves portion 340 when viewed in the z direction. Then, the first bump 630 and the second bonding portion 620 of the first wire 600 overlap both the main full thickness portion 330 and the main eave portion 340 in the z direction. In the figure, a broken line extending in the y direction overlaps the first bump 630 and the second bonding portion 620 of the first wire 600. This dashed line is the boundary between the main total thickness portion 330 and the main eave portion 340 when viewed in the z direction. According to such an embodiment, the size of the semiconductor device 102 can be reduced.

  The semiconductor device according to the present invention is not limited to the above embodiment. The specific configuration of each part of the semiconductor device according to the present invention can be variously changed in design.

  The semiconductor element in the present invention is not limited to a transistor, and various semiconductor elements having a first surface electrode and a second surface electrode can be used.

101 semiconductor device 102 semiconductor device 200 semiconductor element 201 front surface 202 back surface 211 first surface electrode 212 second surface electrode 220 back surface electrode 231 semiconductor layer 232 eutectic layer 300 main lead 310 main lead main surface 311 main surface plating layer 320 main lead back surface 330 Main total thickness portion 340 Main eave portion 341 Main front portion 342 Main side portion 343 Main rear portion 351 Main side connection portion 352 Main rear connection portion 400 First sub lead 410 First sub lead main surface 411 First sub surface Plating layer 420 First sub lead back surface 430 First sub full thickness portion 440 First sub eave portion 441 First sub front portion 442 First sub inner portion 460 First sub extension portion 461 First sub rear portion 462 First Secondary side portion 481 First secondary lead end surface 482 First secondary lead side surface 500 Second secondary lead 510 Second secondary lead main surface 511 Second secondary surface plating Layer 520 Second sub lead back surface 530 Second sub full thickness portion 540 Second sub eave portion 541 Second sub front portion 542 Second sub inner portion 560 Second sub extension portion 561 Second sub rear portion 562 Second sub Side portion 581 Second sub-lead end surface 582 Second sub-lead side surface 600 First wire 610 First bonding portion 620 Second bonding portion 630 First bump 700 Second wire 710 First bonding portion 720 Second bonding portion 730 Second bump 800 Resin package 801 Resin main surface 802 Resin back surface 803 First resin side surface 804 Second resin side surface 805 First resin end surface 806 Second resin end surface 901 Tape Ct1 Line Ct2 Line x direction y direction z Thickness direction 101, 102 Semiconductor device 200 Semiconductor device 201 Front surface 202 Back surface 211 First surface electrode 212 Second surface electrode 213 Electrode layer 214 Removal area 216 Active area 217 MOSFET
218 Unit cell 220 Back electrode (metal single layer)
231 Semiconductor layer 232 Eutectic layer 300 Main lead 310 Die pad part 311 Main surface plating layer 320 Main back terminal part 321 Main back plating layer 330 Main full thickness part 340 Main eave part 341 Main front part 342 Main side part 343 Main rear part 351 Main side connection portion 352 Main rear connection portion 400 First sub lead 410 First wire bonding portion 411 First sub surface plating layer 420 First sub back surface terminal portion 421 First sub back surface plating layer 430 First sub full thickness portion 440 first sub-eave portion 441 first sub-front portion 442 first sub-side portion 443 first sub-rear portion 451 first sub-side connection portion 452 first sub-rear connection portion 500 second sub-lead 510 second wire bonding Portion 511 Second sub-surface plating layer 520 Second sub-back surface terminal portion 521 Second sub-back surface plating layer 530 Second sub-total thickness portion 540 Second sub-eave portion 541 Second Secondary front portion 542 Second secondary side portion 543 Second secondary rear portion 551 Second secondary side connection portion 552 Second secondary rear connection portion 600 First wire 610 First bonding portion 620 Second bonding portion 630 First bump 700 Second Wire 710 First bonding section 720 Second bonding section 730 Second bump 800 Resin package Cp Capillary 601 Wire 602 Ball

Claims (42)

A semiconductor element;
A main lead on which the semiconductor element is arranged;
A first sub-lead separated from the main lead and electrically connected to the semiconductor element;
A resin package that covers the semiconductor element, the main lead and the first sub lead, and has a rectangular shape when viewed in a thickness direction of the semiconductor element;
The resin package has a first surface having a normal direction parallel to the thickness direction and a second surface having a normal direction perpendicular to the thickness direction,
The main lead and the first sub lead are exposed from a first surface of the resin package;
The main lead has a main lead main surface and a main lead back surface facing each other,
The semiconductor element is disposed on the main lead main surface,
The back surface of the main lead is exposed from the first surface of the resin package,
The first sub-lead has a first sub-lead main surface and a first sub-lead rear surface facing each other, and the first sub-lead rear surface is exposed from the resin package.
The main lead back surface, the first sub lead back surface, and the first surface are flush with each other;
The main lead has a first portion exposed from the second surface of the resin package, and the first sub-lead has a second portion exposed from the second surface of the resin package. The thickness direction dimensions of the first part and the second part are different from each other,
In the direction in which the main lead and the first sub-lead are separated from each other, the first portion is located between one end and the other end of the back surface of the main lead ,
The semiconductor device , wherein a dimension of the second part in the thickness direction is larger than a dimension of the first part in the thickness direction . The semiconductor device according to claim 1, wherein the semiconductor element includes a portion that does not overlap with the main lead when viewed in the thickness direction. The main lead includes a main full thickness portion and a main eave portion,
The main total thickness portion is a portion extending from the main lead main surface to the main lead back surface,
3. The semiconductor device according to claim 1, wherein the main eave portion protrudes from the main entire thickness portion in a direction perpendicular to the thickness direction. 4. The semiconductor device according to claim 3 , wherein the whole of the main entire thickness portion overlaps with the semiconductor element as viewed in the thickness direction. 4. The semiconductor device according to claim 3 , wherein the main eave portion has a main front portion, and the main front portion projects from the main full thickness portion toward the first sub lead. 5. The main eave portion has a main side portion, and the main side portion projects from the main full thickness portion in a direction perpendicular to a direction in which the main front portion projects. 6. The semiconductor device according to 5 . The semiconductor device according to claim 6 , wherein the main lead includes a main side connecting portion protruding from the main side portion, and the main side connecting portion has an end face exposed from the resin package. 6. The semiconductor according to claim 5 , wherein the main eave portion has a main rear portion, and the main rear portion protrudes from the main full thickness portion in a direction opposite to a direction in which the main front portion protrudes. 7. apparatus. 9. The semiconductor device according to claim 8 , wherein the main lead includes a main rear connecting portion protruding from the main rear portion, and the main rear connecting portion has an end face exposed from the resin package. 10. 4. The semiconductor device according to claim 3 , wherein said main entire thickness portion is entirely surrounded by said main eave portion when viewed in said thickness direction. 5. 4. The semiconductor device according to claim 3 , wherein the main eave portion entirely overlaps the semiconductor element when viewed in the thickness direction. 5. 4. The semiconductor device according to claim 3 , further comprising a main surface plating layer formed on said main lead and interposed between said semiconductor element and said main lead. The semiconductor device according to claim 12 , wherein the main surface plating layer overlaps the entire main eave portion. The first sub lead includes a first sub full thickness portion and a first sub eave portion,
The first sub total thickness portion is a portion extending from the first sub lead main surface to the first sub lead rear surface,
The first sub-eave portion projects from the first sub-all-thickness portion in a direction perpendicular to the thickness direction of the semiconductor element, and constitutes the first sub-lead main surface. The semiconductor device according to claim 1. The first sub-eave portion has a first sub-front portion,
15. The semiconductor device according to claim 14 , wherein the first sub front portion projects from the first sub full thickness portion toward the main lead. The semiconductor device according to claim 14 , wherein the first sub total thickness portion forms at least a part of a back surface of the first sub lead exposed from the resin package. The first sub lead includes a first sub extension,
The first sub-extending portion extends from the first sub-all-thickness portion in a direction perpendicular to a thickness direction of the semiconductor element, and constitutes a back surface of the first sub-lead. Yes,
The first sub-extending portion is exposed from the resin package,
The semiconductor device according to claim 14 , wherein the first sub-extending portion has an end surface that is parallel to the thickness direction and exposed from the resin package.   The said 1st sub-lead has a 1st sub-lead end surface connected to the said 1st sub-lead back surface, and the said 1st sub-lead end surface faces the opposite side to the side where the said main lead is located, The claim | item. 2. The semiconductor device according to 1. 20. The semiconductor device according to claim 18 , wherein said first sub-lead end surface is exposed from said resin package. The resin package has a first resin end face facing the same direction as the direction of the first sub-lead end face,
19. The semiconductor device according to claim 18 , wherein said first resin end surface is flush with said first sub-lead end surface. The second portion of the first sub-lead includes a first sub-lead side surface connected to the back surface of the first sub-lead, and the first sub-lead side surface has a direction in which the first sub-lead end surface faces and a direction of the semiconductor element. 19. The semiconductor device according to claim 18 , wherein the semiconductor device is oriented in a direction perpendicular to any of the thickness directions. 22. The semiconductor device according to claim 21 , wherein said first sub-lead side surface is exposed from said resin package. The resin package has a first resin side surface facing the same direction as the direction of the first sub lead side surface,
22. The semiconductor device according to claim 21 , wherein said first sub-lead side surface is flush with said first resin side surface. 20. The semiconductor device according to claim 18 , further comprising a first wire directly connected to said semiconductor element and electrically connecting said semiconductor element and said first auxiliary lead. 25. The semiconductor device according to claim 24 , further comprising a first sub-plating layer interposed between the first sub-lead and the first wire. A second sub-lead electrically connected to the semiconductor element;
The semiconductor device according to claim 14 , wherein the second sub-lead is separated from the main lead and the first sub-lead, and is exposed from the resin package. 27. The semiconductor device according to claim 26 , further comprising a second wire directly connected to the semiconductor element and electrically connecting the semiconductor element and the second sub lead. The semiconductor device according to claim 27 , further comprising a second sub-plating layer interposed between the second sub-lead and the second wire.   The semiconductor element has a semiconductor layer stacked on each other, a eutectic layer of a semiconductor and a metal and a single metal layer constituting a back electrode, and the single metal layer is directly bonded to the main lead. The semiconductor device according to claim 1. 30. The semiconductor device according to claim 29 , wherein the eutectic layer is made of a eutectic of Si and Au. 30. The semiconductor device according to claim 29 , wherein the single metal layer is thinner than the eutectic layer. Further comprising a first wire;
The semiconductor device according to claim 3 , wherein the semiconductor element includes a first surface electrode to which the first wire is bonded. Further comprising a second wire;
33. The semiconductor device according to claim 32 , wherein said semiconductor element includes a second surface electrode to which said second wire is bonded. 34. The semiconductor device according to claim 33 , wherein at least one of the first surface electrode and the second surface electrode overlaps the main entire thickness portion when viewed in the thickness direction. The main lead has a third portion exposed from the first surface,
The first sub lead has a fourth portion exposed from the first surface,
The third part is on a first side with respect to a center line of the first surface,
The fourth part is on a second side with respect to the center line of the first surface;
The semiconductor device according to claim 1, wherein the third part and the fourth part have different areas.   The first portion has a first edge perpendicular to the thickness direction, the second portion has a second edge perpendicular to the thickness direction, and the first edge The semiconductor device according to claim 1, wherein the second edge and the second edge are on the same line. A semiconductor element;
A main lead on which the semiconductor element is arranged;
A first sub-lead separated from the main lead and electrically connected to the semiconductor element;
A resin package that covers the semiconductor element, the main lead and the first sub lead, and has a rectangular shape when viewed in a thickness direction of the semiconductor element;
The resin package has a first surface having a normal direction parallel to the thickness direction and a second surface having a normal direction perpendicular to the thickness direction,
The main lead and the first sub lead are exposed from a first surface of the resin package;
The main lead has a main lead main surface and a main lead back surface facing each other,
The semiconductor element is disposed on the main lead main surface,
The back surface of the main lead is exposed from the first surface of the resin package,
The first sub-lead has a first sub-lead main surface and a first sub-lead rear surface facing each other, and the first sub-lead rear surface is exposed from the resin package.
The main lead back surface, the first sub lead back surface, and the first surface are flush with each other;
The main lead has a first portion exposed from the second surface of the resin package, and the first sub-lead has a second portion exposed from the second surface of the resin package. The dimensions of the first part and the second part in the thickness direction are different from each other,
In the direction in which the main lead and the first sub-lead are separated from each other, the first portion is located between one end and the other end of the back surface of the main lead,
The semiconductor device, wherein the semiconductor element includes a portion that does not overlap with the main lead when viewed in the thickness direction. A semiconductor element;
A main lead on which the semiconductor element is arranged;
A first sub-lead separated from the main lead and electrically connected to the semiconductor element;
A resin package that covers the semiconductor element, the main lead and the first sub lead, and has a rectangular shape when viewed in a thickness direction of the semiconductor element;
The resin package has a first surface having a normal direction parallel to the thickness direction and a second surface having a normal direction perpendicular to the thickness direction,
The main lead and the first sub lead are exposed from a first surface of the resin package;
The main lead has a main lead main surface and a main lead back surface facing each other,
The semiconductor element is disposed on the main lead main surface,
The back surface of the main lead is exposed from the first surface of the resin package,
The first sub-lead has a first sub-lead main surface and a first sub-lead rear surface facing each other, and the first sub-lead rear surface is exposed from the resin package.
The main lead back surface, the first sub lead back surface, and the first surface are flush with each other;
The main lead has a first portion exposed from the second surface of the resin package, and the first sub-lead has a second portion exposed from the second surface of the resin package. The dimensions of the first part and the second part in the thickness direction are different from each other,
In the direction in which the main lead and the first sub-lead are separated from each other, the first portion is located between one end and the other end of the back surface of the main lead,
The main lead includes a main full thickness portion and a main eave portion,
The main total thickness portion is a portion extending from the main lead main surface to the main lead back surface,
The main eaves portion projects from the main full thickness portion in a direction perpendicular to the thickness direction,
The semiconductor device, wherein the entire main total thickness portion overlaps with the semiconductor element as viewed in the thickness direction. A semiconductor element;
A main lead on which the semiconductor element is arranged;
A first sub-lead separated from the main lead and electrically connected to the semiconductor element;
A resin package that covers the semiconductor element, the main lead and the first sub lead, and has a rectangular shape when viewed in a thickness direction of the semiconductor element;
The resin package has a first surface having a normal direction parallel to the thickness direction and a second surface having a normal direction perpendicular to the thickness direction,
The main lead and the first sub lead are exposed from a first surface of the resin package;
The main lead has a main lead main surface and a main lead back surface facing each other,
The semiconductor element is disposed on the main lead main surface,
The back surface of the main lead is exposed from the first surface of the resin package,
The first sub-lead has a first sub-lead main surface and a first sub-lead rear surface facing each other, and the first sub-lead rear surface is exposed from the resin package.
The main lead back surface, the first sub lead back surface, and the first surface are flush with each other;
The main lead has a first portion exposed from the second surface of the resin package, and the first sub-lead has a second portion exposed from the second surface of the resin package. The dimensions of the first part and the second part in the thickness direction are different from each other,
In the direction in which the main lead and the first sub-lead are separated from each other, the first portion is located between one end and the other end of the back surface of the main lead,
The main lead includes a main full thickness portion and a main eave portion,
The main total thickness portion is a portion extending from the main lead main surface to the main lead back surface,
The main eaves portion projects from the main full thickness portion in a direction perpendicular to the thickness direction,
The main eave portion has a main front portion, and the main front portion projects from the main full thickness portion toward the first sub-lead,
The main eave portion has a main side portion, and the main side portion projects from the main full thickness portion in a direction perpendicular to a direction in which the main front portion projects,
The semiconductor device, wherein the main lead includes a main side connecting portion protruding from the main side portion, and the main side connecting portion has an end face exposed from the resin package. A semiconductor element;
A main lead on which the semiconductor element is arranged;
A first sub-lead separated from the main lead and electrically connected to the semiconductor element;
A resin package that covers the semiconductor element, the main lead and the first sub lead, and has a rectangular shape when viewed in a thickness direction of the semiconductor element;
The resin package has a first surface having a normal direction parallel to the thickness direction and a second surface having a normal direction perpendicular to the thickness direction,
The main lead and the first sub lead are exposed from a first surface of the resin package;
The main lead has a main lead main surface and a main lead back surface facing each other,
The semiconductor element is disposed on the main lead main surface,
The back surface of the main lead is exposed from the first surface of the resin package,
The first sub-lead has a first sub-lead main surface and a first sub-lead rear surface facing each other, and the first sub-lead rear surface is exposed from the resin package.
The main lead back surface, the first sub lead back surface, and the first surface are flush with each other;
The main lead has a first portion exposed from the second surface of the resin package, and the first sub-lead has a second portion exposed from the second surface of the resin package. The dimensions of the first part and the second part in the thickness direction are different from each other,
In the direction in which the main lead and the first sub-lead are separated from each other, the first portion is located between one end and the other end of the back surface of the main lead,
The main lead includes a main full thickness portion and a main eave portion,
The main total thickness portion is a portion extending from the main lead main surface to the main lead back surface,
The main eaves portion projects from the main full thickness portion in a direction perpendicular to the thickness direction,
The main eave portion has a main front portion, and the main front portion projects from the main full thickness portion toward the first sub-lead,
The main eave portion has a main rear portion, and the main rear portion projects from the main full thickness portion in a direction opposite to a direction in which the main front portion projects,
The semiconductor device, wherein the main lead includes a main rear connecting portion protruding from the main rear portion, and the main rear connecting portion has an end face exposed from the resin package. A semiconductor element;
A main lead on which the semiconductor element is arranged;
A first sub-lead separated from the main lead and electrically connected to the semiconductor element;
A resin package that covers the semiconductor element, the main lead and the first sub lead, and has a rectangular shape when viewed in a thickness direction of the semiconductor element;
The resin package has a first surface having a normal direction parallel to the thickness direction and a second surface having a normal direction perpendicular to the thickness direction,
The main lead and the first sub lead are exposed from a first surface of the resin package;
The main lead has a main lead main surface and a main lead back surface facing each other,
The semiconductor element is disposed on the main lead main surface,
The back surface of the main lead is exposed from the first surface of the resin package,
The first sub-lead has a first sub-lead main surface and a first sub-lead rear surface facing each other, and the first sub-lead rear surface is exposed from the resin package.
The main lead back surface, the first sub lead back surface, and the first surface are flush with each other;
The main lead has a first portion exposed from the second surface of the resin package, and the first sub-lead has a second portion exposed from the second surface of the resin package. The dimensions of the first part and the second part in the thickness direction are different from each other,
In the direction in which the main lead and the first sub-lead are separated from each other, the first portion is located between one end and the other end of the back surface of the main lead,
The main lead includes a main full thickness portion and a main eave portion,
The main total thickness portion is a portion extending from the main lead main surface to the main lead back surface,
The main eaves portion projects from the main full thickness portion in a direction perpendicular to the thickness direction,
The semiconductor device, wherein the main entire thickness portion is entirely surrounded by the main eave portion in the thickness direction view. A semiconductor element;
A main lead on which the semiconductor element is arranged;
A first sub-lead separated from the main lead and electrically connected to the semiconductor element;
A resin package that covers the semiconductor element, the main lead and the first sub lead, and has a rectangular shape when viewed in a thickness direction of the semiconductor element;
The resin package has a first surface having a normal direction parallel to the thickness direction and a second surface having a normal direction perpendicular to the thickness direction,
The main lead and the first sub lead are exposed from a first surface of the resin package;
The main lead has a main lead main surface and a main lead back surface facing each other,
The semiconductor element is disposed on the main lead main surface,
The back surface of the main lead is exposed from the first surface of the resin package,
The first sub-lead has a first sub-lead main surface and a first sub-lead rear surface facing each other, and the first sub-lead rear surface is exposed from the resin package.
The main lead back surface, the first sub lead back surface, and the first surface are flush with each other;
The main lead has a first portion exposed from the second surface of the resin package, and the first sub-lead has a second portion exposed from the second surface of the resin package. The dimensions in the thickness direction of the first part and the second part are different from each other,
In the direction in which the main lead and the first sub-lead are separated from each other, the first portion is located between one end and the other end of the back surface of the main lead,
The main lead includes a main full thickness portion and a main eave portion,
The main total thickness portion is a portion extending from the main lead main surface to the main lead back surface,
The main eaves portion projects from the main full thickness portion in a direction perpendicular to the thickness direction,
The semiconductor device, wherein the main eave portion entirely overlaps the semiconductor element when viewed in the thickness direction.