JP6668798B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

2. Description of the Related Art Conventionally, a configuration in which a trench gate is formed on a substrate surface in a semiconductor element is known (for example, see Patent Document 1). Further, a configuration is known in which a part of a trench gate is connected to an emitter potential or the like to form a dummy gate. The provision of the dummy gate produces a carrier injection promoting effect (IE effect).
[Prior art documents]
[Patent Document]
Patent Document 1 JP-A-2002-353456

  From the viewpoint of reducing the on-state voltage of the semiconductor element, it is preferable to further enhance the IE effect.

  In one embodiment of the present invention, a semiconductor substrate of a first conductivity type, a main body formed on a surface of the semiconductor substrate and extending in a predetermined extending direction, and a direction different from the extending direction from the main body And a dummy trench portion including at least one branch portion extending to the semiconductor substrate, wherein the semiconductor substrate has a first conductivity type emitter region provided in order from the surface of the semiconductor substrate, and a second conductivity type emitter region. The dummy trench portion provides a semiconductor device having a dummy trench penetrating the emitter region and the base region from the surface of the semiconductor substrate and a dummy insulating portion provided in the dummy trench.

  The above summary of the present invention is not an exhaustive listing of all features of the present invention. Further, a sub-combination of these feature groups can also be an invention.

FIG. 2 is a plan view illustrating an example of a semiconductor device 100. It is a figure which shows an example of the aa 'cross section in FIG. FIG. 2 is a diagram illustrating an example of a bb ′ cross section in FIG. 1. FIG. 13 is a plan view illustrating another example of the semiconductor device 100. FIG. 13 is a plan view illustrating another example of the semiconductor device 100. FIG. 9 is a plan view showing another example of the dummy trench section 30. FIG. 4 is a diagram illustrating another example of the cross section taken along the line aa ′ of the semiconductor substrate 10. FIG. 3 is a diagram illustrating another example of the cross section taken along the line aa ′ of the semiconductor substrate 10. FIG. 6 is a diagram illustrating another example of the bb ′ cross section of the semiconductor substrate 10. FIG. 13 is a plan view illustrating another example of the semiconductor device 100. FIG. 3 is a diagram illustrating a cross section taken along line ee ′ of the semiconductor device 100. FIG. 7 is a diagram illustrating a configuration of a semiconductor device 200 according to a comparative example. FIG. 13 shows a cc ′ cross section in FIG. 12. FIG. 13 shows a dd ′ cross section in FIG. 12.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all combinations of the features described in the embodiments are necessarily essential to the solution of the invention.

  FIG. 1 is a plan view showing an example of the semiconductor device 100. The semiconductor device 100 of the present example is a semiconductor chip having a transistor unit 70 including a transistor such as an IGBT (Insulated Gate Bipolar Transistor) and a diode unit 80 including a diode such as an FWD (Free Wheel Diode). FIG. 1 shows the chip surface around the chip end, and other regions are omitted.

  Although FIG. 1 shows an active region of the semiconductor substrate in the semiconductor device 100, the semiconductor device 100 may have a breakdown voltage structure surrounding the active region. The active region refers to a region where a current flows when the semiconductor device 100 is turned on. The withstand voltage structure relieves the electric field concentration on the surface side of the semiconductor substrate. The pressure-resistant structure has, for example, a guard ring, a field plate, a RESURF, and a structure combining these.

  In the semiconductor device 100 of this example, the gate electrode 50, the emitter electrode 52, the gate trench 40, the dummy trench 30, the emitter trench 60, the well region 17, the emitter region 12, the base region 14, It has a region 15, a contact hole 54 and a contact hole 55. The emitter electrode 52 is an example of a first surface side electrode, and the gate electrode 50 is an example of a second surface side electrode.

  The gate trench portion 40, the dummy trench portion 30, the emitter trench portion 60, the well region 17, the emitter region 12, the base region 14, and the contact region 15 are formed inside the front side of the semiconductor substrate, and the emitter electrode 52 and the gate electrode 50 are formed. Is provided above the surface of the semiconductor substrate.

  An interlayer insulating film is formed between the emitter electrode 52 and the gate electrode 50 and the surface of the semiconductor substrate, but is omitted in FIG. The contact hole 54 and the contact hole 55 are formed penetrating the interlayer insulating film. The emitter electrode 52 is in contact with the semiconductor substrate through the contact hole 54. Gate electrode 50 is in contact with the semiconductor substrate through contact hole 55.

  The emitter electrode 52 and the gate electrode 50 are formed of a material containing a metal. For example, at least a part of each electrode is formed of aluminum. Each electrode may have a region formed of a material containing tungsten.

  The one or more gate trenches 40 and the one or more dummy trenches 30 are arranged at predetermined intervals in a predetermined arrangement direction in the region of the transistor unit 70. Dummy trench portion 30 is not electrically connected to gate electrode 50. By providing the dummy trench portion 30 not connected to the gate electrode 50, an IE effect can be generated.

  Gate trench portion 40 is connected to gate electrode 50 via contact hole 55. Gate trench portion 40 controls whether a current channel is formed in a base region formed on the back surface side of emitter region 12 in the semiconductor substrate.

  The gate trench portion 40 has an opposing portion 41 and a protruding portion 43. The facing portion 41 is formed to extend in a predetermined extending direction in a range facing the dummy trench portion 30. The protruding portion 43 further extends from the facing portion 41 and is formed in a range not facing the dummy trench portion 30. In this example, two opposing portions 41 provided on both sides of the dummy trench portion 30 are connected by one projecting portion 43. At least a part of the protrusion 43 may have a curved shape.

  A contact hole 55 is formed in the insulating layer covering the protrusion 43. The contact hole 55 may be formed corresponding to a region of the protruding portion 43 farthest from the facing portion 41. The projecting portion 43 of this example has a portion extending in a direction perpendicular to the facing portion 41 in a region farthest from the facing portion 41. The contact hole 55 may be formed corresponding to the portion of the protrusion 43.

  The dummy trench portion 30 is formed on the surface of the semiconductor substrate by extending a body portion 31 in a predetermined extension direction, and a branch extending from the body portion 31 in a direction different from the extension direction of the body portion 31. And a part 32. The main body 31 in this example has a linear shape, and is formed to extend in a direction perpendicular to the arrangement direction of the trenches described above. The plurality of branches 32 may be provided in parallel with each other. The main body portion 31 of the present example is provided to face the facing portion 41 of the gate trench portion 40 and extends in the same extending direction as the facing portion 41 of the gate trench portion 40. In addition, one or more main units 31 are provided between the two opposing units 41.

  One or more branches 32 are provided for one main body 31. The branch portion 32 in this example has a linear shape, and extends in a direction orthogonal to the extending direction of the main body portion 31. The branch portion 32 may extend in a direction from the main body portion 31 to the facing portion 41 of the gate trench portion 40. The branches 32 may be provided on both sides of the main body 31. In this example, two branch portions 32 are provided on both sides of the main body 31 from the same portion in the extending direction of the main body 31. In another example, the branch portion 32 on one side of the main body portion 31 and the branch portion 32 on the other side may be provided at different portions in the extending direction of the main body portion 31. The branch portions 32 on one side of the main body portion 31 and the branch portions 32 on the other side may be provided alternately in the extending direction of the main body portion 31.

  The branch portion 32 of this example is provided inside the contact region 15 on the surface of the semiconductor substrate. On the surface of the semiconductor substrate, the entire branch portion 32 may be provided so as not to protrude from the contact region 15. At least some of the branch portions 32 need not be in contact with the gate trench portion 40. Further, at least a part of the branch portion 32 may be in contact with the gate trench portion 40. When the branch 32 is provided in the emitter region 12 on the surface of the semiconductor substrate, the branch 32 is preferably not in contact with the gate trench 40. Thereby, a region functioning as a channel can be left between the branch portion 32 and the gate trench portion 40.

  As described above, since the dummy trench portion 30 has the branch portion 32, the area occupied by the dummy trench portion 30 on the surface of the semiconductor substrate can be increased. Thereby, the IE effect can be enhanced. In addition, since the branch portion 32 branches off from the main body portion 31, the shape of the dummy trench portion 30 can be complicated. Thereby, the IE effect can be further enhanced as compared with the case where the linear dummy trench portions having the same area are provided. For example, a region in contact with the dummy trench portion 30 can efficiently suppress the passage of holes. By providing the branch portions 32, it is possible to increase the total length of the side edges of the dummy trench portions 30 on the surface of the semiconductor substrate, and it is possible to efficiently suppress the passage of holes. Further, in the dummy trench portion 30 of the present example, a plurality of corners surrounding two sides of the branch portion 32 and the main body portion 31 are formed at a connection portion between the branch portion 32 and the main body portion 31. Such a corner-shaped region can efficiently suppress the passage of holes. For this reason, the dummy trench portion 30 of the present example can efficiently enhance the IE effect.

  Each branch 32 may have the same width. The width of the branch 32 refers to the length of the branch 32 in a direction perpendicular to the direction in which the branch 32 extends. In another example, the branches 32 may have different widths in the stretching direction. For example, the width of the branch portion 32 may decrease stepwise as the distance from the main body portion 31 increases. Since the branch portion 32 has the step shape, the length of the side edge of the dummy trench portion 30 and the number of corners can be increased.

  Emitter trench portion 60 is provided in the region of diode portion 80. Emitter trench portion 60 may have the same shape as gate trench portion 40 on the surface of the semiconductor substrate. However, the length of the emitter trench 60 in the extending direction may be shorter than that of the gate trench 40. The length of the emitter trench section 60 of the present example is the same as that of the dummy trench section 30.

  The emitter trench 60 has a main body 61 and a branch 62. On the surface of the semiconductor substrate, the shape of the main body 61 may be the same as that of the gate trench 40. That is, the main body 61 may include a plurality of linearly extending portions and a connecting portion that connects two adjacent extending portions. The connecting portion may have a curved portion similarly to the projecting portion 43.

  The branches 62 may have a similar arrangement and shape as the branches 32. One or more branches 62 are provided for one main body 61. The branch portion 62 in this example has a linear shape, and extends in a direction orthogonal to the extending direction of the main body portion 61. The branch part 62 may connect two extending parts in the main body part 61. The branch portion 62 in this example is not connected to the gate trench portion 40.

  The gate electrode 50 is formed to cover a part of the protrusion 43. The gate electrode 50 is formed to cover a portion where the contact hole 55 is provided in the protrusion 43. The gate electrode 50 of this example is not formed above the opposing portion 41, the dummy trench portion 30, and the emitter trench portion 60.

  The emitter electrode 52 is formed above the gate trench portion 40, the dummy trench portion 30, the emitter trench portion 60, the well region 17, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 of this example is formed to cover a part of the well region 17 and the gate trench portion 40.

  The well region 17 is formed in a predetermined range from the end of the semiconductor substrate on the side where the gate electrode 50 is provided. A part of the dummy trench portion 30, the emitter trench portion 60, and the opposing portion 41 on the side of the gate electrode 50 is formed in the well region 17. The entirety of the protrusion 43 may be formed in the well region 17. The semiconductor substrate has a first conductivity type, and the well region 17 has a second conductivity type different from that of the semiconductor substrate. The semiconductor substrate of this example is an N- type, and the well region 17 is a P + type. In this example, the first conductivity type is described as N-type, and the second conductivity type is described as P-type. However, the first and second conductivity types may be opposite conductivity types.

  The base region 14 is formed in at least a part of a region sandwiched between the facing portion 41 of the gate trench portion 40, the main body portion 31 of the dummy trench portion 30, and the extending portion of the emitter trench portion 60. The base region 14 is of the second conductivity type having a lower impurity concentration than the well region 17. The base region 14 of the present example is P-type.

  A second conductivity type contact region 15 having a higher impurity concentration than the base region 14 is formed on the surface of the base region 14. The contact region 15 of this example is of a P + type. In the transistor section 70, the first conductivity type emitter region 12 having a higher impurity concentration than the semiconductor substrate is selectively formed on a part of the surface of the contact region 15. The emitter region 12 of this example is of the N + type.

  Each of the contact region 15 and the emitter region 12 extends from one adjacent trench portion of the facing portion 41 of the gate trench portion 40, the main body portion 31 of the dummy trench portion 30, and the extension portion of the emitter trench portion 60 to the other. Up to the trench portion. The one or more contact regions 15 and the one or more emitter regions 12 of the transistor portion 70 are formed so as to be alternately exposed along the extending direction of the trench portion in a region sandwiched between the trench portions.

  In the transistor section 70, the contact hole 54 is formed above each of the contact region 15, the emitter region 12, and the dummy trench portion 30. In order to maximize the contact area between the emitter region 12 and the emitter electrode 52, the contact hole 54 is formed from one adjacent trench portion to the other trench portion. Further, contact hole 54 may be formed so as to expose the entire area of the surface of emitter region 12. Further, the contact hole 54 may be formed so as to expose the entire area of the surface of the contact region 15. However, contact hole 54 is not formed in a region corresponding to base region 14 and well region 17.

  Further, the contact hole 54 does not have to be formed above the gate trench portion 40 and may be formed. However, when the contact hole 54 is formed above the gate trench portion 40, an insulating portion for insulating the electrode in the trench and the emitter electrode 52 may be formed at the upper end of the gate trench portion 40 in the trench.

  The contact hole 54 exposes the main body portion 31 of the dummy trench portion 30 in a range opposed to the emitter region 12 and the contact region 15. Further, the contact hole 54 also exposes the branch 32 extending from the main body 31. As described later, the emitter region 12 may be exposed on the trench inner wall in the dummy trench portion 30. The emitter electrode 52 may be formed through the contact hole 54 to the inside of the dummy trench 30.

  Thus, the emitter electrode 52 can contact not only the surface of the emitter region 12 exposed on the surface of the semiconductor substrate but also the side surface of the emitter region 12 exposed on the inner wall of the dummy trench portion 30. Contact resistance can be reduced. Therefore, the on-voltage of the semiconductor device 100 can be reduced.

  In the diode portion 80, the contact hole 54 is formed above each of the contact region 15, the base region 14, and the emitter trench portion 60. The contact hole 54 of this example is not formed in the base region 14 closest to the gate electrode 50 among the plurality of base regions 14. In this example, the contact hole 54 of the transistor section 70 and the contact hole 54 of the diode section 80 have the same length in the extending direction of each trench section.

  In the diode section 80, the contact hole 54 is formed from one adjacent extension of the diode section 80 to the other extension in order to maximize the contact area between the contact region 15 and the base region 14 and the emitter electrode 52. You. However, contact hole 54 is not formed in a region corresponding to base region 14 and well region 17.

  The contact hole 54 is formed so as to expose the emitter trench 60. Similarly to the dummy trench portion 30, the base region 14 may be exposed on the inner wall of the trench of the emitter trench portion 60. The emitter electrode 52 is formed through the contact hole 54 and into the trench of the emitter trench portion 60.

  Thereby, the emitter electrode 52 can contact not only the surface of the base region 14 exposed on the surface of the semiconductor substrate but also the side surface of the base region 14 exposed on the inner wall of the trench of the emitter trench portion 60. Therefore, the contact resistance with the base region 14 can be reduced.

  FIG. 2 is a diagram showing an example of an aa ′ cross section in FIG. The semiconductor device 100 of this example has the semiconductor substrate 10, the emitter electrode 52, and the collector electrode 24 in the cross section. The emitter electrode 52 is formed on the surface of the semiconductor substrate 10. Emitter electrode 52 is electrically connected to emitter terminal 53.

  The collector electrode 24 is formed on the back surface of the semiconductor substrate 10. Collector electrode 24 is electrically connected to the collector terminal. The emitter electrode 52 and the collector electrode 24 are formed of a conductive material such as a metal. In this specification, the surface on the emitter electrode 52 side of each member such as a substrate, a layer, and a region is referred to as a front surface, and the surface on the collector electrode 24 side is referred to as a back surface or bottom. The direction connecting the emitter electrode 52 and the collector electrode 24 is referred to as a depth direction.

  Semiconductor substrate 10 may be a silicon substrate, or may be a silicon carbide substrate, a nitride semiconductor substrate, or the like. On the front side of the semiconductor substrate 10, a P-type base region 14 is formed. Further, the N + type emitter region 12 is selectively formed in a part of the surface side of the base region 14.

  The semiconductor substrate 10 further includes an N + type accumulation region 16, an N− type drift region 18, an N− type buffer region 20, a P + type collector region 22, and an N + type cathode region 82. The accumulation region 16 is formed on the back surface side of the base region 14. The impurity concentration of accumulation region 16 is higher than the impurity concentration of drift region 18.

  The accumulation region 16 is formed between adjacent trenches. For example, in the transistor section 70, the accumulation region 16 is formed between the main body section 31 of the dummy trench section 30 and the gate trench section 40. The accumulation region 16 may be provided so as to cover the entire region between the main body 31 and the gate trench 40. By providing the accumulation region 16, the IE effect can be enhanced and the on-state voltage can be reduced.

  The drift region 18 is formed on the back surface side of the accumulation region 16. The buffer region 20 is formed on the back side of the drift region 18. The impurity concentration of buffer region 20 is higher than the impurity concentration of drift region 18. Buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the back surface side of base region 14 from reaching collector region 22 and cathode region 82.

  The collector region 22 is formed on the back surface side of the buffer region 20 in the region of the transistor section 70. The cathode region 82 is formed on the back surface side of the buffer region 20 in the region of the diode section 80. A collector electrode 24 is provided on the back surfaces of the collector region 22 and the cathode region 82.

  On the front side of the semiconductor substrate 10, one or more gate trenches 40, one or more dummy trenches 30 (in FIG. 2, the main body 31 is shown), and one or more emitter trenches 60 are formed. Each trench portion penetrates through base region 14 from the surface of semiconductor substrate 10 to reach drift region 18. In this example, the gate trench portion 40 and the dummy trench portion 30 penetrate the emitter region 12, the base region 14, and the accumulation region 16 from the surface of the semiconductor substrate 10 to reach the drift region 18. The emitter trench portion 60 reaches the drift region 18 from the surface of the semiconductor substrate 10 through the base region 14 and the accumulation region 16.

  The gate trench section 40 has a gate trench 46, an insulating film 42, a gate conductive section 44, and a gate insulating section 37 formed on the front surface side of the semiconductor substrate 10. The gate trench 46 is formed from the surface of the semiconductor substrate 10 to the drift region 18 through the emitter region 12, the base region 14, and the accumulation region 16.

  The insulating film 42 is formed to cover an inner wall of the gate trench 46. The insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench 46. The gate conductive part 44 is formed inside the insulating film 42 inside the gate trench 46. That is, the insulating film 42 insulates the gate conductive part 44 from the semiconductor substrate 10. Gate conductive portion 44 is formed of a conductive material such as polysilicon.

  Gate insulating portion 37 is formed above gate conductive portion 44 and insulates gate conductive portion 44 from emitter electrode 52. The gate insulating part 37 of this example is formed inside the gate trench 46. Gate insulating portion 37 includes, for example, silicon oxide, silicon nitride, or another insulating material. The thickness of the gate insulating portion 37 in the depth direction may be larger than the thickness of the insulating film 42 at the bottom of the gate trench 46.

  In this example, at least a part of the end surface of the gate insulating portion 37 on the semiconductor substrate 10 side is the same height as the surface of the semiconductor substrate 10. As an example, the entire end surface of the gate insulating portion 37 may be formed on the same plane as the surface of the semiconductor substrate 10. Thereby, the unevenness on the surface of the semiconductor substrate 10 is reduced, and a structure in which the semiconductor substrate 10 is stacked above the surface can be easily formed.

  Gate conductive portion 44 includes at least a region facing base region 14 adjacent thereto. Each gate conductive portion 44 is electrically connected to a gate terminal 51. In this example, the gate conductive portion 44 is electrically connected to the gate electrode 50 in the protrusion 43 as shown in FIG. Further, the gate electrode 50 is electrically connected to the gate terminal 51. When a predetermined voltage is applied to gate conductive portion 44 via gate terminal 51, a channel is formed on the surface of base region 14 at the interface in contact with gate trench 46.

  The dummy trench portion 30 (the main body portion 31 in the example of FIG. 2) has a dummy trench 38 and a dummy insulating portion 39 formed on the front surface side of the semiconductor substrate 10. FIG. 2 shows the structure of the main body 31. The branch 32 may have the same structure as the main body 31. The dummy trench 38 is formed from the surface of the semiconductor substrate 10 so as to penetrate the emitter region 12, the base region 14, and the accumulation region 16.

  The dummy insulating portion 39 is provided inside the dummy trench. As shown in FIG. 2, the dummy insulating portion 39 may be filled from the bottom of the dummy trench 38 to a predetermined height in the dummy trench 38. In this case, no conductive material such as polysilicon is provided inside the dummy trench 38. Therefore, the conductive material in the dummy trench 38 does not conduct with the base region 14 of the semiconductor substrate 10 or the like. Therefore, the reliability of the semiconductor device 100 can be improved.

  The width of the dummy trench 38 may be smaller than the width of the gate trench 46. Accordingly, the dummy insulating portion 39 can be filled in the dummy trench 38 in the process of forming the insulating film 42 in the gate trench 46. Note that the insulating film 42 and the dummy insulating section 39 may be formed by different processes. Further, the width of the dummy trench 38 may be the same as the width of the gate trench 46.

  The dummy trench 38 may be formed shallower than the gate trench 46. In this case, the dummy trench 38 having a small width and the gate trench 46 having a large width can be formed in the same etching step. Note that the dummy trench 38 and the gate trench 46 may be formed by different etching steps. Further, the dummy trench 38 may be formed to the same depth as the gate trench 46.

  The dummy insulating portion 39 may fill the entire dummy trench 38 or may fill a part of the dummy trench 38. The dummy insulating portion 39 may be filled in the dummy trench 38 so that at least a part of the emitter region 12 is exposed on the side wall of the dummy trench 38. The upper end of the dummy insulating portion 39 may be provided in the middle of the emitter region 12 in the depth direction.

  As described above, the emitter electrode 52 is formed above the surface of the semiconductor substrate 10 and contacts the surface of the emitter region 12. The emitter electrode 52 of this example is also formed in a region in the dummy trench 38 where the dummy insulating portion 39 is not provided. Thereby, the emitter electrode 52 can be in contact with the surface of the emitter region 12 and also on the side wall of the dummy trench 38 with the emitter region 12. Thereby, the contact resistance between emitter electrode 52 and emitter region 12 can be reduced.

  The structure of the dummy trench section 30 is not limited to the example of FIG. Like the gate trench 40, the dummy trench 30 may include an insulating film covering the inner wall of the dummy trench 38, and a conductive material such as polysilicon surrounded by the insulating film. In this case, the reliability of the insulating film must be ensured. However, since the dummy trench 30 and the gate trench 40 have the same structure, a part of the dummy trench 30 and the gate trench 40 is formed by the same process. Can be formed.

  The emitter electrode 52 may have a plug 36 disposed in the dummy trench 38. The plug portion contacts the emitter region 12 exposed on the side wall of the dummy trench. The plug portion 36 may be formed of the same material as the region of the emitter electrode 52 formed above the surface of the semiconductor substrate 10, or may be formed of a different material.

  As an example, the plug portion 36 is formed of a material containing tungsten, and the emitter electrode 52 other than the plug portion 36 is formed of a material not containing tungsten. By forming the plug portion 36 from a material containing tungsten, the plug portion 36 can be easily formed even inside the fine dummy trench.

  In this example, the gate trench portions 40 and the main body portions 31 of the dummy trench portions 30 are alternately arranged in a predetermined arrangement direction as shown in FIG. Further, the trench portions may be arranged at regular intervals. However, the arrangement of each trench is not limited to the above example. A plurality of gate trench parts 40 may be arranged between two main parts 31. Further, the number of the gate trench portions 40 provided between the main body portions 31 may not be constant.

  The diode unit 80 is provided in a region adjacent to the transistor unit 70. The diode unit 80 has the base region 14, the accumulation region 16, the drift region 18, and the buffer region 20 in the same layer as the transistor unit 70. A cathode region 82 is provided on the back surface side of the buffer region 20 of the diode unit 80. The diode section 80 has one or more emitter trench sections 60. Further, the emitter region 12 is not formed in the diode section 80.

  The emitter trench portion 60 is formed so as to penetrate the base region 14 and the accumulation region 16 from the surface side of the base region 14 and reach the drift region 18. Each emitter trench section 60 has an emitter trench 68 and an emitter insulating section 69, like the dummy trench section 30. The emitter trench portion 60 may have the same structure as the main body portion 31 of the dummy trench portion 30.

  The base region 14 may be exposed on the side wall of the emitter trench 68. Emitter electrode 52 may have a plug portion arranged inside emitter trench 68. The plug portion makes contact with the base region 14 exposed on the side wall of the emitter trench 68. With such a configuration, contact resistance between emitter electrode 52 and base region 14 can be reduced.

  In this example, the interval between the trench portions in the transistor portion 70 and the interval between the emitter trench portions 60 in the diode portion 80 in the cross section are the same. As shown in FIG. 2, when the gate trench portions 40 and the main body portion 31 are alternately arranged in the transistor portion 70, the distance between the gate trench portion 40 and the main body portion 31 and the distance between the emitter trench portions 60 are different from each other. May be the same. Further, the length of the plug portion arranged in the emitter trench 68 may be the same as the length of the plug portion 36 arranged in the dummy trench 38.

  FIG. 3 is a diagram illustrating an example of a bb ′ cross section in FIG. 1. Note that the storage area 16 is omitted in FIG. The semiconductor device 100 of this example has the semiconductor substrate 10, the interlayer insulating film 26, the emitter electrode 52, and the collector electrode 24 in the cross section. The semiconductor substrate 10 has a branch portion 32 of the dummy trench portion 30 in the cross section. The structure and size of the branch portion 32 may be the same as the main body portion 31 shown in FIG.

  The branch portion 32 in this example is formed to penetrate the contact region 15 and the base region 14. Further, in the example of FIG. 3, the branch portions 32 are provided in one contact region 15, but a plurality of branch portions 32 may be provided in one contact region 15. Further, a branch 32 penetrating the emitter region 12 and the base region 14 may be provided.

  The interlayer insulating film 26 is formed between the gate electrode 50 and the emitter electrode 52 and the semiconductor substrate 10. Contact holes 54 and 55 are formed in interlayer insulating film 26.

  The contact hole 54 exposes at least a part of the dummy trench portion 30 (the branch portion 32 in FIG. 3), the emitter region 12 and the contact region 15 on the surface of the semiconductor substrate 10. Emitter electrode 52 passes through contact hole 54 and contacts dummy trench portion 30, emitter region 12 and contact region 15.

  The emitter electrode 52 may be in contact with the contact region 15 in the dummy trench of the branch 32. The emitter electrode 52 of the present example has a plug portion 36 arranged in a dummy trench of the branch portion 32. The branch part 32 and the plug part 36 inserted into the main body part 31 may be formed integrally.

  The contact hole 55 exposes at least a part of the protrusion 43 of the gate trench 40 on the surface of the semiconductor substrate 10. A through hole is formed in the gate insulating portion 37 of the gate trench portion 40 exposed by the contact hole 55. The gate electrode 50 contacts the gate conductive part 44 through the contact hole 55 and the through hole of the gate insulating part 37. The gate electrode 50 has a plug portion 56 that passes through the through hole of the gate insulating portion 37. The plug part 56 may be formed of the same material as the plug part 36 shown in FIG.

  Next, an example of a method for manufacturing the semiconductor device 100 shown in FIGS. 1 to 3 will be described. However, the method for manufacturing the semiconductor device 100 is not limited to this example. First, a semiconductor substrate 10 of the same conductivity type as the drift region 18 (described as an N-type in this example) is prepared.

  Next, an etching mask having a predetermined pattern is provided on the surface of the semiconductor substrate 10 to form a plurality of trenches for the gate trench 40, the dummy trench 30, and the emitter trench 60. After forming the trench, an insulating film is formed on the inner wall of the gate trench. In addition, an insulating portion is filled in the dummy trench and the emitter trench. The insulating film of the gate trench and the insulating portion of the dummy trench emitter trench may be formed in the same step. After forming an insulating film in the gate trench, the inside of the gate trench is filled with a conductive material.

Next, a P-type impurity is implanted from the surface side of the semiconductor substrate, and heat treatment is performed at a temperature of about 1100 ° C. for about 2 hours to form a P-type base region 14 shallower than the trench over the entire surface of the semiconductor substrate 10 I do. Next, an N-type impurity is implanted from the surface side of the semiconductor substrate 10 to form an N-type accumulation region 16 which is deeper than the base region 14 and shallower than the trench. For example, the N-type accumulation region 16 is formed by ion-implanting phosphorus at an acceleration voltage of about 2.8 MeV and about 5.0 × 10 ¹² / cm ² .

  Next, an N-type impurity is selectively implanted from the surface side of the semiconductor substrate 10 using a mask having an opening corresponding to the emitter region 12. Thus, the N + type emitter region 12 is selectively formed inside the P type base region 14.

  After that, an interlayer insulating film 26 is formed on the surface side of the semiconductor substrate 10. The interlayer insulating film 26 is also formed above the conductive part in the gate trench. The interlayer insulating film 26 formed in the gate trench functions as a gate insulating part 37. Here, the insulating portion formed above the dummy trench and the emitter trench may be removed to expose the side surface of the emitter region 12 into the trench.

  In the protruding portion 43 of the gate trench portion 40, a through hole is formed in the gate insulating portion 37. Further, a contact hole 54 and a contact hole 55 are formed in the interlayer insulating film 26. Then, the emitter electrode 52 and the gate electrode 50 are formed. After the plug portion 36 and the plug portion 56 are formed, each electrode may be formed on the surface of the semiconductor substrate 10.

Next, selenium is ion-implanted from the back surface side of the semiconductor substrate 10 at, for example, about 1.0 × 10 ¹⁴ / cm ² , and then heat treatment is performed at a temperature of about 900 degrees for about 2 hours. Thus, an N + type buffer region 20 is formed on the back surface side of the semiconductor substrate 10. The remaining N − type region of the semiconductor substrate 10 becomes the drift region 18. By using selenium having a large diffusion coefficient, the buffer region 20 can be formed at a deep position. Before forming the buffer region 20, the semiconductor substrate 10 may be polished to adjust the thickness.

  Instead of selenium ion implantation, N + type buffer region 20 may be formed by ion implantation of protons a plurality of times at different doses. Thereby, the buffer region 20 in which the impurity concentration increases from the substrate front side toward the substrate back side can be formed.

Next, P-type impurities are ion-implanted from the back surface side of the semiconductor substrate 10 at a dose of, for example, 1.0 × 10 ¹³ / cm ² or more and 4.0 × 10 ¹³ / cm ² or less. Thus, a P + type collector region 22 thinner than the buffer region 20 is formed on the back surface side of the semiconductor substrate 10. If the dose of the P-type impurity is less than 1.0 × 10 ¹³ / cm ^{2, an} ohmic junction between the collector region and the collector electrode cannot be made, which is not preferable. In the diode section 80, a cathode region 82 is formed. Then, a collector electrode 24 and the like are appropriately formed on the back surface side of the semiconductor substrate 10.

  FIG. 4 is a plan view illustrating another example of the semiconductor device 100. The semiconductor device 100 in this example differs from the example of FIG. 1 in that a branch portion 32 is also provided inside the emitter region 12 on the surface of the semiconductor substrate. Other structures may be the same as those of the semiconductor device 100 shown in FIGS.

  In this example, the branch portion 32 is provided for each emitter region 12 and each contact region 15. The branch 32 provided in the emitter region 12 and the branch 32 provided in the contact region 15 may be provided in parallel. The branch 32 provided in the emitter region 12 is not connected to the gate trench 40. That is, in the emitter region 12, a semiconductor region remains between the branch portion 32 and the gate trench portion 40. This region functions as a channel region. The branch 32 provided in the emitter region 12 and the branch 32 provided in the contact region 15 may have the same length.

  By forming the branch portions 32 in this manner, the IE effect can be enhanced. Further, since the branch portion 32 and the gate trench portion 40 are separated from each other in the emitter region 12, a channel region can be secured and the channel density can be maintained.

  FIG. 5 is a plan view showing another example of the semiconductor device 100. FIG. The semiconductor device 100 according to the present embodiment differs from the semiconductor device 100 shown in FIGS. 1 to 4 in that a branch portion 32 provided in the contact region 15 on the surface of the semiconductor substrate is connected to the gate trench portion 40. I do. Other structures may be the same as those of any of the semiconductor devices 100 shown in FIGS. Note that the branch portion 32 provided in the emitter region 12 is not connected to the gate trench portion 40.

  By forming the branch portions 32 in this manner, the IE effect can be enhanced. Further, by connecting the branch portion 32 in the contact region 15 to the gate trench portion 40, the number of corner portions can be increased, and the IE effect can be further enhanced.

  Note that the branch portion 62 in the diode portion 80 may be connected to the gate trench portion 40 or may not be connected. Further, some of the branch portions 62 may be connected to the gate trench portion 40. In the example of FIG. 5, the branch portion 32 provided in the contact region 15 and the branch portion 62 provided on a straight line are connected to the gate trench portion 40.

  When connecting the branch 62 to the gate trench 40, the gate trench 40 and the dummy trench 30 may be formed in different steps. For example, after forming the gate conductive portion 44 inside the gate trench portion 40, the dummy trench 38 connected to the gate trench 46 may be formed. After forming the dummy trench 38, a dummy insulating portion 39 is formed. The step of forming the dummy insulating portion 39 may be the same as the step of forming the interlayer insulating film 26.

  FIG. 6 is a plan view showing another example of the dummy trench section 30. FIG. The dummy trench portion 30 of this example has a plurality of branch portions 32 inside one contact region 15 on the surface of the semiconductor substrate. The dummy trench section 30 of the present embodiment may be applied to any of the semiconductor devices 100 shown in FIGS.

  The number of branches 32 provided in one contact region 15 may be larger than the number of branches 32 provided in one emitter region 12. One branch region 32 may be provided in one emitter region 12, and a plurality of branches 32 may be provided in one contact region 15.

  Further, the width of the contact region 15 in the extending direction of the main body 31 may be larger than the width of the emitter region 12. Further, the interval P1 between the respective branch portions 32 in the extending direction of the main body portion 31 may be constant. The branch portion 32 may not be formed at the boundary between the contact region 15 and the emitter region 12, and may be formed at the boundary between the contact region 15 and the emitter region 12.

  In each of the semiconductor devices 100 shown in FIGS. 1 to 6, the length (D2−D1) of the branch 32 is equal to the distance D2 between the main body 31 and the gate trench 40 (that is, the gate trench 46). It may be more than half and may be more than 3/4. The distance D1 between the branch portion 32 and the gate trench portion 40 may be constant, or may be different for each branch portion 32. The distance between the branch 32 provided in the emitter region 12 and the gate trench 40 may be larger than the distance between the branch 32 provided in the contact region 15 and the gate trench 40.

  Further, the interval P1 between the branch portions 32 may be smaller than the distance D2 between the main body portion 31 and the gate trench portion 40. The interval P1 may be equal to or less than half of the distance D2. By forming the branch portions 32 with high density, the IE effect can be further enhanced.

  FIG. 7 is a diagram illustrating another example of the cross section taken along the line aa ′ of the semiconductor substrate 10. FIG. 7 shows the vicinity of the surface of the semiconductor substrate 10 and other parts are omitted. The semiconductor device 100 of the present example has a plurality of main bodies 31 between two gate trenches 40. Other structures may be the same as any of the semiconductor devices 100 shown in FIGS. With such a configuration, the IE effect can be further enhanced.

  The plurality of main bodies 31 may be arranged at the same interval. Further, the distance between the main body 31 and the gate trench 40 may be the same as the distance between the main bodies 31 or may be wider. By increasing the distance between the main body portion 31 and the gate trench portion 40, the channel region can be left even if manufacturing variations occur.

  FIG. 8 is a diagram illustrating another example of the cross section aa ′ of the semiconductor substrate 10. FIG. 7 shows the vicinity of the surface of the semiconductor substrate 10 and other parts are omitted. The semiconductor device 100 of this example further has a P + type floating region 90 separated from the base region 14 in a region adjacent to the bottom of the dummy trench portion 30 (in FIG. 8, the bottom of the dummy trench 38 in the main body portion 31). . Other structures may be the same as those of any of the semiconductor devices 100 shown in FIGS.

  The floating region 90 is formed along the main body 31 and does not need to be formed in the branch 32. The width of the floating region 90 in the direction connecting the two gate trenches 40 may be larger than the width of the main body 31. The width of the floating region 90 may be at least half the distance between the two gate trench portions 40. The distance between the floating region 90 and the gate trench portion 40 may be larger than the distance between the branch portion 32 and the gate trench portion 40.

  Further, the bottom of floating region 90 may be provided at a position deeper than the bottom of gate trench portion 40 when viewed from the surface of semiconductor substrate 10. The bottom of the main body 31 may be provided at a position shallower than the bottom of the gate trench 40. By providing the floating region 90, the IE effect can be further enhanced.

  As shown in FIG. 7, when a plurality of main bodies 31 are provided between two gate trenches 40, a floating region 90 may be formed at the bottom of each main body 31. The floating regions 90 of each main body 31 may be separated from each other or may be connected.

  FIG. 9 is a diagram showing another example of the bb ′ cross section of the semiconductor substrate 10. The semiconductor device 100 of this example has branch portions 32 having different depths. The other structure may be the same as any one of the semiconductor devices 100 shown in FIGS.

  The dummy trench of the branch 32-1 provided at the position closest to the well region 17 in the extending direction of the main body 31 may be formed to a position deeper than the dummy trench of the other branch 32-2. For example, the dummy trench of the branch 32-1 is formed to a position deeper than the bottom of the well region 17.

  The width of the dummy trench of the branch 32-1 may be larger than the width of the dummy trench of the other branch 32-2. Thus, the branch portions 32 having different depths can be formed in the same step. The branch 32-1 may be connected to the gate trench 40. As a result, the well region 17 and the active region such as the emitter region 12 can be separated by the deep dummy trench. The branch 32-1 is preferably filled with an insulating material.

  FIG. 10 is a plan view showing another example of the semiconductor device 100. FIG. The semiconductor device 100 in this example differs from the examples of FIGS. 1 to 9 in that a branch 45 is also provided in the gate trench 40 on the surface of the semiconductor substrate. Other structures may be the same as those of any of the semiconductor devices 100 shown in FIGS.

  The branch portion 45 in this example has the same structure as the other portion of the gate trench portion 40, and is formed at the same depth as the other portion of the gate trench portion 40. For example, the branch portion 45 has a gate trench 46, an insulating film 42, a gate conductive portion 44, and a gate insulating portion 37. The branch 45 is provided to extend from a predetermined location of the gate trench 40 in a direction different from the direction in which the dummy trench 30 extends. As an example, the branch portion 45 is provided to extend from the gate trench portion 40 in a direction perpendicular to the extending direction. The branch 45 extends in a direction from the gate trench 40 to the dummy trench 30. However, the branch portion 45 is formed in a range that does not contact the dummy trench portion 30.

  The branch portion 32 of the dummy trench portion 30 in this example is formed in the emitter region 12 in a plan view. The branch 45 of the gate trench 40 is formed in the contact region 15 in a plan view. The branch portions 32 and the branch portions 45 may be provided alternately in the direction in which the main body portion 31 of the dummy trench portion 30 extends. With such a structure, the IE effect can be further enhanced.

  FIG. 11 is a diagram illustrating a cross section taken along line ee ′ of the semiconductor device 100. Note that the storage area 16 is omitted in FIG. The semiconductor device 100 of this example is different from the example shown in FIG. 4 in that the semiconductor device 100 further includes a branch 45, and the position of the branch 32 is different. Other structures are the same as the example shown in FIG. Note that the storage area 16 is omitted in FIG.

  Branch portion 45 of gate trench portion 40 is formed to penetrate contact region 15 from the surface of semiconductor substrate 10. The branch 45 further penetrates the base region 14. The branch 45 may further penetrate the accumulation region 16.

  Branch portion 32 of dummy trench portion 30 is formed to penetrate emitter region 12 from the surface of semiconductor substrate 10. The branch portion 32 further penetrates the base region 14. Branch 32 may further penetrate storage region 16. The branch 32 may be formed shallower than the branch 45. The branch 32 and the branch 45 may be formed shallower than the well region 17.

  FIG. 12 is a diagram illustrating a configuration of a semiconductor device 200 according to a comparative example. The semiconductor device 200 has a transistor section 270 and a diode section 280. On the front side of the semiconductor device 200, the gate electrode 250, the emitter electrode 252, the gate trench 240, the dummy trench 230, the emitter trench 260, the well region 217, the emitter region 212, the base region 214, the contact region 215, the contact It has holes 226, 228, 249, 254 and polysilicon layers 221, 225, 248.

  The dummy trench 230 is formed in a straight line and has no branch. For this reason, it is relatively difficult to enhance the IE effect. On the other hand, in the semiconductor device 100, since the dummy trench portion 30 has the branch portion 32, the IE effect can be easily enhanced.

  FIG. 13 shows a cross section taken along the line cc 'in FIG. The semiconductor device 200 has a semiconductor substrate 210, an emitter electrode 252, an insulating portion 238, and a collector electrode 224 in the cross section. Further, the gate terminal 251 is electrically connected to the gate conductive portion 244, and the emitter terminal 253 is electrically connected to the emitter electrode 252.

  On the semiconductor substrate 10, a gate trench 240, a dummy trench 230, an emitter trench 260, an emitter region 212, a base region 214, a storage region 216, a drift region 218, a buffer region 220, a collector region 222, and a cathode region 282 are formed. Is done. Gate trench section 240 has insulating film 242 and gate conductive section 244. The dummy trench section 230 has an insulating film 232 and a dummy conductive section 234. Emitter trench section 260 has insulating film 262 and emitter conductive section 264.

  In the semiconductor device 200, since the dummy conductive portion 234 is provided in the dummy trench portion 230, the insulation reliability of the insulating film 232 must be tested so that the dummy conductive portion 234 is not electrically connected to the semiconductor region of the semiconductor substrate 10. Is preferred. On the other hand, according to the semiconductor device 100 shown in FIG. 2, since the dummy conductive portion is not provided in the dummy trench portion 30, it is not necessary to test the insulation reliability of the dummy insulating portion 39.

  In the semiconductor device 200, the emitter region 212 is not exposed on the sidewall of the trench of the dummy trench portion 230. Therefore, emitter electrode 252 and emitter region 212 are in contact only on the surface of semiconductor substrate 210. When the semiconductor device 200 is miniaturized, the area of the emitter region 212 exposed on the surface of the semiconductor substrate 210 decreases, and the contact resistance between the emitter electrode 252 and the emitter region 212 increases.

  In the semiconductor device 200, the insulating portion 238 is formed on the surface of the semiconductor substrate 210. In this case, in order to reliably insulate gate conductive portion 244 and emitter electrode 252, insulating portion 238 is provided to cover a wider area than gate trench portion 240. That is, the insulating portion 238 covers a part of the surface of the emitter region 212. Therefore, the area of the emitter region 212 exposed on the surface of the semiconductor substrate 210 is further reduced. Therefore, in the semiconductor device 200, it is difficult to achieve both miniaturization of the semiconductor device and low on-voltage.

  On the other hand, according to semiconductor device 100 shown in FIG. 2, emitter electrode 52 can be in contact with the surface and side surface of emitter region 12. Therefore, even if the semiconductor device 100 is miniaturized, the contact resistance between the emitter electrode 52 and the emitter region 12 can be sufficiently reduced.

  According to the semiconductor device 100 shown in FIG. 2, the gate insulating portion 37 is formed in the gate trench, so that the gate insulating portion 37 does not cover the surface of the emitter region 12. For this reason, the contact area between the emitter electrode 52 and the emitter region 12 can be increased.

  FIG. 14 shows a dd ′ cross section in FIG. The semiconductor device 200 includes a semiconductor substrate 210, an emitter electrode 252, a gate electrode 250, a collector electrode 224, a polysilicon layer 221, a polysilicon layer 248, and an insulating portion 238 in the cross section.

  The polysilicon layer 221 and the polysilicon layer 248 are formed on the surface of the semiconductor substrate 210, and connect the conductive portion in each trench to the emitter electrode 252 or the gate electrode 250. The semiconductor device 200 has a polysilicon layer 221 and a polysilicon layer 248 selectively on the surface of the semiconductor substrate 210. Therefore, unevenness is generated on the surface of the semiconductor substrate 210, and it is not easy to form a layer such as the insulating portion 238 formed above the surface of the semiconductor substrate 210.

  On the other hand, according to the semiconductor device 100 shown in FIGS. 2 and 3, the emitter electrode 252 and the gate electrode 250 are in direct contact with the conductive portions in each trench, so that the polysilicon layer is formed on the surface of the semiconductor substrate 10. It is not necessary to provide. Therefore, unevenness on the surface of the semiconductor substrate 10 can be reduced.

  As described above, the present invention has been described using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is apparent to those skilled in the art that various changes or improvements can be made to the above embodiment. It is apparent from the description of the appended claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.

  Note that “upper” and “upper” and “lower” and “lower” in the claims or the specification indicate directions opposite to each other. However, the terms “up” and “up” are not limited to the direction opposite to the direction of gravity. Also, the terms “down” and “down” are not limited to the direction of gravity. For example, in a semiconductor device mounted on an electric device, it is obvious that the semiconductor device can be included in the present invention even when the gate electrode and the like are arranged on the ground-side surface of the semiconductor substrate. is there.

Reference Signs List 10: semiconductor substrate, 12: emitter region, 14: base region, 15: contact region, 16: accumulation region, 17: well region, 18: drift region, 20 ... buffer region, 22 ... collector region, 24 ... collector electrode, 26 ... interlayer insulating film, 30 ... dummy trench portion, 31 ... body portion, 32 ... branch portion 36: plug portion, 37: gate insulating portion, 38: dummy trench, 39: dummy insulating portion, 40: gate trench portion, 41: facing portion, 42: insulating Film, 43 projecting portion, 44 gate conductive portion, 45 branch portion, 46 gate trench, 50 gate electrode, 51 gate terminal, 52 emitter Electrode, 53 ... emitter terminal, 54 ... contour 55, contact hole, 56, plug portion, 60, emitter trench portion, 61, body portion, 62, branch portion, 68, emitter trench, 69, emitter Insulating part, 70 transistor part, 80 diode part, 82 cathode region, 90 floating region, 100 semiconductor device, 200 semiconductor device, 210 semiconductor Substrate, 212: Emitter region, 214: Base region, 215: Contact region, 216: Storage region, 217: Well region, 218: Drift region, 220: Buffer region 221: polysilicon layer 222: collector region 224: collector electrode 225: polysilicon layer 226: contact hole 228 contact hole, 230 dummy trench portion, 232 insulating film, 234 dummy conductive portion, 238 insulating portion, 240 gate trench portion, 242 insulating Film, 244: gate conductive portion, 248: polysilicon layer, 249: contact hole, 250: gate electrode, 251: gate terminal, 252: emitter electrode, 253 ... Emitter terminal, 254 contact hole, 260 emitter trench portion, 262 insulating film, 264 emitter conductive portion, 270 transistor portion, 280 diode portion, 282.・ Cathode area

Claims (21)

A first conductivity type semiconductor substrate;
A gate electrode and an emitter electrode provided above the surface of the semiconductor substrate;
A collector electrode provided on the back surface of the semiconductor substrate,
A main body formed on the surface of the semiconductor substrate and extending in a predetermined extending direction; and a main body formed on the surface of the semiconductor substrate and extending from the main body in a direction different from the extending direction. A dummy trench portion including the above branch portion;
A gate trench portion formed on a surface of the semiconductor substrate and connected to the gate electrode;
With
The semiconductor substrate, the disposed sequentially as viewed from the surface of the semiconductor substrate, and the emitter region of the first conductivity type, a second conductivity type base region, a drift region of a first conductivity type, the second conductivity type And a collector region of
The emitter region contacts the emitter electrode, the collector region contacts the collector electrode,
The dummy trench portion includes:
A dummy trench penetrating the emitter region and the base region from the surface of the semiconductor substrate;
And a dummy insulating portion provided in the dummy trench. The semiconductor device according to claim 1, wherein the dummy insulating portion is filled from a bottom of the dummy trench to a predetermined height in the dummy trench. The semiconductor device according to claim 2, wherein the branch portion extends in a direction orthogonal to the extension direction of the main body. The gate trench portion,
A gate trench penetrating the emitter region and the base region of the semiconductor substrate;
And a gate conductive portion provided inside the gate trench,
The body portion of the dummy trench is provided to face the gate trench,
The branch portion of the dummy trench is provided extending toward the gate trench,
The semiconductor device according to claim 2, wherein at least a part of the branch portion of the dummy trench is not in contact with the gate trench. The semiconductor substrate is connected to the base region, has a higher impurity concentration than the base region, and further includes a second conductivity type contact region exposed on the surface of the semiconductor substrate,
The semiconductor device according to claim 4, wherein at least a part of the branch is provided inside the contact region on a surface of the semiconductor substrate. The branch portion of at least a part of the dummy trench is provided inside the emitter region on a surface of the semiconductor substrate,
The semiconductor device according to claim 5, wherein the branch portion provided inside the emitter region on the surface of the semiconductor substrate is not in contact with the gate trench. The emitter region and the contact region are provided alternately along the extending direction in a region between the gate trench portion and the dummy trench portion on a surface of the semiconductor substrate,
The semiconductor device according to claim 6, wherein on the surface of the semiconductor substrate, the number of the branch portions provided in the contact region is larger than the number of the branch portions provided in the emitter region. The semiconductor device according to claim 7, wherein an interval between the branch portions in the extending direction of the main body portion is constant. The semiconductor device according to claim 4, wherein a length of the branch portion is equal to or longer than a half of a distance between the main body portion of the dummy trench and the gate trench. The semiconductor device according to claim 4, wherein an interval between the branch portions in the extending direction of the main body portion is smaller than a distance between the main body portion and the gate trench. The semiconductor device according to claim 4, wherein the dummy trench is formed to a position shallower than the gate trench. The semiconductor device according to claim 11, wherein a width of the dummy trench is smaller than a width of the gate trench. The semiconductor substrate further includes a first conductivity type accumulation region provided on the back surface side of the base region and having a higher impurity concentration than the semiconductor substrate.
The semiconductor device according to claim 4, wherein the dummy trench further penetrates the storage region. 14. The semiconductor device according to claim 4, wherein the semiconductor substrate further has a second conductivity type floating region separated from the base region in a region adjacent to a bottom of the dummy trench. 15.   The semiconductor device according to claim 14, wherein a bottom of the floating region is provided at a position deeper than a bottom of the gate trench. The semiconductor substrate is provided outside the emitter region on the surface of the semiconductor substrate, and further includes a second conductivity type well region having a higher impurity concentration than the base region,
The dummy trench of the branch portion provided at a position closest to the well region in the extending direction is formed to a position deeper than the dummy trench of another branch portion. 13. The semiconductor device according to item 9. The semiconductor device according to claim 16, wherein a width of the dummy trench in the branch closest to the well region is larger than a width of the dummy trench in another branch. The dummy insulating portion is filled in the dummy trench such that at least a part of the emitter region is exposed on a sidewall of the dummy trench,
The semiconductor device according to claim 4, wherein the emitter electrode is also in contact with the emitter region on a side wall of the dummy trench. 19. The semiconductor device according to claim 18, wherein the gate trench portion further includes a gate insulating portion provided above the gate conductive portion inside the gate trench and insulating the emitter electrode and the gate conductive portion. The semiconductor device according to claim 4, wherein the gate trench portion includes one or more branch portions extending in a direction different from the extending direction.   The branch portion of the dummy trench portion penetrates the emitter region and the base region from a surface of the semiconductor substrate.
  The semiconductor device according to claim 1.

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