JP6665456B2 - Power semiconductor device - Google Patents

Description

  The present invention relates to a power semiconductor device in which a three-phase inverter including a power semiconductor element such as an IGBT with six arms is housed in one module or package, or mounted on one circuit board.

  FIG. 6 shows a main circuit diagram of a general three-phase inverter system using a power semiconductor element such as an IGBT. Reference numeral 1 denotes a DC power supply circuit such as a battery. When the DC power supply circuit 1 is constituted by an AC power supply, the DC power supply circuit 1 can be realized by a rectifier (not shown) and a large-capacity capacitor. Reference numeral 2 denotes a three-phase inverter circuit including an IGBT for converting DC to AC and a diode. Reference numeral 3 denotes a wiring inductance Ls between the DC power supply circuit 1 and the inverter circuit 2, and reference numeral 4 denotes a load such as a motor. The three-phase inverter circuit 2 includes six bridge-connected arms, and each phase has a positive DC terminal (P) and a negative DC terminal (N) of the DC power supply circuit 1 and an AC terminal (U, V) of the phase. , W) between the upper arm and the lower arm. Each arm includes an IGBT 5, a diode 6 connected in anti-parallel to the IGBT 5, a gate drive circuit 7 (actually, Are connected to each IGBT element). By inputting an IGBT on / off command signal 8 from a control circuit (not shown) to each gate drive circuit 7, the IGBT 5 is turned on / off and outputs a desired voltage and frequency to an AC terminal 9 (U, V, W). be able to.

  FIG. 7-1 is a circuit diagram showing a first conventional example of a power semiconductor device in which the three-phase inverter circuit of FIG. 6 is housed in a single package (gate signal lines are not shown; Is the same in the examples of the other figures described below). According to this circuit structure, three AC terminals U, V, and W and a pair of DC terminals P and N are provided in one package or module 10. The feature of this structure is that the P potential wiring and the N potential wiring are shared for each of the three phases inside the package 10. Various modules are known as power semiconductor devices having this kind of characteristic point (for example, see Patent Document 1, Patent Document 2, and Patent Document 3). FIG. 8A is a plan view showing an example of the module. According to this, the AC terminals U, V, and W are arranged on the edge forming the first side of the module 10, and the DC terminals P and N are arranged on the edge forming the second side adjacent thereto (brake). A B terminal, which is a terminal, is also shown, but it is assumed that there is no B terminal because it is not directly related to the present invention).

  FIG. 7-2 is a circuit diagram showing a second conventional example of a power semiconductor device in which the three-phase inverter circuit of FIG. 6 is housed in one package. According to this circuit structure, three AC terminals U, V, and W and two pairs of DC terminals P1, N1 and P2, N2 are provided in one package 10. This type of module is known (for example, see Non-Patent Document 1, Patent Document 4, Patent Document 5, and Patent Document 6), and FIG. 8B is a plan view of an actual module example. According to this, the AC terminals U, V, W are arranged at the edges forming the first side of the module, and the DC terminals P1, N1 and P2, N2 are formed at the edges forming the two sides adjacent to the first side. (Although the B terminal as a brake terminal is also shown in the figure, it is assumed that there is no B terminal because it is not directly related to the present invention.)

FIG. 9 is a circuit diagram showing a third conventional example of a power semiconductor device in which the three-phase inverter circuit of FIG. 6 is housed in one module. FIG. 10 shows a schematic view thereof, and FIG. 11 shows a plan view of an actual module example. As described above, the circuit in the module is divided into each phase, and one package 10 is structurally divided into three phase blocks 21, 22, 23, and each phase block has an IGBT and a diode for one phase of the upper and lower arms. Besides, a configuration in which a pair of DC terminals is provided is known (for example, refer to Patent Literature 7, Patent Literature 8, Non-Patent Literature 1). As a DC terminal, one positive DC terminal and one negative DC terminal are provided for each phase block. That is, a total of six terminals are provided, such as P1, N1 for the U-phase block, P2, N2 for the V-phase block, and P3, N3 for the W-phase block. As AC terminals, _W 1, _{W 2} is provided on the _{V 1, V 2,} W-phase to _{U 1, U} 2, V-phase to the U phase. The two AC terminals of each phase are short-circuited inside the module, as can be seen from the schematic diagram of FIG. Therefore, it is not always necessary to use two AC terminals for each phase. The AC terminals U ₁ , U ₂ , V ₁ , V ₂ , W ₁ , and W ₂ are arranged on an edge that forms a first side of the module 10, and an edge that forms a second side that faces the first side is Six DC terminals P1, N1, P2, N2, P3, and N3 are arranged.

FIG. 12 shows an example of the arrangement of actual components and members inside the module in the conventional power semiconductor device shown in FIG. In the module 10, a U-phase block 21, a V-phase block 22, and a W-phase block 23 having exactly the same configuration are arranged adjacently in this order in the vertical direction in the plane of the drawing. Each of the phase blocks is represented by a reference numeral U phase as a representative, and the upper arm IGBT chip 34, the upper arm diode chip 35, the lower arm IGBT chip 36, the lower arm diode chip 37, and each DCB pattern (positive (A side potential pattern 31, a negative side potential pattern 32, a phase potential pattern 33), and wire wiring for wiring between each chip and each DCB pattern. In each of the phase blocks 21, 22, 23, the positive potential pattern 31 is connected to the positive DC terminal P1, P2 or P3 belonging to the corresponding phase, and the negative potential pattern 31 is connected to the negative DC terminal belonging to the corresponding phase. It is connected to the terminal N1, N2 or N3, phase potential pattern 33, the AC terminal _U, respectively belonging to the phase _(U 1, U 2), to _{V (V} 1, _{V 2)} or _{W (W} 1, _{W 2)} It is connected.

FIG. 13 illustrates the collector-emitter voltage waveform V _CE and the collector current waveform i _C of the IGBT when the IGBT is interrupted (turned off) as a lapse of time t. With the wiring inductor Ls and the current change rate di / dt at the time of interruption, the DC voltage Ed
ΔV _CE = Ls · di _C / dt (1)
Minute surge voltage occurs. System design, withstand voltage IGBT needs, taking into account the surge voltage, there needs to be more than the maximum ultimate value of Ed + ΔV _CE. That is, in order to prevent the required breakdown voltage of the IGBT from unnecessarily increasing, it is necessary to reduce the wiring inductance Ls.

  In order to solve such a problem, in a system having a pair of DC terminals as shown in FIGS. 7-1 and 8-1, the wiring length for the positive potential and the negative potential is increased in the module, and thus the wiring inductance is increased. There is a problem that Ls becomes large, and it is not suitable for a large current system having a large di / dt at the time of interruption. Further, since there is only one pair of wirings of the DC section, there is a problem that the switching of the other phase has a common impedance structure that affects the own phase.

  The above problem can be solved to some extent by adopting a configuration as shown in FIGS. 7-2 and 8-2. However, since the two pairs of DC terminals are arranged on both sides of the module, a DC capacitor is provided. There is a problem that wiring to the device becomes complicated.

  In addition, in FIG. 7-1 or FIG. 7-2, a portion where the wiring inside the module (in the substrate) intersects as in a region 25 indicated by a dotted line in FIG. It is necessary to perform a three-dimensional intersection depending on the wiring structure inside the module (in the case of a board configuration, by a multilayer board configuration).

  On the other hand, in a system in which DC wiring is individually performed for each phase as shown in FIGS. 9 to 12, the above problem is largely solved. FIG. 14 shows the individual components of each phase from the module 10 to the external large DC capacitors 41, 42, 43 attached to each phase via a pair of wiring conductors 44, 45, 46, 47 or 48, 49, respectively. Shows an example of wiring. In the case of this structure, since the positive DC wiring and the negative DC wiring of each phase are close to each other, mutual inductance is generated, thereby reducing the inductance. Further, as shown in FIG. 15, by laminating one positive DC wiring board 441 common to each phase and one negative DC wiring board 442 common to each phase, it is possible to further reduce inductance. . Further, it is possible to configure the wiring without crossing the wiring inside the module (or inside the substrate). However, in this configuration, there are problems such as an increase in cost due to a large number of terminals, an increase in the number of external wirings, and an increase in complexity.

JP 2001-237369 A JP 2005-191233 A JP 2005-347561 A JP 2001-144251 A JP-A-7-111310 JP 2008-166421 A JP 2009-219273 A JP 2003-31738 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide a power semiconductor device which realizes a reduction in wiring inductance and avoids a three-dimensional crossover wiring, and also enables a reduction in size and cost of the device.

  According to the present invention, there is provided a power semiconductor device in which a three-phase inverter having a power semiconductor element composed of six arms is housed in one module or package, or mounted on one circuit board. The first-phase block, the second-phase block, and the third-phase block are arranged side by side in this order, the outer first-phase block and the third-phase block are arranged in the same direction, and the first-phase block and the third-phase block are arranged. The power semiconductor device is characterized in that the second phase block between the first and third phase blocks is inverted with respect to both the first and third phase blocks so as to be substantially line-symmetric with each other.

  The present invention starts from a conventional DC six-terminal structure in which the first phase block, the second phase block, and the third phase block are arranged in this order in the same direction, and only the second phase block is reversed. If the arrangement is changed so that the second phase block is invertedly arranged so that the second phase block is axisymmetric with respect to both the first phase block and the third phase block, the wiring inductance This is based on the idea that the number of DC terminals can be reduced without impairing the advantages of the conventional DC 6-terminal configuration of reducing the number of wires and avoiding the three-dimensional cross wiring.

  To explain this idea more specifically, in the case of the conventional DC six-terminal configuration, the proper arrangement of the six DC terminals is, for example, the first phase positive terminal → the first phase negative terminal → the second phase positive terminal. In the present invention, the side terminal → the second phase negative side terminal → the third phase positive side terminal → the third phase negative side terminal, whereas in the case of the present invention, the first phase positive side terminal → the first phase negative side terminal → The second-phase negative terminal → the second-phase positive terminal → the third-phase positive terminal → the third-phase negative terminal. As can be seen, the negative terminal of the first phase and the negative terminal of the second phase are adjacent to each other and at the same negative potential, so that they can be easily integrated into one common negative DC terminal. Similarly, since the second-phase positive terminal and the third-phase positive terminal are adjacent to each other and have the same positive potential, they can be easily integrated into one common positive DC terminal. Through this integration, the number of DC terminals can be reduced to four without impairing the advantages of the conventional DC six-terminal configuration of reducing wiring inductance and avoiding three-dimensional cross wiring.

  Therefore, according to the embodiment of the power semiconductor device according to the present invention, two positive DC terminals and two negative DC terminals are provided as DC terminals, and the first positive DC terminal and the second positive DC terminal are provided in the first phase block. 1, a first negative DC terminal and a second positive DC terminal are allocated to the second phase block, and a second positive DC terminal and a second negative DC terminal are allocated to the third phase block. By allocating DC terminals, a DC four-terminal configuration can be advantageously realized.

  Furthermore, according to the embodiment of the power semiconductor device according to the present invention, the first positive DC terminal and the first negative DC terminal, the first negative DC terminal and the second positive DC terminal, and the second By arranging the positive-side DC terminal and the second negative-side DC terminal close to each other and arranging the four terminals side by side along an edge forming one side of a module, a package, or a circuit board. The advantages of reducing inductance and avoiding crossover wiring can be realized advantageously.

  According to another advantageous embodiment of the invention, each phase block in the module comprises a positive potential pattern, a negative potential pattern and a phase potential pattern, respectively, wherein the positive potential pattern of the first phase block is the first potential block. The negative potential pattern of the first phase block and the negative potential pattern of the second phase block are connected to the first negative DC terminal in common, and the positive potential pattern of the second phase block is connected to the positive potential pattern of the second phase block. The positive potential pattern of the three-phase block is commonly connected to a second positive DC terminal, and the negative potential pattern of the third phase block is connected to a second negative DC terminal. Thereby, the size and cost of the apparatus can be advantageously reduced. In this case, the negative potential pattern of the first phase block and the negative potential pattern of the second phase block are integrally formed into one common negative potential pattern, and the positive potential pattern of the second phase block and the positive potential pattern of the third phase block. It is particularly advantageous if the potential pattern is formed integrally with one common positive potential pattern.

  Further, of the power semiconductor chips forming the upper arm and the lower arm in each phase block in the module, one power semiconductor chip is mounted on the positive potential pattern or the negative potential pattern in the corresponding phase block, and the other power semiconductor chip is mounted on the other power block. Preferably, the semiconductor chip is mounted on a phase potential pattern in a corresponding phase block, and necessary wiring between the power semiconductor chip and each potential pattern is performed by wire wiring. In this case, the power semiconductor chip may be composed of an IGBT chip and a diode chip.

  According to the present invention, the first phase block, the second phase block, and the third phase block are arranged in this order, and the outer first phase block and the third phase block are arranged in the same direction as each other. The second phase block located between the phase block and the third phase block is invertedly arranged so as to be substantially line-symmetric with respect to the first phase block and the third phase block, thereby reducing wiring inductance and increasing the three-dimensional structure. A four-terminal configuration that is advantageous for miniaturization and cost reduction of the device can be obtained without impairing the advantage of the DC six-terminal configuration of avoiding cross wiring. Also, compared to the conventional configuration in which the DC terminal is one terminal or two terminals on the positive side and the negative side, respectively, it is possible to reduce the wiring inductance and to simplify the wiring structure such as avoiding a three-dimensional cross wiring, and the system is compact. And cost reduction can be achieved.

1 is a schematic diagram showing a first embodiment of a power semiconductor device according to the present invention. 2 is a schematic view showing a second embodiment of the power semiconductor device according to the present invention. FIG. 2 is a schematic diagram showing an example of wiring between a power semiconductor device and a DC capacitor according to the present invention. Arrangement diagram showing a first arrangement example of components and members inside a module of a power semiconductor device according to the present invention. Layout diagram showing a second layout example of components and members inside a module of a power semiconductor device according to the present invention. Circuit diagram showing a general three-phase inverter using a power semiconductor element Circuit diagram showing a first conventional example of a power semiconductor device including a three-phase inverter Circuit diagram showing a second conventional example of a power semiconductor device including a three-phase inverter FIG. 7A is a plan view showing an actual module example of the power semiconductor device according to FIG. FIG. 7B is a plan view showing an actual module example of the power semiconductor device according to FIG. Circuit diagram showing a third conventional example of a power semiconductor device including a three-phase inverter Schematic diagram of the power semiconductor device according to FIG. FIG. 9 is a plan view showing an actual module example of the power semiconductor device according to FIG. 9. Layout of components and members inside the module of the power semiconductor device according to FIG. 9 Voltage and current waveform diagram when IGBT is turned off Schematic diagram showing an example of wiring between the module shown in FIG. 10 and a DC capacitor Schematic diagram showing another example of wiring between the module shown in FIG. 10 and a DC capacitor FIG. 16 is a circuit diagram for explaining one of the problems in the prior art.

  1 and 2 are schematic views showing different embodiments of a semiconductor device having a power conversion circuit constituted according to the present invention. FIG. 1 shows a first embodiment composed of modules, and FIG. 2 shows a second embodiment composed of substrates.

  The inverter circuit in the module 10 in FIG. 1 or the circuit board 10 in FIG. 2 is configured as a three-phase bridge circuit composed of six arms as a whole, and is divided into phase blocks attached to the respective phases U, V, and W. Each phase block is composed of a series connection circuit of an upper arm on the positive (P) side and a lower arm on the negative (N) side, and the power semiconductor forming each arm is configured as, for example, a parallel circuit of an IGBT and a freewheel diode. Have been. Note that a MOSFET can be used as the power semiconductor.

  In the power semiconductor device shown in FIGS. 1 and 2, a first phase block (here, a U-phase block) 21 and a second phase block (here, a U-phase block) 21 are arranged at least at substantially equal intervals in the vertical direction in the drawing plane shown here. Here, a V-phase block 22 and a third-phase block (here, a W-phase block) 23 are arranged in this order. The two outer phase blocks, namely the U-phase block 21 and the W-phase block 23, are structurally oriented in the same direction. On the other hand, the V-phase block 22 between the U-phase block 21 and the W-phase block 23 is structurally turned in the opposite direction to the U-phase block 21 and the W-phase block 23. That is, the V-phase block 23 is invertedly disposed so as to be line-symmetric with respect to both the U-phase block 21 and the V-phase block 23.

In order to connect the inverter circuit in the module to an external element, a pair of AC terminals U ₁ , U ₂ , V ₁ , V _{2 of} each pair of phases are provided on the left side edge of the module or the board 10 as a first side shown in the drawing. , W ₁ , W ₂ (FIG. 1) or one AC terminal U, V, W for each phase (FIG. 2). In the embodiment of FIG. 1, the two AC terminals of each phase are short-circuited to each other inside the module, so that it is not always necessary to have two terminals of each phase. The AC terminal of each phase is connected to a common connection portion of the upper and lower arms, that is, a U-phase potential portion, a V-phase potential portion, and a W-phase potential portion in each phase block 21, 22, 23.

Further, all the DC terminals are arranged in close proximity in an appropriate order to the right side edge of the module or the substrate 10 as a second side facing the first side in the drawing. That is, the first positive-side DC terminals _{(P 1} terminal), the first negative DC terminal _{(N 12} terminals), a second positive DC terminals _{(P 23} terminal), a second negative-side DC terminal (N ₃ terminals) are arranged in this order. That is, the first and positive side DC terminal P ₁ and the first negative-side DC terminal N ₁₂ is disposed near, the first negative-side DC terminal N ₁₂ second positive-side DC terminals P ₂₃ and is disposed close is, the second positive-side DC terminal P ₂₃ is a second negative-side DC terminal N ₃ are arranged close. P ₁ terminal to the positive potential portion of the U-phase block _21, a positive _{N 12} terminal to the lower voltage portions of the U-phase block 21 and the V-phase block _{22, P 23} pin V-phase block 22 and the W-phase block 23 the side potential portion, and N ₃ terminal is connected to the negative potential portion of the W-phase block 23. _{Therefore, N 12} terminal is shared by the U-phase block 21 and the V-phase block _{22, P 23} terminal is shared and V-phase block 22 and W-phase block 23. Thus, thanks to the line-symmetrical arrangement of adjacent phase blocks, a four-terminal configuration in which the positive side and the negative side are alternately arranged and closely arranged is possible. As a result, the number of DC terminals can be reduced from six terminals (see FIG. 10) to four terminals without impairing the advantage of the six-terminal configuration of reducing the wiring inductance and avoiding an internal three-dimensional cross connection.

When wiring to an external DC capacitor is performed by such arrangement of DC terminals, only four wiring conductors are required as shown in FIG. That is, positive electrode connected to the P ₁ terminal via the wiring conductor 53 of the first capacitor 51, the negative pole is connected to the N ₁₂ terminal through a wiring conductor 54 of the first capacitor 51, second capacitor 52 positive electrode via a wiring conductor 55 is connected to the P ₂₃ terminal, the negative electrode of the second capacitor 52 is connected to the N ₃ terminal through a wiring conductor 56. And P ₁ wiring conductor and N ₁₂ wiring conductor, and an N ₁₂ wiring conductor and P ₂₃ wire conductors, since P ₂₃ wiring conductors and N ₃ wiring conductor and a can be close respectively, which phase is also switched Low inductance switching can be achieved, and a low surge voltage can be achieved (FIG. 3 symbolically depicts an inductance reduction effect due to magnetic coupling between adjacent wiring conductors).

  FIGS. 4 and 5 show the actual components and members inside the module with respect to the power semiconductor device according to the present invention in which the V-phase block is arranged to be line-symmetrically inverted with respect to both the U-phase block and the W-phase block. The following shows an example of the arrangement. In the module 10, similarly to the prior art described with reference to FIG. 12, each phase block of the module 10 is composed of a U-phase block 21, a V-phase block 22, and a W-phase block 23 having exactly the same configuration in the vertical direction in the drawing plane. , In this order. As in the prior art described with reference to FIG. 12, each phase block has an upper arm IGBT chip 34, an upper arm diode chip 35, a lower arm IGBT chip 36, a lower arm diode chip 37, each DCB pattern (positive potential pattern 31, negative potential pattern 32, phase potential pattern 33), wire wiring for wiring between each chip and each DCB pattern, and the like. . However, unlike the prior art described with reference to FIG. 12, only the V-phase block 22 is directed in the opposite direction to the other two phase blocks 21 and 23. That is, the V-phase block 22 is invertedly arranged so as to be at least substantially line-symmetric with respect to both the U-phase block 21 and the W-phase block 23.

In FIG. 4, a pair of DC terminals P ₁ , N ₁ , P ₂ , N ₂ , P ₃ , and N ₃ are provided for each of the phase blocks U, V, and W, and have a six-terminal configuration. In the conventional six-terminal configuration (see FIG. 12), the DC terminal is P1 (positive potential) → N1 (negative potential) → P2 (positive potential) → N2 (negative potential) → P3 (positive potential). ) → N3 (negative-side potential), but according to the present invention, the V-phase block 22 is inverted and arranged to be line-symmetric with respect to the U-phase block 21 and the W-phase block 23. As a result, as shown in FIG. 4, the DC terminal is changed from P ₁ (positive potential) → N ₁ (negative potential) → N ₂ (negative potential) → P ₂ (positive potential) → P ₃ (positive potential) → N ₃ (negative potential).

Thus, the DC terminals N ₁ and N ₂ adjacent to the same negative side potential because, can be integrated into one common terminal N ₁₂ as shown in FIG. 5, a negative potential pattern of U-phase block 21 accordingly 32 and the negative potential pattern 32 of the V-phase block 22 can also be integrated into one common negative potential pattern 32 '. Further, the adjacent DC terminals P ₂ and P ₃ can be integrated into one common terminal P ₂₃ as shown in FIG. 5 because of the same positive potential, and accordingly, the positive potential pattern of the V-phase block 22 31 and the positive potential pattern 31 of the W-phase block 23 can also be integrated into one common negative potential pattern 31 '. Thereby, it is possible to further reduce the size and cost of the power semiconductor device.

  As described above, according to the present invention, the three-phase inverter (2) including the power semiconductor elements (5, 6, 34, 35) with six arms is housed in one module or package (10). Alternatively, in a power semiconductor device mounted on one circuit board (10), a first phase block (21), a second phase block (22), and a third phase block (23) are arranged in this order, and The first phase block (21) and the third phase block (23) are arranged in the same direction, and the second phase block (23) between the first phase block (21) and the third phase block (23). 22) is to reduce wiring inductance and to avoid crossover wiring by arranging the first phase block (21) and the third phase block (23) in an inverted manner so as to be substantially line-symmetric with each other. Without sacrificing the benefits of flow 6 pin configuration, the number of DC terminals, a sixth terminal, it is possible to reduce downsizing of the apparatus, advantageously 4 terminals for cost reduction.

Reference Signs List 1 DC power supply circuit 2 3-phase inverter circuit 3 Wiring inductance 4 Load 5 IGBT
6 Diode 7 Gate drive circuit 8 ON / OFF command signal 9 AC output terminal 10 Module or package, or circuit board 21 First phase block (U-phase block)
22 2nd phase block (V phase block)
23 Third phase block (W phase block)
31 P potential pattern 32 N potential pattern 33 Phase potential pattern 34 Upper arm IGBT chip 35 Upper arm diode chip 36 Lower arm IGBT chip 37 Lower arm diode chip 51, 52 DC capacitors 53 to 56 for external connection 53 to 56 Connecting conductor pieces P ₁ to P ₃ , P ₂₃ Positive DC terminals N _{1 to} N ₃ , N ₁₂ Negative DC terminals U, U ₁ , U ₂ U-phase AC terminals V, V ₁ , V ₂ V-phase AC terminals W, W ₁ , W ₂ W-phase AC terminal

Claims (6)

In a power semiconductor device in which a three-phase inverter composed of six arms of a power semiconductor element is housed in one module or package, or mounted on one circuit board,
The first phase block, the second phase block, and the third phase block having the same configuration as the first phase block are arranged in this order, and the outer first phase block and the third phase block are arranged in the same direction as each other, The second phase block between the first phase block and the third phase block is invertedly disposed so as to be substantially line-symmetric with respect to each of the first phase block and the third phase block,
Two positive DC terminals and two negative DC terminals are provided as DC terminals, a first positive DC terminal and a first negative DC terminal are assigned to the first phase block, and the first phase DC terminal is assigned to the second phase block. , A second positive DC terminal and a second negative DC terminal are assigned to the third phase block, and a second negative DC terminal and a second negative DC terminal are assigned to the third phase block.
First positive side DC terminal, the first negative DC terminal, a power semiconductor device in which the second positive-side DC terminal and a second negative-side DC terminal is characterized in that it is arranged close in this order.   A first positive DC terminal, a first negative DC terminal, a second positive DC terminal, and a second negative DC terminal are arranged side by side along an edge forming one side of a module, package, or circuit board. The power semiconductor device according to claim 1, wherein   Each phase block in the module includes a positive potential pattern, a negative potential pattern, and a phase potential pattern. The positive potential pattern of the first phase block is connected to the first positive DC terminal, and the negative potential of the first phase block is controlled. The potential pattern and the negative potential pattern of the second phase block are connected to the first negative DC terminal, and the positive potential pattern of the second phase block and the positive potential pattern of the third phase block are connected to the second positive DC terminal. The negative potential pattern of the third phase block is connected to the second negative DC terminal, and the phase potential pattern of each phase is connected to the AC terminal of the corresponding phase. 3. The power semiconductor device according to 2.   The negative potential pattern of the first phase block and the negative potential pattern of the second phase block are integrally formed into one common negative potential pattern, and the positive potential pattern of the second phase block and the positive potential pattern of the third phase block are 4. The power semiconductor device according to claim 3, wherein the power semiconductor device is formed integrally with one common positive potential pattern.   Of the power semiconductor chips forming the upper arm and the lower arm in each phase block in the module, one power semiconductor chip is mounted on a positive potential pattern or a negative potential pattern in the corresponding phase block, and the other power semiconductor chip 5. The power according to claim 3, wherein the power supply is mounted on a phase potential pattern in a corresponding phase block, and necessary wiring between the power semiconductor chip and each potential pattern is performed by wire wiring. Semiconductor device. The power semiconductor device according to any one of claims 3 to 5, wherein the power semiconductor chip includes an IGBT chip and a diode chip.

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