JP6640773B2 - Time digital converter - Google Patents

Description

  The technology disclosed in this specification relates to a time-to-digital converter (Time-to-Digital Converter). In particular, it relates to a technique for increasing the resolution of a time-to-digital converter.

  A time-to-digital converter capable of outputting a predetermined time interval as a digital signal is known. Time-to-digital converters have two advantages because they can convert time intervals directly into digital signals. One is that time intervals can be measured with high resolution. Another is that it can be made up of digital elements and is therefore suitable for miniaturization.

  The technology of the time digital converter is used for, for example, a temperature sensor (for example, Patent Document 1). The temperature sensor disclosed in Patent Document 1 includes a delay circuit, a clock circuit, and a counter circuit. The delay circuit has an inverter chain in which a plurality of inverters are connected in series, and outputs a delay trigger signal having a delay trigger timing obtained by delaying the input trigger timing of the input trigger signal according to the number of stages of the inverter chain. . The counter circuit counts the number of clocks of the clock signal output by the clock circuit between the input trigger timing and the delay trigger timing. The time from the input trigger timing to the delay trigger timing is obtained as a digital value as the number of clocks. The operation speed of the inverter of the delay circuit has a temperature dependency, and the temperature sensor of Patent Document 1 utilizes the temperature dependency. The time from the input trigger timing to the delay trigger timing changes depending on the environmental temperature of the delay circuit. Therefore, the number of clocks output by the counter circuit has a correlation with the ambient temperature of the delay circuit. By obtaining the correlation in advance, the ambient temperature of the delay circuit can be obtained from the number of clocks.

  One of the features of the time-to-digital converter is high resolution, but its accuracy is also limited. In the time digital converter, a quantization error occurs when the time interval from the input trigger timing to the delay trigger timing is digitized by the number of clocks. Specifically, the quantization error depends on the operation speed of the inverter provided in the clock circuit and the delay circuit.

  On the other hand, as a technique for reducing the quantization error, a technique called dithering for applying a low-pass filter to data obtained by intentionally adding noise to a digital processing circuit is known. It has been proposed to apply a dithering technique to a time-to-digital converter (Patent Document 2). In that technique, more accurate measurement results are obtained by averaging a plurality of measurement results obtained by randomly changing the delay time.

  Patent Document 2 does not disclose any specific means for randomly changing the delay time. On the other hand, Patent Document 3 discloses an example of the technique. Patent Document 3 makes use of the fact that the operating speed (that is, delay time) of an inverter depends on a supply voltage. That is, in the technique of Patent Document 3, a voltage including noise is generated, and the voltage is applied to the inverter.

JP 2013-185985 A JP 2011-526752 A JP 2014-217064 A

  In the technique of Patent Document 3, after generating a digital signal including fluctuation, the digital signal is converted into an analog signal, and a supply voltage including noise is generated through a low-pass filter and an amplifier. As described above, one advantage of the time-to-digital converter is that it is suitable for miniaturization because most of the components can be constituted by digital elements. However, the technique of Patent Document 3 uses some analog elements, and thus hinders the advantage of the time-to-digital converter of miniaturization. The present specification provides a time-to-digital converter that can introduce dithering simply by adding a simple configuration and that has improved resolution without using many analog elements.

The time-to-digital converter disclosed in this specification includes a clock circuit, a delay circuit, a counter circuit, an average calculation circuit, and a resistance element. The clock circuit includes a ring oscillator in which a plurality of first CMOS inverters are connected in a ring, and outputs a clock signal according to an output change of the first CMOS inverter. The delay circuit includes an inverter chain in which a plurality of second CMOS inverters are connected in series, and outputs a delay trigger signal having a delay trigger timing obtained by delaying an input trigger timing of an input trigger signal according to the number of stages of the inverter chain. Output. The operation speed of the plurality of second CMOS inverters depends on the supply voltage. The counter circuit receives the input trigger signal, the delay trigger signal, and the clock signal, and counts the number of clock signals between the input trigger timing included in the input trigger signal and the delay trigger timing included in the delay trigger signal. Count. The average calculation circuit calculates a moving average of the number of clocks corresponding to each of the plurality of input trigger timings included in the input trigger signal, and outputs the calculated moving average as a digital value of the delay time of the delay circuit . One end of the resistance element is connected to the power supply, and the other end is connected to the voltage supply terminals of the first CMOS inverter and the second CMOS inverter. Note that a CMOS inverter is an abbreviation of a complementary metal oxide semiconductor inverter, and is a circuit in which an n-type MOS transistor and a p-type MOS transistor are connected in series.

The time-to-digital converter disclosed in this specification uses a CMOS inverter for a clock circuit. The CMOS inverter is configured by connecting two transistors in series, one end of the series connection is connected to a resistance element as a voltage supply end, and the other end is connected to a ground end. In the series connection of the CMOS inverters , no current flows while the output is held, but a through current flows when the output changes. When the through current flows, the voltage at the voltage supply terminal of the CMOS inverter decreases. When the magnitude of the through current is represented by IPr and the resistance value of the resistance element is represented by R, the voltage fluctuation value on the current downstream side of the resistance element becomes Ipr × R [volt] due to the through current Ipr. The voltage on the current downstream side of the resistance element is equal to the voltage supplied to the second CMOS inverter of the delay circuit. That is, the supply voltage of the CMOS inverter of the delay circuit changes by Ipr × R [volt] due to the through current Ipr when the output of the CMOS inverter in the clock circuit changes. In other words, noise of Ipr × R [volt] is added to the supply voltage. Since the operation speed of the second CMOS inverter of the delay circuit depends on the supply voltage, the operation speed of the delay circuit changes due to a change (noise) in the supply voltage, and the delay trigger timing of the delay trigger signal output from the delay circuit changes. . Since the delay trigger timing changes, the number of clocks counted by the counter circuit changes. By calculating the moving average of the number of clocks corresponding to each of the plurality of input trigger timings included in the input trigger signal, the delay time (from the input trigger timing to the delay trigger timing Time) can be measured. This time-to-digital converter realizes high accuracy by dithering by superimposing noise on the supply voltage to the delay circuit by a clock circuit and a resistance element.

  As described above, the time-to-digital converter disclosed in the present specification can be realized with a simple configuration in which a resistance element is added between the first and second CMOSs and the power supply. In other words, the technology disclosed in the present specification provides a time-to-digital converter with improved resolution without using many analog elements. Hereinafter, in order to distinguish the above-described resistance element from other resistance elements, it is referred to as a noise-inducing resistance element for convenience.

  As is apparent from the above description, the resistance value R of the noise-inducing resistance element corresponds to a voltage variation value obtained by multiplying the through current Ipr flowing when the output of the first CMOS inverter changes (when the output is inverted) by the resistance value R. The time change of the delay trigger timing is set to be equal to or longer than a half cycle of the clock signal. By setting the resistance value R of the noise-inducing resistance element as such, the number of clocks to be counted always changes according to the above-described voltage fluctuation value (Ipr × R). As a result, quantization errors can be reduced by dithering, and higher resolution can be reliably obtained.

  The resistance value R of the noise-inducing resistance element is specifically set to 50 ohms or more. For example, when the current Ipr flowing when the output of the first CMOS inverter changes is 0.2 [mA], the voltage change is 50 × 0.2 = 10 [mV]. Since the drive voltage (supply voltage) of the CMOS inverter is approximately 1 to 5 volts, the voltage change (that is, the noise amplitude) is about 1/100 to 1/500 of the supply voltage. When a noise of this size is added to the supply voltage, the delay time of the delay circuit (the time from the input trigger timing to the delay trigger timing) changes by about a half cycle of one clock (or more). If the delay time is shifted by more than a half cycle of the clock, the measured clock number is shifted by at least one clock. The number of clocks from the input trigger timing to the delay trigger timing fluctuates due to noise. When a moving average of the number of clocks (a plurality of clocks with fluctuations) corresponding to each of a plurality of input trigger timings arranged in time series is obtained, the quantization error of the time-to-digital converter is reduced, and a high resolution is obtained. .

  In the time-to-digital converter described above, the operation of the clock circuit adds noise (voltage fluctuation) to the supply voltage to the delay circuit. The time-to-digital converter disclosed in the present specification may include the following sub-clock circuit so that noise for dithering is added to the supply voltage to the first CMOS inverter of the clock circuit. The sub clock circuit includes another ring oscillator in which a plurality of third CMOS inverters are connected in a ring. The voltage supply terminal of the third CMOS inverter is connected to the other end of the above-described resistance element. The operation speed of the first CMOS inverter depends on the supply voltage. In the sub-clock circuit, as in the case of the clock circuit described above, a through current flows when the output of each third CMOS inverter changes, and the voltage at the other end of the resistance element changes. As a result, the supply voltage of the first CMOS inverter of the clock circuit changes (that is, noise is superimposed). With the change of the supply voltage, the width (period) of the clock at that time changes. When the width of the clock of the clock signal output from the clock circuit changes, the number of clocks measured by the counter circuit changes. By providing the subclock circuit, noise is superimposed on the supply voltage to the clock circuit, and fluctuation (noise) from both the clock circuit and the subclock circuit is superimposed on the supply voltage to the delay circuit. Therefore, the noise is further complicated and becomes close to white noise. Therefore, higher resolution is obtained. Further, since the sub-clock circuit is also a digital circuit, a small-sized time-to-digital converter can be realized even if the sub-clock circuit is included.

  One application of this time-to-digital converter is a temperature sensor that employs a transistor whose operating speed has temperature dependence in the second CMOS inverter of the delay circuit. However, the time-to-digital converter disclosed in this specification is not limited to application to a temperature sensor. The details and further improvements of the technology disclosed in this specification will be described in the following “Detailed description of the invention”.

It is a block diagram of a time digital converter of a 1st example. It is a circuit diagram of a CMOS inverter. 5 is a graph showing changes in an input voltage and an output voltage to a CMOS inverter and changes in a through current. It is a block diagram of a clock circuit. 4 is a graph of a current flowing to a voltage supply terminal of a clock circuit. FIG. 9 is a diagram illustrating the effect of a change in delay time. FIG. 3A is an example of an output when there is no noise. FIG. 3B is an example of an output when noise is added (before averaging). FIG. 3C shows an example of the output when noise is added (after averaging). It is a block diagram of a time digital converter of a 2nd example.

  (First Embodiment) A time-to-digital converter 2 according to a first embodiment will be described with reference to the drawings. In the following, the time-to-digital converter (Time-to-Digital Converter) 2 is simply referred to as TDC2 for convenience of explanation. The TDC 2 can be used as a temperature sensor. FIG. 1 shows a block diagram of the TDC2.

  The TDC 2 includes a clock circuit 10, a delay circuit 20, a counter circuit 6, and an average calculation circuit 7. The clock circuit 10 includes a ring oscillator 12 in which a plurality of first CMOS inverters 4 are connected in a ring. The delay circuit 20 includes an inverter chain 22 in which a plurality of second CMOS inverters 5 are connected in series. The first CMOS inverter 4 of the clock circuit 10 and the second CMOS inverter 5 of the delay circuit 20 are formed by connecting two voltage-driven transistors in series, and receive a voltage from the power supply Vdd via the resistance element 3.

  In the clock circuit 10, the input level of the first CMOS inverter 4 on the left end in the figure is inverted by a start circuit (not shown). Then, the output of the leftmost first CMOS inverter 4 is inverted. The output terminal of the leftmost first CMOS inverter 4 is connected to the input terminal of the second leftmost first CMOS inverter 4. When the output of the leftmost first CMOS inverter 4 is inverted, the input of the second leftmost first CMOS inverter 4 is inverted, and the output of the first CMOS inverter 4 is inverted. Thus, the output inversion of the first CMOS inverter 4 occurs in a chain from left to right in the figure. The output terminal of the rightmost first CMOS inverter 4 is connected to the input terminal of the leftmost first CMOS inverter 4, and the chain of output inversion goes around the ring oscillator 12 indefinitely. The output terminal of the first CMOS inverter 4 at the right end in the figure corresponds to the output terminal 10a of the clock circuit 10. From this output terminal 10a, a clock signal CLK having a cycle corresponding to the operating speed of the first CMOS inverter 4 and the number of stages of the ring oscillator 12 is output.

  The operation of the delay circuit 20 will be described. An input trigger signal Sin having a rising edge is input to the input terminal 20a of the delay circuit 20. The time of the rising edge of the input trigger signal Sin is referred to as input trigger timing. Due to the input of the edge of the input trigger timing, the second CMOS inverter 5 constituting the inverter chain 22 inverts the output in a chain from left to right in the figure. As a result, a delay trigger signal Sd having a delay trigger timing obtained by delaying the input trigger timing of the input trigger signal Sin according to the number of stages of the inverter chain 22 is output from the output terminal 20b of the delay circuit 20. The time from the input trigger timing (the rising edge of the input trigger signal Sin) to the delay trigger timing (the rising edge of the delay trigger signal Sd) is referred to as a delay time.

  The input trigger signal Sin, the delay trigger signal Sd, and the clock signal CLK are input to the counter circuit 6. The counter circuit 6 counts the number of clocks from the input trigger timing of the input trigger signal Sin to the delay trigger timing of the delay trigger signal Sd. Since the counter circuit 6 may have a known configuration, a detailed description is omitted. The output (the number of clocks) of the counter circuit 6 is sent to the average calculation circuit 7.

  Although not shown in FIG. 1, the input trigger signal Sin includes a plurality of input trigger timings (ie, a plurality of rising edges). The delay circuit 20 generates a delay trigger timing corresponding to each input trigger timing. The input trigger signal Sin including a plurality of input trigger timings and the delay trigger signal Sd including the delay trigger timing corresponding to each input trigger timing are input to the counter circuit 6. The counter circuit 6 counts the number of clocks between the input trigger timing input in time series and the delay trigger timing corresponding to each input trigger timing, and sends the counted number to the average calculation circuit 7. A plurality of count numbers are input to the average calculation circuit 7 in time series. The average calculation circuit 7 calculates and outputs a moving average of the time series data of the count number. The output of the average calculation circuit 7 becomes the output of the TDC2. Since a known circuit may be used as the average calculation circuit 7, detailed description is omitted.

  Most of the TDC 2 can be constituted by digital elements and is integrated into one chip. The one-chip TDC 2 is arranged as a temperature measurement target. The operation speed of the second CMOS inverter 5 of the delay circuit 20 has temperature dependency. That is, the time interval (delay time) from the input trigger timing to the delay trigger timing changes depending on the ambient temperature of TDC2. The correlation between the delay time and the ambient temperature has been checked in advance. The received temperature is stored in a temperature specifying circuit (not shown). The temperature specifying circuit specifies the ambient temperature from the number of clocks output from the average calculation circuit 7 using the above table (or conversion formula) and outputs the specified ambient temperature.

  The counter circuit 6 counts the number of clocks in the time (delay time) from the input trigger timing to the delay trigger timing. Therefore, the time resolution of the counter circuit 6 is determined by one clock cycle. A time difference shorter than one clock cycle cannot be measured by the counter circuit 6. This is the quantization error. The TDC 2 includes a resistance element 3 in order to reduce a quantization error and achieve higher accuracy. One end of the resistance element 3 is connected to the power supply Vdd, and the other end is connected to the voltage supply terminals 12 a of the plurality of first CMOS inverters 4 and the voltage supply terminals 22 a of the plurality of second CMOS inverters 5. Next, the role of the resistance element 3 will be described.

  The first CMOS inverter 4 of the clock circuit 10 is formed of a voltage-driven transistor. No current flows while the output is held, but a through current Ipr flows when the output is inverted. When the resistance value of the resistance element 3 is represented by a symbol R, the voltage at the current downstream end 3a of the resistance element 3 fluctuates by dV = Ipr × R every time the through current Ipr flows. This voltage fluctuation dV is superimposed as noise on the voltage supplied to the second CMOS inverter 5 of the delay circuit 20. The operation speed of the second CMOS inverter 5 of the delay circuit 20 varies depending on the supply voltage, and the delay time (the time from the input trigger timing to the delay trigger timing) varies depending on the voltage variation dV. Dithering is performed using the fluctuation of the delay time to reduce a quantization error. Hereinafter, a more specific description will be given.

  FIG. 2 shows a circuit diagram of one first CMOS inverter 4. The first CMOS inverter 4 is configured by a DC connection of two voltage-driven transistors 41 and 42. The first transistor 41 is a p-type MOSFET (Metal Oxide Field Effect Transistor), the drain is connected to the power supply Vdd, and the source is connected to the drain of the second transistor 42. The second transistor 42 is an n-type MOSFET, and has a drain connected to the source of the first transistor 41 and a source connected to the ground terminal Vss. The gate of the first transistor 41 and the gate of the second transistor 42 are connected to each other. A connection point between the first transistor 41 and the second transistor 42 is connected to the gates of two transistors constituting the first CMOS inverter 4 at the next stage.

  FIG. 3 is a graph illustrating the operation of the first CMOS inverter 4. When the input voltage Vin of the first CMOS inverter 4 (that is, the gate voltages of the two transistors 41 and 42) is the off voltage Voff (Low level voltage), the output voltage Vout of the first CMOS inverter 4 is the on voltage Von (High level voltage). Becomes When the input voltage Vin switches from the off voltage Voff to the on voltage Von, the output voltage Vout switches from the on voltage Von to the off voltage Voff. In the switching section Tsw, a current (through current Ipr) flows because neither the transistor 41 nor the transistor 42 is completely turned off. The through current Ipr has a spike-like waveform that becomes maximum at time Tx at which the input voltage Vin and the output voltage Vout intersect (see the lower diagram in FIG. 3).

  FIG. 4 shows a block diagram of the clock circuit 10 (ring oscillator 12). FIG. 5 shows a graph of a current (through current Ipr) flowing through the voltage supply terminal 12a of the ring oscillator 12 (that is, the plurality of first CMOS inverters 4) of the clock circuit 10. The clock circuit 10 (ring oscillator 12) has a structure in which a plurality of first CMOS inverters 4 shown in FIG. 2 are connected in a ring shape. In FIG. 4, a starting circuit for initially inverting the input of any one of the first CMOS inverters 4 is not shown.

  In the ring oscillator 12, once the output of any of the first CMOS inverters 4 is inverted, the output is inverted in a clockwise fashion in the figure. Each time the output of each first CMOS inverter 4 is inverted, the spike-like through current Ipr shown in FIG. 3 flows (see the broken line graph in FIG. 5). As a result, a slightly fluctuating current flows through the common voltage supply terminal 12a that applies a voltage to the plurality of first CMOS inverters 4 (see the solid line graph in FIG. 5). A minute change in the supply voltage caused by the through current Ipr of the clock circuit 10 is applied to the second CMOS inverter 5 of the delay circuit 20.

  The second CMOS inverter 5 has a characteristic that the operation speed depends on the supply voltage. When the supply voltage fluctuates (when noise is added), the operation speed of the second CMOS inverter 5 changes, and as a result, the delay time (the time from the input trigger timing to the delay trigger timing) changes. FIG. 6 is a diagram illustrating the effect of a change in delay time. FIG. 7 is a diagram for explaining a difference in an output result depending on the presence or absence of noise. Since the number of clocks is an integer, the number of clocks is distributed, for example, in a range of a predetermined median ± 1 by adding noise. When the delay time changes in the range of dTd in FIG. 6, the number of clocks measured by the counter circuit 6 is distributed in the range of n ± 1. FIG. 7A shows a coefficient result of the counter circuit 6 when there is no noise. In this example, it is assumed that the number of clocks counted by the counter circuit 6 when there is no noise is 1000. That is, “n” in FIG. 6 corresponds to “1000” in FIG. 7, “n−1” in FIG. 6 corresponds to “999” in FIG. 7, and “n + 1” in FIG. 6 corresponds to “1001” in FIG. ". FIG. 7B is an example of an output of the counter circuit 6 when noise is added. The number of clocks counted by the counter circuit 6 is distributed between “n−1” and “n + 1”, that is, between “999” and “1001”.

  Since the output of the counter circuit 6 is an integer value, the time resolution of the delay time in the output of the counter circuit 6 is equal to the clock cycle.

  When assuming that the delay time can be expressed including the decimal part of the clock number (that is, assuming that there is no quantization error), the value of the clock number including the decimal part is the median value of the integer (in FIG. 7, If it is shifted to the positive side from (1000), the shape of the distribution in FIG. 7B is biased toward the median plus one (ie, “1001”). Conversely, if the value of the number of clocks including the decimal part is shifted to the negative side from the median of the integers, the shape of the distribution in FIG. 7B is shifted toward the median minus one (that is, “999”). Biased. Therefore, by calculating the moving average of the distribution of the number of clocks when noise is added, the number of clocks corresponding to the delay time can be obtained with decimal precision. That is, the quantization error of the counter circuit 6 can be reduced. FIG. 7C shows a result of calculating a moving average of 30 samples for the time-series data of the number of clocks in FIG. 7B. As shown in FIG. 7C, by calculating the moving average, the number of clocks corresponding to the delay time can be represented with an accuracy of a decimal point or less.

  From the above description, the condition for the resistance value R of the resistance element 3 can also be found. The voltage fluctuation dV is obtained by multiplying the through current Ipr of the clock circuit 10 by the resistance value R of the resistance element 3 (dV = Ipr × R). On the other hand, the operation speed of the second CMOS inverter 5 depends on the supply voltage, and the delay time varies with the supply voltage. If the delay time fluctuates by at least a half cycle of one clock, the number of clocks (the output of the counter circuit 6) is dispersed due to the voltage fluctuation (noise). This is because when the clock output is used in addition to the output of the counter circuit for calculating the delay time, the number of clocks output from the counter circuit 6 changes by at least one clock even if the time change of the delay time is a half cycle of the clock. Because you do. The resistance value R of the resistance element 3 must be set so that the time change of the delay trigger timing with respect to the voltage fluctuation dV (= through current Ipr × resistance value R) is equal to or longer than a half cycle of the clock signal. The time change of the delay trigger timing corresponds to the change of the delay time. Therefore, in other words, the resistance value R of the resistance element 3 is set so that the change in the delay time with respect to the voltage fluctuation dV (= through current Ipr × resistance value R) is equal to or longer than a half cycle of the clock signal. It may be expressed that it must be set.

  Generally, the resistance value R of the resistance element 3 is desirably 50 ohm or more from the characteristics of a normal MOSFET. For example, when the through current Ipr of the clock circuit 10 is 0.2 [mA], the voltage fluctuation dV is 0.2 × 50 = 10 [mV]. With a voltage fluctuation smaller than this, there is a high possibility that the fluctuation of the delay time (the fluctuation of the delay trigger timing) in the delay circuit 20 will not be larger than the half cycle of the clock signal.

  (Second Embodiment) FIG. 8 shows a block diagram of a TDC 2a of a second embodiment. The TDC2 is obtained by adding a subclock circuit 50 to the TDC2 of FIG. The subclock circuit 50 includes another ring oscillator 52 in which a plurality of third CMOS inverters 9 are connected in a ring. The voltage supply terminals 52 a of the plurality of third CMOS inverters 9 are connected to the current downstream terminals 3 a of the resistance element 3. In the TDC 2, the plurality of first CMOS inverters 4 of the clock circuit 10 have a characteristic that their operation speed depends on the supply voltage. The configuration of the subclock circuit 50 is the same as that of the clock circuit 10. Therefore, the voltage of the current downstream end 3a of the resistance element 3 also fluctuates due to the operation of the subclock circuit 50. Due to the voltage fluctuation, the operating speed of not only the second CMOS inverter 5 of the delay circuit 20 but also the first CMOS inverter 4 of the clock circuit 10 changes. The change in the operation speed of the first CMOS inverter 4 changes the cycle of the clock of the clock signal CLK. As a result, the number of clocks measured in the delay time changes. Further, the delay circuit 20 receives a voltage fluctuation (noise 2 in FIG. 8) due to the operation of the third CMOS inverter 9 in addition to a voltage fluctuation (noise 1 in FIG. 8) due to the operation of the first CMOS inverter 4. Since the voltage fluctuation received by the delay circuit 20 is complicated, the total noise becomes close to ideal white noise. By adding the subclock circuit 50, the clock circuit 10 receives a voltage change and the delay circuit 20 receives a voltage change close to white noise, so that the quantization error can be further reduced. In other words, a more accurate output can be obtained.

  Since the sub-clock circuit 50 can also be constituted only by digital elements, the TDC 2a can also be realized compactly.

  The resistance value R of the resistance element 3 preferably satisfies the following condition in addition to the above condition. That is, the number of clocks in the delay time is shifted by more than half a clock with respect to the voltage fluctuation value dV obtained by multiplying the through current Ipr flowing when the output of the third CMOS inverter 9 changes (when the output is inverted) by the resistance value R. Is preferably selected. The above conditions are as follows. The time change of the delay trigger timing with respect to the voltage fluctuation value obtained by multiplying the through current Ipr flowing when the output of the first CMOS inverter 4 changes (when the output is inverted) by the resistance value R is equal to or longer than the cycle of the clock signal CLK. Thus, the resistance value R is selected. If the resistance value R is selected so that at least the number of clocks in the delay time is shifted by half a clock or more, the number of clocks (output of the counter circuit) is dispersed due to voltage fluctuation (noise). If the resistance value R is selected such that the number of clocks in the delay time is shifted by one clock or more, the number of clocks (output of the counter circuit) is more reliably dispersed due to voltage fluctuation (noise). In other words, if the resistance value R is selected so that the time change of the delay trigger timing becomes one cycle or more of the clock signal, higher accuracy can be expected more reliably by dithering.

  The transistors forming the first CMOS inverter 4 may be of the same type as the transistors forming the second CMOS inverter 5. Further, the transistor of the third CMOS inverter 9 may be of the same type as the transistor of the second CMOS inverter 5.

  Since the TDC 2 and the TDC 2a can be constituted by digital elements other than the resistance element 3, they can be realized compactly.

  Points to keep in mind regarding the technology described in the embodiment will be described. The TDC 2 of the embodiment has been applied to a temperature sensor. The technology disclosed in this specification is not limited to TDC applied to a temperature sensor.

  As described above, specific examples of the present invention have been described in detail, but these are merely examples, and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings can simultaneously achieve a plurality of objects, and has technical utility by achieving one of the objects.

2, 2a: time digital converter 3: resistance element 3a: current downstream end 4: first CMOS inverter 5: second CMOS inverter 6: counter circuit 7: average calculation circuit 9: third CMOS inverter 10: clock circuit 12: ring oscillator 12a : Voltage supply terminal 20: delay circuit 22: inverter chain 22 a: voltage supply terminals 41 and 42: transistor 50: subclock circuit 52: ring oscillator 52 a: voltage supply terminal

Claims (4)

An input trigger signal includes a delay circuit that outputs a delayed trigger signal obtained by delaying the input trigger signal when the input trigger signal is input, and includes a delay trigger signal included in the delay trigger signal from an input trigger timing included in the input trigger signal. Is a time-to-digital converter that outputs the delay time up to the delay trigger timing as a digital value,
A clock circuit that includes a ring oscillator in which a plurality of first CMOS inverters are connected in a ring, and outputs a clock signal according to an output change of the first CMOS inverter;
The input trigger signal, the delay trigger signal, and the clock signal are input, and the clock is supplied from the input trigger timing included in the input trigger signal to the delay trigger timing included in the delay trigger signal. A counter circuit for counting the number of clocks of the signal,
An average calculation circuit that calculates a moving average of the number of clocks corresponding to each of the plurality of input trigger timings included in the input trigger signal and outputs the calculated moving average as the digital value ,
A resistance element;
With
The delay circuit includes an inverter chain in which a plurality of second CMOS inverters whose operation speeds depend on a supply voltage are connected in series, and the input trigger timing of the input trigger signal is set according to the number of stages of the inverter chain. A circuit that outputs the delay trigger signal having the delayed delay trigger timing,
The resistive element has one end connected to the power supply, the other end it is connected to the voltage supply end of the first 2CMOS inverter and said second 1CMOS inverter, time to digital converter. The first CMOS inverter includes two transistors connected in series, one end of the series connection is connected to the resistance element as the voltage supply end, and the other end is connected to a ground end.
A time change of the delay trigger timing with respect to a voltage change value obtained by multiplying a through current flowing through the series connection by a resistance value of the resistance element when an output of the first CMOS inverter changes is not less than a half cycle of the clock signal. The time-to-digital converter according to claim 1, wherein the resistance value is set so as to be as follows.   3. The time-to-digital converter according to claim 1, wherein the resistance value of the resistance element is equal to or greater than 50 ohms. A subclock circuit including another ring oscillator in which a plurality of third CMOS inverters are connected in a ring,
A voltage supply terminal of the third CMOS inverter is connected to the other end of the resistance element;
A plurality of the first CMOS inverters, wherein an operation speed is dependent on a supply voltage;
The time-to-digital converter according to claim 1.

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