JP6504960B2 - Printed board - Google Patents

Description

  The present invention relates to a printed circuit board having a noise filter.

  A noise filter is mounted on the printed circuit board in order to remove electromagnetic noise in a high frequency band leaking from a circuit element such as an LSI (Large Scale Integrated circuit) or an IC (Integrated Circuit). FIG. 7 is a view showing an example of a conventional noise filter mounted on the printed circuit board 100. As shown in FIG. On the printed circuit board 100, a circuit element 101, a connector circuit 102, a bypass capacitor 104, a power supply wiring pattern 111, and a ground wiring pattern 112 are mounted.

  As shown in FIG. 7, one end of the power supply wiring pattern 111 is connected to the circuit element 101, and the other end of the power supply wiring pattern 111 is connected to the external power supply 103 via the connector circuit 102. One end of the bypass capacitor 104 is connected to the power supply wiring pattern 111 via the lead wiring 113, and the other end of the bypass capacitor 104 is connected to the ground wiring pattern 112 via the lead wiring 114. If the high frequency electromagnetic noise generated in the circuit element 101 propagates to the external power supply 103, for example, the power supply voltage fluctuates to cause malfunction of the circuit element 101, or another circuit element receiving power supply from the external power supply 103 (not shown) The problem of causing the malfunction of) may occur. The bypass capacitor 104 functions as a noise filter for high frequency electromagnetic noise, and can bypass high frequency electromagnetic noise propagating through the power supply wiring pattern 111 to the ground wiring pattern 112. This makes it possible to improve the power supply quality.

  However, parasitic inductance exists in the bypass capacitor 104. Since the bypass performance of the bypass capacitor 104 is degraded by this parasitic inductance, there is a problem that high frequency electromagnetic noise leaking to the external power supply 103 side can not be sufficiently reduced. For this problem, for example, the prior art disclosed in Patent Document 1 (Japanese Patent Application Laid-Open No. 2005-303193) is known. Since the chip type capacitor array disclosed in Patent Document 1 includes a plurality of capacitors connected in parallel with the common external electrode, the parasitic inductance of the chip type capacitor array itself can be reduced.

JP 2005-303193 A (for example, FIGS. 1 to 4 and paragraphs 0020 to 0030)

  However, the prior art of Patent Document 1 can not suppress the deterioration of the bypass performance due to the parasitic inductance of the wiring used for mounting the bypass capacitor.

  In view of the above, it is an object of the present invention to provide a printed circuit board capable of suppressing the performance deterioration of a bypass circuit including a capacitor.

  A printed circuit board according to an aspect of the present invention is a printed circuit board having a structure in which a first wiring layer and a second wiring layer are stacked via an insulating layer, and as a part of the first wiring layer The formed first and second wiring lines and the first wiring layer are disposed, and have a pair of electrode terminals, and one of the pair of electrode terminals is the first A bypass capacitor electrically connected to one end of a wiring line, a third wiring line formed as a part of the second wiring layer, and another part of the second wiring layer And a first interlayer connection hole formed through the insulating layer to electrically connect the one end of the first wiring line to one end of the third wiring line; And one end of the second wiring line is formed through the layer. A second interlayer connection hole electrically connected to the other end of the third wiring line; and the insulating layer formed through the other, and the other of the pair of electrode terminals is electrically connected to the ground conductor surface. And a third interlayer connection hole electrically connected to each other, wherein the first and second wiring lines extend in parallel to each other so as to be magnetically coupled. The one end of the line is opposite to the other end of the second wiring line, and the one end of the second wiring line is opposite to the other end of the first wiring line. I assume.

  According to the present invention, the first wiring line and the second wiring line are connected in series via the third wiring line, and form mutual inductance by magnetic coupling. The negative inductance that appears equivalently to this mutual inductance can cancel the parasitic inductance of the bypass circuit including the bypass capacitor. Therefore, the performance deterioration of the bypass circuit can be suppressed without adding a new electronic component.

It is a figure which shows roughly an example of the cross-section of the double-sided printed circuit board of Embodiment 1 which concerns on this invention. (A), (B) is a top view of the wiring layer which comprises the double-sided printed circuit board of Embodiment 1. FIG. (A) is a figure which shows the mutual induction circuit containing a pair of parasitic inductors, (B) is a figure which shows T-type equivalent circuit of this mutual induction circuit. FIG. 2 schematically shows a main part of an equivalent circuit of the double-sided printed circuit board according to the first embodiment. FIG. 2 is a plan view showing an example of a magnetic body of Embodiment 1; It is a figure which shows roughly the principal part of the cross-section in the VI-VI line of FIG. It is a figure which shows an example of the conventional noise filter mounted in the printed circuit board.

  Hereinafter, various embodiments according to the present invention will be described in detail with reference to the drawings. In addition, the component which attached | subjected the same code | symbol in drawing shall have the same function and the same structure.

Embodiment 1
FIG. 1 is a view schematically showing an example of the cross-sectional structure of double-sided printed circuit board 1 according to the first embodiment of the present invention, and FIGS. 2 (A) and 2 (B) constitute double-sided printed circuit board 1. It is a top view of a wiring layer. FIGS. 2A and 2B show planar configurations of the upper wiring layer WL1 and the lower wiring layer WL2 when viewed from the same direction.

  As shown in FIG. 1, the double-sided printed circuit board 1 includes an upper wiring layer WL1 which is a first wiring layer, a lower wiring layer WL2 which is a second wiring layer, and the upper wiring layer WL1 and the lower wiring layer WL2. And the magnetic material 23 provided on the upper wiring layer WL1. The double-sided printed board 1 has a structure in which the upper wiring layer WL1, the insulating layer IL, and the lower wiring layer WL2 are stacked in the thickness direction (vertical direction in the drawing). Here, the insulating layer IL is made of an electrically insulating material such as a nonconductive resin.

  As shown in FIGS. 2A and 2B, vias Ha, Hb, Hc, Hd, and He, which are interlayer connection holes penetrating through the insulating layer IL, are formed in the double-sided printed board 1. For example, a conductive paste is filled inside the vias Ha, Hb, Hc, Hd, and He, or a metal layer such as copper is formed by electroless plating, so that the vias Ha, Hb, Hc, Hd and He have conductivity. Therefore, the vias Ha, Hb, Hc, Hd, and He can electrically connect the upper wiring layer WL1 and the lower wiring layer WL2.

  The upper wiring layer WL1 is formed on the top surface of the insulating layer IL in the thickness direction. As shown in FIG. 2A, the upper wiring layer WL1 is electrically connected to the circuit element 10, which is an electronic component such as an LSI or IC, and the external power supply 12 such as a DC-DC converter or an on-vehicle battery. The connector circuit 11 and the bypass capacitor 13 for removing electromagnetic noise are provided.

  Further, as the wiring pattern constituting upper wiring layer WL1, power supply wiring pattern W1 connected to the power supply terminal of circuit element 10 and power supply electrically connected to the positive terminal of external power supply 12 through connector circuit 11 Wiring pattern W2, lead wiring W3 electrically connecting one electrode terminal of bypass capacitor 13 to power supply wiring pattern W1, and wiring W4 electrically connecting the other electrode terminal of bypass capacitor 13 to via Hc; A ground wiring W5 electrically connecting the ground terminal of the circuit element 10 to the via Hd and a ground wiring W6 electrically connecting the ground terminal of the connector circuit 11 to the via He are formed. The power supply wiring patterns W1 and W2, the lead wiring W3, the wiring W4 and the ground wirings W5 and W6 may be made of a conductor such as copper foil.

  On the other hand, lower interconnection layer WL2 is formed on the lower surface of insulating layer IL as shown in FIG. As shown in FIG. 2B, the wiring pattern constituting lower wiring layer WL2 includes wiring line W9 electrically connecting between vias Ha and Hb, and ground conductor surface 22 electrically grounded. It consists of The ground conductor surface 22 is electrically isolated from the wiring line W9. The wiring line W9 and the ground conductor surface 22 may be made of a conductor such as copper foil. The negative terminal of the external power supply 12 is connected to the ground conductor surface 22 via the connector circuit 11 in the upper wiring layer WL1, the ground wiring W6, and the via He.

  Although the wiring line W9 has a bent portion which is bent at a right angle as shown in FIG. 2B, the present invention is not limited to this. Instead of such a wiring line W9, a linear wiring line or a circular or oval wiring line may be employed.

  Next, referring to FIG. 2A, in the upper wiring layer WL1, one of the power supply wiring patterns W1 is a first wiring line W1a formed opposite to and in proximity to the other power supply wiring pattern W2. And the other power supply wiring pattern W2 includes a second wiring line W2a formed at a position facing and close to one power wiring pattern W1. The first and second wiring lines W1a and W2a (hereinafter referred to as "proximity wiring lines W1a and W2a") are formed to face each other and to extend in parallel to each other. The wiring line W9 of the lower wiring layer WL2 is a third wiring line for connecting the adjacent wiring lines W1a and W2a in series.

  As shown in FIG. 2A, the left end of the adjacent wiring line W1a is electrically connected to the via Ha. As a result, as shown in FIG. 2B, the adjacent wiring line W1a is electrically connected to the left end of the wiring line W9 of the lower wiring layer WL2 through the via Ha. The right end portion of the other adjacent wiring line W2a is electrically connected to the via Hb as shown in FIG. 2 (A). As a result, as shown in FIG. 2B, the adjacent wiring line W2a is electrically connected to the other end of the right side of the wiring line W9 of the lower wiring layer WL2 through the via Hb. Therefore, the end portions of the adjacent wiring lines W1a and W2a are connected in series via the via Ha, the wiring line W9, and the via Hb. Therefore, the directions of the currents flowing through the adjacent wiring lines W1a and W2a are the same. Further, the directions of the magnetic flux generated in the close wiring lines W1a and W2a due to the parasitic inductance are also substantially the same.

  Further, as shown in FIG. 2A, the left end portion of the close wiring line W1a is electrically connected to one electrode terminal of the bypass capacitor 13 through the lead wiring W3. The other electrode terminal of the bypass capacitor 13 is electrically connected to the via Hc via the wire W4. Thereby, the other electrode terminal is electrically connected to the ground conductor surface 22 of the lower wiring layer WL2 through the via Hc. On the other hand, the other end on the right side of the close wiring line W1a is a portion facing the one end on the right side of the close wiring line W2a (the part connected to the via Hb) although not explicitly shown in FIG. It is electrically connected to the power supply terminal of the circuit element 10 through the other wiring portion of the line W1. Further, the other end on the left side of the close wiring line W2a is also a portion facing the one end on the left side of the close wiring line W1a (a portion connected to the via Ha) although not explicitly shown in FIG. It is electrically connected to the external power supply 12 through the other wiring portion of the line W 2 and the connector circuit 11.

The noise filter of the present embodiment is configured to include the close wiring lines W1a and W2a and the bypass capacitor 13. The adjacent wiring lines W1a and W2a have a pair of parasitic inductors magnetically coupled to each other to cause mutual induction. FIG. 3A schematically shows a mutual induction circuit including the parasitic inductor 41 of the close wiring line W1a and the parasitic inductor 42 of the close wiring line W2a, and FIG. 3B shows the mutual induction circuit. Is a diagram showing a T-type equivalent circuit of FIG. When currents i ₁ and i ₂ flow into the parasitic inductors 41 and 42 from the nodes a 1 and a 2, respectively, mutual inductance -M is formed between the parasitic inductors 41 and 42. Assuming that the nodes b1 and b2 have a common potential, the mutual induction circuit comprises three inductors 51, 52, 53 having three inductances L1 + M, L2 + M, -M as shown in FIG. 3B. It can be considered as an equivalent circuit. This type of equivalent circuit is called a T-type equivalent circuit.

Here, when adjacent wiring lines W1a and W2a face each other at a distance d (unit: m) and line lengths of both adjacent wiring lines W1a and W2a are R (unit: m), adjacent wiring lines W1a , W2a (unit: H = Wb / A) is given by, for example, the following approximate expression (1).
M = (μ ₀ / (2π)) × R × (ln (2 R / d) −1) (1)

Here, μ ₀ is the permeability of vacuum (= 4π × 10 ⁻⁷ H / m). The mutual inductance can be designed based on this equation (1).

The magnitude M of the mutual inductance between the adjacent wiring lines W1a and W2a is also given by the following equation (2).
M = k × (L1 × L2) ^1/2 (2)

  Here, k is a coupling coefficient.

FIG. 4 is a view schematically showing the main part of the equivalent circuit of the double-sided printed circuit board 1 having the noise filter. The equivalent circuit shown in FIG. 4 includes a circuit element 10, the T-type equivalent circuit described above, a bypass capacitor 13, a parasitic inductor 54 having a wiring inductance L4, and a connector circuit 11. The equivalent inductance of the inductor 51 is L1 + M, and the equivalent inductance of the inductor 52 is L2 + M. Further, the bypass capacitor 13 includes a capacitor component 13C having a capacitance C and a parasitic inductor 13 _ESL having a residual inductance Lp which is an equivalent series inductance (ESL). Here, the parasitic inductor 54 is formed by the via Hc of FIGS. 2 (A) and 2 (B). In FIG. 4, for convenience of description, the display of other circuit elements (for example, the resistance component and the parasitic inductor component of the lead wire W3) of the double-sided printed circuit board 1 is omitted.

The bypass circuit of this embodiment is constituted by the lead wire W3, the bypass capacitor 13, the wire W4 and the via Hc shown in FIG. 2A. In this bypass circuit, when the adjacent wiring lines W1a and W2a are magnetically coupled, as shown in FIG. 4, an inductor 53 having a negative inductance -M appears equivalently. That is, the inductor 53 is equivalently connected to the series connection point Np between the inductors 51 and 52. Therefore, at this time, in the bypass circuit, the inductor 53 having the negative inductance -M, the capacitor component 13C, and the parasitic inductor 13 _ESL are connected in series.

  Here, for the wiring inductance L4 of the via Hc, the wiring inductance L4 can be approximately calculated based on the dimensions (for example, the length and the diameter of the via) of the via Hc. Also, by measuring the characteristics of the bypass capacitor 13, it is possible to calculate the residual inductance Lp.

  Therefore, by designing the inductance -M so that the impedances of the negative inductance -M, the wiring inductance L4 of the via Hc, and the residual inductance Lp of the bypass capacitor 13 cancel each other out, the impedance of the bypass circuit becomes the capacitor component 13C. Can be equivalent to the impedance of the For example, using the above equation (1), it is possible to design so that the negative inductance -M is an optimal value. As a result, since the bypass path in the bypass circuit does not substantially include an inductance component, it is possible to prevent the deterioration of the bypass performance even if the frequency of the electromagnetic noise propagating through the power supply wiring pattern W1 is high.

  Here, it is also possible to design the inductance -M in consideration of the parasitic inductance of the lead wire W3 and the wire W4 used for mounting the bypass capacitor 13.

  Next, the magnetic body 23 shown in FIG. 1 will be described. The magnetic body 23 is disposed in the vicinity of the adjacent wiring lines W1a and W2a, and is disposed at least in the region between the adjacent wiring lines W1a and W2a in a plan view. As a result, a part of the magnetic path of the magnetic flux generated between the adjacent wiring lines W1a and W2a can be confined inside the magnetic body 23.

  FIG. 5 is a plan view showing an example of the magnetic body 23 provided on the upper wiring layer WL1, and FIG. 6 is a view schematically showing the main part of the sectional structure taken along line VI-VI in FIG. As shown in FIGS. 5 and 6, the magnetic body 23 is disposed in contact with the adjacent wiring lines W1a and W2a and covers the adjacent wiring lines W1a and W2a. As a result, a magnetic path through which the magnetic flux MF generated between the adjacent wiring lines W1a and W2a passes is formed inside the magnetic body 23. When all of the magnetic flux generated from one of the close wiring lines W1a and W2a is linked to the other without leaking into the air, the parasitic inductors 41 and 42 of the close wiring lines W1a and W2a are interposed between The coupling coefficient k is the highest value "1". Since the magnetic flux MF is concentrated inside the magnetic body 23 by arranging the magnetic body 23 in the vicinity of the adjacent wiring lines W1a and W2a, the amount of magnetic flux leaking out into the air can be reduced. As a result, the coupling coefficient k approaches the value of “1”, and the magnitude M of the mutual inductance becomes high according to the above equation (2). Therefore, the self-inductances L1 and L2 can be set to small values in accordance with the increase in the coupling coefficient k. As a result, the line length R of the adjacent wiring lines W1a and W2a can be shortened. Therefore, the dimensions of the adjacent wiring lines W1a and W2a necessary to obtain the inductance -M can be reduced.

  The magnetic body 23 is preferably a ferrite magnetic body having high permeability to a high frequency signal of several MHz or more. For example, a resin sheet in which soft magnetic metal powder is dispersed, or a ferrite plating film having a thickness of about several μm can be used as the magnetic body 23.

  As described above, in the double-sided printed circuit board 1 of the first embodiment, the adjacent wiring lines W1a and W2a are connected in series via the wiring line W9, and face each other to form mutual inductance by magnetic coupling. And extend in the same direction. The negative inductance -M that appears equivalently to the magnetic coupling can cancel the parasitic inductance of the entire bypass circuit including the bypass capacitor 13. Therefore, it is possible to suppress the deterioration of the bypass performance of the bypass capacitor 13 without adding a new electronic component. Therefore, electromagnetic noise propagating in the power supply wiring pattern W1 can be effectively removed.

  Here, in order to cancel the parasitic inductance of the bypass circuit, it is conceivable to additionally mount an electronic component such as an inductor. However, the addition of a new electronic component causes an increase in the manufacturing cost of the printed circuit board, and the new electronic component may adversely affect the other wiring or other electronic component on the printed circuit board by electromagnetically acting. There is. The double-sided printed circuit board 1 of the present embodiment can suppress the deterioration of the bypass performance without additionally mounting such an electronic component.

  Further, as shown in FIG. 2B, since the wiring line W9 connecting the adjacent wiring lines W1a and W2a in series is formed in the same lower wiring layer WL2 as the ground conductor surface 22, the number of wiring layers can be reduced. The size of the double-sided printed circuit board 1 can be reduced.

  As mentioned above, although the embodiment according to the present invention has been described with reference to the drawings, this embodiment is an example of the present invention, and various modes other than this embodiment can be adopted. For example, although the said embodiment is a double-sided printed circuit board of 2 layer structure, it is not limited to this. The present invention is applicable to a multilayer printed circuit board having three or more wiring layers.

  Further, instead of the external power supply 12, a power supply element which is an internal power supply may be mounted on the double-sided printed circuit board 1 of the above embodiment. Even in this case, it is possible to suppress the propagation of high frequency electromagnetic noise to the mounted power supply element.

  Within the scope of the present invention, free combinations of the components of the above embodiment, deformation of any components of the above embodiment, or omission of any components of the above embodiment are possible.

  WL1 upper interconnection layer, WL2 lower interconnection layer, IL insulating layer, W1, W2 power supply interconnection pattern, W1a, W2a adjacent interconnection line (first and second interconnection lines), W9 interconnection line, Ha, Hb, Hc, Hd, He via, MF magnetic flux, 1 double-sided printed circuit board, 10 circuit elements, 11 connector circuits, 12 external power supplies, 13 bypass capacitors, 22 ground conductor surfaces, 23 magnetics, 41, 42 parasitic inductors, 51 to 53 inductors, 54 parasitic inductors .

Claims (6)

A printed circuit board having a structure in which a first wiring layer and a second wiring layer are stacked via an insulating layer,
First and second wiring lines formed as part of the first wiring layer;
It is arrange | positioned at said 1st wiring layer, has a pair of electrode terminal, and one electrode terminal of said pair of electrode terminals is electrically connected with the one end part of said 1st wiring line. With a bypass capacitor,
A third wiring line formed as a part of the second wiring layer;
A ground conductor surface formed as another part of the second wiring layer,
A first interlayer connection hole formed through the insulating layer to electrically connect the one end of the first wiring line to one end of the third wiring line;
A second interlayer connection hole formed through the insulating layer to electrically connect one end of the second wiring line to the other end of the third wiring line;
And a third interlayer connection hole formed through the insulating layer to electrically connect the other of the pair of electrode terminals to the ground conductor surface.
The first and second wiring lines face each other so as to be magnetically coupled and extend in parallel with each other, and one end of the first wiring line is other than the second wiring line. The end portion is opposed, and the one end portion of the second wiring line is opposed to the other end portion of the first wiring line.
Printed circuit board characterized by   The printed circuit board according to claim 1, wherein the first wiring line and the second wiring line are magnetically coupled to form an equivalent negative inductance. The printed circuit board according to claim 1, further comprising a circuit element disposed in the first wiring layer,
The other end of the first wiring line is electrically connected to a power supply terminal of the circuit element,
The other end of the second wiring line is electrically connected to a power supply,
Printed circuit board characterized by The printed circuit board according to any one of claims 1 to 3, further comprising a magnetic body confining at least a part of the magnetic flux generated between the first wiring line and the second wiring line. Equipped
The magnetic body is disposed in a region between at least the first wiring line and the second wiring line in a plan view from the thickness direction of the first wiring layer.
Printed circuit board characterized by   5. The printed circuit board according to claim 4, wherein the magnetic body is disposed to cover the first wiring line and the second wiring line.   The printed circuit board according to claim 4 or 5, wherein the magnetic body is a ferrite magnetic body.

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