JP6582537B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device using silicon carbide as a substrate and a method for manufacturing the semiconductor device.

  Silicon carbide (SiC) has a high breakdown electric field, and has recently attracted attention as an optimal semiconductor for low-loss power devices.

A silicon dioxide (SiO ₂ ) film can be formed on a SiC substrate by thermal oxidation, and an SiC power MOSFET (Metal Oxide Field Effect Transistor) using the SiO ₂ film has been developed. The junction interface between the gate insulating film of the MOS gate (metal-oxide film-semiconductor insulating gate) formed on the SiC substrate by thermal oxidation and the SiC substrate (hereinafter referred to as the SiC-MOS interface) has a high density. There is an interface state density (Dit), which causes a decrease in channel mobility. As an index for evaluating the interface characteristics between the silicon carbide substrate and the silicon dioxide film, there is an interface state density. In general, the interface characteristics represented by channel mobility tend to be better when the interface state density is lower.

In recent years, a process capable of forming a SiC-MOS interface with reduced Dit by oxidation in a nitrous oxide (N ₂ O) gas atmosphere or a nitric oxide (NO) gas atmosphere has been developed.

The interface state density of the oxide film prepared using N ₂ O · NO gas can be 2 × 10 ¹² cm ⁻² eV ⁻¹ or less, can realize high channel mobility, and can be used as a gate of SiC-MOSFET. It has been considered that the oxide film has a good structure.

  As a general method for improving the interface characteristics between the silicon carbide substrate and the silicon dioxide film, the silicon carbide substrate is oxidized in an atmosphere containing oxygen, and dinitrogen monoxide or post-oxidation annealing (POA) is performed. A method using a nitrogen-containing gas containing nitrogen is known. In this case, nitridation occurs simultaneously with oxidation, and nitrogen atoms contribute to termination of dangling bonds (unbonded hands) in the silicon dioxide film or at the interface between the silicon carbide substrate and the silicon dioxide film, thereby reducing the interface state density. It is said that there is an effect (for example, refer to the following Patent Document 1).

Special table 2004-511101 gazette

Among such background technologies, the issue of putting the SiC power MOSFET into practical use is ensuring the reliability of the SiC-MOSFET. As a result of verifying the reliability test of the SiC-MOSFET, it has been found that there is a problem that the threshold voltage at the negative bias varies greatly. The contents will be described below.

  The SiC power MOSFET must apply a high voltage, both positive and negative, to the gate electrode when driven. In addition, because of the high temperature operation, it is necessary to guarantee the operation at 200 ° C. Therefore, as an operation guarantee, the electric field strength applied to the gate oxide film needs to be plus or minus 2 MV / cm to 4 MV / cm and an operating temperature of 200 ° C. In this case, a phenomenon in which the threshold voltage (Vth) of the MOSFET greatly fluctuates under certain conditions has been observed.

FIG. 4 is a cross-sectional view of a conventional SiC vertical MOSFET. The manufacturing method will be described. First, a low-concentration n-type drift layer 2 doped with nitrogen of 5 × 10 ¹⁵ / cm ³ is deposited on a high-concentration n ⁺ -type substrate 1 to a thickness of 10 μm. Next, a high concentration p ⁺ -type layer 3 is formed by ion implantation. Next, a low concentration p ⁻ -type layer 4 doped with 5 × 10 ¹⁵ / cm ³ of aluminum is deposited on the surface to a thickness of 0.5 μm. Thereafter, the low concentration n ⁻ -type layer 7 is formed by nitrogen ion implantation.

Thereafter, the high concentration n ⁺ type layer 6 is formed by phosphorus ion implantation, and the high concentration p ⁺ type layer 5 is formed by aluminum (Al) ion implantation. Thereafter, activation annealing is performed at 1600 ° C. in an argon atmosphere. Thereafter, a gate oxide film 8 made of SiO _{2 is} formed to 70 nm in an N ₂ O atmosphere by thermal oxidation. Thereafter, the gate electrode 9 and the interlayer insulating film 10 are formed. Thereafter, a nickel silicide electrode 11 is formed in order to form an ohmic electrode. Then, 5 μm of an aluminum (Al) metal layer of the source wiring metal 12 is formed, polyimide as the protective film 14 is formed, polyimide is cured (cured) at 380 ° C., and then a back electrode (drain electrode) 13 is formed. To complete the device.

  With respect to the threshold voltage fluctuation after applying a gate voltage of plus 3 MV / cm and minus 3 MV / cm to the gate oxide film at a high temperature of 200 ° C. for 10 minutes, Although the amount of voltage shift is ± 0.1 V or less, a phenomenon in which the threshold voltage is greatly shifted negatively when negative voltage is applied was observed.

This is because a negative bias is applied to the gate electrode 9 in a high temperature atmosphere, so that it is positive in the vicinity of the interface between the gate oxide film 8 and the SiC semiconductor portion (hereinafter referred to as the SiO ₂ / SiC interface) or in the gate oxide film 8. This shows that the fixed charge is generated. The phenomenon that the threshold voltage shifts to the negative side indicates that holes that are positive charges are generated at the SiO ₂ / SiC interface.

  In Si-based Si-MOSFET and Si-IGBT devices, there are few reports that positive charges are generated at the time of negative bias. Although a phenomenon of threshold voltage shift (slow trap phenomenon) has been reported in a Si-P channel type MOSFET at negative bias, the electric field strength applied to the gate oxide film by applying the gate voltage is -3 MV / cm, and the operating temperature is 150 ° C. Under these conditions, the threshold voltage fluctuation width is a fluctuation width of 0.1 V after 1000 hours.

In the case of the SiC-MOSFET, the electric field strength applied to the gate oxide film by applying the gate voltage varies by −7 V or more under the conditions of −3 MV / cm and the operating temperature of 150 ° C., which is greatly different from the Si-MOSFET. The interface state density at the interface between the gate oxide film and the Si semiconductor portion (hereinafter referred to as SiO ₂ / Si interface) is 1.0 × 10 ¹¹ or less, whereas the interface state density at the SiO ₂ / SiC interface Is 1.0 × 10 ¹² or more, indicating that many hole traps exist at the SiO ₂ / SiC interface. Many studies have been made on reducing the interface state density, but there is no report that the interface state density of the SiO ₂ / SiC interface is equivalent to that of the SiO ₂ / Si interface. The interface state density of SiO ₂ / SiC interface is _high, is a problem specific to SiO 2 / SiC interface, the interface from the difference in the amount of defects, strain amount band structure of SiO ₂ / SiC interface at the current stage It is not clear whether the level density increases.

FIG. 5 is a cross-sectional view of a SiC lateral MOSFET showing a conventional example. Next, in order to investigate the cause of the threshold voltage shift, a lateral MOSFET having no Al wiring metal layer 12 (12a, 12b) on the interlayer insulating film 10 was prepared as shown in FIG. The manufacturing method will be described. First, a low-concentration n-type drift layer 2 doped with nitrogen of 5 × 10 ¹⁵ / cm ³ is deposited on a high-concentration n-type substrate 1 to a thickness of 10 μm. Next, a high concentration p ⁺ type layer 3 is formed by ion implantation. Next, a low concentration p ⁻ -type layer 4 doped with 5 × 10 ¹⁵ / cm ³ of aluminum is deposited on the surface to a thickness of 0.5 μm. Thereafter, the low concentration n-type layer 7 is formed by nitrogen ion implantation.

Next, the high concentration n-type layer 6 is formed by phosphorus ion implantation, and the high concentration p-type layer 5 is formed by aluminum ion implantation. Thereafter, activation annealing is performed at 1600 ° C. in an argon atmosphere. Thereafter, a gate oxide film 8 is formed to a thickness of 70 nm in an N ₂ O atmosphere. Thereafter, the gate electrode 9 and the interlayer insulating film 10 are formed. Thereafter, a nickel silicide electrode 11 is formed to have a thickness of 1.0 μm in order to form an ohmic electrode. Thereafter, an aluminum wiring metal layer 12 is deposited by 5 μm and patterned, and a source Al wiring metal layer (12a) and a drain Al wiring metal layer (12b) are formed without contacting the interlayer insulating film 10, thereby forming a lateral MOSFET. To complete.

  In this device, the threshold voltage fluctuation was ± 0.1 V after a gate voltage of -3 MV / cm applied to the gate oxide film at a high temperature operation of 200 ° C. was applied for 10 minutes. This result shows that the lateral MOSFET having no Al wiring metal layer 12 (12a, 12b) on the MOS gate (on the interlayer insulating film 10) has no threshold voltage fluctuation at the time of negative bias.

Since the structure in which the Al wiring metal layer 12 is not in contact with the interlayer insulating film 10 has no threshold voltage fluctuation, the structural element analysis of the interlayer insulating film 10 / Al wiring metal layer 12 (12a, 12b) is performed at a high temperature. As a result of the analysis by the separated gas spectroscopy, hydrogen atoms and hydrogen ions of 3 × 10 ¹⁴ / cm ² or more were detected at a temperature of 200 ° C. or more. Hydrogen generation in the Al wiring metal layer 12 and from the interface of the interlayer insulating film 10 (SiO ₂ ) / Al wiring metal layer 12 is presumed to be a reaction between the Al wiring metal layer 12 and water.

A large amount of hydrogen ions are taken into the SiO ₂ / SiC interface when the gate oxide film 8 is formed at a high temperature of 800 ° C. or higher or by annealing at a high temperature of 800 ° C. or higher. Hydrogen (Si—H) bonds and carbon-hydrogen (C—H) bonds are not easily changed by low-temperature heat treatment at 400 ° C. or lower.

However, hydrogen atoms and hydrogen ions generated from the Al wiring metal layer 12 deposited at a low temperature (400 ° C. or lower) are not fixed. The high temperature and gate voltage application state, a hydrogen atom, the hydrogen ions generated from the Al wiring metal layer 12 is moved to the SiO ₂ / SiC interface, Si-H bonds of SiO ₂ / SiC interface, C-H bonds are Si + C + dangling of It is thought that it becomes a ring bond and generates a positive charge. The diffusion coefficient of hydrogen atoms / hydrogen ions in the gate oxide film 8 at 200 ° C. is 1.0 × 10 ⁻⁸ [cm ² / s], and the diffusion length of hydrogen atoms / hydrogen ions after 10 minutes is 24.10. It is 5 μm and easily moves in the gate oxide film 8 and diffuses to the SiO ₂ / SiC interface, causing threshold voltage fluctuations.

  As described above, it is possible to make a device having a MOS structure in which the source Al wiring metal layer 12a and the interlayer insulating film 10 are not brought into contact with each other, but the cell size of the MOSFET becomes large and is not suitable for practical use.

  In order to solve the above-described problems, an object of the present invention is to reduce threshold voltage fluctuation after gate voltage application.

In order to achieve the above object, a semiconductor device of the present invention is a semiconductor device in which a silicon dioxide film is formed on a silicon carbide semiconductor substrate, and a titanium film and a titanium nitride film between a source wiring electrode made of aluminum and a gate oxide film. The titanium film or the titanium nitride film has a structure made of columnar polycrystal having a crystal grain size of less than 50 nm.

  The substrate is of a first conductivity type, a first conductivity type drift layer provided on the substrate, a second conductivity type well layer provided on the first conductivity type drift layer, and the second conductivity type well. A first conductivity type impurity region provided in a layer; a gate insulating film of a silicon dioxide film formed on the second conductivity type well layer; a gate electrode formed on the gate insulating film; and the first conductivity A source wiring electrode electrically connected to the type impurity region; a surface on which the first conductivity type drift layer of the substrate is formed; and a drain electrode provided on the opposite surface. To do.

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising: a silicon film formed on a silicon carbide semiconductor substrate; and a titanium film and a titanium nitride between a source wiring electrode made of aluminum and a gate oxide film. A laminate of a film and a titanium film is formed into a columnar polycrystal having a crystal grain size of less than 50 nm.

It pre Symbol titanium film and a titanium nitride film and a titanium film is deposited by sputtering, the pressure of the sputtering is less than or 0.15 Pa 0.4 Pa, temperature of the substrate is less than 200 ° C. or higher 400 ° C. It is characterized by.

  The annealing temperature after the formation of the source wiring electrode is 450 ° C. or lower.

  According to the above configuration, the titanium film and the titanium nitride film are formed into a polycrystalline film having a crystal grain size of less than 50 nm formed by sputtering, so that hydrogen atoms from the source wiring electrode to the gate oxide film / SiC interface. Prevent movement of hydrogen ions.

  According to the present invention, it is possible to reduce the threshold voltage fluctuation after the gate voltage is applied.

FIG. 1 is a cross-sectional view illustrating the configuration of the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view illustrating the configuration of the semiconductor device according to the second embodiment. FIG. 3 is a cross-sectional view illustrating the configuration of the semiconductor device according to the third embodiment. FIG. 4 is a cross-sectional view of a conventional SiC vertical MOSFET. FIG. 5 is a cross-sectional view of a SiC lateral MOSFET showing a conventional example.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted. Further, in this specification, in the notation of Miller index (crystallographic plane index), “−” means a bar attached to the index immediately after that, and “−” is added before the index to make it negative. It represents an index.

(Embodiment 1)
FIG. 1 is a cross-sectional view illustrating the configuration of the semiconductor device according to the first embodiment. FIG. 1 shows a cross-sectional view of a SiC vertical MOSFET. The manufacturing method of this semiconductor device will be described in order. A low concentration first conductivity type (n ⁻ ) drift layer 2 doped with nitrogen of 5 × 10 ¹⁵ / cm ³ is formed on a high concentration first conductivity type (n ⁺ ) substrate 1. Deposit to a thickness of 10 μm. Next, a high concentration second conductivity type (p ⁺ ) layer 3 is formed by ion implantation.

Next, a low-concentration second conductivity type (p ⁻ ) layer 4 doped with 5 × 10 ¹⁵ / cm ³ aluminum is deposited to a thickness of 0.5 μm on the surface. Thereafter, a low concentration first conductivity type (n ⁻ ) layer 7 is formed by nitrogen ion implantation. Next, the high concentration first conductivity type (n ⁺ ) layer 6 is formed by phosphorus ion implantation, and the high concentration second conductivity type (p ⁺ ) layer 5 is formed by aluminum ion implantation. Thereafter, activation annealing at 1600 ° C. is performed in an argon atmosphere.

Thereafter, a gate oxide film 8 is formed to 70 nm in an N ₂ O atmosphere by thermal oxidation. Thereafter, a gate electrode 9 and an interlayer insulating film 10 are formed. Then, a contact hole penetrating through the interlayer insulating film 10 in the depth direction is formed to expose the high concentration first conductivity type (n ⁺ ) layer 6 and the high concentration second conductivity type (p ⁺ ) layer 5. Thereafter, in order to form an ohmic electrode to be an electrical contact portion with the SiC semiconductor portion, the SiC semiconductor portion (high concentration first conductivity type (n ⁺ ) layer 6 and high concentration second conductivity type ( A nickel silicide electrode 11 is formed on the p ⁺ ) layer 5).

  Thereafter, when forming an Al film (Al wiring metal layer) 12 as a source wiring electrode, a titanium (Ti) film 15 and an Al film 12 are sequentially formed on the front surface of the substrate, for example, with a thickness of 0.1 μm and 5.0 μm, respectively. A film is formed (formed) by sputtering (Ti / Al structure). As the sputtering conditions, magnetron sputtering with a substrate temperature of 250 ° C. and an argon pressure of 0.3 Pa can be used. Thereby, the interlayer insulating film 10 is covered with the titanium (Ti) film 15 and an Al film (Al wiring metal layer) 12 in contact with the nickel silicide electrode 11 is formed.

  Thereafter, the Al film 12 is etched to form a source wiring electrode. Thereafter, a polyimide film that is a protective film 14 for protecting the source wiring electrode is formed on the front surface of the substrate, and the protective film 14 is cured (polyimide cure) by annealing at a temperature of about 380 ° C., for example. A back electrode 13 is formed on the substrate to complete the device.

  A TiAl alloy layer 16 is formed at the interface between the Ti film 15 and the Al film 12 by annealing. In the annealing at 380 ° C., the TiAl alloy layer 16 is formed under the Al film 12 with a thickness of 10 nm or less, and the underlying Ti film 15 remains with a thickness of 90 nm. Due to the Ti film 15 under the Al film 12, hydrogen atoms and hydrogen ions in the Al film 12 are absorbed by the Ti film 15, and hydrogen does not diffuse into the gate oxide film 8, and gate oxidation with a stable threshold voltage is achieved. A film 8 can be formed.

  By using the above structure, the threshold voltage fluctuation width after 1000 hours is 0.1 V or less when the electric field strength applied to the gate oxide film when the gate voltage is applied is −3 MV / cm and the operating temperature is 200 ° C. I was able to suppress it.

  Further, the Ti film 15 is a hard material, and cracks occur when the thickness is 1.0 μm or more. Therefore, the thickness of the Ti film 15 is set to 10 nm or more and less than 1.0 μm. That is, the thickness of the Ti film 15 is set to a thickness that is equal to or greater than the thickness of the TiAl alloy layer 16 that can be formed by annealing at 380 ° C. and that does not cause cracks in the Ti film 15. Further, the heat treatment for forming the metal electrode layer made of the Al film 12 is generally performed under a low temperature condition such as about 400 ° C. or less which does not adversely affect the element characteristics. It is known that the TiAl alloy layer 16 reacts at 400 ° C. or higher to form a reaction layer of 50 nm or longer (see, for example, Japanese Patent Laid-Open No. 06-330287). Although the reaction between the Ti film 15 and the Al film 12 does not occur in principle below 400 ° C., in reality, local diffusion at the interface, temperature unevenness of the annealing apparatus, and mixing of impurities that lower the compound generation temperature There is a possibility that it is generated due to various factors such as (contamination). In the experiments by the inventors, in the annealing at 380 ° C., the thickness of the TiAl alloy layer 16 was 10 nm or less. Therefore, the thickness of the TiAl alloy layer 16 is preferably less than 50 nm, which can be formed by a heat treatment at a temperature of 450 ° C. or lower, as will be described later.

  The annealing temperature after forming the source wiring electrode is 450 ° C. or lower. In the experiments by the inventors, it was confirmed that the TiAl alloy layer 16 having a thickness of 50 nm or more is formed at 450 ° C. Since the reaction occurs at the interface between the microcrystalline films, the TiAl alloy layer 16 is not a layer having a uniform thickness. Therefore, the thickness of the TiAl alloy layer 16 formed at an annealing temperature of 450 ° C. is defined as the thinnest value of 50 nm or more within the observed range. As will be described later, since the upper limit of the thickness of the Ti film 15 is less than 50 nm, the upper limit of the temperature of the heat treatment for forming the source wiring electrode is set to 450 ° C.

Due to the effect of occlusion of H by the Ti film 15, the thickness of the Ti film 15 after annealing is set to 10 nm or more. An experiment was conducted on the occlusion effect of the Ti film 15. In the experiment, when hydrogen ions were implanted into the Ti film 15 having a thickness of 100 nm at a temperature of 400 ° C., 6 × 10 ¹⁷ / cm ² of hydrogen atoms and hydrogen ions were occluded. It can occlude hydrogen atoms and hydrogen ions of × 10 ¹⁵ / cm ² or more.

(Embodiment 2)
FIG. 2 is a cross-sectional view illustrating the configuration of the semiconductor device according to the second embodiment. In the first embodiment, the Ti / Al structure is shown. However, in the second embodiment, the Al film 12 that is the source wiring electrode is formed in order to improve the shielding property of hydrogen atoms and hydrogen ions in the Al film 12. Then, a Ti film 15, a titanium nitride (TiN) film 17 and an Al film 12 are sequentially formed on the front surface of the substrate at a thickness of 0.1 μm, 0.1 μm and 5.0 μm by sputtering (Ti / TiN / Al structure). As the sputtering conditions, magnetron sputtering with a substrate temperature of 250 ° C. and an argon pressure of 0.3 Pa can be used.

In order to investigate the hydrogen diffusion coefficient of the TiN film 17, a TiN / SiO ₂ film is formed, annealed in a hydrogen atmosphere at 400 ° C. for 30 minutes, and then subjected to secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry). analyzed. As a result, it was verified that the hydrogen atoms and hydrogen ions were shielded by the TiN film 17 and did not reach the gate oxide film 8. Further, by forming the TiN film 17 between the Ti film 15 and the Al film 12, since the TiAl alloy layer is not formed, the Ti occlusion effect can be enhanced. As described above, according to the second embodiment, by using the Ti / TiN / Al structure, it is possible to further improve the shielding properties of hydrogen atoms and hydrogen ions, and to reduce the threshold voltage fluctuation range.

(Embodiment 3)
FIG. 3 is a cross-sectional view illustrating the configuration of the semiconductor device according to the third embodiment. In the third embodiment, when forming the Al film 12 as the source wiring electrode, the Ti film 15, TiN film 17, Ti film 18 and Al film 12 are formed on the front surface of the substrate by 0.1 μm, 0.1 μm, The layers are sequentially stacked with a thickness of 0.1 μm and 5.0 μm (Ti / TiN / Ti / Al structure). The Ti / TiN / Ti / Al structure is formed by film formation by sputtering, and the sputtering conditions may be magnetron sputtering with a substrate temperature of 300 ° C. and an argon pressure of 0.2 Pa. The TiAl alloy layer 16 formed by the reaction between the Ti film 18 and the Al film 12 is formed in the same manner as in the first embodiment. However, in the third embodiment, the shielding property of hydrogen atoms and hydrogen ions is further improved. Is possible.

As described above, according to each embodiment of the present invention, the Ti film and the TiN film are formed as columnar polycrystalline films having a crystal grain size of less than 50 nm formed by sputtering. The effect of preventing the movement of hydrogen atoms and hydrogen ions from the gate oxide film / SiC interface (SiO ₂ / SiC interface) can be enhanced. Then, by forming the Ti film and the TiN film under the sputtering conditions in which the substrate temperature is 200 ° C. or higher and lower than 400 ° C. and the atmospheric pressure is 0.15 Pa or higher and lower than 0.4 Pa, hydrogen atoms / hydrogen ions The effect of preventing the movement from the source wiring electrode to the gate oxide film / SiC interface can be enhanced.

  This makes it possible to suppress the fluctuation amount of the threshold voltage (Vth) at the time of negative gate bias and positive gate bias (when positive voltage is applied to the gate electrode and when negative voltage is applied), and SiC-MOSFET having stable electrical characteristics. A device can be provided.

  Here, in the Ti film and the TiN film having a crystal grain size of 50 nm or more, the coverage with respect to the fine structure is poor, and in the Ti film and the TiN film having a crystal grain diameter of less than 10 nm, there are many voids and sufficient hydrogen atoms / hydrogen ions. Shielding property cannot be obtained.

  Such an effect is effective in a device having a channel on the SiC C plane (000-1) used for the substrate 1, but other orientation planes (for example, Si plane (0001), (112-0), (033-8)) A device having a channel above has the same effect.

  The same effect can be obtained also in a device having a gate oxide film under the gate electrode (for example, SiC-IGBT). Further, the present invention is similarly established even when the conductivity type is reversed.

  As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for a semiconductor device used for a power conversion device, a power supply device such as various industrial machines, and the like.

1 SiC substrate 2 Epitaxial crystal (drift layer)
3 p ⁺ layer 4 Epitaxial crystal (well layer)
5 p ⁺ layer 6 n ⁺ layer 7 n ⁻ layer 8 Gate oxide film 9 Gate electrode 10 Interlayer insulating film 11 Electrode contact (nickel silicide electrode)
12 Al film (source wiring electrode)
13 Back electrode 14 Protective film 15, 18 Ti film 16 TiAl alloy layer 17 TiN film

Claims (5)

In a semiconductor device in which a silicon dioxide film is formed on a silicon carbide semiconductor substrate,
A titanium film, a titanium nitride film, and a titanium film are laminated between a source wiring electrode made of aluminum and a gate oxide film, and the titanium film or the titanium nitride film is made of a columnar polycrystal having a crystal grain size of less than 50 nm. A semiconductor device having a structure. The substrate is of a first conductivity type; a first conductivity type drift layer provided on the substrate;
A second conductivity type well layer provided in the first conductivity type drift layer;
A first conductivity type impurity region provided in the second conductivity type well layer;
The gate oxide film of a silicon dioxide film formed on the second conductivity type well layer;
A gate electrode formed on the gate oxide film ;
The source wiring electrode electrically connected to the first conductivity type impurity region;
A drain electrode provided on a surface of the substrate on which the first conductivity type drift layer is formed and an opposite surface;
The semiconductor device according to claim 1, further comprising: In a method for manufacturing a semiconductor device in which a silicon dioxide film is formed on a silicon carbide semiconductor substrate,
A method of manufacturing a semiconductor device, comprising: stacking a titanium film, a titanium nitride film, and a titanium film between a source wiring electrode made of aluminum and a gate oxide film into a columnar polycrystal having a crystal grain size of less than 50 nm. . Wherein the pre-Symbol titanium film and a titanium nitride film and a titanium film is deposited by sputtering, the pressure of the sputtering is less than or 0.15 Pa 0.4 Pa, temperature of the substrate is less than 200 ° C. or higher 400 ° C. A method for manufacturing a semiconductor device according to claim 3 . The method for manufacturing a semiconductor device according to claim 3, wherein an annealing temperature after the formation of the source wiring electrode is 450 ° C. or lower.

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