JP6413719B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device in which a power semiconductor element for controlling a load current flowing in a mutual inductance load such as a stepping motor and an integrated circuit for detecting a load abnormality and protecting the power semiconductor element are integrated on the same semiconductor substrate.

  FIG. 7A is a diagram illustrating an overall configuration of a main part of the stepping motor. FIG. 7B shows the arrangement of the rotor 97 and the coil 90 of the stepping motor. The stepping motor includes a rotor 97 and four coils 90 (91 to 94) that rotate the rotor 97. As shown in FIG. 7A, the control circuits 501a to 501d include output stage nMOSFETs 51a to 51d, respectively. The output stage nMOSFETs 51a to 51d control currents flowing through the coils 91 to 94 connected thereto. Parasitic diodes (without reference numerals) are connected in parallel to the output stage nMOSFETs 51a to 51d, respectively. Furthermore, each of the control circuits 501a to 501d includes various detection circuits (such as an overheat detection circuit and an overcurrent detection circuit) and a protection circuit (not shown). In addition, a battery B as a power source is required.

  As shown in FIG. 7B, the four coils 91 to 94 are arranged around the rotor 97. The two opposing coils 91 and 93 are, for example, iron core-containing coils wound around one iron core 95 and having mutual inductance. Similarly, the two coils 92 and 94 facing each other are coils with an iron core wound around one iron core 96 and having mutual inductance. Therefore, the iron cored coils 91 and 93 are referred to as mutual inductance loads, and the iron cored coils 92 and 94 are also referred to as mutual inductance loads. In addition, a pair of output stage nMOSFETs 51a and 51c connected to two coils (a pair of coils 91 and 93) wound around one iron core 95 are complementary to each other (when one is turned on, the other is turned off. So that the actions performed between the two). A pair of output stage nMOSFETs 51b and 51d connected to two coils (a pair of coils 92 and 94) wound around one iron core 96 also perform complementary operations. These four coils 91 to 94 are arranged around the rotor 97 to give a rotational force to the rotor 97.

  The one coil 90 and the output stage nMOSFET 51 of one control circuit 501 constitute one arm. Reference numeral 90 is used when generically referring to the coils 91 to 94, and reference numeral 51 is used when generically referring to the output stage nMOSFETs 51a to 51d. Similarly, reference numeral 501 is used to collectively refer to the control circuits 501a to 501d.

  This stepping motor is controlled by four arms, the first arm to the fourth arm. Load currents flowing through the coils 91 to 94, which are mutual inductance loads, flow through the first to fourth arms. Each arm is provided with one control circuit 501. Stepping motors equipped with these arms are used, for example, for exhaust gas recirculation of automobiles. Therefore, hereinafter, the arm is referred to as EGR. EGR is an abbreviation for Exhaust Gas Recirculation. The first to fourth arms are referred to herein as EGR1 to EGR4, and each of the first to fourth arms includes coils 91 to 94 and output stage nMOSFETs 51a to 51d.

  The control circuit 501 includes an IN terminal (IN) as an input terminal, an OUT terminal (OUT) as an output terminal, an ST terminal (ST) as a status terminal (state output terminal), and a GND terminal (GND) as a ground terminal. Has two terminals.

  FIG. 8 is a block diagram showing a simplified configuration of the first arm EGR1 and the third arm EGR3 shown in FIG. When the first arm EGR1 is turned off and the third arm EGR3 is turned on, an induced electromotive force is generated in the coil 93 containing the iron core 95 which is a mutual inductance load. Due to this induced electromotive force, current flows in the direction of charging the battery power supply B through a parasitic diode (not shown) connected in parallel to the output stage nMOSFET 51c shown in FIG. Flowing. At this time, the polarity of the OUT3 terminal becomes negative. Thereafter, when a steady state is reached, a normal current flows through the iron-core-equipped coil 93 (inductance load) via the output stage nMOSFET 51c of the third arm EGR3 that is already in the on state, and a normal operation is performed. Here, the control circuits 501a and 501c are driven by a signal from the timing generator.

  FIG. 9 is a detailed circuit diagram of the control circuit 501 (501a to 501d) shown in FIG. The circuit configurations of the control circuits 501a to 501d are all the same. The control circuit 501 includes an output stage nMOSFET 51 including voltage dividing resistors 64 and 65 that divide the voltage at the OUT terminal, an nMOSFET portion 52 and a parasitic diode portion 53. The control circuit 501 also includes a dynamic clamp Zener diode 54 connected between the drain 52b and the gate 52a of the output stage nMOSFET 501. The dynamic clamp Zener diode 54 is composed of Zener diodes 54a and 54b connected in reverse series with each other.

  Further, the control circuit 501 includes an nMOSFET 55a that is connected to the gate 52a of the output stage nMOSFET 51 and constitutes a gate charge extraction circuit 55 for protection operation described later. The control circuit 501 further includes a resistor 63 connected to the drain (not shown) of the nMOSFET 55a, and a gate charge extraction circuit 56 in normal operation which is connected to the resistor 63 and includes a constant current source 56a (depletion MOSFET 56b). The control circuit 501 includes a logic circuit 57 that is connected to the connection point 63a of the constant current source 56a and the resistor 63 and is connected to each of the overheat detection circuit 59 and the overcurrent detection circuit 60.

  The ST terminal is connected to a Zener diode 66b and an nMOSFET 58a for detecting (disconnection detection) whether the load is normally connected or abnormally opened due to disconnection or the like. Further connected to the ST terminal is an ST-MOS circuit 58 comprising an nMOSFET 58b for transmitting an abnormal signal to the ST terminal when an abnormal signal is output from the logic circuit 57.

  The IN terminal is connected to the cathode of the Zener diode 66c and the logic circuit 57, the GND terminal is connected to the source of each nMOSFET, and the OUT terminal is connected to the drain of the output stage nMOSFET 51 and the voltage dividing resistors 64 and 65.

  The ST-MOS circuit 58 detects disconnection as follows. When there is no abnormality in the load (coil 90), when the nMOSFET 51 in the output stage is turned off, the voltage at the OUT terminal connected to the battery B through the load increases. Therefore, the voltage taken out from the connection point of the two resistors 65 also rises and the nMOSFET 58a is turned on. Since the drain electrode of the nMOSFET 58a is connected to the ST terminal, a state detection signal when there is no abnormality (normal) in the load is output to the ST terminal.

  On the other hand, when a disconnection occurs such that the load (coil 90) connected to the OUT terminal is burned out or the connector is disconnected, the load is released from the OUT terminal, and the voltage of the battery B is held at the load portion. For this reason, the voltage at the OUT terminal does not rise, and is pulled out from the connection point of the two resistors of the voltage dividing resistor 65, and the voltage applied to the gate of the nMOSFET 58a through the lead of the disconnection detection line 69 does not rise. At this time, the nMOSFET 58a remains in the OFF state, and a state detection signal indicating a state in which the load is opened and disconnected is output from the ST terminal.

  In the same ST-MOS circuit 58, the operation of the nMOSFET 58b connected in parallel with the nMOSFET 58a is as follows. When the logic circuit 57 detects an abnormal state such as overheating or overcurrent of the output stage nMOSFET 51, the logic circuit 57 outputs an abnormal signal (logic high, H) to the gate electrode of the nMOSFET 58b. As a result, the nMOSFET 58b is turned on, and a state detection signal (abnormal signal) is output to the ST terminal.

  A control device (such as a microcomputer) not shown is connected to the ST terminal from the outside. Depending on the combination of the logic value of the gate signal to the output stage nMOSFET 51 output from the timing generator and the logic value of the signal output from the ST terminal, the load connected to the OUT terminal is in an abnormal state or the above The control device determines which of the abnormal states is present.

  FIG. 10 is a cross-sectional view showing a main part of a conventional semiconductor device 500 (500a to 500d) in which the control circuit 501 (501a to 501d) shown in FIG. The circuit configurations of the control circuits 501a to 501d in the semiconductor devices 500a to 500d are all the same. The battery B constituting the control circuit 501 is externally attached.

  The semiconductor device 500 includes a vertical output stage nMOSFET 51. In the semiconductor device 500, a plurality of p well regions 71, 73, 76 are formed in the surface layer of the n semiconductor substrate 70. The semiconductor device 500 also includes a logic circuit 57 formed on the surface layer of one p-well region 76 of the plurality of p-well regions, an overheat detection circuit 59 (not shown), and an overcurrent detection circuit 60 (not shown). . The surface layer of the p-well region 76 is further provided with a lateral nMOSFET 55a of the gate charge extraction circuit 55 for protection operation and a gate charge extraction circuit 56 for normal operation.

As an n ⁺ type region connected to the GND wiring, an n source region 72 (source 52c) of the output stage nMOSFET 51 formed in the surface layer of the p well region 71 which is one of the other p well regions is provided. Further, an n cathode region 74 of a Zener diode 54a (formed in the n semiconductor substrate 70) constituting the dynamic clamp Zener diode 54 formed in the surface layer of the p well region 73 which is the remaining one p well region is provided. In addition, an n ⁺ region 75 is formed on the surface layer of the n semiconductor substrate 70 and connected to the ground GND.

  The ST terminal (ST) is connected to an n drain region 79 of a lateral nMOSFET 58b formed in the p well region 76 and constituting the ST-MOS circuit 58 via a resistor 67e. The IN terminal (IN) is connected to the gate 52a of the output stage nMOSFET 51 through the resistors 67b, 63 and 67a by the gate wiring 68. The OUT terminal (OUT) is connected to an electrode formed on the entire back surface of the n semiconductor substrate 70. The electrode formed on the entire back surface of the n semiconductor substrate 70 becomes the drain electrode of the output stage nMOSFET 51.

  The GND terminal (GND) is connected to the n source region (no symbol) of the lateral nMOSFET 55a that constitutes the gate charge extraction circuit 55 during the protection operation. Further, the GND terminal is connected to the n source region 78 of the depletion MOSFET 56b serving as the constant current source 56a constituting the gate charge extracting circuit 56 in the normal operation. Further, the GND terminal includes an n source region (not indicated) of the lateral nMOSFET 57a of the logic circuit 57, an n source region (not indicated) of the nMOSFET 58b (58a) in which the n drain region 79 is connected to the ST terminal (ST), and a p well region. 76, respectively.

  In addition, the n drain region (not shown) of the lateral nMOSFET 55 a and the n drain region 77 of the depletion MOSFET 56 b are connected to the gate wiring 68. In addition, a surge protection Zener diode 81 connected between the IN terminal and the GND terminal and a Zener diode 82 connected between the GND terminal and the ST terminal are provided.

  Both the p-well region 71 and the n-source region 72 (source 52c) of the output stage nMOSFET 51 are connected to the ground GND. The p well region 71 and the n semiconductor substrate 70 form a parasitic diode portion 53 of the output stage nMOSFET 51.

  The overheat detection circuit 59, the overcurrent detection circuit 60, the logic circuit 57, the protection operation gate charge extraction circuit 55, and the normal operation gate charge extraction circuit 56 shown in FIG. 9 are formed in the p-well region 76 of FIG. , Each is self-separated by a certain distance apart.

  FIG. 11 is an operation waveform diagram showing waveforms of input voltages VIN1 to VIN4 to the first arm EGR1 to the fourth arm EGR4 shown in FIG.

  With respect to the phase of the input voltage VIN1 to the first arm EGR1, the input voltage VIN2 to the second arm EGR2, and the input voltage VIN3 to the third arm EGR3, the input voltage VIN2 to the second arm EGR2 and the third arm EGR3 The phases of the input voltage VIN3 and the input voltage VIN4 to the fourth arm EGR4 are delayed by half the pulse width of the input voltage VIN. This input voltage VIN is transmitted through the gate wiring 68 and becomes the gate voltage of the output stage nMOSFET 51. When VIN is at H level, a load current flows through the output stage nMOSFET 51 of the arm EGR, and the arm EGR is turned on. When the EGR1 to EGR4 are sequentially turned on, the rotor 97 is rotated, and the stepping motor including the coil 90 and the rotor 97 is rotated. By rotating this stepping motor, for example, a valve provided in a route for flowing exhaust gas of an automobile (not shown) is opened and closed, and exhaust gas is recirculated.

  The output stage nMOSFET 51a constituting the first arm EGR1 and the output stage nMOSFET 51c constituting the third arm EGR3 perform a complementary operation (complementary operation) in which when one is turned on, the other is turned off. That is, the first arm EGR1 and the third arm EGR3 are in a complementary relationship. Therefore, the falling point of the input voltage VIN1 of the first arm EGR1 is the rising point of the input voltage VIN3 of the third arm EGR3 (location C). Similarly, EGR2 and EGR4 perform complementary operations.

  12 shows the waveforms of the input voltage VIN3, voltage VST3, voltage VOUT3 and current IOUT3 in the control circuit 501c of the third arm EGR3, and the input voltage VIN1, voltage VST1, voltage VOUT1 and current IOUT1 in the control circuit 501a of the first arm EGR1. It is a wave form diagram which shows these waveforms. Here, the input voltage represented by the symbol VIN is an input voltage (also referred to as a gate voltage or a control voltage) to the IN terminal which is an input terminal represented by the symbol IN, and the voltage represented by the symbol VST is: The voltage of the ST terminal which is a status terminal represented by the symbol ST, and the voltage represented by the symbol VOUT is the drain voltage of the output stage nMOSFET 51 which is the voltage of the OUT terminal which is the output terminal represented by the symbol OUT. , IOUT is a current flowing through the OUT terminal, that is, a drain current flowing through the output stage nMOSFET 51. This current IOUT is also a load current flowing through the coil 90 (mutual inductance load) of the arm EGR.

As shown in FIG. 12, the ON signal as the input voltage VIN3 at time t ₀ is input, the OFF signal is inputted as an input voltage VIN1. Then, the output stage nMOSFET51a of the first arm EGR1 is turned off at time t ₁ after due to the presence of the Miller capacitance of the time delay, current IOUT1 becomes zero, voltage VOUT1 becomes the voltage of the battery B is a power supply voltage. At time t ₁ when the state of the output stage nMOSFET 51a of the first arm EGR1 changes from the on state to the off state, the state of the output stage nMOSFET 51c of the third arm EGR3 shifts from the off state to the on state. As a result, the voltage VOUT3 falls. In the process after time t ₁ , due to the mutual inductance between the coil 93 of the third arm EGR 3 and the coil 91 of the first arm EGR 1, the coil 93 of the third arm EGR 3 moves from the ground GND toward the battery B. A current (reverse current) flows in the opposite direction. The reverse current period lasts determined by the mutual inductance value, then, at time t ₂ when the forward current exceeds the reverse current, the current flowing through the third arm EGR3 is switched to the current (forward current) toward the ground GND from the battery B The This reverse current charges the battery B as a regenerative current.

  In order to prevent this, a free-wheeling diode may be provided in the mutual inductance load.

  The semiconductor device disclosed in Patent Document 1 includes a power semiconductor element for switching control of the load device, and a semiconductor integrated circuit for detecting an abnormality of the load device. Further, a pull-down voltage dividing circuit that divides the output terminal voltage of the power semiconductor element by a pull-down resistor connected in series, a MOSFET that detects the opening of a load device when a power supply voltage is supplied from the voltage dividing circuit, and a semiconductor integrated circuit There is a built-in MOSFET that is turned on or off by an abnormal signal output from the circuit. Further, a state output terminal for outputting the detection result of the open state of the load device to the outside is provided. With this configuration, it is possible to provide a semiconductor device that can detect the load release state in the load driving system without supplying power to the semiconductor integrated circuit. As the load device in this case, it is assumed that a self-inductance load such as a solenoid or a coil is used.

  Patent Document 2 discloses a first switching unit that turns on and off a current flowing through a load, a current detection unit that detects a current flowing through the load, and an on / off unit that opens and closes a connection between the current detection unit and the load. A semiconductor device having second switching means for turning off and control means for controlling the second switching means and the first switching means is described. In this semiconductor device, the control means turns on the second switching means after turning on the first switching means at the start of driving the load, and the current detecting means detects the overcurrent when the current detecting means detects the overcurrent. Only one switching means is turned off. Further, it is described that this configuration can provide a semiconductor device that reliably and quickly turns off the semiconductor element when the load is short-circuited, and protects the semiconductor element from the load short-circuit. Also in this case, it is assumed that a self-inductance load such as a solenoid or a coil is used.

  In Patent Document 3, when the potential of the ground GND becomes higher than the potential of the output of the semiconductor device due to the reverse current of the inductive load, the MOSFET's parasitic transistor connected to the self-diagnosis output is not always turned on. It is described that a voltage is supplied from the drain of the depletion type MOSFET to the back gate of the MOSFET. In this case, it is assumed that a mutual inductance load such as a stepping motor is used.

JP 2010-110093 A Japanese Patent Laid-Open No. 2000-12853 JP2011-239242A

FIG. 13A shows the paths P1 and P2 of the reverse current flowing through the semiconductor device 500c of the third arm EGR3 in which the output stage nMOSFET 51c is on during the off period of the output stage nMOSFET 51a of the first arm EGR1. It is sectional drawing of the apparatus 500c. In the period between the times t ₁ and t ₂ shown in FIG. 12, the induced electromotive force generated in the coil 93 due to the presence of the mutual inductance between the coil 93 of the third arm EGR 3 and the coil 91 of the first arm EGR 1 ( A reverse current caused by (back electromotive force) flows to the semiconductor device 500c. A path P1 passing through the parasitic diode portion 53 of the output stage nMOSFET 51c and a path P2 passing from the p-well region 76 to the n semiconductor substrate 70 are paths of a reverse current flowing through the semiconductor device 500c of the third arm EGR3.

On the other hand, a plurality of n ⁺ -type regions are formed on the surface of the p-well region 76, and some of them are connected to the IN3 terminal via the gate wiring 68 or to the ST3 terminal via the resistor 67e. The partial n ⁺ -type region (n collector region) forms a parasitic transistor 88 together with the p well region 76 (p base region) and the n semiconductor substrate 70 (n emitter region). FIG. 13B is a schematic cross-sectional view of this parasitic transistor 88. Due to the induced electromotive force (back electromotive force) generated in the coil 93, a forward bias voltage is applied to the pn junction between the p well region 76 connected to the GND3 terminal of approximately 0 V and the n semiconductor substrate 70 connected to the OUT3 terminal. Is applied, and a reverse current flows from the GND3 terminal to the OUT3 terminal. In this case, a voltage drop V1 is generated at the OUT3 terminal by an amount of, for example, −0.6 V, which is a built-in potential difference (Vbi) at the pn junction between the p well region 76 and the n semiconductor substrate 70 with respect to the GND3 terminal. Thereby, holes are injected from the p-well region 76 into the semiconductor substrate 70 as shown in FIG.

In the forward-biased pn junction, electrons are injected from the n semiconductor substrate 70 into the p-well region 76. Since some positive voltage is applied to the IN3 terminal with respect to the GND3 terminal, a reverse bias voltage is applied to the pn junction between the n ⁺ -type region connected to the IN3 terminal and the p-well region 76. . Therefore, electrons injected into the p-well region 76 (p-base region) reach an n ⁺ -type region where a part of the electrons is connected to the IN3 terminal while the concentration is reduced. Thus, when the electrons reach the n ⁺ -type region, the collector current Inpn of the parasitic transistor 88 flows from the IN3 terminal toward the OUT3 terminal.

The electrons reach the n ⁺ -type region connected to the ST3 terminal as well as the electrons to the IN3 terminal. For this reason, the collector current Inpn flows from the ST3 terminal toward the OUT3 terminal. Due to the collector current Inpn from the ST3 terminal, the voltage of the ST3 terminal becomes equal to the voltage of the n semiconductor substrate 70. Therefore, during the period in which the reverse current flows, the voltage level of the ST3 terminal is the same L level as that of the n semiconductor substrate 70. In this way, the voltage at the ST terminal is at the L level during a period that should originally be at the H level, which causes erroneous detection in the microcomputer (MC) to which the voltage at the ST3 terminal is input.

  Further, if the free wheel diode is provided as described above, the number of parts increases and the cost increases.

  Further, in the semiconductor devices disclosed in Patent Documents 1 and 2, it is assumed that a self-inductance load is used. Therefore, the malfunction of the parasitic transistor caused when the polarity of the OUT terminal becomes negative in the power semiconductor element connected to the mutual inductance load is not described.

  Further, in the semiconductor device disclosed in Patent Document 3, the operation of the parasitic transistor in the depletion MOSFET is likely to become unstable when, for example, variation in the impurity concentration distribution in the p-well region occurs. For this reason, when the parasitic transistor in the depletion MOSFET does not operate, the parasitic transistor of the MOSFET to which the self-diagnosis output is input malfunctions and the DIAG terminal (corresponding to the ST terminal) is always maintained at a normal voltage. I can't.

  The object of the present invention is to solve the above-mentioned problems, connect to a mutual inductance load, suppress malfunction of a parasitic transistor formed in the semiconductor device, and maintain the voltage of the ST terminal at a regular voltage at all times. An object of the present invention is to provide a semiconductor device that can be used.

An output stage switching element for controlling a current flowing in a load having a mutual inductance;
A detection circuit for detecting an abnormality of the output stage switching element;
A logic circuit that determines a state of the output stage switching element based on an output of the detection circuit; a state detection circuit that outputs a connection state of the load and the output stage switching element and a determination result of the logic circuit to a state output terminal;
A voltage divider diode connected in series to the state detection circuit by connecting a cathode to the state detection circuit, an anode connected to the ground, and the output stage switching element of the second conductivity type The semiconductor layer is formed on the surface layer of the semiconductor layer as a high potential side of the output stage switching element, the semiconductor layer is connected to an output terminal of the control circuit, and the detection circuit and the logic circuit are connected to the second conductive layer. Formed in a first well region of a first conductivity type formed in a surface layer of a semiconductor layer of a type, and the state detection circuit is provided on a surface layer of the semiconductor layer of the second conductivity type. A first conductivity type lateral MOSFET formed on the surface of a first conductivity type second well region formed apart from the one well region, the first conductivity type first well region and the output stage switch; N The low potential side of the element is connected to the ground terminal of the control circuit, the second well region of the first conductivity type constitutes the back gate of the lateral MOSFET of the second conductivity type, and the divided voltage is applied to the back gate. The semiconductor device is configured such that a cathode of a diode is connected, and the second well region of the first conductivity type is connected to the ground terminal via an anode of the voltage dividing diode .

Preferably, the output terminal is connected to the high potential side of the power supply via the load, and the ground terminal is connected to the low potential side of the power supply .

  A forward bias voltage applied to the first pn junction between the first well region and the semiconductor layer is a voltage applied to a second pn junction of the voltage dividing diode, and the second well region and the semiconductor layer It is preferable to be equal to the sum of the voltage applied to the third pn junction.

  The voltage applied to the second pn junction is preferably smaller than the built-in voltage of the second pn junction.

  The voltage applied to the third pn junction is preferably smaller than the built-in voltage of the third pn junction.

  The distance between the first well region and the second well region is preferably 10 μm or more and 500 μm or less.

  The voltage dividing diode is preferably formed on an oxide film formed on the surface side of the semiconductor layer.

  The oxide film is preferably formed on a third well region of the first conductivity type formed on the surface of the semiconductor layer so as to be separated from both the first well region and the second well region.

  Preferably, the distance between the second well region and the third well region and the distance between the second well region and the third well region are 10 μm or more and 500 μm or less, respectively.

  The output stage switching element is preferably a vertical MOSFET of the second conductivity type.

  In addition, it is preferable that a separation distance between the first well region and the second well region is longer than a diffusion length of minority carriers injected from the first well region into the semiconductor layer.

  In addition, it is preferable that a separation distance between the second well region and the third well region is longer than a diffusion length of minority carriers injected from the first well region into the semiconductor layer.

  The voltage dividing diode is preferably formed of polysilicon.

  The voltage dividing diode is a lateral diffusion junction diode, and the lateral diffusion junction diode is deeper than a diffusion depth of the first well region, higher than an impurity concentration of the first well region, and Preferably, it is formed on the surface layer of the third well region of the first conductivity type formed separately from the 1 well region and the second well region.

A fourth well region of the first conductivity type is formed in the region of forming the second conductivity type lateral MOSFET constituting the state detection circuit formed on the surface of the second well region of the first conductivity type. Formed in the second well region of the first conductivity type so as to overlap at least the source region;
The fourth well region has a diffusion depth deeper than the diffusion depth of the second well region and an impurity concentration higher than the impurity concentration of the second well region, and is connected to the cathode of the voltage dividing diode. A configuration is preferable.

  According to the present invention, in the semiconductor device connected to the mutual inductance load, the anode of the diode is connected to the ground GND terminal, and the cathode is connected to the back gate of the lateral nMOSFET constituting the ST-MOS circuit which is the state detection circuit. To do. Thereby, it is possible to suppress the malfunction of the parasitic transistor of the lateral nMOSFET, and the voltage of the ST terminal, which is the output terminal of the ST-MOS circuit, can always be maintained at a normal voltage.

1 is a circuit diagram showing a main part of a control circuit 101 using a semiconductor device 100 or 200 of the present invention. It is sectional drawing which shows the principal part of the semiconductor device 100 which concerns on Embodiment 1 of this invention. The waveforms of the input voltage VIN3, voltage VST3, voltage VOUT3 and current IOUT3 in the control circuit 101c of the third arm EGR3, and the waveforms of the input voltage VIN1, voltage VST1, voltage VOUT1 and current IOUT1 in the control circuit 101a of the first arm EGR1 are shown. FIG. (A) is sectional drawing of the semiconductor device 100c explaining the case where the output stage nMOSFET1a of the 1st arm EGR1 turned off and the output stage nMOSFET1c of the 3rd arm EGR3 turned on, (b) is the voltage by the voltage dividing diode 40 It is sectional drawing which shows a sharing typically. It is sectional drawing which shows the principal part of the semiconductor device 200 concerning Embodiment 2 of this invention. FIG. 10 is a cross-sectional view showing a main part of a modification of the semiconductor device 200. It is a block diagram which shows the principal part of a stepping motor, (a) is a figure which shows the whole structure of a principal part, (b) is a layout drawing of the rotor 97 and the coil 90 of a stepping motor. FIG. 8 is a block diagram showing a simplified configuration of the first arm EGR1 and the third arm EGR3 shown in FIG. FIG. 8 is a detailed circuit diagram of the control circuit 501 shown in FIG. 7 is a cross-sectional view showing a main part of a conventional semiconductor device 500 in which a control circuit 501 shown in FIG. FIG. 8 is a waveform diagram showing waveforms of an input voltage VIN1 to an input voltage VIN4 to the first arm EGR1 to the fourth arm EGR4 shown in FIG. The waveforms of the input voltage VIN3, voltage VST3, voltage VOUT3 and current IOUT3 in the control circuit 501c of the third arm EGR3, and the waveforms of the input voltage VIN1, voltage VST1, voltage VOUT1 and current IOUT1 in the control circuit 501a of the first arm EGR1 FIG. (A) shows the paths P1 and P2 of the reverse current flowing in the semiconductor device 500c of the third arm EGR3 in which the output stage nMOSFET 51c is on during the off period of the output stage nMOSFET 51a of the first arm EGR1. It is sectional drawing, (b) is a schematic cross section which shows operation | movement of a parasitic transistor. It is sectional drawing which shows the voltage dividing diode 40 concerning Embodiment 1 of this invention.

  FIG. 1 is a circuit diagram showing a main part of a control circuit 101 (101a to 101d) using a semiconductor device 100 or 101 of the present invention. The control circuit 101 includes an output stage nMOSFET 1 including voltage dividing resistors 14 and 15 that divide the voltage at the OUT terminal, an nMOSFET portion 2 and a parasitic diode portion 3. The control circuit 101 includes a dynamic clamp Zener diode 4 connected between the drain 2b and the gate 2a of the output stage nMOSFET 1. The dynamic clamp Zener diode 4 is composed of Zener diodes 4a and 4b that are connected in reverse series with each other. The control circuit 101 represents the control circuit 101a, the control circuit 101b, the control circuit 101c, and the control circuit 101d provided in the first arm EGR1, the second arm EGR2, the third arm EGR3, and the fourth arm EGR4, respectively.

  The control circuit 101 includes a lateral nMOSFET 5a that is connected to the gate 2a of the output stage nMOSFET 1 and constitutes the gate charge extraction circuit 5 during the protection operation. The control circuit 101 further includes a resistor 13 connected to the drain (not shown) of the lateral nMOSFET 5a and a gate charge extraction circuit 6 in normal operation which is connected to the resistor 13 and includes a constant current source 6a.

  The control circuit 101 includes a logic circuit 7 connected to the connection point 13a between the depletion MOSFET 6b serving as the constant current source 6a and the resistor 13 and connected to the overheat detection circuit 9 and the overcurrent detection circuit 10, respectively. The overcurrent detection is performed by connecting the detection line drawn from the connection point 14 a of the voltage dividing resistor 14 to the overcurrent detection circuit 10.

  The ST terminal is connected to a Zener diode 16b and a lateral nMOSFET 8a for detecting whether the load is normally connected or abnormally opened due to disconnection or the like (disconnection detection). The disconnection detection is performed by a configuration similar to the configuration shown in FIG. 9 described above by connecting the lead of the disconnection detection line 19 drawn from the connection point 15a of the voltage dividing resistor 15 to the gate of the lateral nMOSFET 8a. Further, a lateral nMOSFET 8b that transmits an abnormal signal to the ST terminal when an abnormal signal is output from the logic circuit 7 is connected to the ST terminal. Abnormality detection is also performed by a configuration similar to the configuration shown in FIG. As described above, the control circuit 101 includes the ST-MOS circuit 8 including the lateral nMOSFETs 8a and 8b.

  The control circuit 101 also includes an IN terminal connected to the cathode of the Zener diode 16c and the logic circuit 7, a GND terminal connected to the source of each nMOSFET, a drain of the output stage nMOSFET 1 and an OUT terminal connected to the voltage dividing resistors 14 and 15. .

  A voltage dividing diode 40 is connected in series to the back gates of the lateral nMOSFET 8a and the lateral nMOSFET 8b constituting the ST-MOS circuit 8 with the anode connected to the GND terminal.

  Next, the semiconductor device according to the present invention will be specifically described in the following embodiments. In the following description, the first conductivity type is p-type, and the second conductivity type is n-type.

(Embodiment 1)
FIG. 2 is a cross-sectional view showing a main part of the semiconductor device 100 according to the first embodiment of the present invention. A control circuit 101 shown in FIG. 1 is formed on the surface of the same n-type semiconductor substrate 20. The battery B and the like constituting the control circuit 101 are externally attached. In the semiconductor device 100, the first arm EGR1, the second arm EGR2, the third arm EGR3, and the fourth arm EGR4 represent the semiconductor device 100a, the semiconductor device 100b, the semiconductor device 100c, and the semiconductor device 100d, respectively.

  The semiconductor device 100 includes a vertical output stage nMOSFET 1. The semiconductor device 100 includes a plurality of p-well regions 21, 23, 26, 26 a formed in the surface layer of the n-type semiconductor substrate 20. The semiconductor device 100 further includes a logic circuit 7, an overheat detection circuit 9 (not shown), and an overcurrent detection circuit 10 formed on the surface layer of one p-well region 26 among the plurality of p-well regions. The surface layer of the p-well region 26 is further provided with a lateral nMOSFET 5a of the gate charge extraction circuit 5 during protection operation and a gate charge extraction circuit 6 during normal operation.

  Lateral nMOSFETs 8a and 8b are provided on the surface layer of the p-well region 26a constituting the ST-MOS circuit 8. The p-well region 26a is connected to the cathode 40a of the voltage dividing diode 40, and its anode 40b is connected to the GND terminal. The p-well region 26a serves as a back gate common to the lateral nMOSFETs 8a and 8b.

As an n ⁺ type region connected to the GND wiring, an n source region 22 (source 2c) of the output stage nMOSFET 1 formed in the surface layer of the p well region 21 which is one of the other p well regions is provided. Furthermore, an n cathode region 24 of a Zener diode 4a (formed in the n-type semiconductor substrate 20) constituting the dynamic clamp Zener diode 4 formed on the surface layer of the p well region 23 which is the remaining one p well region is provided. The cathode of the Zener diode 4b of the dynamic clamp Zener diode 4 is connected to the IN terminal via the resistor 17a, the resistor 13, the resistor 17b, and the like. The IN terminal is connected to the GND terminal via the resistor 17c. In addition, an n ⁺ region 25 connected to GND formed on the surface layer of the n-type semiconductor substrate 20 is provided.

  The ST terminal (ST) is connected to the n drain region 29 of the lateral nMOSFET 8b formed in the p well region 26a and constituting the ST-MOS circuit 8 via the resistor 17e. The ST terminal is connected to the high potential side terminal of the power supply B via the resistor 17d, and the low potential side terminal of the power supply B is connected to the ground (GND). The IN terminal (IN) is connected to the gate 2a of the output stage nMOSFET 1 by the gate wiring 18 via the resistors 17b, 13 and 17a. The ST terminal is further connected to a microcomputer or the like for processing a disconnection detection signal or an abnormal signal.

  The OUT terminal (OUT) is connected to an electrode formed on the entire back surface of the n-type semiconductor substrate 20. The electrode formed on the entire back surface of the n-type semiconductor substrate 20 serves as the drain electrode of the output stage nMOSFET 1.

  The GND terminal (GND) is connected to the n source region (not shown) of the lateral nMOSFET 5a constituting the gate charge extracting circuit 5 during the protection operation. Further, the GND terminal (GND) is connected to the n source region 28 of the depletion MOSFET 6b which becomes the constant current source 6a constituting the gate charge extracting circuit 6 in the normal operation and the n source region (not indicated) of the lateral nMOSFET 7a of the logic circuit 7. Connecting. The GND terminal is connected to the n source region (not shown) and the p well region 26 of the lateral nMOSFET 8b in which the n drain region 29 is connected to the ST terminal (ST).

  In addition, the n drain region (not shown) of the lateral nMOSFET 5 a and the n drain region 27 of the depletion MOSFET 6 b are connected to the gate wiring 18. In addition, a surge protection Zener diode 31 connected between the IN terminal and the GND terminal and a Zener diode 32 connected between the GND terminal and the ST terminal are provided.

  Further, the p-well region 21 and the n-source region 22 (source 2c) of the output stage nMOSFET 1 are both connected to the ground GND. The p well region 21 and the n-type semiconductor substrate 20 form a parasitic diode portion 3 of the output stage nMOSFET 1.

  The p-well region 26 and the p-well region 26a are formed in each other region if the distance L between them is separated from the diffusion length of holes injected from the p-well region 26 into the n-type semiconductor substrate 20. The MOSFETs can be electrically isolated with little interference. For example, the distance L between the p well region 26 and the p well region 26a may be about 10 μm. If the distance L is set to 20 μm or more, or even 50 μm or more, they may not interfere with each other. Further, although the hole diffusion length depends on the concentration of the n-type semiconductor substrate 20, it is about 100 μm or more. Therefore, when the interval L is 100 μm or more, interference can be sufficiently suppressed. On the other hand, if this distance L is increased, the chip size of the semiconductor device 100 increases, which is not preferable. Therefore, the distance L may be set to 500 μm or less, for example. That is, the distance L is 10 μm or more and 500 μm or less, preferably 20 μm or more and 200 μm or less, and more preferably 50 μm or more and 100 μm or less. Alternatively, it may be 200 μm or more and 500 μm or less.

  The voltage dividing diode 40 is a diode such as a Zener diode formed of polysilicon on the n-type semiconductor substrate 20 with an insulating film interposed therebetween. FIG. 14 is a cross-sectional view showing the voltage dividing diode 40 according to the first embodiment of the present invention. A p-well region 26b is formed in the surface layer of n-type semiconductor substrate 20 so as to be separated from both p-well region 26 and p-well region 26a. An oxide film 61 formed by a method such as thermal oxidation or chemical vapor deposition (CVD) is provided on the surface of the p-well region 26. A polysilicon film is formed on the surface of the oxide film 61. A polysilicon diode 42 which is a Zener diode having an n cathode region 42a and a p anode region 42b is formed by ion implantation of dopant into the polysilicon film and subsequent heat treatment. This polysilicon diode 42 is a voltage dividing diode 40. The n cathode region 42a of the voltage dividing diode 40 is electrically connected to a p well region 26a formed apart from the p well region 26b. This p-well region 26a is a back gate of each of the lateral nMOSFETs 8a and 8b constituting the ST-MOS circuit 8. Note that the separation distance between the p-well region 26 and the p-well region 26b and the separation distance between the p-well region 26a and the p-well region 26b are the same as the above-described distance L between the p-well region 26 and the p-well region 26a. It's okay.

  When the output stage nMOSFET has a low breakdown voltage of 100 V or less, or 300 V or less, the above-described p-well region 26b may be omitted. On the other hand, when the output stage nMOSFET has a withstand voltage of 300 V or more, or when the output stage nMOSFET is a switching element having a high withstand voltage of 600 V or more, such as an IGBT, the above-described p well region 26b may be formed. When the switching element is a high breakdown voltage element, a voltage of several hundred volts may be applied between the polysilicon of the voltage dividing diode 40 and the surface of the n-type semiconductor substrate 20 without the p-well region 26b. At that time, the applied voltage may exceed the withstand voltage of the oxide film 61 and dielectric breakdown may occur. However, if the p-well region 26b is formed below the polysilicon, the depletion layer is formed at the pn junction between the p-well region 26b and the n-type semiconductor substrate 20, so that a voltage is applied to the oxide film. Insulation breakdown can be prevented.

  The overheat detection circuit 9, overcurrent detection circuit 10, logic circuit 7, protection operation gate charge extraction circuit 5 and normal operation gate charge extraction circuit 6 shown in FIG. 1 are all formed in the p-well region 26 of FIG. Each is formed by being separated from other circuits by a certain distance, and is self-separated.

  In FIG. 1, reference numeral 18 indicates a gate wiring connecting the IN terminal and the gate 2a of the output stage nMOSFET 1, and reference numeral 19 indicates a disconnection detection line.

  3 shows the waveforms of the input voltage VIN3, voltage VST3, voltage VOUT3 and current IOUT3 in the control circuit 101c of the third arm EGR3, and the input voltage VIN1, voltage VST1, voltage VOUT1 and current IOUT1 in the control circuit 101a of the first arm EGR1. It is a wave form diagram which shows these waveforms. The configurations of the third arm EGR3 and the first arm EGR1 are the same as the configurations of the third arm EGR3 and the first arm EGR1 shown in FIG. 7A, FIG. 7B, and FIG.

  Here, the voltages VIN1 and VIN3 are input voltages (gate voltage and control voltage) input to the IN1 terminal and IN3 terminal which are input terminals, respectively. The voltages VST1 and VST3 are the voltages at the ST1 terminal and ST3 terminal, which are status terminals, respectively. The voltages VOUT1 and VOUT3 are the voltages at the OUT1 and OUT3 terminals, which are output terminals, respectively, and are the drain voltages of the output stage nMOSFETs 1a and 1c. Currents IOUT1 and IOUT3 are drain currents flowing through the output stage nMOSFETs 1a and 1c, respectively. The currents IOUT1 and IOUT3 are load currents flowing through the coils 91 and 93 (mutual inductance loads) of the first arm EGR1 and the third arm EGR3, respectively.

FIG. 4A illustrates a case where the output stage nMOSFET 1a of the first arm EGR1 (corresponding to 51a in FIG. 7) is turned off and the output stage nMOSFET 1c of the third arm EGR3 (corresponding to 51c in FIG. 7) is turned on. 2 is a cross section of a semiconductor device 100c. FIG. 4B is a cross-sectional view schematically showing voltage sharing by the voltage dividing diode 40.
As shown in FIG. 3, the ON signal as the input voltage VIN3 at time t ₀ is input, the OFF signal is inputted as an input voltage VIN1. Then, the output stage nMOSFET1a of the first arm EGR1 is turned off at time t ₁ after due to the presence of the Miller capacitance of the time delay, current IOUT1 becomes zero, voltage VOUT1 becomes the voltage of the battery B is a power supply voltage. At time t ₁ when the state of the output stage nMOSFET 1a of the first arm EGR1 changes from the on state to the off state, the state of the output stage nMOSFET 1c of the third arm EGR3 shifts from the off state to the on state. As a result, the voltage VOUT3 falls. In the process after time t ₁ , the coil 93 of the third arm EGR 3 (from the ground GND toward the battery B due to the influence of the mutual inductance between the coil 93 of the third arm EGR 3 and the coil 91 of the first arm EGR 1. A current (reverse current) flows in the reverse direction in FIG. The reverse current period lasts determined by the mutual inductance value, then, at time t ₂ when the forward current exceeds the reverse current, the current flowing through the third arm EGR3 is switched to the current (forward current) toward the ground GND from the battery B The This reverse current charges the battery B as a regenerative current.

  In this way, the mutual inductance load (corresponding to the coil 93 in FIG. 7) connected to the third arm EGR3 has an induced electromotive force (counterelectromotive force) such that the polarity of the OUT3 terminal is negative and the polarity of the GND terminal is positive. ) Occurs. Due to this electromotive force, as shown in FIG. 4A, a current IOUT3 flows from the GND terminal toward the OUT3 terminal. This current IOUT3 is divided into a current I1 flowing through the parasitic diode portion 3 of the output stage nMOSFET 1c (corresponding to the output stage nMOSFET 51c in FIG. 7), a current I2 flowing through the p-well region 26, and an I3 flowing through the voltage dividing diode 40.

As described above, at times t _{1 to} t ₂ in FIG. 3, the current I 2 flowing from the GND 3 terminal to the OUT 3 terminal through the p well region 26 causes the p well region 26 and the pn junction f between the n-type semiconductor substrate 20 to be connected. A rising voltage V1 (related to the built-in potential) corresponding to a voltage drop at the pn junction f is generated. The rising voltage V1 is, for example, 0.6 to 0.7V. On the other hand, the voltage dividing diode 40 connected to the GND terminal has a pn junction j between the anode 40b and the cathode 40a. As shown in FIG. 4B, a pn junction k is also formed between the p-type well region 26a connected in series with the cathode 40a of the voltage dividing diode 40 and the n-type semiconductor substrate 20. The rising voltage V1 is applied to the pn junction j and the pn junction k.

  The rising voltage V1 (≈0.7V) is divided into a voltage V2 applied to the pn junction j of the voltage dividing diode 40 and a voltage V3 applied to the pn junction k between the p-well region 26a and the n-type semiconductor substrate 20. Pressure (V1 = V2 + V3). Although the voltages V2 and V3 depend on the voltage dividing ratio, for example, when the voltage V1 is equally divided, V2, V3≈0.35V. The voltages V1, V2, and V3 are forward voltages at the pn junctions f, j, and k, respectively. The divided voltages V2 and V3 (≈0.35 V) applied to the pn junctions j and k are both rising voltages (about 0.7 V) applied to the entire pn junctions j and k regardless of the voltage division ratio. ) Lower. Therefore, only a very small current flows through each of the pn junctions j and k. That is, since a voltage lower than the rising voltage (about 0.7 V) of the pn junction f between the p well region 26 and the n-type semiconductor substrate 20 is applied to the pn junction k, the parasitic transistor 38 does not operate. As a result, the ST-MOS circuit 8 does not malfunction and a normal signal is input to the ST terminal.

  The p-well region 26a is a back gate common to the lateral nMOSFETs 8a and 8b. This back gate becomes the base q of the parasitic transistor 38. In order to turn on the parasitic transistor 38, it is necessary to apply a voltage of V3 = 0.7V to the pn junction k between the p-well region 26a and the n-type semiconductor substrate 20. That is, it is necessary to apply a voltage of 0.7 V to the base q. However, since the voltage dividing diode 40 is connected in series to the back gate, only a voltage smaller than V1 is applied to the base q. Thereby, as described above, the parasitic transistor 38 is not turned on. As a result, even when the OUT3 terminal has a negative polarity and the GND3 terminal has a positive polarity, the influence on the voltage of the ST3 terminal is suppressed, and the voltage of the ST terminal is maintained at a normal voltage.

  It is preferable that a plurality of voltage dividing diodes 40 are connected in series instead of one because the voltage applied to the base q of the parasitic transistor 38 is low and further difficult to operate. However, if the number of voltage-dividing diodes 40 connected in series is increased, the potential state of the p-well region 26a tends to become unstable.

(Embodiment 2)
FIG. 5 is a cross-sectional view showing a main part of a semiconductor device 200 according to the second embodiment of the present invention. The difference between the semiconductor device 200 and the semiconductor device 100 shown in FIG. 2 is that the voltage dividing diode 40 of the semiconductor device 100 is a lateral diffusion junction diode 41 formed by impurity diffusion in the n-type semiconductor substrate 20.

  In the second embodiment, a p-well region 26b is newly provided between the p-well region 26 and the p-well region 26a shown in FIG. The impurity concentration of p well region 26b is set higher than that of p well regions 26 and 26a. A lateral diffusion junction type diode 41 corresponding to the voltage dividing diode 40 shown in FIG. 2 is formed in the p-well region 26b having a higher impurity concentration. The diffusion junction type diode 41 has an n cathode region 41a and a p anode region 41b.

  A lateral nMOSFET 8b (8a) is formed in the p-well region 26a. Further, a p-well region 26c is formed so as to overlap the n-source region 29a of the lateral nMOSFET 8b (8a). The p-well region 26c has a diffusion depth deeper than that of the p-well region 26a and has a high impurity concentration comparable to that of the p-well region 26b. Further, a high-concentration p contact region 26d is formed in the p well region 26c apart from the n source region 29a. The p contact region 26d becomes a back gate of the lateral nMOSFET 8b (8a). The n cathode region 41a and the p contact region 26d (back gate) of the lateral diffusion junction diode 41 are connected to each other.

Between times t ₁ and t _{2 in} FIG. 3, the voltage between the GND terminal and the OUT terminal is about 0.7 V that of the pn junction f of the p-well region 26 and the n-type semiconductor substrate 20. This voltage of 0.7 V is divided by the pn junction j of the lateral diffusion junction diode 41 and the pn junction k of the p-well region 26a and the n-type semiconductor substrate 20, and the voltage between the p-well region 26a and the OUT terminal is divided. The voltage (corresponding to V3) is, for example, 0.35V. This p-well region 26 a becomes the base q of the parasitic transistor 38. When the voltage applied between the base q and the OUT terminal is 0.35 V, the parasitic transistor 38 is not turned on. As a result, as in the semiconductor device 100 according to the first embodiment, the voltage at the ST terminal can always be maintained at a normal voltage.

  The reason why the impurity concentration in the p-well regions 26b and 26c is increased is as follows. When the impurity concentration is increased, the rising voltage at the pn junction between the p well region 26b and the n-type semiconductor substrate 20 and at the pn junction between the p well region 26c and the n-type semiconductor substrate 20 is increased. It becomes higher than the rising voltage of the pn junction k with the semiconductor substrate 20. Thereby, it is possible to suppress the current flowing from each of the p well regions 26b and 26c to the n-type semiconductor substrate 20. Further, it is possible to make it difficult to turn on the parasitic transistor 38a formed of the n cathode region 41a, the p well region 26b, and the n type semiconductor substrate 20 of the lateral diffusion junction diode 41.

  Further, if the p well region 26e is formed on the n drain region 29 side of the lateral nMOSFET 8b (8a) with the same impurity concentration as the p well region 26c as shown by the dotted line in FIG. 5, the area of the parasitic transistor 38 is reduced. This makes it more difficult to turn on the parasitic transistor 38.

  The distance between the p-well regions 26b and 26c is preferably set to be approximately the same as the distance L between the p-well regions 26 and 26a.

  FIG. 6 is a cross-sectional view showing a main part of a modification of semiconductor device 200 according to Embodiment 2 of the present invention. Further, as shown in FIG. 6, the lateral resistance of the lateral diffusion junction diode 41 shown in FIG. 5 is obtained by bringing the p anode region 41b and the n cathode region 41a of the lateral diffusion junction diode 41 into contact or sufficiently close to each other. Reduce r. As a result, the current flowing from the p-well region 26b to the n-type semiconductor substrate 20 can be reduced. As a result, the potential can be reliably transmitted from the n cathode region 41a of the lateral diffusion junction diode 41 to the p well region 26a serving as the back gate of the lateral nMOSFET 8b (8a), and the parasitic transistor 38a is hardly turned on. Can do.

1, 1a, 1c Output stage nMOSFET
2 nMOSFET portion 2a gate 2b drain 2c source 3 parasitic diode portion 4 dynamic clamp Zener diode 4a, 4b, 16b, 16c, 31, 32 Zener diode 5 gate charge extraction circuit 6 during protection operation 6 gate charge extraction circuit 6a constant current Source 6b Depletion MOSFET
7 logic circuit 8 ST-MOS circuit 5a, 7a, 7b, 8a, 8b lateral nMOSFET
DESCRIPTION OF SYMBOLS 9 Overheat detection circuit 10 Overcurrent detection circuit 13,17a, 17b, 17c, 17d, 17e Resistance 13a, 14a, 15a Connection point 14,15 Voltage dividing resistor 18 Gate wiring 19 Disconnection detection line 20 N-type semiconductor substrate 21,23 26, 26a, 26b, 26c, 26e p well region 22, 28, 29a n source region 25 n ⁺ region 26d p contact region 27, 29 n drain region 38, 38a parasitic transistor 40 voltage dividing diode 40a cathode 40b anode 41 diffusion junction Type diode 24, 41a, 42a n cathode region 41b, 42b p anode region 42 polysilicon diode 61 oxide film 90, 91, 93 coil 97 rotor 100, 100a, 100b, 100c, 100d, 200 semiconductor device 101, 101a, 101b, 101c, 101d Control circuit IN IN terminal ST ST terminal OUT OUT terminal GND GND terminal

Claims (15)

An output stage switching element for controlling a current flowing in a load having a mutual inductance;
A detection circuit for detecting an abnormality of the output stage switching element;
A logic circuit that determines the state of the output stage switching element based on the output of the detection circuit;
A state detection circuit that outputs a connection state of the load and the output stage switching element and a determination result of the logic circuit to a state output terminal;
A voltage dividing diode connected in series to the state detection circuit by connecting a cathode to the state detection circuit, connecting an anode to the ground, and
A control circuit having
The output stage switching element is formed on a surface layer of a semiconductor layer of a second conductivity type with the semiconductor layer as a high potential side of the output stage switching element, and the semiconductor layer is connected to an output terminal of the control circuit,
The detection circuit and the logic circuit are formed in a first conductivity type first well region formed in a surface layer of the second conductivity type semiconductor layer,
The state detection circuit is formed on the surface layer of the second conductivity type semiconductor layer and on the surface of the first conductivity type second well region formed on the surface layer of the second conductivity type semiconductor layer and spaced apart from the first conductivity type first well region. It is composed of a lateral MOSFET of the second conductivity type,
The first well region of the first conductivity type and the low potential side of the output stage switching element are connected to the ground terminal of the control circuit,
The second well region of the first conductivity type constitutes a back gate of the lateral MOSFET of the second conductivity type, and a cathode of the voltage dividing diode is connected to the back gate, and the second conductivity type of the second well region. A semiconductor device , wherein a well region is connected to the ground terminal via an anode of the voltage dividing diode . The output terminal is connected to the high potential side of the power supply via the load;
The semiconductor device according to claim 1, wherein the ground terminal is connected to a low potential side of the power source . The forward bias voltage applied to the first pn junction between the first well region and the semiconductor layer is equal to the voltage applied to the second pn junction of the voltage dividing diode, and the first bias voltage between the second well region and the semiconductor layer. The semiconductor device according to claim 1 , wherein the semiconductor device is equal to a sum of a voltage applied to a 3 pn junction. 4. The semiconductor device according to claim 3 , wherein a voltage applied to the second pn junction is smaller than a built-in voltage of the second pn junction. 4. The semiconductor device according to claim 3 , wherein a voltage applied to the third pn junction is smaller than a built-in voltage of the third pn junction. Distance between the first well region and the second well region, the semiconductor device according to any one of claims 1 to 5, wherein the at 10μm or 500μm or less. The content pressure diode semiconductor device according to any one of claims 1 to 6, characterized in that formed on the semiconductor layer oxide film formed on the surface side of the. The oxide film is formed on a third well region of the first conductivity type formed on the surface of the semiconductor layer so as to be separated from both the first well region and the second well region. The semiconductor device according to claim 7 . 9. The semiconductor according to claim 8 , wherein a separation distance between the first well region and the third well region and a separation distance between the second well region and the third well region are 10 μm or more and 500 μm or less, respectively. apparatus. The semiconductor device according to claim 1 , wherein the output stage switching element is a second conductivity type vertical MOSFET. Distance between the first well region and the second well region, any of the first well region of claim 1, wherein the longer than the diffusion length of the minority carriers injected into the semiconductor layer The semiconductor device according to one item. Distance between the second well region and the third well region, according to claim 8 or 9, characterized in that longer than the diffusion length of the minority carriers injected into the semiconductor layer from the first well region Semiconductor device. The semiconductor device according to claim 7 , wherein the voltage dividing diode is made of polysilicon. The voltage dividing diode is a lateral diffusion junction type diode;
The lateral diffusion junction type diode is formed deeper than the diffusion depth of the first well region, higher than the impurity concentration of the first well region, and separated from the first well region and the second well region. the semiconductor device according to any one of claims 1 to 6, characterized in that formed on the surface layer of the third well region of the first conductivity type. A fourth well region of the first conductivity type is formed on the surface of the second well region of the first conductivity type. At least a source in a region forming the lateral MOSFET of the second conductivity type constituting the state detection circuit. Formed in the second well region of the first conductivity type so as to overlap the region,
The fourth well region has a diffusion depth deeper than the diffusion depth of the second well region and an impurity concentration higher than the impurity concentration of the second well region, and is connected to the cathode of the voltage dividing diode. the semiconductor device according to any one of claims 1 to 14, characterized in that.