JP6470029B2 - Display device driver - Google Patents

Description

  The present invention relates to a display device driver that drives a display device in accordance with a video signal.

  For example, a liquid crystal display panel or an electroluminescence display panel as a display device is provided at each intersection of a plurality of scanning lines extending in the horizontal direction of the two-dimensional screen and a plurality of signal lines extending in the vertical direction of the two-dimensional screen. Pixels are formed. Further, in such a display panel, a signal driver that applies a gradation voltage corresponding to the luminance level of each pixel represented by video data to each of the signal lines, and a scan that sequentially applies a scanning voltage to each of the scanning lines. And a driver. The signal driver described above includes a data latch that captures a video data piece corresponding to each pixel represented by the video data every horizontal period, and converts the video data piece held in the data latch into an analog gradation voltage. A circuit is installed.

  Here, as the above-described signal driver, a plurality of video data pieces for one horizontal period captured from the outside are grouped, and the timing for supplying the video data group to the data latch is shifted for each video data group. The thing is proposed (for example, refer patent document 1). In the signal driver, by supplying each of the video data groups to the data latch via a plurality of delay circuits having different delay times, currents flowing from the delay circuits to the plurality of circuit elements formed between the data latches Are dispersed over time. As a result, noise generated by the simultaneous operation of the circuit elements is prevented.

JP 2010-39061 A

  However, in the signal driver, depending on the delay time of each delay circuit, the timing at which a current flows through the circuit element formed in the path between the delay circuit and the data latch, and the circuit element before the delay circuit, In some cases, the timing of current flow coincides, and at this time, noise cannot be sufficiently reduced.

  Therefore, an object of the present invention is to provide a display device driver capable of sufficiently reducing noise generated in the driver.

  The display device driver according to the present invention applies a gradation voltage to n (n is an integer of 2 or more) data lines of a display device based on an input pixel data piece representing a luminance level for each pixel. A driver that simultaneously captures L (L is an integer of 2 or more) input pixel data pieces in synchronization with a reference clock signal, and uses the acquired L input pixel data pieces as a first pixel data group. A first latch for outputting, a first buffer for outputting a first amplified pixel data group obtained by amplifying the first pixel data group, and the reference clock signal being different in phase and the reference The first amplified pixel data group is simultaneously fetched in synchronization with a first clock signal having the same frequency as the clock signal, and the fetched first amplified pixel data group is taken as a second pixel data. A second latch for outputting as a data group, a second buffer for outputting a second amplified pixel data group obtained by amplifying the second pixel data group, and the second amplified pixel data group. And a data latch that outputs the captured second amplified pixel data group for every n pixels.

  In the present invention, when the pixel data group synchronized with the reference clock signal is sent to the second buffer for driving the data latch through the first buffer for data transmission, the pixel data output from the first buffer is sent. The group is transmitted to the second buffer with a phase different from that of the reference clock signal. Accordingly, it is possible to reduce noise generated due to simultaneous operation current flowing in consideration of the operation timing of the first buffer provided in the previous stage of the second buffer.

It is a figure which shows schematic structure of the display apparatus carrying the driver of the display device which concerns on this invention. 2 is a block diagram showing an internal configuration of a data driver 13. FIG. It is a block diagram which shows the internal structure which shows the 1st Example of the data taking-in part 131. It is a time chart which shows operation | movement of the data acquisition part 131 which has an internal structure shown in FIG. It is a block diagram which shows the internal structure which shows the 2nd Example of the data taking-in part 131. It is a time chart which shows operation | movement of the data acquisition part 131 which has an internal structure shown in FIG. It is a block diagram which shows the internal structure which shows the 3rd Example of the data taking-in part 131. It is a time chart which shows the operation | movement of the data acquisition part 131 which has an internal structure shown in FIG. It is a block diagram which shows the modification of the data acquisition part 131 shown in FIG. It is a block diagram which shows the modification of the data acquisition part 131 shown in FIG. It is a block diagram which shows the internal structure which shows the 4th Example of the data taking-in part 131.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a schematic configuration of a display device equipped with a display device driver according to the present invention. As shown in FIG. 1, the display device includes a drive control unit 11, a scan driver 12, a data driver 13, and a display device 20.

The display device 20 is a display panel such as a liquid crystal display panel or an organic EL (electroluminescence) panel. The display device 20 includes m horizontal scanning lines S _{1 to} S _m (m is a natural number of 2 or more) extending in the horizontal direction of the two-dimensional screen, and n (n is a vertical extension of the two-dimensional screen). (Natural numbers of 2 or more) data lines D _{1 to} D _n are formed. Further, display cells serving as pixels are formed in the regions of the crossing portions of the horizontal scanning lines and the data lines, that is, the regions surrounded by the broken lines in FIG.

  Based on the video data signal VD, the drive control unit 11 generates a series of pixel data PD that represents the luminance level of each pixel in, for example, 8 bits for each pixel, and each pixel data PD is in a 1-bit serial form, for example. The data are sequentially supplied to the data driver 13. Further, the drive control unit 11 generates a vertical synchronization signal synchronized with the frame of each image based on the video data signal VD, and supplies this to the data driver 13.

The scan driver 12 generates a horizontal scan pulse having a predetermined peak voltage in synchronization with the vertical synchronization signal supplied from the drive control unit 11, and sequentially generates it on each of the scan lines S _{1 to} S _m of the display device 20. Apply alternatively.

  FIG. 2 is a block diagram showing the internal configuration of the data driver 13. As shown in FIG. 2, the data driver 13 includes a data capturing unit 131, a gradation voltage conversion unit 132, and an output amplifier 133.

The data capturing unit 131 sequentially captures the pixel data PD supplied from the drive control unit 11. The data acquisition unit 131 supplies the _n pixel data PD as pixel data P _{1 to} P _n to the gradation voltage conversion unit 132 for each horizontal scanning period, that is, every time n pixel data PD is acquired. . The details of the pixel data PD capturing operation in the data capturing unit 131 will be described later.

The gradation voltage conversion unit 132 converts the pixel data P _{1 to} P _n into gradation voltages V _{1 to} V _n corresponding to the respective luminance levels, and supplies them to the output amplifier 133.

The output amplifier 133 uses pixel drive voltages G _{1 to} G _n obtained by amplifying each of the gradation voltages V _{1 to} V _n as desired, and applies them to the data lines D _{1 to} D _n of the display device 20.

  Hereinafter, the operation of taking in the pixel data PD in the data taking-in unit 131 will be described.

FIG. 3 is a block diagram showing the internal configuration of the data fetch unit 131 according to the first embodiment. In FIG. 3, the total number n of data lines D _{1 to} D _n of the display device 20 is 1440, that is, the number of output channels of the data driver 13 is 1440 channels. The configuration is shown.

  In FIG. 3, the serial / parallel conversion circuit SP converts the pixel data PD supplied from the drive control unit 11 in a 1-bit serial form into 48-bit parallel pixel data QDB and supplies the converted data to the first latch DF1. That is, the serial / parallel conversion circuit SP supplies pixel data PD for one channel, that is, 8-bit pixel data for six channels simultaneously to the first latch DF1 as pixel data QDB.

  As shown in FIG. 4, the clock generation circuit CG generates a reference clock signal CKR having the same cycle CY as that of the pixel data QDB, and supplies this to the latch DF1, the delay circuit DC, and the latch clock generation circuit LCK.

  The latch DF1 captures 48-bit pixel data QDB in synchronization with the timing of the rising edge of the reference clock signal CKR, and supplies this to the data transmission buffer BF1 as a 48-bit pixel data group RDB.

  That is, as shown in FIG. 4, the latch DF1 has 6 channels for each of the 8-bit pixel data pieces corresponding to the first to 1440th channels in one horizontal scanning period in synchronization with the reference clock signal CKR. What is taken in at the same time is supplied to the buffer BF1 as a pixel data group RDB.

  The buffer BF1 supplies a 48-bit pixel data group SDB obtained by individually amplifying signals corresponding to each bit in the pixel data group RDB to the latch DF2 via the data transmission bus BS1.

  The delay circuit DC generates a clock signal CK1 obtained by delaying the reference clock signal CKR by a predetermined time DQ as shown in FIG. That is, the delay circuit DC generates the clock signal CK1 having the same frequency as the reference clock signal CKR and having a phase different from that of the reference clock signal. The delay circuit DC supplies the clock signal CK1 to the latch DF2. The time DQ is a time shorter than the cycle CY.

  As shown in FIG. 4, the latch DF2 simultaneously captures the 48-bit pixel data group SDB in synchronization with the timing of the rising edge portion of the clock signal CK1, and uses this as the pixel data group TDB via the data transmission bus BS2. The data is supplied to the data latch driving buffer BF2.

  That is, as shown in FIG. 4, the latch DF2 converts 8-bit pixel data corresponding to the first to first 1440 channels into six channels (48 bits) in synchronization with the clock signal CK1 within one horizontal scanning period. ) At the same time are supplied to the buffer BF2 as a pixel data group TDB.

  The buffer BF2 supplies a 48-bit pixel data group UDB obtained by individually amplifying signals corresponding to each bit of the 48-bit pixel data group TDB to the data latches DL1 to DL240.

The latch clock generation circuit LCK generates latch capture signals L _{1 to} L ₂₄₀ obtained by sequentially delaying one pulse signal every cycle CY in synchronization with the reference clock signal CKR as shown in FIG. 4 for each horizontal scanning period. Generate. Data latch clock generation circuit LCK supplies a latch capture signal L ₁ to the data latch DL1, supplies a latch capture signal L ₂ to the data latch DL2, supplies a latch capture signal L ₃ to the data latch DL3. Similarly, the data latch clock generation circuit LCK supplies latch fetch signals L _{4 to} L ₂₄₀ to the data latches DL ₄ to DL ₂₄₀ , respectively.

Each of the data latches DL1 to DL240 takes in the 48-bit pixel data group UDB supplied from the buffer BF2 at the timing of the rising edge portion of the latch take-in signal L supplied to the data latches DL1 to DL240. The corresponding pixel data P _{1 to} P ₁₄₄₀ are output.

For example, first, the data latch DL1 in accordance with the latch accepting signal L ₁ supplied to itself, as shown in FIG. 4, it takes in the first to 48-bit pixel data group UDB corresponding to the sixth channel, Each outputs 8-bit pixel data P _{1 to} P ₆ . Next, the data latch DL2 is, in response to a latch capture signal L ₂ supplied to itself, as shown in FIG. 4, it takes in 48 bits of pixel data groups UDB corresponding to seventh through twelfth channels, respectively There outputs 8-bit pixel data P ₇ to P _12. Next, the data latch DL3, in response to a latch capture signal L ₃ supplied to it, as shown in FIG. 4, takes in 48 bits of pixel data groups UDB corresponding to thirteenth 18 channel, respectively There outputs 8-bit pixel data P ₁₃ to P _18. Similarly, in the order of data latches DL4, DL5,..., DL239, DL240, each data latch DL captures a 48-bit pixel data group UDB in accordance with a latch capture signal L supplied to itself, Each outputs 8-bit pixel data P _{19 to} P ₁₄₄₀ .

  As described above, in the data fetch unit 131 having the internal configuration shown in FIG. 3, the pixel data group RDB fetched in synchronization with the reference clock signal CKR is sent to the data latch groups (DL1 to DL240) via the buffer BF1. In this case, a latch DF2 is provided between the buffer BF1 and the buffer BF2. The latch DF2 captures the pixel data group SDB supplied from the buffer BF1 in synchronization with the clock signal CK1 shifted in phase by the time DQ with respect to the reference clock signal CKR as shown in FIG. This is supplied as TDB to the buffer BF2.

  Therefore, as shown in FIG. 4, the timing at which the operating current accompanying the amplification process flows in the buffer BF1 is the time of the rising edge portion of the reference clock signal CKR. On the other hand, the timing at which the operating current accompanying the amplification process flows in the buffer BF2 is the time of the rising edge portion of the clock signal CK1, as shown in FIG.

  As a result, the timings of the operating currents flowing through the buffers BF1 and BF2 existing in the path from the latch DF1 that captures the input pixel data PD to the data latch DL1 are temporally dispersed. Therefore, it is possible to suppress noise that is generated when the operating current flows simultaneously.

  In short, as the data fetch unit 131 having the configuration shown in FIG. 3, the following first latch (DF1), first buffer (BF1), second latch (DF2), second buffer (BF2), and Those including data latches (DL1 to DL240) are employed.

  The first latch simultaneously captures L (L is an integer of 2 or more) input pixel data pieces (PD) in synchronization with the reference clock signal (CKR), and takes in the L input pixel data pieces taken in the first. Are output as a pixel data group (RDB). The first buffer outputs a first amplified pixel data group (SDB) obtained by amplifying the first pixel data group. The second latch simultaneously captures the first amplified pixel data group in synchronization with the first clock signal (CK1) having a phase different from that of the reference clock signal and having the same frequency as the reference clock signal. 2 pixel data groups (TDB). The second buffer outputs a second amplified pixel data group (UDB) obtained by amplifying the second pixel data group. Then, the data latch takes in the second amplified pixel data group and outputs the fetched second amplified pixel data group for every n pixels (n is an integer of 2 or more).

  By adopting such a configuration, the operating current flows simultaneously in consideration of the operation timing of the first buffer BF1 for data transmission provided in the preceding stage of the second buffer (BF2) for driving the data latch. This makes it possible to reduce the noise generated.

  FIG. 5 is a block diagram showing the internal configuration of the data fetch unit 131 according to the second embodiment. In FIG. 5, the serial / parallel conversion circuit SP, the clock generation circuit CG, the latch DF1, and the buffer BF1 are the same as those shown in FIG.

  In the configuration shown in FIG. 5, a delay circuit DCX is adopted instead of the delay circuit DC shown in FIG. 3, and latches DF2a and 2b are adopted instead of the latch DF2. 5 employs buffers BF2a and BF2b instead of the buffer BF2 shown in FIG. 3, and employs data latches DLa1 to DLa240 and DLb1 to DLb240 instead of the data latches DL1 to DL240.

  The delay circuit DCX generates a clock signal CK1 obtained by delaying the reference clock signal CKR by a predetermined time DQ as shown in FIG. 6, and supplies this to the latch DF2a. Further, the delay circuit DCX generates a clock signal CK2 obtained by delaying the clock signal CK1 by a predetermined time DQx as shown in FIG. 6, and supplies this to the latch DF2b. That is, the delay circuit DCX generates the clock signals CK1 and CK2 having different phases from each other by delaying the reference clock signal CKR by different first time (DQ) and second time (DQ + DQx).

Latch DF2a is divided pixel data groups SD ₁ of 3 channels consisting of upper 24 bits at the time of divided into two 48-bit pixel data group SDB by 24 bits minutes, as shown in FIG. 6, the rising edge of the clock signal CK1 Capture in synchronization with the timing of the edge portion. Latch DF2a as a divided pixel data groups SD ₁ taken divided pixel data groups TD _1, supplied to the buffer BF2a via a data transmission bus BS2a.

Latch DF2b is divided pixel data groups SD ₂ of 3 channels consisting of lower 24 bits at the time of divided into two 48-bit pixel data group SDB by 24 bits minutes, as shown in FIG. 6, the rising edge of the clock signal CK2 Capture in synchronization with the timing of the edge portion. Latch DF2b as a divided pixel data groups SD ₂ captured divided pixel data groups TD _2, supplied to the buffer BF2b via a data transmission bus BS2B.

Buffer BF2a supplies the divided pixel data groups TD divided pixel data groups UD ₁ of 24 bits obtained by individually amplified signals corresponding to each bit of ₁ of 24-bit data latch DLa1～DLa240.

Buffer BF2b supplies 24 of 24 bits obtained by individually amplified signals corresponding to each bit of the divided pixel data groups TD ₂ consisting of bits divided pixel data groups UD ₂ to the data latch DLb1～DLb240.

The latch clock generation circuit LCK generates latch capture signals L _{1 to} L ₂₄₀ obtained by sequentially delaying one pulse signal every cycle CY in synchronization with the reference clock signal CKR as shown in FIG. 6 for each horizontal scanning period. Generate. Data latch clock generation circuit LCK supplies a latch capture signal L ₁ to the data latch DLa1 and DLb1 supplies a latch capture signal L ₂ to the data latch DLa2 and DLB2, data latches latch capture signal L ₃ DLa3 And supplied to DLb3. In the same manner, the data latch clock generation circuit LCK supplies respectively a latch capture signal L ₄ ~L ₂₄₀ data latches DLa4～DLa240, as well as DLb4～DLb240.

Each data latch DLa1~DLa240 is divided pixel data groups UD ₁ of 24 bits supplied from the buffer BF2a, capture at the rising edge of the latch accepting signal L supplied to itself. Each data latch DLb1~DLb240 is divided pixel data groups UD ₂ of 24 bits supplied from the buffer BF2b, capture at the rising edge of the latch accepting signal L supplied to itself.

For example, the data latch DLa1 takes in the 24-bit divided pixel data group UD ₁ at the timing of the rising edge of the latch take-in signal L ₁ supplied to the data latch DLa1, and corresponds to the first to third channels. Output as 8-bit pixel data P _{1 to} P ₃ . Data latch DLb1 takes a divided pixel data groups UD ₂ of 24 bits at the rising edge of the latch accepting signal L ₁ supplied to it, corresponding it to the fourth to sixth channels, respectively 8 bits and outputs as pixel data P ₄ to P _6.

Data latch DLa2 takes a 24-bit divided pixel data groups UD ₁ at the rising edge of the latch accepting signal L ₂ supplied to it, corresponding it to the seventh to ninth channels, each 8-bit and outputs as pixel data P ₇ to P _9. Data latch DLb2 takes a divided pixel data groups UD ₂ of 24 bits at the rising edge of the latch accepting signal L ₂ supplied to it, corresponding it to the tenth to twelfth channels, each 8-bit and outputs as pixel data P ₁₀ to P _12.

In the same manner, the data latch DLa3～DLa240, and DLb3~DLb240 is divided in 24-bit at the rising edge of the latch accepting signal L ₃ ~L ₂₄₀ supplied to their pixel data group UD ₁ and UD ₂ uptake, and outputs it as each pixel 8-bit data P ₁₃ to P _1437.

As described above, the data capturing unit 131 having the internal configuration shown in FIG. 5 divides the pixel data group RDB captured in synchronization with the reference clock signal CKR into _two divided pixel data groups SD ₁ and SD ₂ , The data is supplied to the data latch groups (DLa1 to DLa240, DLb1 to DLb240).

Furthermore, in the configuration shown in FIG. 5, the divided pixel data groups SD ₁ is supplied to the first buffer BF2a through the first latch DF2a, divided pixel data groups SD ₂ the second through the second latch DF2b To the buffer BF2b. Latch DF2a is divided pixel data groups SD ₁ supplied from the buffer BF1, the uptake in synchronization with the clock signal CK1 obtained by shifting the reference clock signal CKR only time DQ to the phase as shown in FIG. 6, divides this supplied to the buffer BF2a as pixel data group TD _1. Latch DF2b is divided pixel data groups SD ₂ supplied from the buffer BF1, in synchronization with the clock signal CK2 which is shifted only phase time the reference clock signal CKR (DQ + DQx) as shown in FIG. 6 uptake, which supplied to the buffer BF2b as divided pixel data groups TD _2.

In other words, the divided pixel data groups SD ₁ and SD ₂ obtained by dividing the pixel data group RDB into two by the multi-phase unit including the delay circuit DCX and the latches DF2a and DF2b are different in phase from the reference clock signal CKR and out of phase with each other. The data is supplied to the second buffers BF2a and BF2b for driving the data latch in different first to second phases.

  With such a configuration, the timing at which the operating current accompanying the amplification process in the buffer BF1 flows is at the time of the rising edge portion of the reference clock signal CKR as shown in FIG. On the other hand, the timing when the operating current accompanying the amplification process of the buffer BF2a flows is the time of the rising edge portion of the clock signal CK1, as shown in FIG. As shown in FIG. 6, the timing at which the operating current accompanying the amplification process of the buffer BF2b flows is at the time of the rising edge portion of the clock signal CK2.

  Therefore, as shown in FIG. 6, the operating current that flows along with the amplification processing of each of the buffers BF1, BF2a, and BF2b is temporally distributed at three locations.

As a result, when the configuration shown in FIG. 5 is adopted as the internal configuration of the data acquisition unit 131, the operating current of the data transmission buffer (BF1) is compared with the case where the configuration shown in FIG. 3 is adopted. Thus, it is possible to greatly reduce the noise generated when the operating currents of the data latch driving buffers (BF2a and BF2b) flow simultaneously.

  FIG. 7 is a block diagram showing an internal configuration of the data fetch unit 131 according to the third embodiment. 7 employs a data control circuit DCC and AND gates ANa and ANb in place of the delay circuit DCX and latches DF2a and DF2b shown in FIG. 5, and a latch clock generation circuit in place of the latch clock generation circuit LCK. Except for the point of adopting LCX, the other configuration is the same as that shown in FIG.

In FIG. 7, the data control circuit DCC generates a data validation signal ENa indicating whether the divided pixel data group SD ₁ composed of the upper 24 bits in the pixel data group SDB is to be validated or invalidated. This is supplied to the AND gate ANa. Further, the data control circuit DCC generates the one or the data enable signal ENb indicating whether to disable to enable the divided pixel data groups SD ₂ consisting of lower 24 bits in the pixel data group SDB, and this Supply to gate ANb.

  For example, the data control circuit DCC indicates a logical level 1 representing the validity of the pixel data for a period of ½ of the period CY for each period CY, and the invalidity of the pixel data for the remaining half of the period. Data enable signals ENa and ENb indicating a logic level 0 representing the conversion are generated. The data enable signals ENa and ENb transition from the logic level 1 to 0 or from the logic level 0 to 1 complementarily as shown in FIG.

  Here, the phase of the rising edge portion of the data enable signal ENa and the phase of the falling edge portion of the data enable signal ENb are equal to the time DQy with respect to the rising edge portion of the reference clock signal CKR as shown in FIG. Only out of phase.

AND gate ANa as it divided pixel data groups TD ₁ divided pixel data groups SD ₁ of 24 bit while a logic level 1 to the data enable signal ENa indicates data enable, via the data transmission bus BS2a buffer Supply to BF2a. On the other hand, while the data validation signal ENa is at the logic level 0 indicating data invalidation, the AND gate ANa transmits the divided pixel data group TD _{1 in} which all 24 bits are at the logic level 0 via the data transmission bus BS2a. This is supplied to the buffer BF2a.

AND gate ANb as it divided pixel data groups TD ₂ divided pixel data groups SD ₂ 24 bits while a logic level 1 to the data enable signal ENb indicates data enable, via the data transmission bus BS2b buffer Supply to BF2b. On the other hand, while the data enable signal ENb is at the logic level 0 indicating data invalidation, the AND gate ANb transmits the divided pixel data group TD _{2 in} which all 24 bits are at the logic level 0 via the data transmission bus BS2b. This is supplied to the buffer BF2b.

Latch clock generation circuit LCX is every horizontal scanning period, 1 pulse signals as shown in FIG. 8, the reference clock signal latched accepting signal delayed one by the period of 1/2 of the period CY of CKR L ₁ to generate a ~L _480. The data latch clock generation circuit LCX supplies the latch capture signal L ₁ to the data latch DLa ₁ , supplies the latch capture signal L ₂ to the data latch DLa 1, and supplies the latch capture signal L ₃ to the data latch DLa 2, The latch fetch signal L ₄ is supplied to the data latch DLb2. Similarly, the data latch clock generation circuit LCX is a latch capture signal L ₅ ~L _480, data latch DLa3, DLb3, DLa4, DLb4, ···, DLa240, DLb240 supplied respectively to the.

Each data latch DLa1~DLa240 is divided pixel data groups UD ₁ of 24 bits supplied from the buffer BF2a, capture at the rising edge of the latch accepting signal L supplied to itself. Each data latch DLb1~DLb240 is divided pixel data groups UD ₂ of 24 bits supplied from the buffer BF2b, capture at the rising edge of the latch accepting signal L supplied to itself.

For example, the data latch DLa1 takes in the 24-bit divided pixel data group UD ₁ at the timing of the rising edge of the latch take-in signal L ₁ shown in FIG. 8 and corresponds to the first to third channels. Output as bit pixel data P _{1 to} P ₃ . Data latch DLb1 captures a latch capture signal L ₂ of the 24-bit at the rising edge portion divided pixel data groups UD ₂ shown in FIG. 8, which corresponds to the fourth to sixth channels, each 8-bit and outputs it as pixel data P ₄ to P _6.

Data latch DLa2 takes a divided pixel data groups UD ₁ of 24 bits at the rising edge of the latch accepting signal L ₃ shown in FIG. 8, which corresponds to the seventh to ninth channels, each 8-bit and outputs it as pixel data P ₇ to P _9. Data latch DLb2 captures a latch capture signal L 24-bit at the rising edge portion of the _four divided pixel data groups UD ₂ shown in FIG. 8, which corresponds to the tenth to twelfth channels, each 8-bit Output as pixel data P _{10 to} P ₁₂ .

In the same manner, the data latch DLa3～DLa240, and DLb3~DLb240 is divided in 24-bit at the rising edge of the latch accepting signal L ₅ ~L ₄₈₀ supplied to their pixel data group UD ₁ and UD ₂ uptake, and outputs it as each pixel 8-bit data P ₁₃ to P _1437.

As described above, in the data capturing unit 131 having the internal configuration illustrated in FIG. 7, the pixel data group RDB captured in synchronization with the reference clock signal CKR is divided into the divided pixel data group SD, as in the configuration illustrated in FIG. ₁ and SD ₂ are divided into _two and supplied to the data latch groups (DLa1 to DLa240, DLb1 to DLb240). However, in the configuration shown in FIG. 7, the divided pixel data group SD ₁ is sent to the first buffer BF2a via the first AND gate ANa, and the divided pixel data group SD ₂ is sent via the second AND gate ANb. The data is sent to the second buffer BF2b. Further, in the configuration shown in FIG. 7, as shown in FIG. 8, the data enable signal ENa that makes a transition from the logic level 0 to 1 or complementarily from the logic level 1 to 0 every 1/2 cycle of the cycle CY. ENb is supplied to the AND gates ANa and ANb.

In other words, the divided pixel data groups SD ₁ and SD ₂ obtained by dividing the pixel data group RDB into two by the multi-phase unit including the data control circuit DCC and the AND gates ANa and ANb are different from each other in phase with the reference clock signal CKR. The first and second phases having different phases are supplied to the second buffers BF2a and BF2b for driving the data latch.

  Therefore, the timing when the operating current accompanying the amplification process flows in the buffer BF1 is the time of the rising edge portion of the reference clock signal CKR as shown in FIG. On the other hand, as shown in FIG. 8, the timing at which the operating current flows along the amplification process in the buffer BF2a is the time when the phase is shifted by the time DQy with respect to the time of the rising edge portion of the reference clock signal CKR. In addition, as shown in FIG. 8, the timing at which the operating current flows along the amplification process in the buffer BF2b is set to a period ½ of the period CY at time DQy with respect to the time point of the rising edge of the reference clock signal CKR. The phase is shifted by the amount added.

  Accordingly, the timings of the amplification processes in the buffers BF1, BF2a, and BF2b are shifted from each other, so that the operating currents that flow with each amplification process are temporally dispersed.

  As a result, it is possible to reliably suppress noise generated by the simultaneous operation of the operating current of the data transmission buffer BF1 and the operating current of the data latch driving buffers BF2a and BF2b.

Here, in the data fetch unit 131 according to the second embodiment shown in FIG. 5, the pixel data group SDB fetched in synchronization with the reference clock signal CKR is divided into two (SD ₁ , SD ₂ ), and each is different from each other. Although data is supplied to the data latch group at two timings (CK1, CK2), it is not limited to such a configuration.

9 has been made in view of the above, it is a block diagram showing a modification of the data acquisition unit 131 shown in FIG. In the configuration shown in FIG. 9, the serial-parallel conversion circuit SP, a clock generation circuit CG, the latch DF1, the buffer BF1 and the latch clock generation circuit LCK is identical to that shown in Figure 5. In the configuration shown in FIG. 9 employs a delay circuit DCZ instead of the delay circuit DCX shown in FIG.

  The delay circuit DCZ generates N (N is an integer of 2 or more) clock signals CK1 to CK (N) having different phases from each other by delaying the reference clock signal CKR by different first to Nth periods. .

Furthermore, the configuration shown in FIG. 9 has divided data latch units Q _{1 to} Q _N each having the same internal configuration. Each of the divided data latch portions Q _{1 to} Q _N includes a latch DF2a, a buffer BF2a, and data latches DLa1 to DLa240 shown in FIG. As shown in FIG. 9, to each of the divided data latch unit Q ₁ to Q _N as pixel data, the divided pixel data groups SD ₁ to SD _N of the pixel data groups SDB and N divided is supplied. Furthermore, in each of the divided data latch unit Q ₁ to Q _N as the clock signal, the clock signal CK1~CK having different phases (N) is supplied to one another.

  That is, as a second embodiment of the data capturing unit 131, the pixel data group RDB synchronized with the reference clock signal CKR is divided into N (N is an integer of 2 or more) pieces of pixel data, and each of them is divided into N pieces. Any configuration that supplies data latch groups at different timings is acceptable.

  Further, in the data fetching unit 131 according to the third embodiment shown in FIG. 7, the pixel data group RDB fetched in synchronization with the reference clock signal CKR is divided into two, and each of them is complementarily validated or invalidated 2. Although system AND gates (ANA, ANb) are provided, the present invention is not limited to this configuration.

FIG. 10 is a block diagram showing a modification of the data capturing unit 131 shown in FIG. In the configuration shown in FIG. 10, the serial / parallel conversion circuit SP, the clock generation circuit CG, the latch DF1, the buffer BF1, and the latch clock generation circuit LCX are the same as those shown in FIG. In the configuration shown in FIG. 10, a data control circuit DCQ is employed instead of the data control circuit DCC shown in FIG. Data control circuit DCQ, for each cycle CY, data enable signal EN ₁ ～EN logic level 1 becomes a time period of 1 / N within its cycle CY, other period becomes the logic level 0 to invalidate the pixel data Generate _N. Note that the phases of the reference clock signal CKR and the data enable signals EN _{1 to} EN _N are different from each other.

Furthermore, the configuration shown in FIG. 10 has divided data latch portions W _{1 to} W _N each having the same internal configuration. Each of divided data latch units W _{1 to} W _N includes AND gate ANa, buffer BF2a, and data latches DLa1 to DLa240 shown in FIG. As shown in FIG. 10, to each of the divided data latch section W ₁ to _W-N as pixel data, the divided pixel data groups SD ₁ to SD _N of the pixel data groups SDB and N divided is supplied. Further, data enable signals EN _{1 to} EN _N having different phases are supplied to each of the divided data latch units W _{1 to} W _N as data enable signals.

  That is, as a third embodiment of the data capturing unit 131, the pixel data group RDB captured in synchronization with the reference clock signal CKR is divided into N pixel data, and N pixels are formed by N AND gates. Any configuration in which one of the data is sequentially validated at different timings and supplied to the data latch group may be used.

  In short, the data fetch unit 131 having the configuration shown in FIGS. 5 to 10 includes the following first latch (DF1), first buffer (BF1), multiphase unit (DCX, DF2a, DF2b, DCC, ANa, ANb, DCZ, DCQ), a second buffer (BF2), and data latches (DLa1 to DLa240, DLb1 to DLb240) may be used.

The first latch simultaneously captures L (L is an integer of 2 or more) input pixel data pieces (PD) in synchronization with the reference clock signal (CKR), and takes in the L input pixel data pieces taken in the first. Are output as a pixel data group (RDB). The first buffer outputs a first amplified pixel data group (SDB) obtained by amplifying the first pixel data group. The polyphase conversion unit converts _first to Nth divided pixel data groups (SD _{1 to} SD _N ) obtained by dividing the first amplified pixel data group into N (N is an integer of 2 or more) as a reference clock signal. Are converted into first to Nth multi-phase pixel data groups (TD) having first to Nth phases that are different in phase and different from each other. The second buffer outputs first to Nth divided amplified pixel data groups obtained by amplifying the first to Nth multiphased divided pixel data groups output from the multiphase conversion unit. The data latch takes in the first to Nth divided amplified pixel data groups and outputs the fetched first to Nth divided amplified pixel data groups for every n pixels.

  By adopting such a configuration, the timing of the operating current flowing through each buffer is set to the time in consideration of the operation timing of the data transmission buffer BF1 provided in the preceding stage of the second buffer BF2 for driving the data latch. Therefore, it is possible to disperse at three or more points. Therefore, it is possible to significantly reduce the amount of noise that is generated when the operating current flows simultaneously as compared with the case where the configuration shown in FIG. 3 is adopted.

  The configuration of the data capturing unit 131 includes the configuration of the data capturing unit 131 according to the second embodiment shown in FIG. 5, the data control circuit DCC and the AND gate ANa in the third embodiment shown in FIG. ANb may be incorporated.

For example, as shown in FIG. 11, an AND gate ANa is provided between the buffer BF1 and the latch DF2a, and an AND gate ANb is provided between the buffer BF1 and the latch DF2b. At this time, as shown in FIG. 8, the data control circuit DCC generates data enable signals ENa and ENb that transit from the logic level 0 to the logic level 1 or from the logic level 1 to the logic level 0 in a complementary manner. AND gate ANa supplies only divided pixel data groups SD ₁ when the data enable signal ENa is at logic level 1 to the latch DF2a, all bits in the case where the data enable signal ENa is at logic level 0 is logic It supplies the divided pixel data groups SD ₁ as a level 0 in the latch DF2a. AND gate ANb supplies only divided pixel data groups SD ₂ when the data enable signal ENb is a logic level 1 to the latch DF2b, all bits in the case where the data enable signal ENb is a logic level zero logic It supplies the divided pixel data groups SD ₂ as a level 0 in the latch DF2a.

  According to the configuration shown in FIG. 11, the data transition can be forcibly stopped not only in the latches DF2a and DF2b but also in the AND gates ANa and ANb, so that the noise reduction effect can be enhanced. The place where the AND gates ANa and ANb are incorporated in the configuration of the data fetch unit 131 according to the second embodiment shown in FIG. 5 is not limited between the buffer BF1 and the latch DF2a (DF2b) as shown in FIG. For example, the AND gate ANa may be provided between the latch DF2a and the buffer BF2a, and the AND gate ANb may be provided between the latch DF2b and the buffer BF2b. Alternatively, an AND gate ANa may be provided between the buffer 2a and the data latches DLa1 to DLa240, and an AND gate ANb may be provided between the buffer 2b and the data latches DLb1 to DLb240.

DESCRIPTION OF SYMBOLS 11 Drive control part 13 Data driver 20 Display device 131 Data acquisition part BF1, BF2 Buffer CG Clock generation circuit DC Delay circuit DF1, DF2 Latch DL1-DL240 Data latch

Claims (2)

A driver of the display device for applying a gradation voltage to n (n is an integer of 2 or more) data lines of a display device based on an input pixel data piece representing a luminance level for each pixel;
Synchronously with a reference clock signal, L (L is an integer of 2 or more) input pixel data pieces are simultaneously acquired, and the acquired L input pixel data pieces are output as a first pixel data group. A latch,
A first buffer for outputting a first amplified pixel data group obtained by amplifying the first pixel data group;
The first amplified pixel data group is simultaneously captured in synchronization with a first clock signal having a phase different from that of the reference clock signal and having the same frequency as the reference clock signal, and the captured first amplified pixel data group A second latch that outputs as a second pixel data group;
A second buffer for outputting a second amplified pixel data group obtained by amplifying the second pixel data group;
A display device driver, comprising: a data latch that takes in the second amplified pixel data group and outputs the fetched second amplified pixel data group for every n pixels. The display device driver according to claim 1, further comprising: a delay circuit that generates a signal obtained by delaying the reference clock signal by a predetermined period as the first clock signal .

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