JP6339714B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device incorporating a memory circuit and a microprocessor.

  There is a semiconductor integrated circuit device incorporating a memory circuit and a microprocessor (hereinafter referred to as a CPU). For example, there is a semiconductor integrated circuit device called SoC (System on a Chip) in which a memory circuit and a CPU are formed in one semiconductor chip. Such semiconductor integrated circuit devices are used in various fields.

  On the other hand, the market for electronic commerce services performed via the Internet, such as e-commerce and net banking, is steadily expanding. In addition, electronic money services using IC cards are already in widespread use and entering an expansion period. In these electronic commerce services and electronic money services, many semiconductor integrated circuit devices are used. In particular, in these services, since money and / or personal information is handled, a higher level of security is always required. Therefore, a higher level of security is also required for semiconductor integrated circuit devices used in such services.

  As security technology, there are a software level technology and a hardware level technology. At the software level, for example, an attempt is made to achieve a higher level of security by using an encryption technique centered on a strong encryption algorithm. On the other hand, at the hardware level, an attempt is made to physically implement and implement an encryption algorithm. However, it has also been pointed out that an attack by an attacker such as a so-called hacker (cracker) may permit the decryption of the secret key.

  In a semiconductor integrated circuit device, an ID (IDentification) is stored in a fuse (Fuse) or a non-volatile memory circuit incorporated in the semiconductor integrated circuit device when the semiconductor integrated circuit device is manufactured. In this case, a problem has been pointed out that there is a risk that data (ID) stored at the time of manufacture may be falsified during actual use, or the semiconductor chip itself may be duplicated.

  In order to solve such a problem, it has been proposed to generate an ID unique to the semiconductor integrated circuit device by paying attention to variations occurring when the semiconductor integrated circuit device is manufactured. For example, in a semiconductor chip in which a field effect transistor (hereinafter referred to as a MOSFET) is formed as an element, an ID (unique ID) unique to the semiconductor chip is generated using variations in MOSFETs that occur during manufacturing. It has been proposed. According to such a proposal, it is possible to generate a semiconductor chip unique ID (PUF) that cannot be physically duplicated.

JP 2012-43517 A JP 2012-73955 A

  Japanese Patent Application Laid-Open No. 2004-228688 discloses a technique in which a memory test is performed by the memory BIST 104 when a supply voltage to the memory 103 is lowered compared to that during normal operation, and a unique ID is generated using an address where an error has occurred. Is shown (FIG. 7). In Patent Document 2, after initial data is written to an SRAM memory cell, “Low” is simultaneously written to both bit lines of the SRAM memory cell, and a unique ID is used using the data read from the SRAM memory cell. The technique of creating is shown.

  In the technique disclosed in Patent Document 1, a configuration for controlling the power supply voltage of the memory 103 is required, and there is a concern that overhead may occur. Further, since the memory test is executed by the memory BIST 104, it is feared that time is required to create the unique ID. In the technique disclosed in Patent Document 2, it is required to write “Low” to both bit lines at the same time, and there is a concern that overhead may occur in order to realize this.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  In one embodiment, when generating the unique ID, the potential of the word line of the SRAM (Static Random Access Memory) memory cell is made higher than the power supply voltage of the SRAM and then lower than the power supply voltage of the SRAM. When the potential of the word line is higher than the power supply voltage of the SRAM, the same data (“High” or “Low”) is applied to both bit lines of the memory cell. As a result, the state of the SRAM memory cell is changed to an indefinite state (destroyed state), and then changed so as to hold data according to the characteristics of the elements constituting the SRAM. When manufacturing the SRAM, the characteristics of the elements constituting the memory cell vary. Therefore, the SRAM memory cell holds data in accordance with variations that occur during its manufacture. That is, the unique ID is generated and stored in the SRAM memory cell.

  In one embodiment, the voltage applied to the word line of the SRAM memory cell when generating the unique ID is formed by a booster circuit. As a result, it is possible to suppress the overhead with respect to the circuit scale and the operation speed.

  Note that a relatively high potential may be applied to the word line of the SRAM memory cell when data is written to the memory cell. This is performed to assist the data writing to the SRAM memory cell, and does not form and store the unique ID in the memory cell. Further, since this is a technique for assisting writing, when a relatively high potential is applied to the word line, the potentials of both bit lines are different from each other according to the data to be written (“High” or “Low”). )).

  According to one embodiment, a semiconductor integrated circuit device capable of generating a unique ID while suppressing overhead can be provided.

1 is a block diagram showing a configuration of a semiconductor integrated circuit device according to an embodiment. 1 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a first embodiment. 1 is a block diagram showing a configuration of an SRAM according to a first embodiment. (A) And (B) is a wave form diagram which shows operation | movement of SRAM concerning Embodiment 1. FIG. 5 is a block diagram showing a configuration of an SRAM according to a second embodiment. FIG. 5 is a block diagram showing a configuration of an SRAM according to a second embodiment. FIG. (A)-(C) are the wave forms which show operation | movement of SRAM concerning Embodiment 2. FIG. 5 is a block diagram showing a configuration of an SRAM according to a second embodiment. FIG. (A)-(C) are the wave forms which show operation | movement of SRAM concerning Embodiment 2. FIG. (A)-(C) are circuit diagrams which show the structure of the non-volatile memory concerning Embodiment 3. FIG. FIG. 10 is a block diagram showing a configuration of an SRAM according to a fourth embodiment. FIG. 10 is a circuit diagram illustrating a circuit of a main part of an SRAM according to a fourth embodiment. (A)-(G) is a wave form diagram which shows operation | movement of SRAM concerning Embodiment 4. FIG. FIG. 10 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a fifth embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  First, the structure of the semiconductor integrated circuit device according to the embodiment will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit device. In FIG. 1, reference numeral 100 denotes a semiconductor chip sealed in a semiconductor integrated circuit device. In the manufacture of a semiconductor integrated circuit device, a plurality of semiconductor chips are formed on a semiconductor wafer through a plurality of manufacturing steps. The semiconductor chip shown in FIG. 1 is a semiconductor chip formed through a plurality of manufacturing steps. In a semiconductor manufacturing process, due to variations in manufacturing conditions in the manufacturing process, characteristics vary in elements such as MOSFETs and / or wirings even between a plurality of semiconductor chips formed on the same semiconductor wafer. Of course, if the semiconductor wafers are different, the characteristics of elements (including elements such as MOSFETs and wirings) vary among the semiconductor chips formed on the respective semiconductor wafers. The semiconductor integrated circuit device is not particularly limited, but a semiconductor chip formed through a plurality of manufacturing steps is sealed in a package to be a finished product.

  Various circuit blocks are formed on the semiconductor chip 100. In this embodiment, among various circuit blocks, a microprocessor (CPU) 101 and memory circuits 103 and 104 connected to the CPU 101 via a bus 102 are shown. In this embodiment, each of the memory circuits 103 and 104 is composed of an SRAM.

  The CPU 101 fetches a program via the bus 102 and performs predetermined processing according to the fetched program. In the predetermined processing, for example, data is read from the memory circuit via the bus 102 or data is supplied to the memory circuit or the like via the bus 102. The program fetched by the CPU 101 may be read from the SRAMs 103 and 104, but may be read from other memory circuits not shown. When processing is performed by the CPU 101 in accordance with the program, data read to the CPU 101 via the bus 102 may be output from one of the memories 103 and 104, or other memory not shown in the figure. It may be output from a circuit or the like. Similarly, when the CPU 101 is executing processing, data output from the CPU 101 via the bus 102 may be supplied to either of the memory circuits 103 and 104, and other data not shown in the figure may be provided. In some cases, it is supplied to a circuit block.

  In FIG. 1, SRAMs 103 and 104 have the same configuration. However, the SRAM 103 is different from the SRAM 104 in that a function for generating a unique ID (unique ID) is added to the semiconductor chip 100. The SRAM 103 generates a unique ID by supplying a unique ID generation instruction signal (IDgen) 105 for generating a unique ID to the semiconductor chip 100 from the CPU 101 to the SRAM 103. The unique ID generated in the SRAM 103 is held in the SRAM 103. The CPU 101 reads the unique ID held from the SRAM 103 via the bus 102 and uses it for security. For example, the read unique ID is used to generate a secret key. When the unique ID is generated by the SRAM, the CPU 101 can be regarded as constituting a control circuit from the viewpoint of controlling the unique ID generation.

  Hereinafter, a plurality of embodiments of the configuration of the SRAM 103 (memory circuit) with the ID generation function will be described.

  FIG. 1 shows an example in which two SRAMs 103 with an ID generation function are provided. In this way, a plurality of unique IDs can be easily generated by using a plurality of SRAMs 103 with ID generation functions. However, the present invention is not limited to providing a plurality, and the number of SRAMs 103 with an ID generation function may be one.

(Embodiment 1)
FIG. 2 is a block diagram showing a configuration of the semiconductor integrated circuit device according to the first embodiment. In FIG. 2, the same parts as those in FIG. In FIG. 2, reference numeral 200 denotes a booster circuit (voltage generation circuit), and 202 denotes a voltage wiring to which a boosted voltage boosted by the booster circuit 200 is supplied. In the figure, reference numeral 203 denotes a power supply voltage terminal provided on the semiconductor chip 100, and 201 denotes a power supply voltage VDD supplied to the power supply voltage terminal to each circuit block formed in the semiconductor chip 100. Power supply voltage wiring. In the figure, the power supply voltage wiring 201 is connected to the CPU 101, SRAMs 103 and 104, and the booster circuit 200. Although not shown in the figure, the ground voltage GND is supplied to the circuit blocks (including the CPU 101, the SRAMs 103 and 104, and the booster circuit 200) in the semiconductor chip 100 through the ground voltage wiring. Each of CPU 101, SRAM 103, 104 and booster circuit 200 operates using a potential difference (VDD-GND) between power supply voltage wiring 201 and a ground voltage wiring (not shown) as a power supply voltage.

  In this embodiment, the booster circuit 200 boosts the power supply voltage VDD, and the boosted boosted voltage is supplied to the SRAM 103 with an ID generation function among the plurality of SRAMs 103 and 104 via the voltage wiring 202. The Next, as will be described with reference to FIGS. 3, 4 </ b> A, and 4 </ b> B, the SRAM 103 with an ID generation function receives the unique ID generation instruction signal 105 and uses the boosted voltage boosted by the booster circuit 200. A unique ID is generated and held.

  FIG. 3 is a block diagram showing a configuration of the SRAM 103 with an ID generation function shown in FIG. In the figure, 300 is a cell array (memory array), 301 is a word line decoder (WL decoder), 302 is a bit line control circuit, 303 is an input / output circuit, and 304 is a control unit.

  The cell array has a plurality of memory cells M arranged in a matrix. A word line is arranged in each row of the matrix, and a plurality of memory cells M arranged in the row are connected to each word line. A bit line pair is arranged in each column of the matrix, and a plurality of memory cells M arranged in the column are connected to each bit line pair.

  A plurality of address signals are supplied to the SRAM 103 with an ID generation function via the bus 102. Some of the plurality of address signals are row address signals and are supplied to the word line decoder 301. Some of the plurality of address signals are column address signals and are supplied to the bit line control circuit 302. The word line decoder 301 decodes the supplied row address signal and selects one word line according to the row address signal from a plurality of word lines (not shown). On the other hand, the bit line control circuit 302 decodes the column address signal and selects one or more bit line pairs according to the column address signal from the plurality of bit line pairs. That is, the word line decoder 301 can be regarded as a row selection circuit, and the bit line control circuit 302 can be regarded as a column selection circuit.

  One bit line pair or a plurality of bit line pairs selected in this way is connected to the bus 102 via the input / output circuit 303.

  When one word line is selected by the word line decoder 301, a plurality of memory cells M (a plurality of memory cells in one row) connected to the word line are selected, and the bit line control circuit 302 One or more pairs of bit lines are selected. Thereby, one or a plurality of memory cells M arranged at the intersection of one selected word line and one or more pairs of bit lines are selected from the memory array 300.

  The control unit 304 receives instructions for reading and writing operations from the CPU 101 (FIG. 1) as a read / write instruction signal R / W. Also, the unique ID generation instruction signal 105 is received. When the read / write instruction signal R / W from the CPU 101 instructs a read operation, the word line decoder 301 is instructed to apply the power supply voltage VDD to the word line specified by the row address signal. . At this time, the control unit 304 instructs the input / output circuit 303 to output data in the selected one or more pairs of bit lines to the bus 102. As a result, the data held in the selected one or a plurality of memory cells is read out to the CPU 101 via the bus 102.

  On the other hand, when the read / write instruction signal R / W from the CPU 101 instructs a write operation, the control unit 304 instructs the word line decoder 301 to supply the power supply voltage VDD to the word line specified by the row address signal. Is applied. At this time, the control unit 304 instructs the input / output circuit 303 to transmit (input) the data on the bus 102 to the selected one or more pairs of bit lines. As a result, the data from the CPU 101 is transmitted to the selected one or a plurality of memory cells via the bus 102 and written to the memory cells.

  In the first embodiment, when the unique ID generation instruction signal 105 is supplied to the control unit 304, the control unit 304 applies a boost voltage generated by the boost circuit 200 to the word line decoder 301. Instructs application to the word line specified by the address signal. In response to this instruction, the word line decoder 301 applies a boosted voltage that is higher than the power supply voltage VDD to the selected word line, and after a predetermined time has elapsed, the word line decoder 301 reduces the potential of the word line to a potential lower than the power supply voltage VDD. To lower. At this time, the control unit 304 instructs the input / output circuit 303 to apply a voltage corresponding to the power supply voltage VDD to each of the selected one or more pairs of bid lines. In response to this instruction, the input / output circuit 303 electrically isolates the bit line control circuit 302 from the bus 102, and supplies the power supply voltage VDD to each of the selected one or more pairs of bit lines. A voltage corresponding to is applied. In other words, a voltage corresponding to the power supply voltage VDD is applied to both bit lines of the selected bit line pair.

  When the unique ID generation instruction signal 105 is supplied to the control unit 304 in this way, a boosted voltage exceeding the power supply voltage VDD is supplied to the selected one or a plurality of memory cells via the word line. Is done. At this time, a voltage corresponding to the power supply voltage VDD is supplied to each of a pair of bit lines constituting the bit line pair. Further, the potential of the word line is lowered to a potential lower than the power supply voltage VDD when a predetermined time elapses.

  In FIG. 3, a circuit of one memory cell of a plurality of memory cells arranged in the cell array 300 is shown as a representative in the upper right of FIG.

  The memory cell M includes P-channel MOSFETs (hereinafter referred to as P-MOSFETs) P1 and P2 and N-channel MOSFETs (hereinafter referred to as N-MOSFETs) N1 to N4. The source of the P-MOSFET P1 is connected to the power supply voltage wiring 201 to which the power supply voltage VDD is supplied via the power supply voltage node Vn, and the source of the N-MOSFET N3 is connected to the ground voltage via the ground voltage node Vs. The GND is connected to the ground voltage wiring to which power is supplied. The drain of the P-MOSFET P1 and the drain of the N-MOSFET N3 are connected in common. Further, the gate of the P-MOSFET P1 and the gate of the N-MOSFET N3 are connected in common to each other. Thus, the P-MOSFET P1 and the N-MOSFET N3 constitute a first inverter circuit that operates using the power supply voltage VDD and the ground voltage GND as the power supply voltages.

  Similarly, the source of the P-MOSFET P2 is connected to the power supply voltage wiring 201 supplied with the power supply voltage VDD, and the source of the N-MOSFET N4 is connected to the ground voltage wiring supplied with the ground voltage GND. The drain and the drain of the N-MOSFET N4 are connected in common with each other. Further, the gate of the P-MOSFET P2 and the gate of the N-MOSFET N4 are connected in common with each other. Thus, the P-MOSFET P2 and the N-MOSFET N4 constitute a second inverter circuit that operates using the power supply voltage VDD and the ground voltage GND as the power supply voltages.

  The gates of the P-MOSFET P1 and N-MOSFET N3 that are inputs of the first inverter circuit are connected to the drains of the P-MOSFET P2 and N-MOSFET N4 that are outputs of the second inverter circuit. Similarly, the gates of P-MOSFET P2 and N-MOSFET N4, which are inputs of the second inverter circuit, are connected to the drains of P-MOSFET P1 and N-MOSFET N3, which are outputs of the first inverter circuit. ing. That is, a so-called latch circuit (holding circuit) is configured by the first inverter circuit and the second inverter circuit. In this case, since the latch circuit is composed of the first and second inverter circuits, the latch circuit operates using the voltage difference (voltage) between the power supply voltage VDD and the ground voltage GND as the power supply voltage.

  The input of the first inverter circuit is connected to one bit line BB constituting a pair of bit lines via an N-MOSFET N2, and the input of the second inverter circuit is connected to a pair of bits via an N-MOSFET N1. It is connected to the other bit line BT constituting the bit line. The gates of the N-MOSFETs N1 and N2 are connected to the word line WL. The N-MOSFETs N1 and N2 function as MOSFETs for data transfer between a pair of bit lines and a latch circuit. Each of the N-MOSFETs N1 and N2 has a first input / output electrode connected to the bit line and a second input / output electrode connected to a pair of input / output nodes I2 and I1 of the latch circuit. These first and second input / output electrodes function as sources or drains, but since the source and drain change depending on the voltage during operation, they are simply expressed as input / output electrodes here.

  4A and 4B show operation waveforms when the memory cell M described above is selected by the row address signal and the column address signal. 4A and 4B, during a period Tr, the change in the voltage of the word line and the voltage of the bit line pair when the read operation (mode) is instructed by the read / write instruction signal R / W. Show. A period Tw indicates a change in the voltage of the word line and the voltage of the bit line pair when the write operation (mode) is instructed by the read / write instruction signal R / W. Further, a period Ti indicates a change in the voltage of the word line and the voltage of the bit line pair (BL pair) when the unique ID generation instruction signal 105 instructs the unique ID generation operation (mode).

  When a read operation is instructed (Read), the potential of the selected word line WL rises from the ground voltage GND to the power supply voltage VDD (select voltage) as shown in FIG. It is done. Each of the bit lines BB and BT constituting the bit line pair is precharged to a predetermined voltage in advance before the read operation. When the voltage of the word line WL is changed toward the power supply voltage VDD, the transfer MOSFETs N1 and N2 are changed to a conductive state. Thereby, according to the data held in the memory cell M, the potential of one bit line constituting the bit line pair or the other bit line is lowered from the precharged potential.

  For example, if the memory cell M holds data such that the N-MOSFET N4 is turned on and the N-MOSFET N1 is turned off, the potential of the word line WL rises to store in the bit line BB in advance. The charges thus discharged are discharged through the transfer MOSFET N2 and the N-MOSFET N4, and the potential of the bit line BB is lowered. At this time, since the N-MOSFET N3 maintains the off state, the potential of the bit line BT is also maintained (FIG. 4B).

  When a write operation is instructed (Write), the potential of the selected word line WL rises from the ground voltage GND to the power supply voltage VDD (select voltage) as shown in FIG. It is done. At this time, a potential corresponding to data to be written is applied from the CPU 101 to the one bit line and the other bit line constituting the bit line pair via the bus 102 and the input / output circuit 303. That is, a voltage having a complementary relationship is applied to the bit line pair.

  For example, a voltage corresponding to the power supply voltage VDD is supplied to one bit line BB constituting the bit line pair, and a voltage corresponding to the ground voltage GND is supplied to the other bit line BT (FIG. 4 ( B)). As the potential of the word line WL rises toward the power supply voltage VDD, the transfer MOSFETs N1 and N2 are turned on. As a result, a voltage corresponding to the power supply voltage VDD is applied to the gates of the P-MOSFET P1 and the N-MOSFET N3 constituting the first inverter circuit. On the other hand, a voltage corresponding to the ground voltage GND is applied to the gates of the P-MOSFET P2 and the N-MOSFET N4 constituting the second inverter circuit. Since the latch circuit is constituted by the first inverter circuit and the second inverter circuit, the action of positive feedback works, and the N-MOSFET N4 constituting the second inverter circuit shifts to the off state, and the first inverter circuit The N-MOSFET N3 constituting the circuit shifts to the ON state.

  In this manner, according to the data to be written, the N-MOSFET N4 or N3 is turned on (off state), and data is written. After the data is written, the voltage of the word line WL is lowered from the power supply voltage VDD toward the ground voltage GND. Thereby, each of the transfer MOSFETs N1 and N2 is turned off, and the state (stable state) of the latch circuit is maintained. In other words, the data written in the memory cell M is held.

  Next, a case where an operation for generating a unique ID is instructed will be described. When the operation for generating the unique ID is instructed, in response to the unique ID generation instruction signal 105, the control unit 304 causes the word line decoder 301 to select the boosted voltage formed by the booster circuit 200 as the selected word. Instruct to apply to line WL. As a result, the word line decoder 301 applies a voltage exceeding the power supply voltage VDD to the selected word line WL. At this time, the control unit 304 instructs the input / output circuit 303 to supply a voltage corresponding to the power supply voltage VDD to each of the selected bit lines. As a result, the input / output circuit 303 supplies a voltage corresponding to the power supply voltage VDD to each of the bit lines BB and BT constituting the bit line pair, as shown in FIG. . The word line decoder 301 reduces the voltage at the time t1 after a predetermined time has elapsed after setting the voltage of the word line WL to a voltage exceeding the power supply voltage VDD.

  By making the voltage of the word line WL higher than the power supply voltage VDD, the voltage loss caused by the threshold voltage in each of the transfer MOSFETs N1 and N2 can be reduced, and the input / output of the latch circuit included in the memory cell Voltage transfer is performed between the nodes I1 and I2 and the bit line pair BB and BT. In other words, the same voltage (voltage corresponding to the power supply voltage VDD) is applied to the inputs of the first and second inverter circuits constituting the latch circuit. By the action of positive feedback constituted by the first inverter circuit and the second inverter circuit, the potentials of the respective inputs (input / output nodes I1 and I2 of the latch circuit) of the first inverter circuit and the second inverter circuit are changed to the power supply voltage VDD. And the ground potential GND. In other words, the latch circuit constituted by the first inverter circuit and the second inverter circuit is in an indefinite state.

  At time t1, when the potential of the word line WL decreases and the transfer MOSFETs N1 and N2 are turned off, the input / output nodes I1 and I1 of the latch circuit according to the characteristics of the P-MOSFETs P1 and P2 and the N-MOSFETs N3 and N4, The voltage at I2 changes. For example, when the characteristics of the N-MOSFET N4, for example, the threshold voltage thereof is lower than the threshold voltage of the N-MOSFET N3, the voltage at the input / output node I1 drops before the voltage at the input / output node I2. The potential difference between the input / output nodes I1 and I2 is amplified by the action of positive feedback. This amplification stabilizes the N-MOSFET N4 in the on state and the N-MOSFET N3 in the off state. Differences in the characteristics of these MOSFETs are caused by, for example, variations during manufacturing. Therefore, when the voltage of the word line WL is lowered and the transfer MOSFET is turned off, the memory cell holds data according to the variation in characteristics of elements such as the MOSFET.

  As a result, the unique ID can be generated based on the variation in characteristics of elements and the like at the time of manufacture. Since the generated unique ID is held in the memory cell M, the CPU 101 can read the value and use it as an authentication key. In this case, for example, a unique ID may be generated as described above in each of a plurality of memory cells connected to one word line, or a unique ID may be generated by one memory cell. It may be.

  According to the first embodiment, in response to the unique ID generation instruction signal, the voltage of the word line of the memory cell is made higher in absolute value than the power supply voltage VDD of the memory cell, and the memory is connected via the bit line pair. A voltage corresponding to the power supply voltage VDD of the memory cell is supplied to the cell. As a result, the loss of the voltage transmitted from the bit line pair to the latch circuit constituting the memory cell can be reduced, and the memory cell can be reliably brought into an indefinite state. In addition, by reducing the voltage of the word line to a value that is absolutely smaller than the power supply voltage VDD of the memory cell, data (unique ID) according to the characteristics of the MOSFET that constitutes the memory cell is generated in the memory cell. And retained.

  As the booster circuit 200 described above, a booster circuit that is formed on the same semiconductor chip 100 and supplies a boosted voltage to other circuit blocks may be used. For example, in the above-described write assist, a relatively high voltage is used, and a voltage generation circuit for generating this voltage is provided in the semiconductor chip. This voltage generation circuit may also be used as the booster circuit 200 described above.

  As described above, according to this embodiment, it is possible to generate a unique ID while suppressing overhead.

(Embodiment 2)
FIG. 5 is a block diagram showing a configuration of the SRAM according to the second embodiment. The configuration of the SRAM shown in FIG. 5 is similar to the configuration of the SRAM shown in FIGS. In FIG. 5, the same parts as those in FIGS. 2 and 3 are denoted by the same reference numerals, and the differences will be mainly described.

  As described with reference to FIG. 3, the cell array 300 includes a plurality of memory cells M arranged in a matrix. In the second embodiment, the supply of power supply voltage VDD and / or ground voltage GND to memory cell M is controlled by unique ID generation instruction signal 105.

  In FIG. 5, reference numeral 500 denotes a cell power supply control circuit (voltage control circuit) that receives the unique ID generation instruction signal 105 and controls power supply of the power supply voltage VDD (ground voltage GND) to the cell array 300. In the second embodiment, the cell power supply control circuit 500 is connected between the power supply voltage wiring 201 and a ground voltage wiring (not shown), and determines the voltage difference between the power supply voltage VDD and the ground voltage GND. It is composed of an inverter circuit that operates as a power source. The inverter circuit is supplied with a unique ID generation instruction signal 105 as its input. The output of the inverter circuit, that is, the output of the cell power supply control circuit 500 is connected to each power supply node of the plurality of memory cells M included in the cell array 300. The power supply node will be described later with reference to FIGS. 6 and 8, but the memory cell M is a node that receives a power supply voltage or a ground voltage as its operating voltage.

  In FIG. 5, reference numeral 501 denotes a peripheral circuit of the cell array 300. The peripheral circuit 501 includes a word line decoder (WL decoder) 502, a bit line control circuit 505, an input / output circuit 503, and a control unit 504. Peripheral circuit 501 is connected to power supply voltage wiring 201 and a ground voltage wiring (not shown), and is supplied with power supply voltage VDD and ground voltage GND. Each circuit block (the word line decoder 502, the bit line control circuit 505, the input / output circuit 503, the control unit 504, etc.) included in the peripheral circuit 501 supplies the difference voltage between the power supply voltage VDD and the ground voltage GND as a power supply. Operates as a voltage.

  The control unit 504, the word line decoder 502, the bit line control circuit 505, and the input / output circuit 503 shown in FIG. 5 are respectively the control unit 304, the word line decoder 301, the bit line control circuit 302, and the input / output described in FIG. Since it is similar to each of the circuits 303, different parts will be described.

  The control unit 504 receives the read / write instruction signal R / W and the unique ID generation instruction signal 105. When the generation of the unique ID is instructed by the unique ID generation instruction signal 105, the control unit 304 described with reference to FIG. Behaves differently than That is, when the generation of the unique ID is instructed, in response to this, the control unit 504 instructs the word line decoder to set the selected word line to the circuit ground voltage. When generation of the unique ID is instructed, the control unit 504 instructs the bit line control circuit 505 and the input / output circuit 503 to maintain each of the plurality of bit line pairs in the precharged state. .

  Similar to the word line decoder 301 described with reference to FIG. 3, the word line decoder 502 supplies a voltage corresponding to the power supply voltage VDD to the selected word line in the read operation and the write operation. On the other hand, when generating the unique ID, the word line selected by the row address signal is set to a voltage corresponding to the ground voltage GND according to an instruction from the control unit 504. Similarly, the bit line control circuit 505 and the input / output circuit 503 perform the same operations as the bit line control circuit 302 and the input / output circuit 303 described in FIG. 3 in the read operation and the write operation. However, when the generation of the unique ID is instructed, the bit line pair is maintained in the precharge state.

  The unique ID generation instruction signal 105 is changed from, for example, a low level to a high level when instructing generation of a unique ID. When the unique ID generation instruction signal 105 changes to a high level, the cell power supply control circuit (inverter circuit) 500 changes the power supply voltage supplied to the memory cell M from the power supply voltage VDD to the ground voltage GND. As a result, the power supply voltage VDD is not supplied to the memory cell M. Therefore, the memory cell M cannot hold information. The power supply to the memory cell M is resumed after a predetermined time after the power supply is stopped. When the power supply voltage VDD is supplied to the memory cell M by resuming the power supply, the state of the latch circuit included in the memory cell M is determined according to the characteristics of the elements (such as MOSFETs) constituting the memory cell M. As a result, data in accordance with variations at the time of manufacture is generated and stored in the memory cell M, and a unique ID is generated.

  Resumption of power supply is achieved, for example, by changing the unique ID generation instruction signal 105 to a high level and then changing it to a low level after a predetermined time. The unique ID generation instruction signal 105 changing in this way is formed by the CPU 101 (FIG. 1) which is a control circuit. As the memory cell M for generating the unique ID, one or a plurality of memory cells in the cell array 300 can be used. In this way, the unique ID generated and stored in the memory cell M is read from the SRAM 103 (FIG. 1) by the CPU 101 when it is used.

  When power supply to the cell array 300 is stopped, power supply to the peripheral circuit 501 may also be stopped. As a result, power consumption can be reduced. However, in the second embodiment, the power supply to the peripheral circuit 501 is separated from the power supply to the cell array 300. As a result, power is supplied to the peripheral circuit 501 even during the period when the supply of the power supply voltage VDD to the cell array 300 is stopped. By doing so, it is possible to prevent a change in the potential of a signal (for example, a word line signal) supplied from the peripheral circuit 501 to the cell array 300 when power supply to the cell array 300 is resumed. It is possible to prevent undesired data from being written to the memory cells in the cell array 300.

  FIG. 6 is a diagram showing in detail the circuit of the memory cell M in the SRAM described with reference to FIG. Also in FIG. 6, the same parts as those in FIG. 5 are denoted by the same reference numerals, and the description of the same parts is omitted. In FIG. 6, the power supply voltage wiring 201 shown in FIG. 5 is omitted. The cell power supply control circuit is also shown as a block 500, not an inverter circuit.

  In FIG. 6, the circuit of the memory cell M is shown as a representative example at the upper left in the figure. The circuit of the memory cell M has the same configuration as that of the memory cell M shown in FIG. 3. In the circuit of the memory cell, the same parts as those in FIG. The sources of the P-MOSFETs P1 and P2 constituting the memory cell M are connected to the power supply voltage node Vn, and the sources of the N-MOSFETs N3 and N4 are connected to the power supply voltage (ground voltage) node Vs. By applying a voltage difference between the power supply voltage VDD and the ground voltage GND between the power supply voltage node Vn and the ground voltage node Vs, the latch circuit constituting the memory cell operates.

  7A to 7C are waveform diagrams showing the operation of the SRAM shown in FIG. The operation will be described based on this waveform diagram. Similar to FIGS. 4A and 4B, FIG. 7A shows the voltage waveform of the selected word line, and FIG. 7B shows the selected bit line. A voltage waveform of the line pair BL is shown. In FIG. 7C, a waveform of the power supply voltage of the cell array 300 is shown. In other words, the voltage waveform of the power supply voltage node Vn of the memory cell M is shown in FIG.

  7A to 7C, Tr indicates a period of a read operation (Read), Tw indicates a period of a write operation (Write), and Ti indicates a unique ID generation operation (ID generation). Shows the period. In FIG. 7C, the cell power source (power source of the cell array 300) is a power source because the unique ID generation instruction signal 105 (FIG. 5) is at a low level during the read operation period Tr and the write operation period Tw. The voltage is VDD. Therefore, the read operation and the write operation in the read period Tr and the write period Tw are the same as the operations described with reference to FIG.

  In the period Ti of the unique ID generation operation, the unique ID generation instruction signal 105 is changed from the low level to the high level by the CPU 101. The unique ID generation instruction signal 105 is changed to a low level by the CPU 101, for example, at a time t1 after a predetermined time after being changed to a high level. When the unique ID generation instruction signal 105 is changed from the low level to the high level, the cell power supply control circuit 500 configured by the inverter circuit supplies the voltage supplied to the cell array 300 as shown in FIG. Change to ground voltage GND. At time t1, the unique ID generation instruction signal 105 is changed from the high level to the low level, so that it is changed again to the power supply voltage VDD.

  The power supply voltage of the cell array 300, that is, the voltage at the power supply voltage node Vn of the memory cell M changes to the ground voltage GND when the unique ID generation instruction signal 105 changes to high level. As a result, the potential difference between the power supply voltage node Vn and the ground voltage node Vs of the memory cell M decreases. As a result, the latch circuit in the memory cell constituted by the P-MOSFETs P1 and P2 and the N-MOSFETs N3 and N4 cannot hold data. That is, the data held in the memory cell is destroyed (indefinite state). After the data is destroyed, that is, at time t1, the unique ID generation instruction signal 105 is changed to the low level again. As a result, the power supply voltage VDD is supplied to the power supply voltage node Vn of the memory cell M, the potential difference between the power supply voltage node Vn and the ground voltage node Vs increases, and the latch circuit starts operating.

  When the latch circuit starts operating, the voltage at the pair of input / output nodes I1 and I2 of the latch circuit changes according to the characteristics of the elements such as P-MOSFETs P1 and P2 and N-MOSFETs N3 and N4. The characteristics of these MOSFETs are determined according to variations in manufacturing semiconductor chips. For this reason, the voltages at the input / output nodes I1 and I2 of the latch circuit are also determined in accordance with variations in manufacturing. The latch circuit performs a positive feedback operation to increase the potential difference between the input / output nodes I1 and I2. As a result, the latch circuit in the memory cell M holds data according to the manufacturing variation.

  In this way, data serving as a unique ID is stored in the memory cell M. In the second embodiment, as shown in FIG. 7A, the voltage of the word line WL is set to the ground voltage GND during the ID generation period Ti. This prevents the transfer MOSFETs N1 and N2 in the memory cell M from being turned on during the ID generation period. When the transfer MOSFET in the memory cell M is turned on during the ID generation period, the voltage of the bit line pair BL may be transmitted to the input / output nodes I1 and I2 via the transfer MOSFET. It is conceivable that the internal latch circuit holds data according to the voltage from the bit line pair BL. Thus, in order to control the voltage of the word line WL, as described in FIG. 5, the peripheral circuit 501 is supplied with power through the power supply voltage wiring 201 even when the power supply of the cell array 300 is shut off. Will continue.

  FIG. 8 shows a modification of the SRAM shown in FIG. Also in FIG. 8, the same parts as those in FIG. Therefore, a different part from FIG. 6 is mainly demonstrated.

  In the SRAM shown in FIG. 8, a cell power control circuit (voltage control circuit) 800 for controlling the ground voltage GND of the cell array 300 is provided instead of the cell power control circuit 500 shown in FIG. The cell power supply control circuit 800 controls the ground voltage of the memory cell M provided in the cell array 300. That is, the voltage applied to the ground voltage node Vs of the memory cell M is controlled according to the unique ID generation instruction signal 105.

  Cell power supply control circuit 800 includes two inverter circuits (not shown) that receive power supply voltage VDD and ground voltage GND as operating voltages, although not particularly limited. A unique ID generation instruction signal 105 is input to a first inverter circuit of the two inverter circuits, and a signal obtained by inverting the phase of the unique ID generation instruction signal 105 is formed and output. The output of the first inverter circuit is input to the second inverter circuit, and the output of the second inverter circuit is used as the ground voltage of the cell array 300. That is, the cell array 300 is buffered with the unique ID generation instruction signal 105 by the cell power supply control circuit 800 and supplied with power as the ground voltage GND. As a result, when the unique ID generation instruction signal 105 is set to a high level, which is a level for instructing generation of the unique ID, the ground voltage GND of the cell array 300 changes to the power supply voltage VDD.

  9A to 9C are waveform diagrams showing the operation of the SRAM of FIG. Since (A) to (C) in FIG. 9 are similar to (A) to (C) in FIG. 7, differences will be mainly described.

  FIG. 9C, unlike FIG. 7C, shows the voltage change of the ground voltage (cell VSS) of the cell array 300. In the period Tr of the read operation (Read) and the period Tw of the write operation (Write), the unique ID generation instruction signal 105 is at a low level, and thus the ground voltage GND is supplied to the cell array 300. That is, the ground voltage GND is supplied from the cell power supply control circuit 800 to the ground voltage node Vs of the memory cell M. Thereby, the read operation and the write operation are performed as in FIG.

  In the period Ti of the unique ID generation operation (ID generation), as described in FIG. 7, the unique ID generation instruction signal 105 changes from the low level to the high level, and then changes to the low level again after a predetermined time t1. . This unique ID generation instruction signal 105 is buffered by the cell power supply control circuit 800 and supplied to the cell array 300 as the ground voltage GND. Therefore, during the unique ID generation period Ti, the ground voltage of the cell array 300 changes from the ground voltage GND to the power supply voltage VDD, and then changes to the ground voltage GND again after a predetermined time t1.

  As the ground voltage supplied to cell array 300, that is, the voltage supplied to ground voltage node Vs of memory cell M approaches power supply voltage VDD, the potential difference between power supply voltage node Vn and ground voltage node Vs decreases. . Thereby, the data of the latch circuit in the memory cell M is destroyed. When the potential of the ground voltage node Vs decreases again after the predetermined time t1, the latch circuit holds data according to the characteristics of the MOSFETs that constitute the latch circuit. As a result, as described with reference to FIGS. 6 and 7, the data of the unique ID corresponding to the manufacturing variation is generated and stored in the memory cell M.

  Also in this modified example, the ground voltage is separately supplied to the peripheral circuits such as the word line decoder 502 and the cell array 300. Thus, the ground voltage GND is supplied to the peripheral circuit even during the period Ti of the unique ID generation operation. The word line decoder 502 supplies the ground voltage GND to the word line WL during the period Ti because the ground voltage GND is supplied even during the period Ti of the unique ID generation operation. By doing so, it is possible to reduce the writing of undesired data in the memory cell M.

  According to the second embodiment, the semiconductor integrated circuit device includes a voltage control circuit that generates a power supply voltage for operating the latch circuit in the memory cell. In response to the unique ID generation instruction, the power supply voltage control circuit changes the power supply voltage so that the voltage difference supplied to the latch circuit as its operating voltage decreases, and then the above voltage difference increases. Change the power supply voltage. As a result, the latch circuit in the memory cell is set in an indefinite state, and thereafter data (unique ID) according to the characteristics of the elements such as MOSFETs constituting the memory cell is generated and held.

  According to this embodiment, it is possible to generate and hold a unique ID while suppressing an increase in overhead.

(Embodiment 3)
10A to 10C are circuit diagrams illustrating the configuration of the semiconductor integrated circuit device according to the third embodiment.

  In the above-described embodiment, the SRAM incorporated in the semiconductor integrated circuit device has been described as an example. In the third embodiment, an example in which a nonvolatile memory is used instead of the SRAM will be described. 10A to 10C show the configuration of the cells of the nonvolatile memory.

  Although not particularly limited, the semiconductor integrated circuit device according to the third embodiment includes two types of nonvolatile memories. That is, a nonvolatile memory for storing data in advance and a nonvolatile memory for generating a unique ID are provided. A nonvolatile memory for storing data in advance is used, for example, instead of the SRAM 104 in FIG. 1, and a nonvolatile memory for generating a unique ID is used in place of the SRAM 103 with an ID generation function in FIG.

  A nonvolatile memory for storing data in advance has a plurality of memory cells. The configuration of this memory cell is shown in FIGS. 10A and 10B. Similarly, the non-volatile memory for generating the unique ID has a plurality of memory cells, and the configuration of one of the memory cells is shown in FIG.

  First, the structure of the memory cell will be described with reference to FIGS. One memory cell (nonvolatile memory cell: described as a nonvolatile cell in the figure) has N-MOSFETs N5 and N6 each having a gate connected to the word line WL. Of these two N-MOSFETs N5 and N6, one electrode (source or drain) of one N-MOSFET N5 is connected to one bit line BT in one pair of bit lines BL, and the other N -One electrode (source or drain) of MOSFET N6 is connected to the other bit line BB. One of the other electrodes (drain or source) of the N-MOSFETs N5 and N6 is connected to the ground voltage GND according to data stored in advance. At this time, the other electrode not connected to the ground voltage GND is brought into a floating state.

  In FIG. 10A, the other electrode of the N-MOSFET N5 is connected to the ground voltage GND, and the other electrode of the N-MOSFET N6 is in a floating state. The state connected in this way is, for example, a state in which “1” data is stored. On the other hand, in FIG. 10B, the other electrode of the N-MOSFET N6 is connected to the ground voltage GND, and the other electrode of the N-MOSFET N5 is in a floating state. The state connected in this way is, for example, a state in which “0” data is stored. In this way, data is stored in advance in the memory cell.

  Reading of the memory cell is performed by precharging the bit line pair BL and then setting the word line WL to high level. That is, when the word line WL is set to the high level, the charge precharged on the bit line is discharged via the MOSFET whose other electrode is connected to the ground voltage GND, and the bit line BL The voltage of any of the bit lines decreases. By detecting this voltage drop, data stored in advance is read out.

  FIG. 10C shows a configuration of a memory cell for generating a unique ID (nonvolatile memory cell: described as an ID generating cell in the figure). The memory cell for generating the unique ID has N-MOSFETs N7 and N8 whose gates are connected to the word line WL. One electrode (source or drain) of the N-MOSFET N7 is connected to one bit line BT of the bit line pair BL, and one electrode (source or drain) of the N-MOSFET N8 is connected to the bit line pair BL. Are connected to one bit line BB. The other electrode (drain or source) of each of the N-MOSFETs N7 and N8 is connected to the ground voltage GND.

  In the memory cell for generating the unique ID shown in FIG. 10, the bit line pair BL is precharged in advance, and then the potential of the word line WL is set to the high level. In this way, the charges precharged to the bit lines BT and BB are discharged via the N-MOSFETs N7 and N8, and the potentials of the bit lines BT and BB are lowered. The rate of potential drop at this time is determined according to the characteristics of the N-MOSFETs N7 and N8. Due to variations in the manufacturing process of the semiconductor chip, a difference occurs between the characteristics of the N-MOSFET N7 and the characteristics of the N-MOSFET N8, so that a potential difference is generated between the bit line BT and the bit line BB. In the third embodiment, this potential difference is detected and used as a unique ID. In this way, it is possible to generate a unique ID in a memory cell having the same structure as a memory cell that stores data in advance, and it is possible to facilitate design.

  In FIG. 10, one unique ID generation memory cell has been described. However, a plurality of unique ID generation memory cells may be provided. Further, the MOSFET constituting the memory cell may be a P-MOSFET. Further, instead of precharging the bit line pair, a current may be constantly supplied. The potential difference between the bit line pair may be amplified by a differential amplifier circuit or the like, or may be detected by a latch circuit using positive feedback.

  Further, the data and unique ID stored in the nonvolatile memory are read out by the CPU 101 via the bus 102 (FIG. 1).

  Further, instead of providing the nonvolatile memory instead of the SRAM, the above-described nonvolatile memory may be provided separately from the SRAMs 103 and 104 shown in FIG.

  According to the third embodiment, it is possible to obtain a non-volatile memory cell for generating a unique ID with the same configuration as that of a non-volatile memory cell that stores data in advance, so that the ease of design can be improved. Become. It is also possible to prevent an increase in overhead.

(Embodiment 4)
FIG. 11 is a block diagram showing a configuration of the SRAM according to the fourth embodiment. The SRAM shown in the figure is formed on one semiconductor chip.

  In the fourth embodiment, the cell array has a plurality of memory blocks 1100. Each memory block 1100 has the same configuration. Therefore, in FIG. 11, one memory block is representative and the internal configuration is shown. Although not particularly limited, writing and reading for each bit can be performed for each memory block. That is, writing D [0] to D [n] or reading Q [0] to Q [n] of a plurality of bits of data in parallel in time is possible.

  Hereinafter, the representative memory block 1100 will be described, but it should be understood that the remaining memory blocks have the same configuration.

  The memory block 1100 has a plurality of memory cells MC arranged in a matrix. Word lines W1 to Wn are arranged in each row in the matrix, and each of the memory cells MC arranged in each row is connected to a word line arranged in that row. In addition, bit line pairs BL1 to BLn are arranged in each column of the matrix, and each of the memory cells MC arranged in each column is connected to the bit line pair arranged in that column. Each of the bit line pairs BL1 to BLn has a pair of bit lines BT1, BB1 to BTn, BBn.

  The configuration of the memory cell MC is not shown, but has the same configuration as the memory cell M described in FIG. That is, each of the memory cells MC includes the P-MOSFETs P1 and P2 and the N-MOSFETs N1 to N4 shown in FIG. Of the N-MOSFETs N1 to N4, the gates of the transfer N-MOSFETs N1 and N2 are connected to the word lines in the row where the memory cells are arranged. Each electrode of the transfer N-MOSFETs N1 and N2 is connected to a bit line pair in a column in which the memory cell is arranged. That is, the electrode of the transfer N-MOSFET N1 is connected to one bit line BT in the bit line pair BL in the corresponding column, and the electrode of the transfer N-MOSFET N2 is connected to the other of the bit line pair BL in the corresponding column. Are connected to the bit line BB.

  In FIG. 11, reference numeral 1101 denotes a row selection circuit. The row selection circuit 1101 includes the word line decoder 301 described with reference to FIG. 3, decodes the row address signal X supplied from the address control circuit 1102, and selects a row address signal from the plurality of word lines W1 to Wn. The word line designated by X is selected. The address control circuit 1102 takes in the address signal A based on the address control signal TDEC from the control unit 1103 and separates the address signal A into a row address signal X and a column address signal Y. As described above, the separated row address signal X is supplied to the row selection circuit 1101, and the separated column address signal Y is supplied to the column selection circuit 1104. In the figure, each of the address signal A, the row address signal X, and the column address signal Y is shown by one signal line, but each address signal is composed of a plurality of address signals. .

  The column selection circuit 1104 decodes the supplied column address signal, and selects a bit line pair designated by the column address signal from the plurality of bit line pairs BL1 to BLn. The selected bit line pair is connected to the common write bit line pair and the common read bit line pair. The common write bit line pair has a pair of common write bit lines CTW and CBW, and the common read bit line pair has a pair of common read bit lines CTR and CBR. Although not particularly limited, of the selected bit line pair BL, the bit line BT1 (BTn) is connected to the common write bit line CTW and the common read bit line CTR, and the bit line BB1 (BBn) is the common write bit line. Connected to CBW and common read bit line CBR.

  The common write bit lines CTW and CBW are connected to the write driver 1105. The write driver 1105 receives 1-bit data D [0] supplied from an input terminal as input data DI via an input / output circuit (IO buffer) 1107. When the write enable signal WTE instructs writing, the write driver 1105 gives a potential according to the input data DI to the common write bit lines CTW and CBW. Here, the potentials applied to the common write bit lines CTW and CBW are complementary potentials. That is, for example, when a high level voltage is applied to the common write bit line CTW, a low level voltage is applied to the common write bit line CBW.

  The common read bit lines CTR and CBR are connected to the sense amplifier 1106. The sense amplifier 1106 amplifies the potential difference between the common read bit lines CTR and CBR when the read operation is instructed by the read enable signal RDE and the activation of the sense amplifier is instructed by the sense amplifier activation signal SAE. The output data DO is supplied to the input / output circuit 1107. The input / output circuit 1107 outputs 1-bit data Q [0] according to the supplied output data DO.

  The voltage of the pair of bit lines in the selected bit line pair becomes a complementary voltage according to the data stored (stored) in the selected memory cell. For example, when the voltage of the bit line BT1 constituting the bit line pair BL1 becomes high level according to the data stored in the selected memory cell, the voltage of the other bit line BB1 constituting the bit line pair BL1 Becomes low level. As a result, the voltages of the common read bit lines CTR and CBR to which the selected bit line pair is connected also become complementary voltages.

  The control unit 1103 receives the clock signal CLK, the output enable signal CEN, the write enable signal WEN, and the unique ID generation instruction signal IDEN, and forms the control signals TDEC, WTE, RDE, and SAE based on these signals. .

  Based on the address signal A, a word line and a bit line pair are selected, and memory cells connected to the selected word line and bit line pair are selected from a plurality of memory cells arranged in a matrix. In the case of a write operation on the selected memory cell, complementary voltages according to data to be written from the write driver 1105 are applied to the common write bit lines CTW and CBW and the bit lines BT1 and BB1 (BTn and BBn). Then, the data is supplied to the selected memory cell, and writing to the memory cell is performed. Similarly, in the case of a read operation from the selected memory cell, the voltages of the bit lines BT1, BB1 (BTn, BBn) become complementary voltages according to the data stored in the memory cell. This complementary voltage is applied to the sense amplifier 1106 via the common read bit lines CTR and CBR, and the potential difference is amplified and output from the input / output circuit 1107 as data Q [0].

  The word lines W1 to Wn are wired over a plurality of memory blocks 1100, and a row according to the row address signal X is selected from the row in each memory block. On the other hand, although omitted in the figure, the column address signal Y is supplied from the address control circuit 1102 to the column selection circuit 1104 in each memory block, and a column is selected in each memory block. The same operation as that of the representative memory block described in (1) is performed.

  As will be described later with reference to FIGS. 12 and 13, a unique ID is generated by a unique ID generation instruction signal IDEN.

  FIG. 12 is a circuit diagram showing the configuration of SRAM column selection circuit 1104 and sense amplifier 1106 shown in FIG. 13A to 13G are waveform diagrams for explaining the operation of the circuit shown in FIG.

  In FIG. 11, the column selection circuit 1104 has a plurality of unit column selection circuits corresponding to the plurality of bit line pairs BL1 to BLn, respectively. In FIG. 12, each of the broken-line blocks 1200-1 to 1200-n is a unit column selection circuit. In the figure, the unit column selection circuit 1200-1 is shown as a representative circuit. Only the representative unit column selection circuit 1200-1 will be described below, but the same applies to other unit column selection circuits.

  Unit column selection circuit 1200-1 receives P-MOSFETs P3 and P4 connected between bit line pair BLn and the common read bit line pair, column address signal Y, and an inverted signal of sense amplifier activation signal SAE. A NAND circuit 1201. That is, the drain-source path of the P-MOSFET P3 is connected between the bit line BTn constituting the bit line pair BLn and the common read bit line CTR, and the drain-source path of the P-MOSFET P4 is Are connected between the bit line BBn constituting the bit line pair BLn and the common read bit line CBR. The gates of the P-MOSFETs P3 and P4 are connected in common, and the selection signal formed by the NAND circuit 1201 is supplied. Each of the P-MOSFETs P3 and P4 functions as a column switch that selectively connects the bit lines BTn and BBn and the common read bit lines CTR and CBR according to a selection signal from the NAND circuit 1201.

  In the drawing, in order to avoid the complexity of the drawing, one column address signal Y is shown to be supplied to the NAND circuit 1201. However, it should be understood that a plurality of column address signals Y are supplied to the NAND circuit 1201. Accordingly, the NAND circuit 1201 forms a low-level selection signal when the combination of the voltages (levels) of the plurality of column address signals is a predetermined combination and the sense amplifier activation signal SAE is at the low level. . By this low level selection signal, the P-MOSFETs P3 and P4, which are column switches, are turned on, and the bit lines BTn and BBn and the common read bit lines CTR and CBR are electrically connected.

  Each of the other unit column selection circuits 1200-2 to 1200-n has the same configuration as the unit column selection circuit 1200-1. However, the conditions under which the NAND circuit 1201 in each of the unit column selection circuits 1200-2 to 1200-n outputs a low-level selection signal are different. That is, the combination of the potentials of the plurality of column address signals Y is made different between the NAND circuits 1201. As a result, the column address signal Y causes one unit column selection circuit among the plurality of unit column selection circuits 1200-1 to 1200 to n to connect the bit line corresponding to (connected to) the unit column selection circuit. Connected to common read bit lines CTR, CBR.

  The sense amplifier 1106 connected to the common read bit lines CTR and CBR has a sense amplifier circuit and a precharge circuit for precharging the common read bit lines CTR and CBR. The precharge circuit has a source / drain path between the power supply voltage VDD and the common read bit lines CTR and CBR, and a source / drain path connected between the P-MOSFETs P6 and P5 and the common read bit lines CTR and CBR. And a P-MOSFET P7 to which a drain path is connected.

  A precharge control signal is supplied to each gate of these P-MOSFETs P5 to P7. When the precharge control signal becomes low level, these P-MOSFETs P5 to P7 are turned on to precharge the common read bit lines CTR and CBR to the power supply voltage VDD. In these P-MOSFETs, when the P-MOSFET P7 is turned on, the common read bit lines CTR and CBR are electrically short-circuited and the voltages of the common read bit lines CTR and CBR are equalized. To function.

  The sense amplifier circuit operates so as to amplify the potential difference between the common read bit lines CTR and CBR. In this embodiment, the sense amplifier circuit has P-MOSFETs P9 and P10 and N-MOSFETs N9, N10, and N11.

  The source / drain path of the P-MOSFET P9 is connected between the power supply voltage VDD and the input / output node IO1, and the source / drain path of the N-MOSFET N9 is connected to the input / output node IO1 and the drain of the N-MOSFET N11. . The gate of the P-MOSFET P9 and the gate of the N-MOSFET N9 are made common and connected to the input / output node IO2. The source / drain path of the P-MOSFET P10 is connected between the power supply voltage VDD and the input / output node IO2, and the source / drain path of the N-MOSFET N10 is connected to the input / output node IO2 and the drain of the N-MOSFET N11. ing. The gate of the P-MOSFET P10 and the gate of the N-MOSFET N10 are made common and connected to the input / output node IO1.

  The source of the N-MOSFET N11 is connected to the ground voltage GND, and a control signal based on the sense amplifier activation signal SAE is supplied to its gate. The input / output node IO1 is connected to the common read bit line CBR, and the input / output node IO2 is connected to the common read bit line CTR.

  With the above connection, the P-MOSFET P9 and the N-MOSFET N9 constitute a first inverter circuit, and the P-MOSFET P10 and the N-MOSFET N10 constitute a second inverter circuit. The input of the first inverter circuit is connected to an input / output node IO2 corresponding to the output of the second inverter circuit, and the input of the second inverter circuit is input / output node IO1 corresponding to the output of the first inverter circuit. It is connected to the. That is, the first and second inverter circuits constitute a latch circuit. Thus, when the N-MOSFET N11 that operates as a switch is turned on by the sense amplifier activation signal SAE, the latch circuit operates so as to amplify the potential difference between the input / output nodes IO1 and IO2. That is, it operates so as to amplify the potential difference between the common read bit lines CTR and CBR.

  The sense amplifier 1106 receives the read enable signal RDE and the sense amplifier activation signal SAE from the control unit 1103 (FIG. 11), and controls the sense amplifier circuit, the precharge circuit, and the plurality of unit column selection circuits. The control circuit which forms is comprised. Of course, this control circuit may be provided in the control unit 1103 shown in FIG. The control circuit receives a sense amplifier activation signal SAE that is a control signal, receives a buffer circuit 1204 that forms a control signal of the N-MOSFET N11 that functions as a switch, and a sense amplifier activation signal SAE, and selects a plurality of unit columns. It has an inverter circuit 1202 for generating a selection signal for the circuits 1200-1 to 1200-n.

  The control circuit also has a NOR circuit 1203 that receives the read enable signal RDE and the sense amplifier activation signal SAE. The output of the NOR circuit 1203 is supplied to the gates of P-MOSFETs P5 to P7 constituting the precharge circuit. The output of the NOR circuit 1203 is also supplied to the gate of the P-MOSFET P11 having its source / drain path connected between the drain of the N-MOSFET N11 and the power supply voltage VDD.

  The P-MOSFET P11 is turned on when the common read bit lines CTR and CBR are precharged, and raises the drain of the N-MOSFET N11 to the power supply voltage VDD. In other words, the sources of the N-MOSFETs N9 and N10 are raised to the power supply voltage VDD. Thereby, when precharging is performed, the power supply voltage VDD is applied to the power supply voltage node Vn and the ground voltage node Vs of the latch circuit, and the stable state of the latch circuit constituting the sense-up circuit is destroyed. can do.

  In FIG. 12, the common write bit lines CTW and CBW are omitted.

  13A to 13G show the waveforms of the signals shown in FIG. 13A shows the waveform of the unique ID generation instruction signal IDEN, FIG. 13B shows the waveform of the clock signal CLK, and FIG. 13C shows the waveform of the address signal A. 13D shows the column address signal Y, and FIG. 13F shows changes in the voltages of the common read bit lines CTR and CBR. 13E shows the waveform of the read enable signal RDE formed by the control unit 1103 (FIG. 11), and FIG. 13G shows the sense amplifier activation signal formed by the control unit 1103. The waveform of SAE is shown.

  The read enable signal RDE and the sense amplifier activation signal SAE are formed by the control unit 1103 based on the clock signal CLK, the output enable signal CEN, the write enable signal WEN, and the unique ID generation instruction signal IDEN. Similarly to the read enable signal RDE and the sense amplifier activation signal SAE, the write enable signal WTE and the address control signal TDEC shown in FIG. 11 also have the clock signal CLK, the output enable signal CEN, the write enable signal WEN, and the unique ID generation instruction. The control unit 1103 forms based on the signal IDEN. The control unit 1103 can be realized, for example, by combining a plurality of logic circuits.

  Next, the operation of the SRAM according to this embodiment will be described based on the waveform shown in FIG.

  The SRAM according to the present embodiment is not particularly limited, but operates in synchronization with the clock signal CLK. In FIG. 13, a period indicated by Tr indicates a read operation (Read) period, and a period indicated by Ti indicates a unique ID generation operation (ID generation) period. Tp indicates the period of the operation before the read operation (Read).

  In order to operate in synchronization with the clock signal CLK, the address control signal TDEC is generated when the potential of the clock signal CLK ((B) in FIG. 13) rises at time t1 in FIG. When the address control signal TDEC is generated, the address control circuit 1102 (FIG. 11) takes in the address signal A at that time (FIG. 13C) and generates a row address signal X and a column address signal Y.

  Based on the generated row address signal A, one of the plurality of word lines W1 to Wn is selected by the row selection circuit 1101 (FIG. 11) and is set to the high level. In the period Tp before reading, each of the bit line pairs BL1 to BLn is precharged. For example, when the word line W1 is selected and set to the high level by the row selection circuit 1101, the bit line pairs BL1 to BL1 are set according to the data stored in each of the plurality of memory cells MC connected to the word line W1. The charges precharged in each of BLn are discharged, and the potential of each bit line pair is determined.

  Based on the column address signal Y (FIG. 13D), the column selection circuit 1104 (FIG. 11) selects a bit line pair from the plurality of bit line pairs BL1 to BLn, and the selected bit line pair is common. Connected to read bit lines CTR and CBR. In FIG. 13D, all column address signals supplied to the NAND circuit 1201 in the unit column selection circuit 1200-1 are in a high level state. In this case, the bit lines BT1 and BB1 are connected to the common read bit lines CTR and CBR via the P-MOSFETs P3 and P4 that operate as column switches.

  The operation (write operation or read operation) in the period Tp before the read operation (Read) is completed. Therefore, at a time before time t1, the write enable signal WEN and the output enable signal CEN are set to a low level, for example. Thereby, at a time before time t1, both the read enable signal RDE and the sense amplifier activation signal SAE are at a low level. Therefore, at a time before time t1, the output of the NOR circuit 1203 is at a low level, and the P-MOSFETs P5 to P7 in the precharge circuit are turned on. Through these P-MOSFETs P5 and P6, the common read bit lines CTR and CBR are precharged by the power supply voltage VDD. Further, the common read bit lines CTR and CBR are short-circuited by the P-MOSFET P7 so that the potential difference between the common read bit lines CTR and CBR is reduced.

  Since the sense amplifier activation signal SAE is also at a low level, the N-MOSFET N11 that is a switch for activating the sense amplifier is turned off. On the other hand, the precharge P-MOSFET P11 is turned on by the output of the NOR circuit 1203. Therefore, the ground voltage node Vs of the latch circuit in the sense amplifier circuit is precharged with the power supply voltage VDD via the P-MOSFET P11. As a result, the potential difference between the power supply voltage node Vn and the ground voltage node Vs of the sense amplifier circuit is reduced, and the stable state of the sense amplifier circuit is destroyed.

  At time t1, for example, when the read operation (Read) is designated by the output enable signal CEN and the write enable signal WEN, the read enable signal RDE ((E) in FIG. 13) is set to the high level accordingly. Change. After a predetermined time after the read enable signal RDE changes to high level, the sense amplifier activation signal SAE ((G) in FIG. 13) is changed from low level to high level.

  As the read enable signal RDE changes to high level, the output of the NOR circuit 1203 also changes to high level. Thereby, each of the P-MOSFETs P5 to P7 in the precharge circuit is turned off. The precharge P-MOSFET P11 is also turned off. Accordingly, the potential of the common read bit line CTR ((F) in FIG. 13) changes according to the potential of the bit line BT1 connected via the P-MOSFET P4, and the potential of the common read bit line CBR is P−. It changes according to the potential of the bit line BB1 connected via the MOSFET P3.

  As the sense amplifier activation signal SAE changes from the low level to the high level, the N-MOSFET N11 for activating the sense amplifier is turned on, and the potential difference between the common read bit lines CTR and CBR is amplified. The amplified result is transmitted to the input / output circuit 1107 via the same common read bit lines CTR and CBR.

  The sense amplifier activation signal SAE changes to high level after a predetermined time has elapsed after changing to high level. The read enable signal RDE also changes to a low level when a predetermined time elapses after it changes to a high level.

  In this way, the data stored in the memory cell is read out. Also, the read enable signal RDE and the sense amplifier activation signal SAE change to low level, so that the P-MOSFETs P5 to P7 in the precharge circuit are turned on, and the precharge P-MOSFET P11 is also turned on. Is done. As a result, the common read bit lines CTR and CBR are precharged and the potentials are equalized again, and the latch circuit in the sense amplifier is destroyed in its stable state to prepare for the next operation.

  Next, the unique ID generation operation will be described. The unique ID generation operation is instructed to the SRAM by a unique ID generation instruction signal IDEN. In this embodiment, the specific ID generation instruction signal IDEN is changed to a high level to give the instruction.

  In FIG. 13, the unique ID generation instruction signal IDEN is changed from the low level to the high level at time t2. That is, an operation for generating a unique ID is instructed at time t2.

  Based on the high level of the unique ID generation instruction signal IDEN, the control unit 1103 (FIG. 11) grasps that the operation of generating the unique ID is specified, and is not particularly limited, but stops issuing the address control signal TDEC. Thus, even if the clock signal CLK changes to a high level during the period Ti, the address control circuit 1102 does not capture the address signal A and generate the row address signal X and the column address signal Y.

  Further, since the unique ID generation instruction signal IDEN is set to the high level, the control unit 1103 does not change the read enable signal RDE to the high level even when the clock signal CLK changes to the high level in the period Ti. In this case, the control unit 1103 changes the sense amplifier activation signal SAE to high level at time t3 after a predetermined time after the clock signal CLK changes to high level.

  Since the read enable signal RDE does not change to the high level, the NOR circuit 1203 receives the low level read enable signal RDE and the sense amplifier until the time t3 after the sense amplifier activation signal SAE changes to the low level in the period Tr. An activation signal SAE is supplied. Therefore, during this period, the NOR circuit 1203 forms a low level control signal.

  By this low level control signal, the P-MOSFETs P5 to P7 and the precharge P-MOSFET P11 in the procharge circuit are turned on. That is, the common read bit lines CTR and CBR are connected to the power supply voltage VDD by the P-MOSFETs P6 and P5, respectively, and the precharge is continuously performed. During this period, the common read bit lines CTR and CBR are short-circuited by the P-MOSFET P7 that is in the on state, and the potentials are equalized. Further, the ground voltage node Vs of the latch circuit in the sense amplifier circuit is precharged to the power supply voltage VDD by the P-MOSFET P11 in the on state, and the stable state of the latch circuit in the sense amplifier circuit is destroyed. Yes.

  At time t3, the sense amplifier activation signal SAE changes from the low level to the high level, so that the NOR circuit 1203 outputs a high level control signal. As a result, each of the P-MOSFETs P5 to P7 in the precharge circuit shifts to an off state. Further, the precharge P-MOSFET P11 is also turned off.

  On the other hand, the N-MOSFET N11 which is a switch for activating the sense amplifier circuit changes to an ON state when the sense amplifier activation signal SAE changes to a high level. As a result, the sense amplifier circuit starts operating. At this time, the sense amplifier activation signal SAE is inverted by the inverter circuit 1202, and the selection signal formed by the inversion is supplied to the NAND circuit 1201 in each of the unit column selection circuits 1200-1 to 1200-n. .

  This selection signal obtained by inverting the phase of the sense amplifier activation signal SAE is transmitted between the bit line pair and the common read bit line pair for each of the unit column selection circuits 1200-1 to 1200-n. It functions as a control signal for instructing electrical separation. In other words, the NAND circuit 1201 in each unit column selection circuit supplies a high level signal to the P-MOSFETs P3 and P4 functioning as column switches by this low level selection signal. Accordingly, the plurality of bit line pairs BL1 to BLn and the common read bit lines CTR and CBR are electrically separated by the P-MOSFETs P3 and P4.

  When the sense amplifier circuit starts to operate, the potentials of the common read bit lines CTR and CBR, which are the respective inputs (IO1 and IO2) of the sense amplifier circuit, are precharged to the power supply voltage VDD. . Therefore, there is no potential difference between the inputs of the sense amplifier circuit. In this case, the sense amplifier circuit shifts to a state in accordance with variations in characteristics of the P-MOSFETs P9 and P10 and the N-MOSFETs N9 and N10 that constitute the sense amplifier circuit. That is, the potentials of the input / output nodes IO1 and IO2 are determined by variations in the characteristics of the P-MOSFETs P9 and P10 and the N-MOSFETs N9 and N10 caused by variations in manufacturing. The potential difference between the input / output nodes IO1 and IO2 is amplified by the positive feedback action of the latch circuit constituted by the inverter circuit, and a stable state is obtained. The generated unique ID is transmitted to the input / output circuit 1107 via the common read bit lines CTR and CBR and used by the CPU or the like.

  In this embodiment, the unique ID is generated using variations in elements such as MOSFETs constituting the sense amplifier circuit.

  The unique ID may be generated in each memory block shown in FIG. In this case, a plurality of unique IDs can be obtained.

  As an example of the sense amplifier circuit, in this embodiment, the case of using a sense amplifier circuit having a latch circuit is described; however, the present invention is not limited to this. For example, a first MOSFET whose gate is connected to the common read bit line CTR and a second MOSFET whose gate is connected to the common read bit line CBR are prepared. In the sense amplifier circuit in which the prepared first MOSFET and the second MOSFET source are connected to each other and a current source is provided at this connection point, and the difference between the currents flowing through the first and second MOSFETs is detected. Can be applied. In this case, it is possible to generate a unique ID by using the variation in characteristics of the first and second MOSFETs.

  In this embodiment, the SRAM is described as an example. However, the embodiment may be a nonvolatile memory, a DRAM, or a flash memory.

  According to the fourth embodiment, the sense amplifier circuit amplifies the potential difference between the bit line pair (common read bit line pair) precharged to the same voltage. Therefore, the sense amplifier changes to a state in accordance with the characteristics of the MOSFET that constitutes the sense amplifier. This state is used as a unique ID by the CPU or the like.

(Embodiment 5)
FIG. 14 is a block diagram showing a configuration of a semiconductor integrated circuit device according to the fifth embodiment. The semiconductor integrated circuit device shown in FIG. 14 is similar to the semiconductor integrated circuit device shown in FIG. 1, and therefore, differences from FIG. 1 will be mainly described.

  In the semiconductor integrated circuit device shown in FIG. 1, a unique ID generation instruction signal 105 is supplied from the CPU 101 to the SRAM 103 with an ID generation function, and the unique ID generated in the SRAM 103 is supplied to the CPU 101 via the bus 102. It is supposed to be done. In contrast, in the fifth embodiment, an ID generation module 1400 is formed on the semiconductor chip 100 of the semiconductor integrated circuit device.

  In this embodiment, a unique ID generation instruction signal 1403 is supplied from the CPU 101 to the ID generation module 1400, and the ID generation module 1400 receives the unique ID generation instruction signal 1403, whereby the above-described unique ID generation instruction signal 1403 is received. The signal 105 or IDEN is supplied to the SRAM 103 with an ID generation function. The SRAM 103 with ID generation function has the same configuration as the SRAM 103 with ID generation function shown in FIG.

  Each of the plurality of SRAMs 103 with an ID generation function receives a unique ID generation instruction signal 105 (IDEN), and generates a unique ID as described in the above embodiments. The generated unique ID is supplied not to the bus 102 but to the ID generation module 1400 via an individual signal line. The ID generation module 1400 generates a unique ID based on the unique ID supplied from each of the SRAMs 103 with an ID generation function, and supplies the unique ID 1401 to the CPU 101. By doing so, it is possible to generate a stronger unique ID. In FIG. 14, the CPU 101 controls the ID generation module 1400. In order to clearly indicate that control is performed, the CPU 101 is described as a control circuit CPU in FIG.

  The third embodiment described above relates to a nonvolatile memory. In FIG. 14, the SRAM 104 may be a non-volatile memory in which data is stored in advance, and 103 may be an ID generation non-volatile memory. In this case, the nonvolatile memory 104 includes the nonvolatile cells shown in FIGS. 10A and 10B, and the ID generation nonvolatile memory 103 includes the ID generation cells shown in FIG. Including.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention.

100 Semiconductor chip 101 CPU
103 SRAM with ID generation function
104 SRAM
105 Unique ID generation instruction signal 200 Booster circuit M, MC Memory cells P1 to P11 P-MOSFET
N1-N11 N-MOSFET

Claims (8)

A holding circuit arranged in a matrix, each having a plurality of MOSFETs and a pair of input / output nodes, and operating with a voltage difference between a first voltage and a second voltage as an operating voltage; A plurality of memory cells each comprising a pair of transfer MOSFETs connected to a pair of input / output nodes and supplied with a selection signal at their gates;
A plurality of word lines arranged in each row of the matrix and connected to the gates of a pair of transfer MOSFETs in a plurality of memory cells arranged in the corresponding row;
A plurality of bit line pairs that are arranged in each column of the matrix and to which a pair of transfer MOSFETs in a plurality of memory cells arranged in the corresponding column are connected;
A cell array comprising:
A peripheral circuit for selecting a word line from the plurality of word lines and selecting a bit line pair from the plurality of bit line pairs;
A voltage control circuit for generating the first voltage, wherein in response to a unique ID generation instruction, the voltage value of the first voltage is changed so that the voltage difference decreases, and then the voltage difference is increased. A voltage control circuit for changing the voltage value of the first voltage;
Equipped with,
The operating voltage of the peripheral circuit is a semiconductor integrated circuit device that is not changed during a period in which the voltage control circuit changes the voltage value of the first voltage . The semiconductor integrated circuit device according to claim 1,
The semiconductor integrated circuit device includes a voltage wiring for supplying the first voltage,
The voltage control circuit is connected to the voltage wiring,
The semiconductor integrated circuit device, wherein the peripheral circuit is connected to the voltage wiring and operates using a voltage in the voltage wiring as an operating voltage. The semiconductor integrated circuit device according to claim 2,
The peripheral circuit is
A row selection circuit for selecting a word line from the plurality of word lines;
A column selection circuit for selecting a bit line pair from the plurality of bit line pairs;
A semiconductor integrated circuit device comprising: The semiconductor integrated circuit device according to claim 3.
The semiconductor integrated circuit device includes a CPU that issues the unique ID generation instruction. The semiconductor integrated circuit device according to claim 3.
The row selection circuit is a semiconductor integrated circuit device in which the word line is deselected in response to the unique ID generation instruction. The semiconductor integrated circuit device according to claim 3 or 5,
The column selection circuit is a semiconductor integrated circuit device that maintains the bit line pair in a precharge state in response to the unique ID generation instruction. The semiconductor integrated circuit device according to claim 1,
The semiconductor integrated circuit device, wherein the first voltage is supplied to a power supply voltage node of the holding circuit, and the second voltage is supplied to a ground voltage node of the holding circuit. The semiconductor integrated circuit device according to claim 1,
The semiconductor integrated circuit device, wherein the first voltage is supplied to a ground voltage node of the holding circuit, and the second voltage is supplied to a power supply voltage node of the holding circuit.

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