JP6213520B2 - ヘテロ接合半導体装置及びその製造方法 - Google Patents
ヘテロ接合半導体装置及びその製造方法 Download PDFInfo
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- JP6213520B2 JP6213520B2 JP2015101118A JP2015101118A JP6213520B2 JP 6213520 B2 JP6213520 B2 JP 6213520B2 JP 2015101118 A JP2015101118 A JP 2015101118A JP 2015101118 A JP2015101118 A JP 2015101118A JP 6213520 B2 JP6213520 B2 JP 6213520B2
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- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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Description
第1の実施の形態におけるヘテロ接合半導体装置は、図1に示すように、基板10、バッファ層12、チャネル層14、バリア層16、p型半導体層18、n型半導体層20、ゲート電極22、ソース電極24、ドレイン電極26及び保護膜28を含んで構成される。
以下、図4A〜図4Iを参照しつつ、第1の実施の形態におけるヘテロ接合半導体装置の製造方法について説明する。
第2の実施の形態におけるヘテロ接合半導体装置は、図5に示すように、第1の実施の形態におけるヘテロ接合半導体装置のp型半導体層18上に絶縁層50を備える。なお、絶縁層50以外の構成は、第1の実施の形態におけるヘテロ接合半導体装置と同様であるので、同一の符号を付して説明を省略する。
第3の実施の形態におけるヘテロ接合半導体装置は、図7に示すように、第1の実施の形態におけるヘテロ接合半導体装置のn型半導体層20の上面及び側面にゲート電極22が設けられる。なお、ゲート電極22の形成領域以外の構成は、第1の実施の形態におけるヘテロ接合半導体装置と同様であるので、同一の符号を付して説明を省略する。
第4の実施の形態におけるヘテロ接合半導体装置は、図9に示すように、p型半導体層18のトレンチ構造のコーナー部18bが曲面形状を有する。なお、p型半導体層18の形状以外の構成は、第1の実施の形態におけるヘテロ接合半導体装置と同様であるので、同一の符号を付して説明を省略する。
Claims (7)
- 第1の半導体を含むチャネル層と、
前記チャネル層上に設けられ、前記第1の半導体よりバンドギャップの大きい半導体を含むバリア層と、を備えるヘテロ接合半導体装置であって、
前記バリア層上に設けられ、前記バリア層とオーミック接合されたソース電極及びドレイン電極と、
前記バリア層上の前記ソース電極と前記ドレイン電極との間の領域に設けられたp型半導体層と、前記p型半導体層上に設けられたn型半導体層と、前記n型半導体層と接合されたゲート電極と、を備え、
前記p型半導体層と前記n型半導体層の接合面は凹凸構造とされており、前記凹凸構造の前記p型半導体層が凸部となる領域において、前記p型半導体層と前記ゲート電極とが絶縁層を介して接合されていることを特徴とするヘテロ接合半導体装置。 - 請求項1に記載のヘテロ接合半導体装置であって、
前記ゲート電極は、前記n型半導体層の上面及び側面に設けられていることを特徴とするヘテロ接合半導体装置。 - 請求項1又は2に記載のヘテロ接合半導体装置であって、
前記凹凸構造のコーナー部が曲面状であることを特徴とするヘテロ接合半導体装置。 - 請求項1〜3のいずれか1項に記載のヘテロ接合半導体装置であって、
前記チャネル層はGaNで構成され、前記バリア層はAlGaNで構成され、前記p型半導体層はp型−GaNで構成され、前記n型半導体層はn型−GaNで構成されていることを特徴とするヘテロ接合半導体装置。 - 第1の半導体を含むチャネル層上に、前記第1の半導体よりバンドギャップの大きい半導体を含むバリア層を形成する第1の工程と、
前記バリア層上に、前記バリア層とオーミック接合されるソース電極及びドレイン電極を形成する第2の工程と、
前記バリア層上の前記ソース電極と前記ドレイン電極との間の領域に、p型半導体層を形成する第3の工程と、
前記p型半導体層を凹凸構造に加工する第4の工程と、
前記p型半導体層上に、前記p型半導体層との接合面が凹凸構造となるようにn型半導体層を形成する第5の工程と、
前記n型半導体層上に、ゲート電極を形成する第6の工程と、
前記第3の工程と前記第4の工程の間に、前記p型半導体層上に絶縁層を形成する第7の工程と、
を備え、
前記第4の工程では、前記p型半導体層と共に前記絶縁層を凹凸構造に加工することを特徴とするヘテロ接合半導体装置の製造方法。 - 請求項5に記載のヘテロ接合半導体装置の製造方法であって、
前記第6の工程では、前記n型半導体層の上面及び側面に前記ゲート電極を形成することを特徴とするヘテロ接合半導体装置の製造方法。 - 請求項5又は6に記載のヘテロ接合半導体装置の製造方法であって、
前記第4の工程では、前記凹凸構造のコーナー部を曲面状に加工することを特徴とするヘテロ接合半導体装置の製造方法。
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US15/138,808 US9559197B2 (en) | 2015-05-18 | 2016-04-26 | Hetero-junction semiconductor device and method of manufacturing a hetero-junction semiconductor device |
TW105114449A TWI626747B (zh) | 2015-05-18 | 2016-05-10 | 異質接面半導體裝置及製造異質接面半導體裝置的方法 |
CN201610319919.6A CN106169507B (zh) | 2015-05-18 | 2016-05-13 | 异质结半导体装置以及制造异质结半导体装置的方法 |
DE102016108911.7A DE102016108911B4 (de) | 2015-05-18 | 2016-05-13 | Heteroübergang-Halbleitervorrichtung und Verfahren zur Herstellung einer Heteroübergang-Halbleitervorrichtung |
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