JP6210434B2 - Group III nitride semiconductor light emitting device manufacturing method - Google Patents

Description

  The technical field of the present specification relates to a method for manufacturing a group III nitride semiconductor light emitting device. More specifically, the present invention relates to a method for manufacturing a group III nitride semiconductor light-emitting device that improves the positional accuracy between an electrode and a reflective layer.

  Group III nitride semiconductor light-emitting devices include a face-up type light-emitting device that extracts light from a semiconductor layer on the opposite side of the substrate and a flip-chip type light-emitting device that extracts light from the substrate side. Among these light emitting elements, there are those in which electrodes are stretched around in a comb shape. This is because the current is sufficiently diffused in the light emitting surface to improve the amount of emitted light.

  For example, Patent Document 1 discloses a light-emitting element (2) having a p-electrode (90) for bonding that includes a comb-like extension region (904) and a bonding region (903) (Patent Document 1). Paragraphs [0052]-[0082] and FIGS. 7 and 8). The p-electrode for bonding (90) and the n-electrode for bonding (94) easily absorb light emitted from the light emitting layer (25) (paragraph [0067] of Patent Document 1). However, the reflective film (92) in the insulating layer (40) reflects most of the light directed to the bonding p-electrode (90) and the bonding n-electrode (94). Thus, it is described that by reflecting light, absorption of light emitted from the light emitting layer (25) is suppressed, and light extraction efficiency of the light emitting element (2) is improved.

JP 2011-192960 A

  The p-electrode for bonding (90) and the n-electrode for bonding (94) as referred to in Patent Document 1, and the reflective film (92) formed thereunder along these shapes, of course, It is preferable to form with high positional accuracy. If the positional accuracy is low, the degree of reflection varies depending on the light emitting element. Or the luminous efficiency of a light emitting element falls.

  The technique of this specification has been made to solve the problems of the conventional techniques described above. That is, the object is to provide a method for manufacturing a group III nitride semiconductor light-emitting device in which the positional accuracy between the comb-shaped wiring electrode and the reflective layer along the wiring electrode is improved. It is.

  A method for manufacturing a group III nitride semiconductor light-emitting device according to the first aspect includes a first semiconductor layer forming step of forming a first semiconductor layer of a first conductivity type on a substrate, A light emitting layer forming step of forming a light emitting layer on the light emitting layer, a second semiconductor layer forming step of forming a second semiconductor layer of the second conductivity type on the light emitting layer, and a first semiconductor layer on the side of the second semiconductor layer. A first semiconductor layer exposing step for exposing a part of the semiconductor layer, a first contact electrode electrically connected to the first semiconductor layer, and an electrical connection to the second semiconductor layer A contact electrode forming step of forming a second contact electrode, a first insulating layer forming step of forming a first insulating layer on the first contact electrode and the second contact electrode, and a first insulating layer Forming a reflective layer on the reflective layer; and a second insulating layer on the reflective layer. A second insulating layer forming step for forming an edge layer; and a portion of the second insulating layer, the reflective layer, and the first insulating layer are removed to expose the first contact electrode and the second contact electrode A contact electrode exposing step, a wiring electrode forming step of forming a first wiring electrode on the exposed first contact electrode and forming a second wiring electrode on the exposed second contact electrode; A second insulating layer shaping step for arranging the second insulating layer in a shape along the first wiring electrode and the second wiring electrode; and a reflecting layer in a shape along the first wiring electrode and the second wiring electrode. A reflecting layer shaping step for shaping. In the reflective layer forming step, one or more metal layers including at least an Al layer are formed. In the wiring electrode formation step, a first exposed portion where the second insulating layer is exposed without being covered with the first wiring electrode and the second wiring electrode, and the first wiring electrode and the second wiring electrode And a first unexposed portion where the second insulating layer is not exposed. In the second insulating layer shaping step, the first exposed portion is etched using the first wiring electrode and the second wiring electrode as a mask, and a part of the Al layer of the reflective layer is exposed to expose the second exposed portion. In addition, the remaining portion of the Al layer of the reflective layer is not exposed to be a second non-exposed portion. In the reflective layer shaping step, the second exposed portion is etched using the first wiring electrode and the second wiring electrode as a mask to remove the second exposed portion and leave the second unexposed portion.

  In this method for manufacturing a group III nitride semiconductor light emitting device, the first reflective layer and the second reflective layer are formed by performing etching using the first wiring electrode and the second wiring electrode as a mask. Therefore, the positional accuracy between the first reflective layer and the second reflective layer and the first wiring electrode and the second wiring electrode is very high. Therefore, the yield of semiconductor light emitting devices is high. Further, a photolithography process for adjusting the shape of the reflective layer can be omitted. That is, the productivity of this manufacturing method is high.

  In the Group III nitride semiconductor light-emitting device manufacturing method according to the second aspect, the contact electrode exposure step includes a first removal step of removing the second insulating layer by dry etching, and a removal of the reflective layer by wet etching. A second removal step; and a third removal step of removing the first insulating layer by dry etching and exposing the first contact electrode and the second contact electrode. In the second removal step, the Al layer of the reflective layer is side-etched using an alkaline aqueous solution.

  In the method for manufacturing a group III nitride semiconductor light emitting device according to the third aspect, in the third removal step, at least a part of the Al layer of the reflective layer is oxidized by using an etching gas containing oxygen gas.

  In the group III nitride semiconductor light-emitting device manufacturing method according to the fourth aspect, the Al layer of the reflective layer is used as an etch stop layer in the first removal step.

  In the present specification, there is provided a method for manufacturing a group III nitride semiconductor light emitting device in which the positional accuracy between a comb-shaped wiring electrode and a reflective layer formed along the wiring electrode is improved.

It is a schematic block diagram which shows the structure of the light emitting element in embodiment. It is sectional drawing which shows the II-II cross section of FIG. It is FIG. (1) for demonstrating the manufacturing method of the light emitting element in embodiment. It is FIG. (2) for demonstrating the manufacturing method of the light emitting element in embodiment. It is FIG. (3) for demonstrating the manufacturing method of the light emitting element in embodiment. It is FIG. (4) for demonstrating the manufacturing method of the light emitting element in embodiment. It is FIG. (5) for demonstrating the manufacturing method of the light emitting element in embodiment. It is FIG. (6) for demonstrating the manufacturing method of the light emitting element in embodiment. It is FIG. (7) for demonstrating the manufacturing method of the light emitting element in embodiment. It is FIG. (8) for demonstrating the manufacturing method of the light emitting element in embodiment. It is FIG. (9) for demonstrating the manufacturing method of the light emitting element in embodiment.

  Hereinafter, specific embodiments will be described with reference to the drawings, taking a semiconductor light emitting element and a manufacturing method thereof as examples. However, it is not limited to these embodiments. Moreover, the laminated structure and electrode structure of each layer of the semiconductor light emitting element described later are examples. Of course, a laminated structure different from that of the embodiment may be used. And the thickness of each layer in each figure is shown conceptually and does not indicate the actual thickness.

1. Semiconductor Light Emitting Element FIG. 1 is a plan view showing a light emitting element 100 of the present embodiment. The light emitting element 100 is a face-up type semiconductor light emitting element. The light emitting element 100 has a plurality of semiconductor layers made of a group III nitride semiconductor. As shown in FIG. 1, the light emitting element 100 has a comb-like electrode structure.

  FIG. 2 is a cross-sectional view showing a II-II cross section of FIG. As shown in FIG. 2, the light-emitting element 100 includes a substrate 110, an n-type semiconductor layer 120, a light-emitting layer 130, a p-type semiconductor layer 140, a first insulating layer I1, an n-side reflective layer RN1, n-side insulating layer IN1, n-contact electrode Nc, n-electrode N1, p-side reflective layer RP1, p-side insulating layer IP1, transparent electrode TE1, p-contact electrode Pc, p-electrode P1, and protective film F1. Here, the n-type semiconductor layer 120 is a first semiconductor layer of a first conductivity type. The p-type semiconductor layer 140 is a second semiconductor layer of the second conductivity type.

  As shown in FIG. 2, on the main surface of the substrate 110, an n-type semiconductor layer 120, a light emitting layer 130, and a p-type semiconductor layer 140 are formed in this order. The transparent electrode TE1 is formed on the p-type semiconductor layer 140. The p contact electrode Pc is formed on a part of the transparent electrode TE1. The p electrode P1 is formed on the p contact electrode Pc. The n contact electrode Nc is formed on a part of the n-type semiconductor layer 120. The n electrode N1 is formed on the n contact electrode Nc.

  A first insulating layer I1 is formed on the remaining portion of the transparent electrode TE1 and the remaining portion of the n-type semiconductor layer 120. An n-side reflective layer RN1 and a p-side reflective layer RP1 are formed on part of the first insulating layer I1. An n-side insulating layer IN1 is formed on the n-side reflective layer RN1. A p-side insulating layer IP1 is formed on the p-side reflective layer RP1.

  The n electrode N1 is electrically connected to the n-type semiconductor layer 120. The n electrode N1 has an n wiring electrode N1a and an n pad electrode portion N1b. The n wiring electrode N1a is an electrode portion having a comb-like wiring shape. The n pad electrode portion N1b is a first pad electrode portion that is electrically connected to an external electrode of the element. The n pad electrode portion N1b is exposed from the protective film F1.

  The p electrode P1 is electrically connected to the p-type semiconductor layer 140. The p electrode P1 includes a p wiring electrode P1a and a p pad electrode portion P1b. The p wiring electrode P1a is an electrode portion having a comb-like wiring shape. The p pad electrode portion P1b is a first pad electrode portion that is electrically connected to an external electrode of the element. The p pad electrode portion P1b is exposed from the protective film F1.

  The substrate 110 is a growth substrate for forming each of the semiconductor layers on the main surface by MOCVD. And it is good for the main surface to be uneven | corrugated. The material of the substrate 110 is sapphire. In addition to sapphire, materials such as SiC, ZnO, Si, GaN, and AlN may be used.

  The n-type semiconductor layer 120 is formed on the substrate 110. A buffer layer may be provided between the substrate 110 and the n-type semiconductor layer 120. The n-type semiconductor layer 120 is in contact with the n-contact electrode Nc. As described above, the n-type semiconductor layer 120 is electrically connected to the n-electrode N1.

  The light emitting layer 130 is a layer that emits light by recombination of electrons and holes. The light emitting layer 130 is formed on the n-type semiconductor layer 120. The light emitting layer 130 has at least a well layer and a barrier layer. For example, an InGaN layer or a GaN layer can be used as the well layer. As the barrier layer, for example, a GaN layer or an AlGaN layer can be used. These are examples, and other AlInGaN layers may be used.

  The p-type semiconductor layer 140 is formed on the light emitting layer 130. The p-type semiconductor layer 140 is in contact with the transparent electrode TE1. That is, the p-type semiconductor layer 140 is electrically connected to the p-electrode P1 via the transparent electrode TE1 and the p-contact electrode Pc.

  The transparent electrode TE1 is an electrode layer that is electrically connected to the p-type semiconductor layer 140 and transmits light. The material of the transparent electrode TE1 is IZO.

  The n-side reflective layer RN1 and the p-side reflective layer RP1 are Al layers. Alternatively, it is one or more metal layers including at least an Al layer.

2. Manufacturing Method of Semiconductor Light-Emitting Element Here, a manufacturing method of the light-emitting element 100 according to this embodiment will be described. The manufacturing method includes a first semiconductor layer forming step (n-type semiconductor layer forming step), a light emitting layer forming step, a second semiconductor layer forming step (p-type semiconductor layer forming step), and a first semiconductor layer. An exposure step (n-type semiconductor layer exposure step), a transparent electrode formation step, a contact electrode formation step, a first insulation layer formation step, a reflection layer formation step, a second insulation layer formation step, and a contact electrode An exposure step, a wiring electrode formation step, a second insulating layer shaping step, and a reflective layer shaping step.

In the present embodiment, crystals of each semiconductor layer are epitaxially grown by metal organic chemical vapor deposition (MOCVD). Examples of the carrier gas used here include hydrogen (H ₂ ), nitrogen (N ₂ ), or a mixed gas of hydrogen and nitrogen (H ₂ + N ₂ ). Any of these may be used in each step described later unless otherwise specified. Ammonia gas (NH ₃ ) is used as a nitrogen source. Trimethylgallium (Ga (CH ₃ ) ₃ : “TMG”) is used as the Ga source. Trimethylindium (In (CH ₃ ) ₃ : “TMI”) is used as the In source. Trimethylaluminum (Al (CH ₃ ) ₃ : “TMA”) is used as the Al source. Silane (SiH ₄ ) is used as the n-type dopant gas. Cyclopentadienyl magnesium (Mg (C ₅ H ₅ ) ₂ ) is used as the p-type dopant gas.

2-1. First semiconductor layer forming step (n-type semiconductor layer forming step)
First, the substrate 110 is cleaned using hydrogen gas. Next, the n-type semiconductor layer 120 is formed on the main surface of the substrate 110. A buffer layer may be formed before the n-type semiconductor layer 120 is formed. The substrate temperature at this time is in the range of 700 ° C. or more and 1200 ° C. or less.

2-2. Next, the light emitting layer 130 is formed on the n-type semiconductor layer 120. For example, an InGaN layer, a GaN layer, and an AlGaN layer are repeatedly stacked. The substrate temperature at this time is set in the range of 700 ° C. or higher and 900 ° C. or lower.

2-3. Second semiconductor layer forming step (p-type semiconductor layer forming step)
Next, the p-type semiconductor layer 140 is formed on the light emitting layer 130. The substrate temperature at this time is in the range of 800 ° C. or higher and 1200 ° C. or lower. The outermost layer of the p-type semiconductor layer 140 is a p-type contact layer (see FIG. 3).

2-4. Second semiconductor layer exposure step (n-type semiconductor layer exposure step)
Next, the n-type semiconductor layer 120 is partially exposed across a part of the semiconductor layer from the p-type semiconductor layer 140 side by laser or etching. This exposed portion is a portion where the n wiring electrode N1a is formed. Thereby, a part of the n-type semiconductor layer 120 can be exposed to the p-type semiconductor layer 140 side.

2-5. Transparent Electrode Formation Step Next, the transparent electrode TE1 is formed on a part of the p-type semiconductor layer 140. Therefore, a transparent electrode is uniformly formed on the p-type semiconductor layer 140 by sputtering. Patterning is performed by photolithography. Then, the region for exposing the n-type semiconductor layer 120 in the transparent electrode is removed by wet etching or the like. After that, heat treatment may be performed. Thereby, the transparent electrode TE1 can be formed (see FIG. 3).

2-6. Contact Electrode Formation Step Next, a plurality of n contact electrodes Nc are formed on the n-type semiconductor layer 120. That is, the n-contact electrode Nc that is electrically connected to the n-type semiconductor layer 120 is formed. A plurality of p contact electrodes Pc are formed on the transparent electrode TE1. That is, the p-contact electrode Pc that is electrically connected to the p-type semiconductor layer 140 is formed.

2-7. First Insulating Layer Formation Step Next, as shown in FIG. 3, the first insulating layer Nc, the p-contact electrode Pc, the remaining portion of the n-type semiconductor layer 120, and the remaining portion of the transparent electrode TE1 are formed by CVD. The insulating layer I1a is uniformly formed. The film thickness of the first insulating layer I1a is in the range of 100 nm to 1000 nm. If the film thickness is 100 nm or more, it is easy to completely cover the semiconductor layer and the like regardless of the step on the semiconductor layer side. An example of the material of the first insulating layer I1a is SiO ₂ .

2-8. Next, as shown in FIG. 3, the reflective layer R1a is uniformly formed on the first insulating layer I1a by vapor deposition, as shown in FIG. An Al layer is formed as the reflective layer R1a. Alternatively, one or more metal layers including at least an Al layer are formed as the reflective layer R1a. Here, the thickness of the Al layer in the reflective layer R1a needs to be sufficiently thick. There are two reasons for ensuring sufficient reflectivity by the Al layer and for providing an etch stop function to be described later. The thickness of the Al layer in the reflective layer R1a is 100 nm or more.

2-9. Second Insulating Layer Formation Step Next, as shown in FIG. 4, the second insulating layer I2a is uniformly formed on the reflective layer R1a by the CVD method. An example of the material of the second insulating layer I2a is SiO ₂ . The thickness of the second insulating layer I2a is preferably 10 nm to 200 nm. This is to suppress variation in the amount of removal in the surface when the portion is later removed by etching.

2-10. Contact Electrode Exposing Step Next, as shown in FIG. 5, a trench for exposing the n contact electrode Nc and the p contact electrode Pc is formed. For this purpose, a part of the second insulating layer I2a, the reflective layer R1a, and the first insulating layer I1a is removed. The contact electrode exposure step includes a first removal step of removing a part of the second insulating layer I2a by dry etching, a second removal step of removing a part of the reflective layer R1a by wet etching, and dry etching. To remove the first insulating layer I1a and expose the n-contact electrode Nc and the p-contact electrode Pc.

2-10-1. First Removal Step For this purpose, a resist is arranged, and a resist pattern K1 is formed by photolithography. The resist pattern K1 has through holes formed at positions corresponding to the n contact electrode Nc and the p contact electrode Pc. Then, dry etching is performed. At that time, dry etching is performed using fluorine-based plasma. For example, etching is performed using a plasma of a mixed gas containing CF ₄ and O ₂ . At this time, the Al layer of the reflective layer R1a is used as an etch stop layer. Thereby, a non-through hole in which the reflective layer R1a is the bottom surface is formed. That is, the reflective layer R1a is exposed.

2-10-2. Second removal step Thereafter, wet etching is performed. At that time, etching is performed using an alkaline aqueous solution such as a tetramethylammonium hydroxide aqueous solution (TMAH). Thereby, the reflective layer R1a is etched. Thereby, the alkaline aqueous solution removes the exposed portion of the reflective layer R1a by etching. After that, the alkaline aqueous solution side-etches the side portions R1b and R1c of the Al layer of the reflective layer R1a (see FIG. 5). Therefore, the degree of side etching of the Al layer can be controlled by adjusting the wet etching time. At this stage, the first insulating layer I1a is exposed at the bottom of the recess.

2-10-3. Third removal step Then, dry etching is performed again. At that time, etching is performed using a plasma of a mixed gas containing CF ₄ and O ₂ . Alternatively, other gas for exposing the first insulating layer I1a may be used. By this dry etching, a groove exposing the n contact electrode Nc and the p contact electrode Pc is formed. Then, as shown in FIG. 6, the resist is removed.

  Note that in this step, an etching gas containing oxygen gas may be used. Thereby, at least a part of the Al layer of the reflective layer R1a can be oxidized. Specifically, the side portions R1b and R1c of the Al layer of the reflective layer R1a. Thereby, the electrical resistivity of the Al layer in the oxidized part increases. Thereby, it can suppress more that an electric current flows into Al layer of reflective layer R1a.

2-11. Wiring electrode formation process (electrode formation process)
Next, as shown in FIG. 7, an n wiring electrode N1a and an n pad electrode portion N1b are formed on the exposed n contact electrode Nc. Further, the p wiring electrode P1a and the p pad electrode portion P1b are formed on the exposed p contact electrode Pc.

  For this purpose, first, a photoresist is applied on the entire surface of the second insulating layer I2a from the state shown in FIG. Then, using the photolithography technique, the resist at the formation scheduled places such as the n wiring electrode N1a and the p wiring electrode P1a is removed. Thereafter, an electrode material is formed by evaporation on the resist and the exposed portion of the second insulating layer I2a.

  For example, Ti having a thickness of 50 nm, Au having a thickness of 1500 nm, and Al having a thickness of 10 nm are stacked in this order from the n-contact electrode Nc side. The film thickness of Ti is in the range of 10 nm to 100 nm. The film thickness of Au is in the range of not less than 1000 nm and not more than 1500 nm. The film thickness of Al is in the range of 10 nm to 100 nm. Then, for example, the resist is removed by a tape lift-off method.

  Thus, the first exposed portion J1a where the second insulating layer I2a is exposed without being covered by the n wiring electrode Nc and the p wiring electrode Pc, and the n wiring electrode Nc and the p wiring electrode Pc are covered. A first unexposed portion J1b in which the second insulating layer I2a is not exposed is formed.

2-12. Second insulating layer shaping process (dry etching process)
Next, as shown in FIG. 8, dry etching is performed to arrange the second insulating layer I2a into a shape along the n wiring electrode N1a and the p wiring electrode P1a. At this time, the n wiring electrode N1a and the p wiring electrode P1a are used as a mask. Thereby, the second insulating layer I2a shown in FIG. 7 is partially etched. Then, the n-side insulating layer IN1 and the p-side insulating layer IP1 located under the n-wiring electrode N1a and the p-wiring electrode P1a remain without being etched. That is, by this etching, the second insulating layer I2a becomes the n-side insulating layer IN1 and the p-side insulating layer IP1.

  Here, as described above, when an electrode structure in which an Al layer is laminated on an Au layer is used, the Al layer functions as an etch stop layer. Further, when the RF power, the etching time, and the like are adjusted, the etching can be stopped more suitably in the Al layer.

  That is, the first exposed portion J1a is etched using the n electrode N1 and the p electrode P1 as a mask to expose a part of the Al layer of the reflective layer R1a to form the second exposed portion J2a and the Al layer of the reflective layer R1a The remaining portion is not exposed and is defined as a second non-exposed portion J2b.

2-13. Reflective layer shaping process (wet etching process)
Next, as shown in FIG. 9, wet etching is performed to arrange the reflective layer R1a into a shape along the n wiring electrode N1a and the p wiring electrode P1a. Also at this time, the n wiring electrode N1a and the p wiring electrode P1a are used as a mask. Here, the alkaline aqueous solution used in the contact electrode exposure step may be used. Of course, different types of alkaline aqueous solutions may be used.

  Thereby, the reflective layer R1a can be partially etched. That is, the etching does not proceed at a location immediately below the n wiring electrode N1a. Etching proceeds at a portion not covered with the n wiring electrode N1a. Further, the etching does not proceed at a position immediately below the p wiring electrode P1a. Etching proceeds at a location not covered by the p wiring electrode P1a.

  That is, the second exposed portion J2a is etched using the n-electrode N1 and the p-electrode P1 as a mask to remove the second exposed portion J2a and leave the second unexposed portion J2b on the substrate 110 side.

2-14. Next, as shown in FIG. 10, the semiconductor layer and the metal layer thereon are covered with a protective film F1. Then, as shown in FIG. 11, the n pad electrode portion N1b and the p pad electrode portion P1b are exposed using the resist K2. Then, the resist K2 is removed.

2-15. Other Steps In addition to the above steps, other steps such as a heat treatment step may be performed. Thus, the light emitting device 100 of FIG. 1 is manufactured.

3. Effects of the present embodiment 3-1. Positional accuracy of n-side reflective layer and p-side reflective layer In the method of manufacturing the light emitting device 100 of this embodiment, the n wiring electrode N1a and the p wiring electrode P1a are used as a mask. Therefore, the region where the n-side reflective layer RN1 is projected onto the substrate 110 overlaps with the region where the n-wiring electrode N1a is projected onto the substrate 110. The region where the p-side reflective layer RP1 is projected onto the substrate 110 overlaps with the region where the p-wiring electrode P1a is projected onto the substrate 110. Therefore, alignment of the n-side reflective layer RN1 and the p-side reflective layer RP1 with the n-wiring electrode N1a and the p-wiring electrode P1a can be performed with very high accuracy.

  As described above, since the alignment can be performed in a self-aligning manner, the positional accuracy between the n-side reflective layer RN1 and the p-side reflective layer RP1, and the n-wiring electrode N1a and the p-wiring electrode P1a is high. . There is almost no variation in the brightness of the light emitting element 100 due to the positional accuracy of the reflective layer. Therefore, the yield of the light emitting element 100 is high.

3-2. In the present embodiment, the n-side reflective layer RN1 and the p-side reflective layer RP1 are formed by performing etching using the n wiring electrode N1a and the p wiring electrode P1a as a mask. Conventionally, the n-side reflective layer and the p-side reflective layer are formed by performing a photolithography process and etching on the reflective layer R1a after the process of FIG. In the present embodiment, patterning for forming the shapes of the n-side reflective layer RN1 and the p-side reflective layer RP1 is performed using the n wiring electrode N1a and the p wiring electrode P1a as a mask. Therefore, it is not necessary to perform a photolithography process. Therefore, the cycle time of the present embodiment is shorter than the conventional one.

4). Modified example 4-1. Flip chip type, substrate lift-off type In this embodiment, the face-up type light emitting device 100 is applied. However, it is of course applicable to other semiconductor light emitting elements. For example, the present invention can naturally be applied to a flip chip having a light extraction surface on the substrate side or a substrate lift-off type semiconductor light emitting device from which a growth substrate is removed.

4-2. In the present embodiment, the material of the transparent electrode TE1 is IZO. However, transparent conductive oxides such as ITO, ICO, ZnO, TiO ₂ , NbTiO ₂ , and TaTiO ₂ can be used in addition to IZO.

4-3. Conductive Type In this embodiment, the first conductive type is n-type and the second conductive type is p-type. However, the reverse may be possible. That is, the first conductivity type may be p-type and the second conductivity type may be n-type.

5. Summary of the present embodiment As described in detail above, in the method for manufacturing the light emitting device 100 of the present embodiment, the n-side reflective layer RN1 and The p-side reflection layer RP1 is formed. Therefore, the positional accuracy between the n-side reflective layer RN1 and the p-side reflective layer RP1 and the n-wiring electrode N1a and the p-wiring electrode P1a is very high.

  In the present embodiment, the n-side reflective layer RN1 and the p-side reflective layer RP1 are formed by performing etching using the n-wiring electrode N1a and the p-wiring electrode P1a as a mask. Therefore, it is not necessary to separately perform a photolithography process for forming a resist mask for adjusting the shape of the reflective layer. That is, in the method for manufacturing the light emitting device 100 of the present embodiment, the cycle time is shorter than the conventional one.

  The embodiment described above is merely an example. Therefore, naturally, various improvements and modifications can be made without departing from the scope of the invention. The semiconductor stacked structure is not necessarily limited to that shown in the figure. You may select arbitrarily, such as a laminated structure and a film thickness of a semiconductor. Moreover, it is not restricted to a metal organic chemical vapor deposition method (MOCVD method). The semiconductor layer may be formed using other vapor phase epitaxy methods and liquid phase epitaxy methods.

DESCRIPTION OF SYMBOLS 100 ... Light emitting element 110 ... Substrate 120 ... N type semiconductor layer 130 ... Light emitting layer 140 ... P type semiconductor layer TE1 ... Transparent electrode RN1 ... N side reflection layer RP1 ... P side reflection layer IN1 ... N side insulation layer IP1 ... P side insulation Layer Pc ... p contact electrode P1 ... p electrode P1a ... p wiring electrode P1b ... p pad electrode portion Nc ... n contact electrode N1 ... n electrode N1a ... n wiring electrode N1b ... n pad electrode portion J1a ... first exposed portion J1b ... First unexposed portion J2a ... Second exposed portion J2b ... Second unexposed portion

Claims (4)

A first semiconductor layer forming step of forming a first semiconductor layer of a first conductivity type on a substrate;
A light emitting layer forming step of forming a light emitting layer on the first semiconductor layer;
A second semiconductor layer forming step of forming a second semiconductor layer of a second conductivity type on the light emitting layer;
A first semiconductor layer exposing step of exposing a part of the first semiconductor layer on the second semiconductor layer side;
A contact electrode forming step of forming a first contact electrode electrically connected to the first semiconductor layer and forming a second contact electrode electrically connected to the second semiconductor layer;
A first insulating layer forming step of forming a first insulating layer on the first contact electrode and the second contact electrode;
A reflective layer forming step of forming a reflective layer on the first insulating layer;
A second insulating layer forming step of forming a second insulating layer on the reflective layer;
A contact electrode exposing step of exposing a part of the second insulating layer, the reflective layer, and the first insulating layer to expose the first contact electrode and the second contact electrode;
Forming a first wiring electrode on the exposed first contact electrode and forming a second wiring electrode on the exposed second contact electrode; and
A second insulating layer shaping step of arranging the second insulating layer in a shape along the first wiring electrode and the second wiring electrode;
A reflective layer shaping step of arranging the reflective layer in a shape along the first wiring electrode and the second wiring electrode;
Have
In the reflective layer forming step,
Forming one or more metal layers including at least an Al layer;
In the wiring electrode forming step,
A first exposed portion where the second insulating layer is exposed without being covered by the first wiring electrode and the second wiring electrode; and the first wiring electrode and the second wiring electrode. Forming a first unexposed portion that is covered and does not expose the second insulating layer;
In the second insulating layer shaping step,
Using the first wiring electrode and the second wiring electrode as a mask, the first exposed portion is etched to expose a part of the Al layer of the reflective layer as a second exposed portion, and A second non-exposed portion without exposing the remainder of the Al layer of the reflective layer;
In the reflective layer shaping step,
Etching the second exposed portion using the first wiring electrode and the second wiring electrode as a mask to remove the second exposed portion and leave the second unexposed portion. A method for producing a group III nitride semiconductor light emitting device. In the manufacturing method of the group III nitride semiconductor light-emitting device according to claim 1,
The contact electrode exposing step includes
A first removal step of removing the second insulating layer by dry etching;
A second removal step of removing the reflective layer by wet etching;
A third removal step of removing the first insulating layer by dry etching and exposing the first contact electrode and the second contact electrode;
Have
In the second removal step,
A method for producing a group III nitride semiconductor light-emitting device, wherein the Al layer of the reflective layer is side-etched using an alkaline aqueous solution. In the manufacturing method of the group III nitride semiconductor light-emitting device according to claim 2,
In the third removal step,
A method for manufacturing a group III nitride semiconductor light-emitting device, wherein at least a part of the Al layer of the reflective layer is oxidized by using an etching gas containing oxygen gas. In the manufacturing method of the group III nitride semiconductor light-emitting device according to claim 2 or 3,
In the first removal step,
A method of manufacturing a group III nitride semiconductor light emitting device, wherein the Al layer of the reflective layer is an etch stop layer.

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