JP6201331B2 - Synchronous serial interface circuit - Google Patents

Description

  The present invention relates to a synchronous serial interface circuit, and more particularly to a synchronous serial interface circuit having a plurality of channels.

  Synchronous serial communication is serial communication in which data is transmitted or received in synchronization with a clock. A synchronous serial interface (hereinafter abbreviated as “SSI”) is widely used as a standard interface between a master and a slave used for industrial purposes.

  For example, Japanese Patent Laid-Open No. 5-63754 (Patent Document 1) discloses a signal transmission device that serially transmits an NRZ (Non Return to Zero) signal sequence from a transmission circuit to a reception circuit in synchronization with a clock signal sequence. This signal transmission device performs horizontal and vertical parity checks. The signal transmission device further generates a signal indicating detection of the header and a reception error signal or a reception end signal.

JP-A-5-63754

  In SSI, an SSI interface circuit (master) serving as an interface with a host device outputs a clock to an SSI compatible device (slave). The SSI-compatible device is, for example, an absolute encoder or a distance measuring sensor. The slave transmits data to the master in synchronization with the clock. Therefore, in the case of data acquisition using SSI, the time required for one data acquisition is determined by the clock cycle and the size (number of bits) of the data. For this reason, the update of data is also repeated at intervals equal to or longer than the time required for data acquisition.

  In the implementation of SSI, it is conceivable to use a functional module (for example, a serial communication module) for communication control. SSI is a simple data exchange means. Therefore, in order to reduce the cost of equipment, it is conceivable to realize SSI using a general-purpose input / output port.

  However, when each of a plurality of general-purpose input / output ports is used as an SSI channel, it is necessary to execute transmission of a synchronous clock and acquisition of data for each channel. When data acquisition is executed in series (that is, update of each channel is executed in order), in order to update a certain channel, a time interval determined by (update interval for one channel) × (number of channels) Is required. Therefore, as the number of channels increases, the update interval for one channel becomes longer. Furthermore, the time required to update all the channels also becomes longer.

  On the other hand, when serial communication modules are prepared for each channel in order to shorten the time, the same number of communication modules as the number of channels are required. Therefore, there is a problem that the number of communication modules increases.

  An object of the present invention is to provide a synchronous serial interface circuit capable of realizing SSI communication of a plurality of channels without increasing the data update interval per channel by a small number of communication modules.

  In one aspect, the present invention is a synchronous serial interface circuit including a plurality of channels. Each channel outputs a synchronization clock and receives data sent to each channel in synchronization with the output synchronization clock. At the start of data reception, the plurality of channels simultaneously lower the synchronous clock.

  Preferably, each of the plurality of channels sets the frequency of the synchronization clock during a period from when the synchronization clock is lowered to when the synchronization clock is raised at the start of data reception.

  Preferably, the plurality of channels can set the frequency of the synchronous clock independently of each other.

  Preferably, the synchronous serial interface circuit further includes a storage unit that stores the received data. Each channel has a synchronous clock generator for generating a synchronous clock, a clock controller for operating the synchronous clock generator for a period according to the length of data to be received by the channel, And a DMA control unit for transferring the received data.

  According to the present invention, SSI communication of a plurality of channels can be realized without increasing the data update interval per channel with a small number of communication function modules.

It is the block diagram which showed the schematic structure of the motion control system provided with the interface circuit which concerns on embodiment of this invention. It is the figure which showed the example of the connection of the SSI input unit which has two channels, and an SSI encoder. It is the figure which demonstrated typically the data transmission which concerns on embodiment of this invention. It is the timing chart which showed an example of the form which receives data by a some channel. It is the block diagram which showed roughly the function of the SSI input unit which concerns on embodiment of this invention. It is a timing diagram which shows an example of operation | movement of the SSI input unit which concerns on embodiment of this invention. It is a timing diagram which shows the other example of operation | movement of the SSI input unit which concerns on embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, the same parts are denoted by the same reference numerals, and detailed description thereof will not be repeated.

  FIG. 1 is a block diagram showing a schematic configuration of a motion control system including an interface circuit according to an embodiment of the present invention. Referring to FIG. 1, motion control system 1 includes a control unit 2, a communication unit 3, a position interface unit 4, a motor driver 5, a motor 6, an encoder 7A, and an SSI encoder 7B.

  The communication unit 3 is connected to the control unit 2 via a network such as a LAN (Local Area Network). As an example, the communication unit 3 is configured to communicate with the control unit 2 using EtherCAT (registered trademark) or the like.

  The control unit 2 executes positioning control or motion control of the motor driver 5 in cooperation with the position interface unit 4. The control unit 2 is composed of, for example, a PLC (Programmable Logic Controller).

  The position interface unit 4 is a unit having an input / output processing function of position data for performing positioning control or motion control. The position interface unit 4 is connected to the communication unit 3 and periodically communicates with the control unit 2 via the communication unit 3 and the network. From the position interface unit 4 to the control unit 2, the count values of the encoders 7A and 7B are sent. Conversely, a position command or a speed command is sent from the control unit 2 to the position interface unit 4.

  The position interface unit 4 includes a pulse output unit 4A, a pulse input unit 4B, and an SSI input unit 4C. The control unit 2 performs a motion calculation at regular intervals, and generates a command value for the pulse output unit 4A. The command value is sent to the pulse output unit 4A every predetermined communication cycle. The pulse output unit 4 </ b> A generates a pulse having a pulse number and a frequency according to the command value and outputs the pulse to the motor driver 5. The motor driver 5 drives the motor 6 according to the pulse from the pulse output unit 4A.

  Encoder 7A and SSI encoder 7B detect the rotation of motor 6. The pulse input unit 4B receives the pulses output from the encoder 7A and counts the pulses. The SSI encoder 7B is an absolute encoder that supports the SSI interface. The SSI input unit 4C implements a “synchronous serial interface circuit” according to the present invention. Specifically, the SSI input unit 4C outputs a synchronous clock to the SSI encoder 7B. The SSI encoder 7B outputs a pulse in synchronization with the clock. The SSI input unit 4C receives data from the SSI encoder 7B. The count value of the pulse input unit 4B and the data received by the SSI input unit 4C are transmitted to the control unit 2 at a predetermined communication cycle.

  In the configuration shown in FIG. 1, an SSI encoder 7B (absolute encoder) is connected to the SSI input unit 4C. However, in addition to the absolute encoder, a sensor corresponding to the SSI interface can be connected to the SSI input unit 4C. As an example of such a sensor, for example, a distance measuring sensor corresponding to an SSI interface can be cited.

  In the present embodiment, the SSI input unit 4C has a function as a master unit, and the SSI encoder 7B has a function as a slave unit. The SSI input unit 4C according to the embodiment of the present invention has a plurality of (for example, two) channels. Hereinafter, in order to simplify the description, the number of channels of the SSI input unit 4C is assumed to be two.

  FIG. 2 is a diagram illustrating an example of connection between an SSI input unit 4C having two channels and an SSI encoder. Referring to FIG. 2, SSI input unit 4C has two channels (indicated as “1CH” and “2CH” in FIG. 2). The synchronous clock CLK1 is transmitted from one channel (1CH) to the SSI encoder 7B1. The SSI encoder 7B1 transmits data D1 to the SSI input unit 4C in synchronization with the synchronous clock CLK1.

  Similarly, the synchronous clock CLK2 is transmitted from the other channel (2CH) to the SSI encoder 7B2. The SSI encoder 7B2 transmits data D2 to the SSI input unit 4C in synchronization with the synchronous clock CLK2. In many cases, a twisted pair line is used for clock transmission and data transmission.

  In the configuration shown in FIG. 2, all of the two channels of the SSI input unit 4C are used. However, it is not limited in this way. Only one channel may be used.

  FIG. 3 is a diagram schematically illustrating data transmission according to the embodiment of the present invention. Referring to FIG. 3, before the time t1, both the synchronous clock and the data are at the H (logic high) level.

  At time t1, the SSI input unit 4C falls the synchronization clock from the H level to the L (logic low) level. As a result, data transfer from the SSI encoder 7B (see FIG. 1) is started. Thereafter, data is output bit by bit from the SSI encoder 7B in synchronization with the rising or falling edge of the synchronous clock (whichever is acceptable). The SSI input unit 4C receives data bit by bit. That is, serial communication is performed between the SSI input unit 4C and the SSI encoder 7B. When the data transfer ends at time t2, both the synchronous clock and the data become H (logic high) level.

  Here, as shown in FIG. 2, the SSI input unit 4C receives data from the two SSI encoders 7B1 and 7B2. For example, as shown in FIG. 4, the SSI input unit 4C acquires the data D1 from the SSI encoder 7B1 on the first channel (1CH), and then from the SSI encoder 7B2 on the second channel (2CH). A method for obtaining the data D2 is conceivable. However, since data acquisition is performed in series, the update interval of each channel increases.

  Furthermore, the time at which data is generated at the SSI encoder 7B1 is different from the time at which data is generated at the SSI encoder 7B2. In other words, the detection time differs between the data from the SSI encoder 7B1 and the data from the SSI encoder 7B2. Depending on the system, it may be required that the detection times of a plurality of SSI encoders be the same.

  As one proposal for solving these problems, it is conceivable that each of a plurality of channels receives a plurality of data in parallel. In order to realize parallel data reception, it is conceivable to provide a plurality of SSI input units. However, since the same number of SSI input units as the number of channels is required, the number of SSI input units increases.

  In order to reduce the number of SSI input units, it is conceivable to provide a plurality of channels in one SSI input unit. In this case, for example, it is conceivable to distribute the clock to a plurality of channels within the SSI input unit. However, the data transmission rate is determined by the clock frequency. For this reason, it is difficult to vary the data transmission rate for each channel.

  According to this embodiment, the SSI input unit 4C can achieve different data transfer rates for each channel. Furthermore, the SSI input unit 4C can synchronize the start of data transfer between the two channels. That is, the detection result at the same time can be received from the SSI encoder 7B1 and the SSI encoder 7B2. Such processing will be described below.

  FIG. 5 is a block diagram schematically showing functions of the SSI input unit 4C according to the embodiment of the present invention. Referring to FIG. 5, SSI input unit 4 </ b> C includes a trigger generation unit 11, data reception units 12 and 13, a storage unit 14, and an I / O unit 15.

  The trigger generator 11 generates the trigger signal Str at a predetermined cycle, for example. This cycle is determined, for example, according to the communication cycle between the control unit 2 (see FIG. 1) and the position interface unit 4 (see FIG. 1). The trigger signal Str is sent to the data receiving units 12 and 13.

  The data receiver 12 outputs a synchronous clock CLK1 and receives data D1 from the SSI encoder 7B1 (see FIG. 2). The data receiver 12 includes a synchronous clock generator 21A, a clock controller 22A, and a DMA (Dynamic Access Memory) controller (DMAC) 24A.

  The synchronous clock generation unit 21A generates a pulse train. This pulse train is output from the synchronous clock generator 21A as the synchronous clock CLK1. For example, the synchronous clock generation unit 21A can be realized by a timer or a counter.

  The clock control unit 22A controls the generation and stop of the synchronous clock CLK1 by controlling the synchronous clock generation unit 21A in response to the trigger signal Str. Note that the clock control unit 22A may read the set value of the period of the synchronous clock CLK1 stored in the storage unit 14 and load the set value into the synchronous clock generation unit 21A.

  The DMAC 23A acquires the data D1 bit by bit in synchronization with the clock generated by the synchronous clock generation unit 21A, and transmits the bit to the storage unit 14. By using the DMAC, it is possible to cope with high-speed (for example, MHz order) data transmission.

  Data receiving unit 13 is different from data receiving unit 12 in that it transmits synchronous clock CLK2 instead of synchronous clock CLK1 and receives data D2 instead of data D1. The data receiver 13 includes a synchronous clock generator 21B, a clock controller 22B, and a DMAC 24B. Since the function of each part of data receiving unit 13 is the same as the function of the corresponding part of data receiving unit 12, the following detailed description will not be repeated.

  The storage unit 14 stores setting values related to the frequencies of the synchronous clocks CLK1 and CLK2, and setting values related to the number of pulses of the synchronous clock. The storage unit 14 may be either a volatile memory or a nonvolatile memory. For example, if the storage unit 14 is a volatile memory, when the SSI input unit 4C is activated, it is transferred from the control unit 2 to the storage unit 14 of the SSI input unit 4C via the network and the communication unit 3 (both see FIG. 1). The set value is input.

  For example, the I / O unit 15 receives a command from the control unit 2 illustrated in FIG. 1 and transmits the acquired data D1 and D2 to the control unit 2. The SSI input unit 4C may perform appropriate processing on the data D1 and D2 and transmit the processed data to the control unit 2.

  FIG. 5 shows a configuration according to one embodiment, and does not limit the configuration of the SSI input interface. For example, a plurality of functional blocks may be integrated into one. Conversely, one functional block can be divided into a plurality of functional blocks.

  FIG. 6 is a timing chart showing an example of the operation of the SSI input unit 4C according to the embodiment of the present invention. Referring to FIGS. 5 and 6, first, trigger generation unit 11 generates trigger signal Str at time t10. The synchronous clock generators 21A and 21B and the clock controllers 22A and 22B are started in response to the trigger signal Str and change the synchronous clocks CLK1 and CLK2 from H level to L level, respectively. As a result, the synchronous clocks CLK1 and CLK2 fall simultaneously at time t11.

  The frequency of the synchronous clocks CLK1 and CLK2 is set during a period from time t11 to time t12. In this example, the frequencies of the synchronous clocks CLK1 and CLK2 are the same. Therefore, after time t12, the synchronous clocks CLK1 and CLK2 change in the same cycle.

  One bit of data is acquired for each period of the synchronous clock. As shown in FIG. 6, the lengths of the data D1 and D2 are different in this example. That is, the number of bits of the data D1 is 5, and the number of bits of the data D2 is 8. At time t13, the transfer of data D1 (acquisition of data D1 by SSI input unit 4C) ends. The clock control unit 22A turns off the synchronous clock generation unit 21A. Therefore, after time t12, the synchronous clock CLK1 becomes H level. Thereafter, at time t14, the transfer of the data D2 is completed. The clock control unit 22B turns off the synchronous clock generation unit 21B. After time t14, the synchronous clock CLK2 becomes H level.

  Thereafter, at time t15, the trigger generator 11 generates the trigger signal Str again. The synchronous clock generators 21A and 21B and the clock controllers 22A and 22B are started in response to the trigger signal Str and change the synchronous clocks CLK1 and CLK2 from H level to L level, respectively. Therefore, synchronous clocks CLK1 and CLK2 fall at the same time at time t16. Since the transfer of data D1 and D2 after time t21 is the same as the above processing, the following description will not be repeated.

  FIG. 7 is a timing chart showing another example of the operation of the SSI input unit according to the embodiment of the present invention. With reference to FIG. 6 and FIG. 7, the operation of SSI input unit 4C at each of times t20 to t24 corresponds to the operation of SSI input unit 4C at each of times t10 to t14. That is, at time t20, the trigger generator 11 generates the trigger signal Str. Accordingly, synchronous clocks CLK1 and CLK2 fall simultaneously at time t21. For example, according to the signal Str, the synchronous clock generators 21A and 21B are activated and measure a certain time. The time when the time measurement ends is time t21. Then, the frequencies of the synchronous clocks CLK1 and CLK2 are set between time t21 and time t22. In the example shown in FIG. 7, the frequencies of the synchronous clocks CLK1 and CLK2 are different. Specifically, the frequency of the synchronous clock CLK2 is lower than the frequency of the synchronous clock CLK1.

  The SSI encoder 7B requires a certain amount of time to determine data. Therefore, as shown in FIG. 7, synchronous clocks CLK1 and CLK2 are once lowered at time t21. Thereafter, the frequencies of the synchronous clocks CLK1 and CLK2 are set. The synchronous clock generators 21A and 21B output a clock having the set frequency. As described above, the means for generating the clock is not particularly limited, and the clock may be generated by a timer, for example.

  In FIG. 7, for the convenience of illustration, the data D2 is expressed as 4-bit data. However, the number of bits of the data D2 is not limited in this way.

  As described above, according to the embodiment of the present invention, the synchronous clock is simultaneously lowered at the time of data reception on a plurality of channels. Thereby, the start of data transfer can be synchronized between the two channels. That is, the detection result at the same time can be received from the SSI encoder 7B1 and the SSI encoder 7B2.

  Furthermore, according to the embodiment of the present invention, the functional blocks that generate the synchronous clock are independent of each other. Thus, data reception on a plurality of channels can be executed in parallel. Therefore, the data update interval can be shortened in each channel.

  Furthermore, according to the embodiment of the present invention, the frequency of the synchronous clock can be varied among a plurality of channels. As a result, even when the data transmission speed differs between channels, data can be received by one unit. Accordingly, it is possible to suppress an increase in cost due to the use of a method of using a high-function (and therefore expensive) microcomputer or providing a plurality of input units.

  The embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 motion control system, 2 control unit, 3 communication unit, 4 position interface unit, 4A pulse output unit, 4B pulse input unit, 4C SSI input unit, 5 motor driver, 6 motor, 7A encoder, 7B, 7B1, 7B2 SSI encoder , 11 Trigger generating unit, 12, 13 Data receiving unit, 14 Storage unit, 15 I / O unit, 21A, 21B Synchronous clock generating unit, 22A, 22B Clock control unit.

Claims (3)

A synchronous serial interface circuit,
With multiple channels,
Each of the channels outputs a synchronization clock, receives data sent to each of the channels in synchronization with the output synchronization clock,
At start of reception of data, the plurality of channels, the synchronous clock simultaneously Tatsuka up,
Each of the plurality of channels sets the frequency of the synchronization clock during a period from when the synchronization clock is lowered to when the synchronization clock is raised at the start of reception of the data. A synchronous serial interface circuit for simultaneously raising the synchronous clock ; The synchronous serial interface circuit according to claim 1, wherein the plurality of channels can set the frequency of the synchronous clock independently of each other. The synchronous serial interface circuit includes:
A storage unit for storing the received data;
Each said channel is
A synchronous clock generator for generating the synchronous clock;
A clock controller for operating the synchronous clock generator for a period according to the length of data to be received by the channel;
The synchronous serial interface circuit according to claim 1 , further comprising: a DMA control unit that receives the data and transfers the received data to the storage unit.

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