JP6112972B2 - Imaging device - Google Patents

Description

  The present invention relates to an imaging apparatus, and more particularly to an imaging apparatus that records a moving image.

  2. Description of the Related Art Conventionally, an imaging device such as a digital camera that captures a moving image and records it on a recording medium such as a memory card is known (for example, Patent Document 1). In recent years, consumer digital cameras that can take images with a large number of pixels have also appeared.

  When the number of pixels of an image to be captured increases, the amount of data to be processed increases. In particular, during continuous shooting of still images, it is necessary to process image data faster than before. In order to increase the processing capacity of the image data, a processing circuit such as a memory having a large storage capacity and a high-speed access and a microcomputer capable of processing the image data at a higher speed is required.

  However, using such a high-performance memory or microcomputer leads to an increase in circuit scale and an increase in power consumption. A consumer digital camera may not be able to use a high-performance memory or microcomputer because of restrictions on size and cost, or due to a demand for minimizing power consumption.

  Therefore, it is conceivable to provide a plurality of processing circuits and process and record the captured images in parallel by the plurality of processing circuits. Also, when playing back recorded images, an index screen including a list of reduced images (thumbnail) images of the recorded images is displayed, and an image selected by the user from the thumbnail images displayed on the index screen is played back Is common.

JP 2005-101835 A

  When the index screen is displayed, it is necessary to reduce the screen size after reproducing and decoding the image data from the recording medium. Therefore, there is a problem that it takes time to display the index screen. Therefore, when the captured image is stored in the memory and the index screen is displayed, the image data stored in the memory is reduced and displayed, so that the index screen can be displayed quickly after shooting. Conceivable.

  However, as described above, when images recorded by a plurality of processing circuits are stored in a memory, each processing circuit needs to read image data from the memory and generate an index screen. For this reason, it may be time-consuming to display.

  An object of the present invention is to solve such a problem and to provide an imaging apparatus capable of quickly displaying an index screen.

According to an aspect of the present invention, a first processing circuit having an imaging unit, a first CPU, and a first communication unit records image data acquired from the imaging unit in response to a shooting instruction. A second processing circuit that has a first processing circuit that records the acquired image data in a first memory and stores the acquired image data in a first memory, a second CPU, and a second communication means, In response, the image data acquired from the imaging means is recorded on the recording medium, the acquired image data is stored in the second memory, and the image stored in the second memory in response to an index screen display instruction is stored. And a second processing circuit for displaying an index screen of the image data recorded on the recording medium using the data, wherein the first CPU responds to the recording processing of the image data of one screen according to the photographing instruction. The second Transmits image data of one screen to the sense circuit, said second CPU is to store the image data received from the first processing circuit through the second communication means to the second memory An imaging device is provided.

  According to the present invention, it is possible to quickly display an index screen.

1 is a block diagram illustrating a configuration of an imaging device according to an embodiment. 7 is a flowchart showing processing at the time of recording by the processing circuit 200. 5 is a flowchart showing processing at the time of recording by the processing circuit 100. The flowchart which shows the display process of an index screen. 7 is a flowchart showing processing at the time of recording by the processing circuit 200. 5 is a flowchart showing processing at the time of recording by the processing circuit 100. 6 is a flowchart showing continuous shooting speed determination processing executed in a shooting standby state. 6 is a flowchart showing a continuous shooting speed determination process executed during a shooting process. The flowchart which shows the display process of an index screen.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to the following embodiment, It shows only the specific example advantageous for implementation of this invention. Moreover, not all combinations of features described in the following embodiments are indispensable for solving the problems of the present invention.

(First embodiment)
FIG. 1 is a block diagram illustrating an exemplary configuration of an imaging apparatus 500 according to an embodiment of the present invention. The imaging apparatus 500 includes two processing circuits 100 (first processing circuit) and a processing circuit 200 (second processing circuit). In the present embodiment, each of these two processing circuits 100 and 200 is configured as one integrated circuit (IC).

  In addition, a data bus 300 for performing communication between the two processing circuits 100 and 200 is provided. The processing circuits 100 and 200 can acquire moving image data from the imaging unit 400 independently of each other. Each of the processing circuits 100 and 200 can process moving image data acquired from the imaging unit 400.

  Next, the configuration of the processing circuit 100 and the processing circuit 200 will be described. The processing circuit 100 includes an image processing unit 101, a CPU 102 (Central Processing Unit) (first CPU), a memory 103, a recording / reproducing unit 104, a codec unit 105, a communication unit 106, and a bus 107. In this embodiment, an SDRAM is used as the memory 103. Further, the memory 103 is built in the processing circuit 100, but may be provided outside the processing circuit 100.

  The CPU 102 controls the operation of the entire imaging apparatus 500 according to a computer program (software) stored in the memory 103. The memory 103 functions as a work area for the CPU 102. The work area of the CPU 102 is not limited to the memory 103, and may be an external recording device such as a hard disk drive. The image processing unit 101 performs image processing such as pixel interpolation processing and color conversion processing on still image data acquired from the imaging unit 400. The image processing unit 101 converts moving image data in the RGB color space acquired from the imaging unit 400 into a data format in the YUV color space. Further, the image processing unit 101 reduces or enlarges (resizes) the number of pixels (screen size) of the image acquired by the imaging unit 400.

  The imaging unit 400 and the image processing unit 101 are controlled by the CPU 102 to perform autofocus (AF) processing and automatic exposure control (AE) processing. When the CPU 102 instructs to perform shooting, the imaging unit 400 and the image processing unit 101 execute shooting processing including processing such as exposure processing and development processing. The imaging unit 400 includes an imaging element such as a CCD or CMOS, an AD converter, and the like. The imaging unit 400 converts an analog signal obtained by the imaging element into digital data and outputs the digital data. The still image data acquired from the imaging unit 400 is stored in the memory 103 as YUV format still image data. The still image data stored in the memory 103 is encoded by the codec unit 105 (first encoding unit, first decoding unit), and the data amount of the still image data is compressed.

  The recording / playback unit 104 writes the encoded still image data in the recording medium 211 during recording. The codec unit 105 encodes still image data acquired from the imaging unit 400 by a known encoding method such as JPEG at the time of shooting.

  The communication unit 106 (first communication unit) transmits and receives moving image data and other necessary commands to and from the processing circuit 200. The communication unit 106 includes a data reception unit 106a for receiving moving image data, a data transmission unit 106b for transmitting image data, and a message communication unit 106c for sending messages such as control commands. Communication in the communication unit 106 is performed via the data bus 300. Each communication can be performed independently.

  In the present embodiment, as will be described later, after continuous shooting, the index image data processed by the processing circuit 100 is transmitted to the processing circuit 200 by the communication unit 106.

  The processing circuit 200 includes an image processing unit 201, a CPU 202 (second CPU), a memory 203, a recording / playback unit 204, a codec unit 205, a communication unit 206, a file control unit 207, a display unit 208, an operation unit 209, and a bus 210. Have. In the present embodiment, an SDRAM is used as the memory 203. Further, although the memory 203 is built in the processing circuit 100, the memory 203 can be provided outside the processing circuit 200. Each block of the image processing unit 201, CPU 202, memory 203, codec unit 205, and communication unit 206 (second communication unit) has the same function as each block in the processing circuit 100.

  At the time of shooting, the processing circuit 200 acquires moving image data from the imaging unit 400 and performs encoding processing by the codec unit 205 (second encoding unit, second decoding unit). The recording / playback unit 204 records still image data encoded by the codec unit 205 on the recording medium 212 during recording. The recording medium 211 is a random access medium such as a memory card. Further, in the present embodiment, mounting and discharging can be easily performed by a mounting and discharging mechanism (not shown). Further, the recording medium 211 may be built in the imaging apparatus 500. The CPU 202 controls recording of still image data in accordance with the number of pixels specified by the operation unit 209 and the image quality setting. The recording / playback unit 204 reads still image data selected by the user from the recording medium 211 during playback, as will be described later. The codec unit 205 decodes still image data read from the recording medium 211 during reproduction.

  The image processing unit 201 (second resizing unit) changes the image size of the moving image data acquired from the imaging unit 400 according to the size of the display unit 208 and stores it in the memory 203 at the time of shooting. Then, the resized data is supplied to the display unit 208 and displayed. At the time of reproduction, the image processing unit 201 changes the size of the reproduced still image data in accordance with the size of the display unit 208 and stores it in the memory 203. Then, the resized data is supplied to the display unit 208 and displayed. The display unit 208 displays various necessary information in addition to the captured image and the reproduced image. The CPU 202 generates information to be displayed on the display unit 208 and sends it to the display unit 208.

  The file control unit 207 manages still images recorded on the recording medium 211 as files according to a predetermined file system. In the present embodiment, image files recorded on the recording medium 211 are managed according to the FAT file system. In the present embodiment, the file control unit 207 is provided in the processing circuit 200. The file control unit 207 reads management information (such as FAT and directory entry) related to the file system from the recording medium 211 when the power is turned on or when a recording medium is loaded, and stores the management information in the memory 203. Then, the management information stored in the memory 203 is changed (updated) with the recording process on the recording medium 211. Then, management information is read from the memory 203 at a predetermined timing such as when a still image is recorded, and is recorded on the recording medium 211 by the recording / playback unit 204, thereby updating the management information on the recording medium 212.

  The operation unit 209 functions as a user interface for operating the imaging apparatus 500. The operation unit 209 includes a power button for operating the imaging apparatus 500, a mode change button, a shutter button, a cross button, a menu button, and the like, and each button includes a switch, a touch panel, and the like. The CPU 202 controls the imaging device 500 in accordance with a user instruction input via the operation unit 209. When a button on the operation unit 209 is operated by the user, an operation signal corresponding to each button is input from the operation unit 209 to the CPU 202. The CPU 202 analyzes the operation signal input from the operation unit 209 and determines processing corresponding to the operation signal according to the analysis result. The CPU 202 controls each unit of the imaging device 500 so as to execute processing corresponding to the operation signal input from the operation unit 209.

  By operating the operation unit 209, the user can set the exposure time (shutter speed) of the image to be captured, the size (number of pixels) of the image to be recorded, the image quality (compression rate), and the like. Also, the user can set whether or not to perform special processing such as noise reduction processing on the captured image by operating the operation unit 209. Based on these settings by the user, the CPU 202 controls the exposure time of image data captured by the imaging unit 400 and processing for the captured image. In addition, when the shutter button of the operation unit 209 is continuously operated by the user, the CPU 202 performs continuous shooting of still images by issuing shooting instructions continuously at a predetermined timing. Further, the CPU 202 issues during continuous shooting depending on the exposure time of the image data to be shot, the processing for the shot image, the free capacity of the memory 203 for temporarily storing the image data, the data writing speed by the recording / playback unit 204, and the like. The interval between shooting instructions to be performed can be changed.

  Next, processing at the time of recording in the imaging apparatus 500 will be described. FIG. 2 is a flowchart showing processing at the time of recording in the processing circuit 200. The processing in FIG. 2 is executed by the CPU 202 controlling each unit. First, prior to recording, the file control unit 207 determines a free area in the recording medium 211 based on management information (FAT) read from the recording medium 211. The file control unit 207 determines a write address for writing data to the recording medium 211 based on the free space.

  When there is an instruction to shoot a still image from the operation unit 209, the CPU 202 communicates through the communication unit 206 so that the processing circuit 100 processes a still image captured by the imaging unit 400 in a shooting standby state. It is determined whether or not there is (S201). When the processing circuit 100 is in a standby state, the CPU 202 outputs a photographing instruction to the processing circuit 100 through the communication unit 206 (S212). When the processing circuit 100 is not in the standby state, the CPU 202 acquires one frame of still image data from the imaging unit 400, converts it into YUV color space data in the image processing unit 201, and stores it in the memory 203 (S202). . Next, the CPU 202 encodes the still image data stored in the memory 203 by the codec unit 205 and stores the encoded still image data in the memory 203. Here, since the still image data stored in the memory 203 is used as an index image, the still image data is held in the memory 203 until the power is turned off or the empty area of the memory 203 is deleted and deleted.

  When the processing of still image data for one screen is completed, the CPU 202 instructs the file control unit 207 to write the encoded data. The file control unit 207 determines a write address from the free area of the recording medium 212 and instructs the recording / playback unit 204 to write data. The recording / playback unit 204 reads the encoded data from the memory 203 and writes it in the designated address of the recording medium 211 (S203). When the data writing is completed, the file control unit 207 updates the contents of the management information stored in the memory 203 and also updates the free area.

  Next, the CPU 202 determines whether or not information on the amount of encoded still image data has been notified from the processing circuit 100 (S204). When the data amount information is notified, the CPU 202 encodes the code by the processing circuit 100 based on the write address of the still image data written immediately before to the recording medium 211 by the recording / playback unit 204 and the notified data amount. Determine the write address of the data. Then, the determined write address is transmitted from the data transmission unit 206a to the processing circuit 100 (S205). In other words, the CPU 202 determines the write address so that the processing circuit 100 writes the encoded data from the beginning of the next cluster after the cluster including the last write address of the still image data written immediately before the continuous shooting.

  After transmitting the write address information in this way, the CPU 202 determines whether or not a notification of completion of writing of encoded data has been transmitted from the processing circuit 100 (S206). When the writing completion notification is received by the data receiving unit 206b, the CPU 202 instructs the file control unit 207 to update the FAT. The file control unit 207 updates the contents of the FAT stored in the memory 203 in accordance with the writing by the processing circuit 100 (S207).

  Next, as will be described later, the CPU 202 determines whether or not the data receiving unit 206b has received an index image from the processing circuit 100 (S208). If the data receiving unit 206b receives the index image data, it stores it in the memory 203 (S209). At this time, if there is no free space in the memory 203 for the index image data, the CPU 202 can delete the oldest image data from the memory 203. In this way, an empty area in the memory 203 is secured, and the received image data is stored in the memory 203.

  Next, the CPU 202 determines whether or not a shooting instruction is operated by the operation unit 209 (S210). If a shooting instruction operation has been performed, the CPU 202 returns to S201 and continues processing. When the shooting instruction operation is not performed, the CPU 202 instructs the recording / playback unit 204 to write the management information stored in the memory 203 to the recording medium 211. The recording / playback unit 204 reads the management information from the memory 203 and records it in the recording medium 211 (S211).

  FIG. 3 is a flowchart showing processing at the time of recording in the processing circuit 100. The processing in FIG. 3 is executed by the CPU 102 controlling each unit. The CPU 102 determines whether or not a photographing instruction (see S212 in FIG. 2) is received from the processing circuit 200 through the communication unit 106 (S301). If a shooting instruction has not been received, the process proceeds to S307. When receiving a shooting instruction, the CPU 102 acquires one frame of image data from the imaging unit 400, converts the image data into YUV color space data in the image processing unit 101, and stores the YUV color space data in the memory 103 (S302). Here, the still image data stored in the memory 103 is transferred to the processing circuit 100 as an index image after the recording of the still image is completed. For this reason, the data is retained in the memory 103 until the power is turned off, the empty area of the memory 103 is deleted and deleted, or the transfer to the processing circuit 200 is completed. Next, the CPU 102 transmits the size information of the encoded still image data to the processing circuit 200 by the message communication unit 106c (S304).

  Next, the CPU 102 determines whether or not the write address information (see S205 in FIG. 2) in the recording medium 211 has been received from the processing circuit 200 (S305). If the write address information has been received, the CPU 102 instructs the recording / playback unit 104 to write the still image data stored in the memory 103 to the designated write address in the recording medium 211. The recording / playback unit 104 reads the encoded still image data from the memory 103 and writes it to the specified write address of the recording medium 211 (S306). When writing of the encoded data is completed, the CPU 102 transmits a writing completion notification to the processing circuit 200 by the message communication unit 106c (S307). Next, the CPU 102 reads the index image data from the memory 103, and transmits it to the processing circuit 200 from the data transmission unit 106b (S308). (See S208 in FIG. 2.)

  As described above, after the recording of the image data by the processing circuit 100 is completed, the image data for the index image is transmitted from the processing circuit 100 to the processing circuit 200 and stored in the memory 203.

  Next, index screen generation processing during playback will be described. When there is an index display instruction from the operation unit 209, the CPU 202 generates an index screen. In this embodiment, when there is an instruction to display an index screen, thumbnail images for n screens are generated from the latest images in the order of shooting, and an index screen including these n thumbnail images is displayed. Note that the number n of thumbnail images to be displayed on one screen may be determined by the user operating the operation unit 209. In this case, the CPU 102 determines a thumbnail image to be displayed based on the set number of screens n.

  FIG. 4 is a flowchart showing index screen display processing by the processing circuit 200. The processing in FIG. 4 is executed by the CPU 202 controlling each unit. First, the CPU 202 designates one of the thumbnail images determined as described above (S401). Then, the CPU 202 determines whether or not the designated image data is stored in the memory 203 (S402). When the designated image data is stored in the memory 203, the CPU 202 decodes the designated image data by the codec unit 205 (S403). The CPU 202 reduces the size of the image data decoded by the image processing unit 201 and stores it in the storage area for the index screen in the memory 203 (S404). Next, the CPU 202 determines whether or not all thumbnail images to be displayed are stored in the memory 203 and display preparation is completed (S405). When all thumbnail images are stored in the memory 203 and display preparation is completed, the CPU 202 reads each thumbnail image data from the memory 103, generates an index screen, and displays it on the display unit 208 (S406).

  If the designated image data is not stored in the memory 203 in S402, the CPU 202 causes the recording / playback unit 204 to read the designated image data from the recording medium 211 (S407). Then, the read image data is decoded by the codec unit 205.

  After the index screen is displayed on the display unit 208 in this way, the user can specify an image to be played by operating the operation unit 209 and can instruct playback. When reproduction is instructed, the CPU 202 reads the designated image data from the recording medium 211 by the recording / reproducing unit 204 and decodes it by the codec unit 205. Then, the decoded still image data is reduced by the image processing unit 201 and displayed by the display unit 208.

  As described above, in the present embodiment, in the configuration in which still images are captured and recorded by the two processing circuits 100 and 200, the image data is transferred to the processing circuit 200 after the processing circuit 100 finishes recording one-screen image data. . The transferred image data is stored in the memory 203 in the processing circuit 200. Therefore, when there is an instruction to display the index screen, a thumbnail image is generated from the image data stored in the memory 203, and the index screen can be displayed quickly to display the index screen. Further, every time recording of a still image of one screen is completed, image data is transferred to the processing circuit 100 and stored in the memory 203. Therefore, even when there is an index display after continuous shooting, the index screen can be displayed quickly.

  In this embodiment, the image data recorded by the processing circuit 100 is transmitted to the processing circuit 200 as index image data. However, the processing circuit 100 transmits the image data to the processing circuit 200 in a state of being reduced to the size of the thumbnail image. It is good also as a structure. By doing so, the time required to transmit the image data to the processing circuit 200 is shortened, the processing load on the CPU 202 is reduced, and the occupation time of the bus 210 is also shortened. Furthermore, the number of index images that can be stored in the memory 203 can be increased.

(Second Embodiment)
Next, a second embodiment will be described. Also in this embodiment, the configuration of the imaging apparatus is the same as the configuration of FIG. In the first embodiment, the processing circuit 100 transmits the index image data to the processing circuit 200 after the image data recording process for one screen is completed. On the other hand, in the second embodiment, the CPU 202 of the processing circuit 200 instructs the processing circuit 100 to transmit the index image data, and the processing circuit 100 sends the index image data to the processing circuit 200 in response to the transmission instruction. Send. Then, the CPU 202 determines whether or not the continuous shooting speed is low and the capacity of the CPU 202 and the processing bandwidth of the bus 210 are sufficient based on the continuous shooting speed in the processing circuit 200. Then, based on the determination result, the CPU 202 instructs the processing circuit 100 to transmit the index image data.

  FIG. 5 is a flowchart showing recording processing by the processing circuit 200 in the present embodiment. The same processing steps as those in FIG. 2 according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. In FIG. 5, the processing steps S502, S503, and S504 are interposed between S201 and S202. When the processing circuit 100 is not in the standby state in S201, the CPU 202 determines whether or not the continuous shooting speed in the processing circuit 200 is low and the index image data from the processing circuit 100 is received (S502). When it is determined that the index image data is received, the CPU 202 instructs the processing circuit 100 to transmit the index image data through the message communication unit 206c (S503). On the other hand, when determining that the index image data is not received, the CPU 202 instructs the processing circuit 100 to stop the transmission of the index image data (S504). In the processing circuit 100, when the message communication unit 106 c receives an index image transmission instruction or a transmission stop instruction, the received instruction is stored in the memory 103.

  Next, the determination process in S502 will be described. The CPU 202 determines whether or not the continuous shooting speed is low based on the state where the shooting instruction is not output from the operation unit 209 and the state of the processing circuit 200 during continuous shooting. Then, when it is determined that the continuous shooting speed is low, the processing of the CPU 202 by the processing circuit 200 is sufficient, and the processing bandwidth of the bus 210 is sufficient, it is determined that the index image from the processing circuit 100 is received.

  FIG. 7 is a flowchart showing a continuous shooting speed determination process executed by the CPU 202 in a state where no shooting instruction is output. 7 is repeatedly executed by the CPU 202 in the shooting standby state. The CPU 202 determines whether or not the exposure time based on the shutter speed set by the user is longer than a threshold value (S701). If the exposure time is longer than the threshold, the CPU 202 determines that the continuous shooting speed is low (S702). If the exposure time is equal to or less than the threshold value in S701, the CPU 202 determines whether or not a predetermined long-time process that takes a long time such as a noise reduction process is set by the user (S703). If long-time processing has been set, the CPU 202 determines that the continuous shooting speed is low (S704). If long-time processing is not set, the CPU 202 determines whether or not the amount of data of the processed image is large based on the size and image quality of the image set by the user (S705). A setting with a large amount of processing data, for example, when the image size is set to the largest among a plurality of sizes, and the image quality is the highest among the multiple types of image quality, and the amount of data after compression is large. The CPU 202 determines that the continuous shooting speed is low (S706). As described above, when it is determined that the continuous shooting speed is low, the CPU 202 stores the determination result in the memory 203.

  FIG. 8 is a flowchart showing a determination process executed by the CPU 202 after the start of shooting (continuous shooting). The processing in FIG. 8 is repeatedly executed by the CPU 202 during execution of the photographing processing. The CPU 202 determines whether or not the writable speed of data on the recording medium 211 is higher than a threshold value (S801). If the data writing speed is not higher than the threshold, it is determined that the continuous shooting speed is low (S802). When the data writing speed is higher than the threshold value, the CPU 202 determines whether or not the memory 203 has an empty buffer memory area for temporarily storing image data to be recorded, and data can be stored. (S803). When there is no more space in the buffer memory area, the CPU 202 changes the interval for acquiring image data from the imaging unit 400 to be longer. Therefore, the CPU 202 determines that the continuous shooting speed is low when there is no space in the buffer memory area (S804). As described above, when it is determined that the continuous shooting speed is low, the CPU 202 stores the determination result in the memory 203.

  In S502, the CPU 202 determines that the index image is received when it is determined that the continuous shooting speed is low based on the determination result stored in the memory 203 by the processing of FIGS.

  FIG. 6 is a flowchart showing processing at the time of recording by the processing circuit 100 according to the second embodiment. The same processing steps as those in FIG. 3 according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. In FIG. 6, after notifying the processing circuit 200 of the completion of writing in S307, the CPU 102 determines whether or not an instruction to transmit an index image has been received from the processing circuit 200 (S608). If the index image transmission instruction has been received, the CPU 102 transmits the newest image data among the untransmitted image data stored in the memory 103 from the data transmission unit 106b to the processing circuit 200 (S308). Here, every time image data of one screen is transmitted, the CPU 102 confirms an instruction from the processing circuit 200 and transmits untransmitted image data until receiving an instruction to stop transmission of an index image from the processing circuit 200. to continue. When all untransmitted image data is transmitted, the CPU 102 stops transmitting image data to the processing circuit 200.

  On the other hand, even if untransmitted image data is stored in the memory 103, if an instruction to stop transmission of an index image is issued from the processing circuit 200, the CPU 102 does not transmit image data to the processing circuit 200. , Stored in the memory 103. If there is no free space in the memory 103 and the newly generated index image data cannot be stored, the CPU 102 deletes the transmitted image data and stores the newly generated image data in the memory 103. Remember.

  Next, index screen generation processing during playback will be described. FIG. 9 is a flowchart showing index screen display processing by the processing circuit 200. The processing in FIG. 9 is executed by the CPU 202 controlling each unit. The same processing steps as those in FIG. 4 according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. In S402, when the designated image data is not stored in the memory 203, the CPU 202 inquires of the processing circuit 100 whether or not the designated image data is stored in the memory 103 of the processing circuit 100 by the message communication unit 206c. (S907). As a result, when the message communication unit 206c receives a response from the processing circuit 100 that the designated image data is stored in the memory 103, the CPU 202 instructs the processing circuit 100 to transfer the designated image data. (S908). The CPU 202 receives image data by the data receiving unit 206b (S909), and decodes the designated image data by the codec unit 205 (S403). As described above, when the image data related to the display instruction is not stored in the memory 203, the CPU 202 tries to acquire the image data related to the display instruction to the memory 103 of the processing circuit 100.

  If a response indicating that the designated image data is not stored in the memory 103 is received in S907, the CPU 202 causes the recording / playback unit 204 to read the designated image data from the recording medium 211 (S407). In this way, the CPU 202 can acquire the image data related to the display instruction from the recording medium 211 when the acquisition of the image data related to the display instruction due to the trial of S907 to S909 fails. Then, the read image data is decoded by the codec unit 205 (S403).

  After the index screen is displayed on the display unit 208 in this way, the user can specify an image to be played by operating the operation unit 209 and can instruct playback. When reproduction is instructed, the CPU 202 reads the designated image data from the recording medium 211 by the recording / reproducing unit 204 and decodes it by the codec unit 205. Then, the decoded still image data is reduced by the image processing unit 201 and displayed by the display unit 208.

  As described above, in the second embodiment, the CPU 202 issues an image data transmission instruction or a transmission stop instruction to the processing circuit 100 according to the processing load of the processing circuit 200. The processing load can be determined by, for example, the continuous shooting speed. When the continuous shooting speed by the processing circuit 200 is low and the processing circuit 200 can receive and store the index image data generated by the processing circuit 100, the image data is transmitted from the processing circuit 100 to the processing circuit 200. For this reason, transmitting image data from the processing circuit 100 to the processing circuit 200 during continuous shooting increases the load on the CPU 202, and further, the photographing process is interrupted due to the processing bandwidth of the bus 210 being compressed. There is no.

(Other embodiments)
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, etc.) of the system or apparatus reads the program. It is a process to be executed. In this case, the program and the storage medium storing the program constitute the present invention.

Claims (7)

Imaging means;
A first processing circuit having a first CPU and a first communication unit, which records image data acquired from the imaging unit in response to a shooting instruction on a recording medium and stores the acquired image data in a first A first processing circuit stored in the memory of
A second processing circuit having a second CPU and a second communication unit, which records image data acquired from the imaging unit in response to a shooting instruction on the recording medium and stores the acquired image data in the second processing circuit. A second processing circuit for displaying an index screen of image data recorded on the recording medium using image data stored in the second memory in response to an instruction to display the index screen; With
The first CPU transmits the image data of the one screen to the second processing circuit in response to a recording process of the image data of the one screen corresponding to the photographing instruction, and the second CPU An image pickup apparatus that stores image data received from the first processing circuit via the communication means in the second memory. The first CPU determines whether transmission of image data is instructed by the second CPU in response to completion of the recording processing of the image data of the one screen, and the second CPU 2. The imaging apparatus according to claim 1, wherein the image data of the one screen is transmitted to the second processing circuit when it is determined that the transmission of the image data is instructed by the second processing circuit. The second CPU issues an image data transmission instruction to the first processing circuit according to a processing load of the second processing circuit,
The imaging apparatus according to claim 2, wherein the first CPU transmits the image data of the one screen in response to the transmission instruction.   The imaging apparatus according to claim 3, wherein the second CPU determines the processing load based on a continuous shooting speed of the imaging unit. The first CPU does not transmit the image data of the one screen to the second processing circuit when it is not determined that the transmission of the image data is instructed by the second CPU. The imaging device according to claim 2. The second CPU instructs the first CPU to transmit the image data according to the display instruction when the image data according to the display instruction is not stored in the second memory; The imaging apparatus according to claim 2, wherein the image data transmitted from the first processing circuit is stored in the second memory in response to an instruction to transmit image data according to the display instruction . The second CPU, if the can not obtain the image data according to the display instruction from said first processing circuit, to claim 6, characterized in that for acquiring image data according to the display instruction from the Symbol recording medium The imaging device described.

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