JP6197901B2 - Solid-state imaging device and electronic device - Google Patents

Description

  The present technology relates to a solid-state imaging device and an electronic apparatus.

A CMOS (Complementary Metal Oxide Semiconductor) solid-state imaging device known as a solid-state imaging device has a low power supply voltage and low power consumption. For this reason, it is used in various mobile terminal devices such as digital still cameras, digital video cameras, and mobile phones with cameras.
The CMOS solid-state imaging device includes a pixel including a photodiode as a photoelectric conversion unit and a plurality of pixel transistors. The pixel unit includes a pixel unit in which a plurality of pixels are regularly arranged in a two-dimensional array, and a peripheral circuit unit disposed around the pixel unit.

Recently, attention has been focused on backside illumination type CMOS solid-state imaging devices (see Patent Document 1 and Patent Document 2). In the backside illumination type CMOS solid-state imaging device, the side opposite to the side (base surface) on which the wiring is arranged (base surface) is the light incident surface. For this reason, it becomes possible to arrange the wiring of the pixel portion also on the photodiode, and the layout flexibility is drastically improved.
Furthermore, a pixel sharing type CMOS solid-state imaging device in which a plurality of photodiodes share one other pixel transistor group excluding a transfer transistor with a reduction in pixel size is also known (Patent Literature 3, Patent Literature 3). 4).

JP 2007-115994 A JP 2003-31785 A JP 2008-294218 A JP 2009-135319 A

  In the back-illuminated CMOS solid-state imaging device described above, capacitive coupling between wirings cannot be ignored when the spacing between adjacent wirings becomes smaller as the pixel size becomes finer. In the transfer wiring, the pulse voltage supplied to the transfer gate varies due to the influence of other wiring. In particular, when the off-time voltage supplied to the transfer gate varies, the potential in the substrate under the transfer gate varies. Due to this potential fluctuation, the charge accumulated in the photodiode leaks to the floating diffusion (FD), the saturation signal amount (Qs) changes, and the variation in the saturation signal amount between the photodiodes increases. There are problems such as. As described above, when the variation of the saturation signal amount for each pixel is large, the image quality of the solid-state imaging device is deteriorated.

  The present technology provides a solid-state imaging device and an electronic apparatus having a configuration capable of improving the image quality.

  The solid-state imaging device of the present technology includes a first semiconductor substrate having a pixel region in which a plurality of pixels including photoelectric conversion elements are arranged, and a first multilayer wiring layer provided on the first semiconductor substrate. A second semiconductor chip portion having a first semiconductor chip portion, a second semiconductor substrate on which a logic circuit is formed, and a second multilayer wiring layer provided on the second semiconductor substrate; The first multilayer wiring layer side of the first semiconductor chip and the second multilayer wiring layer side of the second semiconductor chip are bonded together, and the first multilayer wiring layer is connected to the first wiring layer and the second wiring layer A first wiring layer having a first wiring, and a second wiring layer being disposed at a distance from the second wiring and the second wiring. The first wiring, the second wiring, and the third wiring are arranged in parallel, and the first wiring And also overlap partially with the second wiring and the planar position, and are arranged at positions overlapping intervals and plane position which is provided between the second wiring and the third wiring.

According to the above-described solid-state imaging device, the transfer wiring is arranged in parallel with a uniform opening width. For this reason, the coupling capacitance between the transfer wirings is constant, and the change in the saturation signal amount between the pixels is constant. Therefore, the saturation signal amount between the pixels becomes uniform, and the image quality of the solid-state imaging device can be improved.
Further, by using this solid-state imaging device, it is possible to improve the image quality of the electronic device.

  According to the present technology, it is possible to provide a solid-state imaging device and an electronic device that can achieve high image quality.

It is a top view which shows the structure of the solid-state imaging device of embodiment. A and B are schematic views showing the structure of a solid-state imaging device. It is sectional drawing which shows the structure of the solid-state imaging device of embodiment. A is a cross-sectional structure of the wiring layer. B is a planar structure of the wiring layer. It is a figure which shows the structure of the pixel structure of a 4-pixel sharing unit. A is a top view which shows the structure of the light-shielding structure of the solid-state imaging device of 1st Embodiment. B is a cross-sectional view of a wiring layer constituting the light shielding structure. A is a top view which shows the structure of the light-shielding structure of the solid-state imaging device of 2nd Embodiment. B is a cross-sectional view of a wiring layer constituting the light shielding structure. A is a top view which shows the structure of the light-shielding structure of the solid-state imaging device of 3rd Embodiment. B is a cross-sectional view of a wiring layer constituting the light shielding structure. A is a top view which shows the structure of the light-shielding structure of the solid-state imaging device of 4th Embodiment. B is a cross-sectional view of a wiring layer constituting the light shielding structure. It is a figure which shows the structure of an electronic device.

Hereinafter, examples of the best mode for carrying out the present technology will be described, but the present technology is not limited to the following examples.
The description will be given in the following order.
1. 1. Overview of solid-state imaging device 1. First embodiment of solid-state imaging device 2. Second embodiment of solid-state imaging device 3. Third embodiment of solid-state imaging device 4. Fourth embodiment of solid-state imaging device Electronics

<1. Overview of solid-state imaging device>
Hereinafter, an outline of the solid-state imaging device will be described.
In a back-illuminated CMOS solid-state imaging device, a horizontal overflow structure is generally formed as a countermeasure against blooming. In the horizontal overflow structure, electric charges are released from the bottom of the transfer gate through the floating diffusion. For this reason, in the backside illuminated CMOS solid-state imaging device, the potential fluctuation of the transfer gate is likely to occur due to the influence of the lateral overflow structure. As described above, in the transfer wiring that supplies the pulse voltage to the transfer gate, the saturation signal amount (Qs) changes and the variation in the saturation signal amount between the photodiodes increases due to the influence of capacitive coupling between the wirings. There is a possibility.

  In order to suppress the variation in the saturation signal amount, it is necessary to make the potential fluctuation of the transfer gate uniform. If the potential fluctuation of the transfer gate is uniform, the fluctuation of the potential in the substrate below the transfer gate becomes the same, and the saturation signal amount does not vary.

  In order to make the fluctuation of the transfer gate potential uniform, it is necessary to take measures from the viewpoint of wiring arrangement in the pixel portion. Therefore, the coupling capacitance between the transfer wiring and the other wiring is made uniform by devising the arrangement of the wiring in the pixel portion. Thus, if the coupling capacitance can be made uniform, the potential fluctuation of the transfer wiring becomes the same in each transfer gate. Therefore, it is possible to suppress variations in the saturation signal amount.

  On the other hand, in solid-state imaging devices, as one of the methods for downsizing multiple functions and multiple chips, efforts have been started to enable high-speed transmission by bonding multiple chips together. . In this case, since the photoelectric conversion element portion and the peripheral circuit portion are formed at very close positions, problems specific to the image sensor occur. Since photoelectric conversion elements handle minute carriers (electrons) as signals, the influence of heat and electromagnetic fields from surrounding circuits is likely to be mixed as noise. In addition, minute hot carrier light emission, which is hardly a problem in normal circuit operation of transistors and diodes, greatly affects image sensor characteristics.

  Hot carrier light emission is light emission caused by generation and recombination of electrons and holes produced when carriers accelerated between a source and a drain collide and ionize at the drain end, or state transition of one of them. This light emission is small but steady even in a transistor having no problem in characteristics. Light emission diffuses in all directions, so the effect is very small if you move away from the transistor, but if the photoelectric conversion element and the circuit are placed very close, the light emission does not diffuse so much and a significant number of photons are injected into the photoelectric conversion element. Is done.

  Thus, since the diffusion of hot carrier light emission is insufficient, the distribution of hot carrier light emission due to the difference in circuit transistor arrangement density and active rate is reflected in the image as two-dimensional information. For this reason, the structure for light-shielding in order to suppress the injection amount to a photoelectric conversion element below a detection limit is required.

In the prior art, the wiring arrangement in the pixel portion is devised for the purpose of suppressing variation in the saturation signal amount, and the coupling capacitance between the transfer wiring and other wiring is made uniform.
However, when the conventional wiring arrangement is used, at least one gap is generated between adjacent wirings, and a light shielding structure is separately prepared to suppress the influence of the hot carrier light emission as described above. There is a need to.
When a light shielding structure is formed by adding a light shielding film, the light shielding film is formed of a material such as W, Cu, Ti, TiN, or C, for example. The absorbing film may be formed using a material that absorbs light instead of the light shielding film, but in any case, there is a disadvantage in terms of cost and the like.
Therefore, in the present embodiment, a wiring structure that can achieve both a uniform coupling capacitance and a light shielding structure without adding a new light shielding structure is configured.

<2. First Embodiment of Semiconductor Device>
[Schematic configuration of solid-state imaging device]
FIG. 1 shows a schematic configuration of a MOS type solid-state imaging device applied to the solid-state imaging device of the present embodiment. This MOS type solid-state imaging device is applied to the solid-state imaging device of each embodiment. The solid-state imaging device 1 of this example includes a pixel region (so-called pixel array) 3 in which pixels 2 including a plurality of photoelectric conversion units are regularly arranged in a two-dimensional array on a semiconductor substrate (not shown), for example, a silicon substrate, And a circuit portion. The pixel 2 includes, for example, a photodiode serving as a photoelectric conversion unit and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors can be constituted by three transistors, for example, a transfer transistor, a reset transistor, and an amplification transistor. In addition, a selection transistor may be added to configure the transistor with four transistors. Since the equivalent circuit of the unit pixel is the same as usual, the detailed description is omitted. The pixel 2 can be configured as one unit pixel. Further, the pixel 2 may have a shared pixel structure. This pixel sharing structure is a structure in which a plurality of photodiodes share a floating diffusion constituting a transfer transistor and other transistors other than the transfer transistor.

The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.
The control circuit 8 receives an input clock and data for instructing an operation mode and outputs data such as internal information of the solid-state imaging device. That is, the control circuit 8 generates a clock signal and a control signal that serve as a reference for operations of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6 and the like based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. To do. These signals are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

  The vertical drive circuit 4 is configured by, for example, a shift register, selects a pixel drive wiring, supplies a pulse for driving the pixel to the selected pixel drive wiring, and drives the pixels in units of rows. That is, the vertical drive circuit 4 selectively scans each pixel 2 in the pixel region 3 in the vertical direction sequentially in units of rows, and according to the amount of light received in, for example, a photodiode serving as a photoelectric conversion unit of each pixel 2 through the vertical signal line 9. A pixel signal based on the generated signal charge is supplied to the column signal processing circuit 5.

  The column signal processing circuit 5 is disposed, for example, for each column of the pixels 2, and performs signal processing such as noise removal for each pixel column on a signal output from the pixels 2 for one row. That is, the column signal processing circuit 5 performs signal processing such as CDS, signal amplification, and AD conversion for removing fixed pattern noise unique to the pixel 2. A horizontal selection switch (not shown) is connected to the horizontal signal line 10 at the output stage of the column signal processing circuit 5.

  The horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and the pixel signal is output from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.

  The output circuit 7 performs signal processing and outputs the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10. For example, only buffering may be performed, or black level adjustment, column variation correction, various digital signal processing, and the like may be performed. The input / output terminal 12 exchanges signals with the outside.

  Next, the structure of the MOS type solid-state imaging device according to this embodiment will be described. 2A and 2B are schematic configuration diagrams showing the structure of the MOS type solid-state imaging device according to the present embodiment.

  As shown in FIG. 2A, the MOS type solid-state imaging device 21 of the present embodiment has a pixel region 23 mounted on the first semiconductor chip portion 22, and a control circuit 24 and a signal processing circuit on the second semiconductor chip portion 26. The logic circuit 25 including is mounted. The first semiconductor chip portion 22 and the second semiconductor chip portion 26 are electrically connected to each other to constitute the MOS type solid-state imaging device 21 as one semiconductor chip.

  Further, in the MOS type solid-state imaging device 27 in the embodiment, as shown in FIG. 2B, the pixel region 23 and the control circuit 24 are mounted on the first semiconductor chip unit 22, and signal processing is performed on the second semiconductor chip unit 26. A logic circuit 25 including a signal processing circuit for mounting is mounted. The first semiconductor chip portion 22 and the second semiconductor chip portion 26 are electrically connected to each other to constitute a MOS solid-state imaging device 27 as one semiconductor chip.

Although not shown in the drawings, the MOS type solid-state imaging device according to another embodiment includes a first semiconductor chip unit 22, a pixel region 23, and a control circuit unit suitable for controlling a pixel region that is a part of the control circuit, Is installed. In addition, the logic circuit 25 and a control circuit unit suitable for controlling the logic circuit that is the other part of the control circuit are mounted on the second semiconductor chip unit 26. The first semiconductor chip portion 22 and the second semiconductor chip portion 26 are electrically connected to each other to constitute a MOS solid-state imaging device 27 as one semiconductor chip.
The MOS type solid-state imaging device according to the above-described embodiment has a structure in which different types of semiconductor chips are stacked, and is characterized by the configuration described later.

[Cross-sectional configuration of solid-state imaging device]
FIG. 3 shows a solid-state imaging device according to this embodiment, particularly a first embodiment of a MOS solid-state imaging device. The MOS type solid-state imaging device of the present embodiment is a backside illumination type solid-state imaging device. The MOS type solid-state imaging device of the present embodiment has applied the configuration shown in FIG. 2B. However, the other configuration shown in FIG. 2A or a configuration in which the control circuit is separately mounted on each of the first and second semiconductor chip portions. Is also applicable. The second embodiment and the following embodiments can be similarly applied to the following embodiments.

  The solid-state imaging device according to the first embodiment is configured by bonding a first semiconductor chip unit 31 and a second semiconductor chip unit 45 together. The first semiconductor chip unit 31 includes a pixel array (hereinafter referred to as a pixel region 23) in which a plurality of pixels each including a photodiode PD serving as a photoelectric conversion unit and a plurality of pixel transistors are two-dimensionally arranged, and a control. A circuit 24 is formed.

  The photodiode PD is formed having an n-type semiconductor region 34 and a p-type semiconductor region 35 on the substrate surface side in the semiconductor well region 32. A gate electrode 36 is formed on the surface of the substrate constituting the pixel via a gate insulating film, and pixel transistors Tr1 and Tr2 are formed by the source / drain regions 33 paired with the gate electrode 36. In FIG. 3, a plurality of pixel transistors are represented by two pixel transistors Tr1 and Tr2. The pixel transistor Tr1 adjacent to the photodiode PD corresponds to the transfer transistor, and the source / drain region thereof corresponds to the floating diffusion FD. Each unit pixel is separated by the element isolation region 38.

  On the other hand, the control circuit 24 includes a plurality of MOS transistors formed in the semiconductor well region 32. In FIG. 3, a plurality of MOS transistors constituting the control circuit 24 are representatively shown as MOS transistors Tr3 and Tr4. Each of the MOS transistors Tr3 and Tr4 is formed by an n-type source / drain region 33 and a gate electrode 36 formed through a gate insulating film.

  On the substrate surface side, a multilayer wiring layer 41 is formed by arranging a plurality of layers of wirings 40 with an interlayer insulating film 39 interposed therebetween. The wiring 40 is formed by a copper wiring, for example. The pixel transistor and the MOS transistor of the control circuit are connected to a required wiring 40 through a connection conductor 44 that penetrates the first insulating film 43a and the second insulating film 43b. The first insulating film 43a is formed of, for example, a silicon oxide film, and the second insulating film 43b is formed of, for example, a silicon nitride film that serves as an etching stopper.

  An antireflection film 61 is formed on the back surface of the semiconductor well region 32. In the region corresponding to each photodiode PD on the antireflection film 61, a waveguide 70 made of a waveguide material film (eg, SiN film) 69 is formed. In the insulating film 62 made of, for example, a SiO film on the back surface of the semiconductor well region 32, a light shielding film 63 that shields a required region is formed. Further, a color filter 73 and an on-chip microlens 74 are formed through the planarization film 71 so as to correspond to each photodiode PD.

  On the other hand, a logic circuit 25 including a signal processing circuit for signal processing is formed in the second semiconductor chip portion 45. The logic circuit 25 is configured, for example, by forming a plurality of MOS transistors in a p-type semiconductor well region 46 so as to be isolated by the element isolation region 50. Here, the plurality of MOS transistors are represented by MOS transistors Tr6, Tr7, Tr8. Each of the MOS transistors Tr6, Tr7, Tr8 is formed having a pair of n-type source / drain regions 47 and a gate electrode 48 formed through a gate insulating film.

  On the semiconductor well region 46, a multilayer wiring layer 55 is formed in which a plurality of wirings 53 and a wiring 57 having a barrier metal layer 58 are arranged via an interlayer insulating film 49. Each MOS transistor Tr6, Tr7, Tr8 is connected to a required wiring 53 through a connection conductor 54 that penetrates the first insulating film 43a and the second insulating film 43b.

  The first semiconductor chip portion 31 and the second semiconductor chip portion 45 are bonded together, for example, via an adhesive layer 60 so that the multilayer wiring layers 41 and 55 face each other. On the bonding surface of the multilayer wiring layer 55 on the second semiconductor chip portion 45 side, a stress correction film 59 for reducing the bonding stress is formed. In addition, the bonding can be performed by plasma bonding.

  Further, the first semiconductor chip portion 31 and the second semiconductor chip portion 45 are electrically connected via a connection conductor 68. That is, a connection hole that penetrates the semiconductor well region 32 of the first semiconductor chip portion 31 and reaches the required wiring 40 of the multilayer wiring layer 41 is formed. In addition, a connection hole that penetrates the semiconductor well region 32 and the multilayer wiring layer 41 of the first semiconductor chip portion 31 and reaches the required wiring 53 of the multilayer wiring layer 55 of the second semiconductor chip portion 45 is formed. Connection conductors 68 connected to each other are buried in these connection holes, and the first semiconductor chip portion 31 and the second semiconductor chip portion 45 are electrically connected. The periphery of the connection conductor 68 is covered with an insulating film 67 in order to insulate it from the semiconductor well region 32. The wirings 40 and 57 connected to the connection conductor 68 correspond to vertical signal lines. The connection conductor 68 is connected to an electrode pad (not shown) or may be an electrode pad.

  The connection conductor 68 is formed after the first semiconductor chip portion 31 and the second semiconductor chip portion 45 are bonded together, and then the semiconductor well region 32 of the first semiconductor chip portion 31 is thinned. Thereafter, a cap film 72, a planarizing film 71, a color filter 73, and an on-chip microlens 74 are formed. In the semiconductor well region 32, an insulating spacer layer 42 is formed in a region surrounding the connection conductor 68.

In the present embodiment, a light shielding structure by wiring is formed in a region between the photodiode PD in the pixel region 23 and the logic circuit 25 in the peripheral circuit portion and covering the pixel region without a gap.
For example, in the solid-state imaging device, the wiring 40 is arranged on the multilayer wiring layer 41 of the photoelectric conversion element in the pixel region so as to cover the pixel region without any gap. At this time, by using two or more wiring layers and arranging the wirings 40 so as to overlap each other to some extent, the influence of light diffraction can be prevented and the incidence of light from below can be suppressed.

  In addition, the light shielding structure combines transfer wirings arranged at equal intervals in the same layer with other wirings arranged in different layers so as to have a certain overlap with the transfer wiring in order to make the coupling capacitance uniform. Configure. With this configuration, it is possible to form a light blocking structure that blocks light emitted during the operation of the active elements in the peripheral circuit section using only the wiring layer without adding a new light blocking layer. With this structure, it is possible to prevent hot carrier light from entering the photodiode PD of the pixel. Examples of the active element include a MOS transistor and a protective diode.

[Shading structure by wiring]
4A and 4B show a configuration example of a light shielding structure using wiring. 4A is a diagram illustrating a cross-sectional structure of the wiring layer, and FIG. 4B is a diagram illustrating a planar structure of the wiring layer.
The light shielding structure is configured by at least two layers of wiring 40A and wiring 40B.
In this light shielding structure, the interval between the lower wiring 40A and the upper wiring 40B is defined as a distance 81 between the wirings. Similarly, a length in which the lower layer wiring 40A and the upper layer wiring 40B overlap in the planar direction is defined as an overlapping amount 82. An interval between the lower wirings 40 </ b> A is defined as an opening width 83.

The overlap amount 82 is determined from the distance 81 between the wirings and the opening width 83. Since hot carrier light is generated as a point light source, it is necessary to shield light coming from an oblique direction. For this reason, by making the overlap amount 82 at least larger than the distance 81 between the wirings, the light shielding property of the hot carrier light from the oblique direction is improved.
Further, the opening widths 83 of the wirings 40A formed in the same layer of each wiring are all arranged to be equal. Further, the overlapping amount 82 is formed uniformly. With this configuration, the positional relationship between the wirings 40A and 40B can be made uniform, and the coupling capacitance can be made uniform.

[Pixel sharing unit: pixel configuration]
Next, the configuration of the pixel unit applied to the solid-state imaging device of the present embodiment will be described. FIG. 5 shows a configuration of a pixel unit composed of a 4-pixel sharing unit applied to the present embodiment. As shown in FIG. 5, a 4-pixel sharing unit in which 4-pixel photodiodes PD [PD1 to PD4] are arranged is arranged in a two-dimensional array to form a pixel portion.

  The 4-pixel sharing unit is configured to share one floating diffusion FD with respect to a total of four photodiodes PD of 2 × 2 in total. The four photodiodes PD1 to PD4, the four photodiodes PD1 to PD4, four transfer gate electrodes 75 to 78, and one floating diffusion FD are configured. Each of the photodiodes PD1 to PD4, the floating diffusion FD, and each of the transfer gate electrodes 75 to 78 constitute transfer transistors Tr11 to Tr14. The floating diffusion FD is disposed at the center surrounded by the four photodiodes PD1 to PD4, and the transfer gate electrodes 75 to 78 are disposed at positions corresponding to the corners on the center side of the photodiodes PD1 to PD4. Is done.

  In FIG. 5, the selection transistor Tr23 and the amplification transistor Tr22 are arranged above the 4-pixel sharing unit. A reset transistor Tr21 is arranged below the 4-pixel sharing unit. The selection transistor Tr23 includes a pair of source / drain regions 94 and 95 and a selection gate electrode 79. The amplification transistor Tr22 includes a pair of source / drain regions 95 and 96 and an amplification gate electrode 80. The reset transistor Tr21 includes a pair of source / drain regions 97 and 98 and a reset gate electrode 99. Each of the gate electrodes is formed of, for example, a polysilicon film. FD1 is connected to the amplification gate electrode 80 of the amplification transistor Tr23 and the source region of the reset transistor Tr21.

The light shielding structure described above is formed in the wiring layer in the region where the photodiode PD is formed. The light shielding region by the wiring layer preferably covers the entire region where the photodiode PD is formed.
However, the effect of the light shielding structure can be obtained without covering the entire photodiode PD region. For example, as in the light shielding region 100 shown in FIG. 5, it is preferable to shield at least a square region having one short side of the photodiode PD1 on the photodiode PD1. Similarly, in the photodiodes PD1 to PD4, a square region having the short side of the photodiodes PD2 to PD4 as one side is shielded from light. By forming a light shielding structure by wiring on the light shielding region 100, a sufficient light shielding effect can be obtained. As described above, even when the light shielding layer that covers a part of the photodiode PD region is provided without covering the entire region where the photodiode PD is formed, the effect of the light shielding structure can be obtained.

[Wiring configuration: Configuration example of light shielding structure]
Next, a light shielding structure using a wiring layer provided on the pixel portion in which the above-described 4-pixel sharing unit is configured will be described.
In the back-illuminated CMOS solid-state imaging device, as shown in FIG. 3 described above, a pixel transistor is formed on the surface side of the semiconductor substrate, and a plurality of layers of metal layers are disposed above the pixel transistor via an interlayer insulating film. A layer is formed. A color filter layer and an on-chip lens are formed on the back side of the semiconductor substrate, and light is incident from the back side of the substrate. That is, the backside illumination type has a configuration in which the wiring layer is formed on the side opposite to the light incident surface.

  FIG. 6 shows a first embodiment of a light shielding structure formed on the pixel portion. FIG. 6A is a plan view showing the configuration of various wirings formed on the 4-pixel sharing unit. 6B is a cross-sectional view taken along line AA of the wiring structure shown in FIG. 6A. 6A has the same configuration as the configuration illustrated in FIG. 5 described above, and the same configuration is denoted by the same reference numeral and detailed description thereof is omitted.

  The wiring that forms the light shielding structure on the pixel portion includes a transfer wiring and other wirings arranged in parallel with the transfer wiring. In this embodiment, pulse wiring and dummy wiring are used as wiring arranged in parallel with the transfer wiring. The wiring other than the transfer wiring is not particularly limited, and various wirings provided in the CMOS solid-state imaging device, dummy wirings, and the like can be used as appropriate.

As shown in FIG. 6A, in the pixel portion, transfer wirings 84 to 87 extending in the horizontal direction when viewed from above and arranged in parallel in the vertical direction are arranged at a required interval. For example, at least one of the four transfer wirings 84 to 87 is arranged in parallel so as to cross over the photodiode PD. In this example, the transfer wirings 84 and 87 are formed so as to cross the vicinity of the center of the photodiode PD.
The transfer wirings 84 to 87 are connected to the transfer gate electrodes 75 to 78 of the transfer transistors Tr11 to 14 in the 4-pixel sharing unit. At this time, it is preferable that the four transfer wirings 84 to 87 have the same wiring width and spacing between the wirings.

Further, as shown in FIG. 6A, pulse wirings 88 to 91 are provided adjacent to the transfer wirings 84 to 87. In FIG. 6, two pulse wirings 88, 89, 90, and 91 are arranged for transfer wirings 84 and 87 provided outside, respectively. The pulse wirings 88 to 91 are arranged in parallel with the transfer wirings 84 to 87. It is preferable that the pulse wirings 88 to 91 and the transfer wirings 84 to 87 have the same wiring width and spacing between the wirings.
As shown in FIG. 6B, in the first embodiment, the transfer wirings 84 to 87 and the pulse wirings 88 to 91 are all formed in the same wiring layer.

  6A and 6B, dummy wirings 92 are formed in a wiring layer different from the transfer wirings 84 to 87 and the pulse wirings 88 to 91. As shown in FIG. 4 described above, the dummy wiring 92 is arranged at a position where the transfer wirings 84 to 87 and the pulse wirings 88 to 91 partially overlap each other. The dummy wiring 92 may be electrically floating, or may be fixed to the power supply voltage and the ground.

In the light shielding structure of the first embodiment, in the multilayer wiring layer, transfer wirings 84 to 87 and pulse wirings 88 to 91 are provided in the lower wiring layer, and a dummy wiring 92 is provided in the upper wiring layer.
The lower transfer wirings 84 to 87 and the pulse wirings 88 to 91 and the upper dummy wiring 92 are larger than the distance 81 between the wirings in the wiring layer as in the wirings 40A and 40B shown in FIG. They are arranged with an overlap amount 82.
Further, the opening widths 83 of the transfer wirings 84 to 87 and the pulse wirings 88 to 91 are formed with uniform lengths. Further, the opening width 83 of the dummy wiring 92 is formed with a certain length.

  By arranging the transfer wirings 84 to 87, the pulse wirings 88 to 91, and the dummy wiring 92 as described above, between the photodiode PD and an active element such as a logic circuit located at a close distance of the photodiode PD. A light shielding structure is formed. For this reason, hot carrier light generated in a MOS transistor such as a logic circuit can be blocked by the wiring layer constituting the light blocking structure. Further, light generated during the operation of the protective diode can be blocked by the wiring layer constituting the light blocking structure. Accordingly, it is possible to prevent the hot carrier light from entering the photodiode PD of the pixel portion.

In particular, the transfer wirings 84 to 87, the pulse wirings 88 to 91, and the dummy wiring 92 are arranged with an overlapping amount 82 that is larger than the distance 81 between the wirings. Can block the hot carrier light. For this reason, it can be set as the light-shielding structure which can further suppress incidence | injection of the hot carrier light to the photodiode PD.
Accordingly, it is possible to provide a solid-state imaging device in which hot carrier light is prevented from being reflected in the pixel region, and thus the image quality is improved.

  Further, since the transfer wirings 84 to 87, the pulse wirings 88 to 91, and the opening widths 83 of the dummy wirings 92 are formed with uniform lengths, the positional relationship between the wirings can be made the same. . For this reason, the coupling capacitance between the wirings can be made uniform, and the potential fluctuation of the transfer gate can be made uniform. Accordingly, the potential variation of the transfer wiring is the same in each transfer gate, and variation in the saturation signal amount of each pixel can be suppressed.

<3. Second Embodiment of Solid-State Imaging Device>
Next, the configuration of the solid-state imaging device according to the second embodiment will be described. Also in the second embodiment, a solid-state imaging device similar to that in the first embodiment described above can be applied except for the configuration of the wiring that forms the light shielding structure. Therefore, in the following description, the configuration of the wiring that forms the light shielding structure will be described.

[Wiring: Configuration example of light shielding structure]
FIG. 7 shows a wiring structure that constitutes a light shielding structure provided on a pixel portion in which a pixel sharing unit is configured. FIG. 7A is a plan view showing a configuration of various wirings formed on the 4-pixel sharing unit shown in FIG. 5 described above. 7B is a cross-sectional view taken along line AA of the wiring structure shown in FIG. 7A.

  The transfer wirings 84 to 87 and the pulse wirings 88 to 91 are configured in the same arrangement as in the first embodiment. A wiring layer in which a dummy wiring 92 is formed is provided above the wiring layer in which the transfer wirings 84 to 87 and the pulse wirings 88 to 91 are formed.

  The dummy wiring 92 is formed so as to cover the photodiode PD of the 4-pixel sharing unit so as to cover the transfer wirings 84 to 87 and the pulse wirings 88 to 91. The formation area of the dummy wiring 92 is preferably equal to or larger than the light shielding area shown in FIG. In particular, it is preferably formed over the entire pixel portion. The dummy wiring 92 may be electrically floating, or may be fixed to the power supply voltage and the ground.

  In addition, the transfer wirings 84 to 87 and the pulse wirings 88 to 91 have a constant opening width 83 between the wirings shown in FIG. Since the dummy wiring 92 is formed so as to cover the whole of the transfer wirings 84 to 87 and the pulse wirings 88 to 91, the overlapping amount 82 is uniform for all the wirings. Further, by increasing the widths of the transfer wirings 84 to 87 and the pulse wirings 88 to 91 rather than the distance 81 between the wirings, the overlap amount 82 becomes larger than the distance 81 between the wirings.

  As described above, by arranging the transfer wirings 84 to 87, the pulse wirings 88 to 91, and the dummy wiring 92, the positional relationship between the wirings can be made the same. For this reason, the coupling capacitance between the wirings can be made uniform, and the potential fluctuation of the transfer gate can be made uniform. Therefore, the effect of the potential fluctuation of the transfer wiring is the same in each transfer gate, and variation in the saturation signal amount between the photodiodes can be suppressed.

  Further, by forming the dummy wiring 92 that covers the transfer wirings 84 to 87 and the pulse wirings 88 to 91, a light shielding structure having an overlapping amount 82 larger than the distance 81 between the wirings is formed on the pixel portion. The For this reason, it is possible to prevent the hot carrier emission from entering the photodiode PD of the pixel portion. In particular, the configuration is effective in preventing the incidence of hot carrier light from an oblique direction due to the influence of light diffraction.

<4. Third Embodiment of Solid-State Imaging Device>
Next, the configuration of the solid-state imaging device according to the third embodiment will be described. Also in the third embodiment, a solid-state imaging device similar to that in the first embodiment described above can be applied except for the configuration of the wiring that forms the light shielding structure. Therefore, in the following description, the configuration of the wiring that forms the light shielding structure will be described.

[Wiring: Configuration example of light shielding structure]
FIG. 8 shows a wiring structure that constitutes a light shielding structure provided on a pixel portion in which a pixel sharing unit is configured. FIG. 8A is a plan view showing the configuration of various wirings formed on the 4-pixel sharing unit shown in FIG. 5 described above. 8B is a cross-sectional view taken along line AA of the wiring structure shown in FIG. 8A.

  As shown in FIG. 8, the transfer wirings 84 to 87 and the pulse wirings 88 to 91 are configured in the same arrangement as in the first embodiment. A wiring layer in which a dummy wiring 92 is formed is provided above the wiring layer in which the transfer wirings 84 to 87 and the pulse wirings 88 to 91 are formed.

The light shielding structure using wiring according to the third embodiment is an example in which an opening is provided in a part of the light shielding structure. For this reason, the configuration shown in FIG. 8 is a configuration in which an opening is provided on the pixel portion and outside the light shielding region of the photodiode PD in addition to the light shielding structure of the second embodiment described above.
Thus, in the light shielding structure using wiring, an opening may be provided on the pixel portion.

  The dummy wiring 92 is formed so as to cover the photodiode PD of the 4-pixel sharing unit so as to cover the transfer wirings 84 to 87 and the pulse wirings 88 to 91. The formation area of the dummy wiring 92 is preferably equal to or larger than the light shielding area shown in FIG. In particular, it is preferably formed over the entire pixel portion. The dummy wiring 92 may be electrically floating, or may be fixed to the power supply voltage and the ground.

The dummy wiring 92 is provided with an opening 101 from which a part of the wiring is removed. In the light shielding structure using wiring, the opening 101 is a region where the upper wiring layer and the lower wiring layer do not overlap. That is, in the example of the third embodiment, the areas where the transfer wirings 84 to 87 and the pulse wirings 88 to 91 formed in the lower wiring layer and the dummy wiring 92 formed in the upper layer are not formed are blocked by the wiring. Opening 101 of the structure.
Since it is difficult to partially remove the transfer wirings 84 to 87 and the pulse wirings 88 to 91, the opening 101 is formed by removing a part of the dummy wiring 92.

  The opening 101 is preferably formed at a position other than on the photodiode PD in the pixel portion in order to block hot carrier light emission generated by the MOS transistor located at a close distance. However, the aperture 101 has a size that does not affect the acquired image of the solid-state imaging device, for example, the aperture 101 is formed on the photodiode PD so that only the hot carrier emission below the detection limit is incident. It may be provided on the diode PD.

For example, on the photodiode PD shown in FIG. 5 described above, a square region having at least one short side of the photodiode PD is the light shielding region 100 1.
For example, the position and number of openings 101 are not limited as long as the opening center is not on the photodiode PD.

  However, the positional relationship between the transfer wirings 84 to 87 and the pulse wirings 88 to 91 is such that the opening width 83 between the wirings shown in FIG. If there is uniformity in the arrangement of the transfer wirings 84 to 87 and the pulse wirings 88 to 91, there is no particular problem with the uniformity with the dummy wiring. In the region where the opening 101 is provided, the positional relationship between the transfer wiring and the dummy wiring is not maintained uniform with other regions, but the uniformity between the transfer wiring and the dummy wiring is limited by the coupling capacitance. Can be ignored because it has little effect on

  As described above, by arranging the transfer wirings 84 to 87 and the pulse wirings 88 to 91, the positional relationship between the wirings can be made the same. For this reason, the coupling capacitance between the wirings can be made uniform, and the potential fluctuation of the transfer gate can be made uniform. Therefore, the effect of the potential fluctuation of the transfer wiring is the same in each transfer gate, and variation in the saturation signal amount between the photodiodes can be suppressed.

  Further, by forming the dummy wiring 92 that covers the transfer wirings 84 to 87 and the pulse wirings 88 to 91, a light shielding structure having an overlapping amount 82 larger than the distance 81 between the wirings is formed on the pixel portion. The For this reason, it is possible to prevent the hot carrier emission from entering the photodiode PD of the pixel portion. In particular, the configuration is effective in preventing the incidence of hot carrier light from an oblique direction due to the influence of light diffraction.

  Also in the first embodiment described above, a part of the dummy wiring 92 is removed, and a region where the upper dummy wiring 92 and the lower transfer wirings 84 to 87 and the pulse wirings 88 to 91 do not overlap is provided. Thus, an opening can be provided at an arbitrary position.

<5. Fourth Embodiment of Solid-State Imaging Device>
Next, the configuration of the solid-state imaging device according to the fourth embodiment will be described. Also in the fourth embodiment, a solid-state imaging device similar to that in the first embodiment described above can be applied except for the configuration of the wiring that forms the light shielding structure. Therefore, in the following description, the configuration of the wiring that forms the light shielding structure will be described.

[Wiring: Configuration example of light shielding structure]
FIG. 9 shows a wiring structure that constitutes a light shielding structure provided on a pixel portion in which a pixel sharing unit is configured. FIG. 9A is a plan view showing the configuration of various wirings formed on the 4-pixel sharing unit shown in FIG. 5 described above. 9B is a cross-sectional view taken along line AA of the wiring structure shown in FIG. 9A.

  Transfer wirings 84 to 87 and dummy wiring 92 are formed in the lower wiring layer. Pulse wirings 88 to 91 and dummy wirings 93 are formed in the upper wiring layer.

In the lower wiring layer, transfer wirings 84 to 87 and dummy wirings 92 extending in the horizontal direction as viewed from above and arranged in parallel in the vertical direction are alternately arranged at a predetermined interval.
In the upper wiring layer, pulse wirings 88 to 91 and dummy wirings 93 extending in the horizontal direction as viewed from above and arranged in parallel in the vertical direction are alternately arranged at a predetermined interval.

  The transfer wirings 84 to 87 and the dummy wirings 93, and the transfer wirings 84 to 87 and the pulse wirings 88 to 91 are larger than the distance 81 between the wirings of the wiring layer, like the wirings 40A and 40B shown in FIG. They are arranged with an overlap amount 82. Similarly, the dummy wiring 92 and the pulse wirings 88 to 91, and the dummy wiring 92 and the dummy wiring 93 overlap more than the distance 81 between the wirings in the wiring layer, like the wirings 40A and 40B shown in FIG. The quantity 82 is arranged. Thus, in the upper and lower wiring layers, the overlapping amount 82 of each wiring is formed with a certain length.

  Further, the opening width 83 between the transfer wirings 84 to 87 and the dummy wiring 92 and the opening width 83 between the pulse wirings 88 to 91 and the dummy wiring 93 are formed with a constant length. Further, the distance between the lower transfer wirings 84 to 87 and the upper pulse wirings 88 to 91 is constant.

  As described above, by arranging the transfer wirings 84 to 87, the pulse wirings 88 to 91, and the dummy wirings 92 and 93, the positional relationship between the wirings can be made the same. For this reason, the coupling capacitance between the wirings can be made uniform, and the potential fluctuation of the transfer gate can be made uniform. Therefore, the effect of the potential fluctuation of the transfer wiring is the same in each transfer gate, and variation in the saturation signal amount between the photodiodes can be suppressed.

  Further, by forming the transfer wirings 84 to 87, the pulse wirings 88 to 91, and the dummy wirings 92 and 93, a light shielding structure having an overlapping amount 82 larger than the distance 81 between the wirings is formed on the pixel portion. Is done. For this reason, it is possible to prevent the hot carrier emission from entering the photodiode PD of the pixel portion. In particular, the configuration is effective in preventing the incidence of hot carrier light from an oblique direction due to the influence of light diffraction.

As described above, in the two wiring layers constituting the light shielding structure, the transfer wirings 84 to 87 and the pulse wirings 88 to 91 may be formed in different wiring layers. And you may form the light-shielding structure of the structure where the transfer wiring 84-87 and the pulse wiring 88-91 overlap. Further, dummy wirings may be formed in both wiring layers. The light shielding structure may be formed by overlapping the upper and lower dummy wirings.
As described above, in addition to the light shielding structure formed by the overlapping of the transfer wirings 84 to 87 and the pulse wirings 88 to 91 and the dummy wiring 92 as in the first to third embodiments, a light shielding structure using wiring is configured. Can do.

<6. Electronics>
Next, an embodiment of an electronic device including the above-described solid-state imaging device will be described.
The above-described solid-state imaging device can be applied to electronic devices such as a camera system such as a digital camera or a video camera, a mobile phone having an imaging function, or another device having an imaging function. FIG. 10 illustrates a schematic configuration when the solid-state imaging device is applied to a camera capable of capturing a still image or a moving image as an example of an electronic device.

  The camera 110 in this example includes a solid-state imaging device 111, an optical system 112 that guides incident light to a light receiving sensor unit of the solid-state imaging device 111, a shutter device 113 provided between the solid-state imaging device 111 and the optical system 112, and a solid state And a drive circuit 114 that drives the imaging device 111. Furthermore, the camera 110 includes a signal processing circuit 115 that processes an output signal of the solid-state imaging device 111.

  As the solid-state imaging device 111, the solid-state imaging device described in the first to fourth embodiments can be applied. The optical system (optical lens) 112 forms image light (incident light) from the subject on an imaging surface (not shown) of the solid-state imaging device 111. Thereby, signal charges are accumulated in the solid-state imaging device 111 for a certain period. The optical system 112 may be constituted by an optical lens group including a plurality of optical lenses. The shutter device 113 controls the light irradiation period and the light shielding period of the incident light to the solid-state imaging device 111.

  The drive circuit 114 supplies drive signals to the solid-state imaging device 111 and the shutter device 113. The drive circuit 114 controls the signal output operation to the signal processing circuit 115 of the solid-state imaging device 111 and the shutter operation of the shutter device 113 by the supplied drive signal. That is, in this example, a signal transfer operation from the solid-state imaging device 111 to the signal processing circuit 115 is performed by a drive signal (timing signal) supplied from the drive circuit 114.

  The signal processing circuit 115 performs various types of signal processing on the signal transferred from the solid-state imaging device 111. The signal (video signal) that has been subjected to various signal processing is stored in a storage medium (not shown) such as a memory, or is output to a monitor (not shown).

  According to the electronic apparatus such as the camera 110 described above, in the solid-state imaging device 111, variation in the saturation signal amount accompanying the reduction in pixel size can be suppressed. Further, in the solid-state imaging device, it is possible to suppress incidence of light such as hot carrier light from an active element such as a MOS transistor or a diode during operation in the peripheral circuit section to the photodiode. Therefore, a high-quality electronic device with improved image quality can be provided.

  In each of the above-described embodiments, the example in which the light shielding structure is configured by two wiring layers has been described. However, the number of wiring layers used in the light shielding structure may be three or more. Also in this case, the light shielding structure can be configured by making the amount of overlapping of the wiring larger than the distance between the wirings of the wiring layer. Even when the light shielding structure is composed of three or more wiring layers, if the wiring width and the wiring interval are formed uniformly between the transfer wiring and other wirings constituting the light shielding structure, the coupling capacitance can be made uniform. it can.

  In the above-described embodiment, the pixel region, the control region, and the logic circuit are manufactured on separate substrates, and these substrates are bonded. However, the pixel region, the control region, and the logic circuit are the same. It may be formed in the substrate. Further, the pixel area, the control area, and the logic circuit do not need to be in the vertical direction, and may be in the same plane. In either case, the present invention can be applied to a structure in which the pixel region, the control region, and the logic circuit are at a close distance.

In addition, this indication can also take the following structures.
(1) formed in a pixel region in which a plurality of pixels including photoelectric conversion elements are arranged, a transfer wiring formed in parallel with a uniform opening width on the pixel region, and a wiring layer above the transfer wiring; A solid-state imaging device including at least a part of the other wiring provided at a position overlapping with the transfer wiring at a planar position, wherein a light shielding structure is formed in the pixel region by the transfer wiring and the other wiring.
(2) The solid-state imaging device according to (1), wherein the photoelectric conversion element is provided on a surface on the first surface side of the base, and the wiring layer is provided on a second surface of the base.
(3) A second substrate bonded to the second surface side of the substrate via the wiring layer is provided, the second substrate has a peripheral circuit section, and the pixel region and the peripheral circuit section (2) The solid-state imaging device according to (2), in which the light shielding structure is formed therebetween.
(4) The solid-state imaging device according to any one of (1) to (3), including an active element for signal processing at a short distance of the photoelectric conversion element.
(5) The solid-state imaging device according to (4), which includes at least one of a field effect transistor or a diode as the active element.
(6) The solid-state imaging device according to any one of (1) to (5), including a pulse wiring and a dummy wiring as the other wiring.
(7) An electronic apparatus comprising: the solid-state imaging device according to any one of (1) to (6); and a signal processing circuit that processes an output signal of the solid-state imaging device.

  1,111 solid-state imaging device, 2 pixels, 3,23 pixel area, 4 vertical drive circuit, 5 column signal processing circuit, 6 horizontal drive circuit, 7 output circuit, 8, 24 control circuit, 9 vertical signal line, 10 horizontal signal Line, 12 input / output terminal, 21, 27 MOS type solid-state imaging device, 22, 31 first semiconductor chip portion, 25 logic circuit, 26, 45 second semiconductor chip portion, 32, 46 semiconductor well region, 33, 47 , 94, 95, 97 Source / drain region, 34 n-type semiconductor region, 35 p-type semiconductor region, 36, 48 gate electrode, 38, 50 element isolation region, 39, 49 interlayer insulation film, 40, 40A, 40B, 53 , 57 wiring, 41, 55 multilayer wiring layer, 42 insulating spacer layer, 43a first insulating film, 43b second insulating film, 44, 54, 68 connecting conductor, 58 bar Rear metal layer, 59 Stress correction film, 60 Adhesive layer, 61 Antireflection film, 62, 67 Insulating film, 63 Light shielding film, 69 Waveguide material film, 70 Waveguide, 71 Planarization film, 72 Cap film, 73 Color filter 74 On-chip microlens, 75 Transfer gate electrode, 79 Select gate electrode, 80 Amplification gate electrode, 81 Distance between wiring, 82 Overlap amount, 83 Opening width, 84 Transfer wiring, 88 Pulse wiring, 92, 93 Dummy wiring, 99 reset gate electrode, 100 light shielding region, 101 opening, 110 camera, 112 optical system, 113 shutter device, 114 drive circuit, 115 signal processing circuit, FD floating diffusion, PD1, PD2, PD1, PD4 photodiode, Tr1 pixel transistor , Tr11, Tr12 Tr13, Tr14 transfer transistors, Tr21 reset transistor, Tr22 amplifying transistor, Tr23 select transistor

Claims (18)

A first semiconductor chip portion having a first semiconductor substrate having a pixel region in which a plurality of pixels including photoelectric conversion elements are arranged, and a first multilayer wiring layer provided on the first semiconductor substrate;
A second semiconductor chip portion having a second semiconductor substrate on which a logic circuit is formed, and a second multilayer wiring layer provided on the second semiconductor substrate;
The first multilayer wiring layer is provided on a side opposite to a direction in which light enters the photoelectric conversion element with respect to the first semiconductor substrate,
The first multilayer wiring layer side of the first semiconductor chip part and the second multilayer wiring layer side of the second semiconductor chip part are bonded together,
The first multilayer wiring layer includes a first wiring layer and a second wiring layer;
The first wiring layer has a first wiring;
The second wiring layer includes a second wiring electrically connected to the transfer gate, and a third wiring spaced apart from the second wiring;
The first wiring, the second wiring, and the third wiring are arranged in parallel,
At the position where the first wiring, the second wiring, and the third wiring are arranged in parallel, at least a part of the first wiring is in a planar position with respect to the second wiring. It is arranged at a position where it overlaps at a plane position and an interval provided between the second wiring and the third wiring,
The position where the first wiring overlaps the second wiring at a planar position, and the distance between the second wiring and the third wiring and the planar position overlaps at least the pixel. Is placed at a position that overlaps with the plane position ,
A solid-state imaging device in which the third wiring is a dummy wiring .   The solid-state imaging device according to claim 1, wherein the first wiring layer and the second wiring layer are adjacent wiring layers.   The solid-state imaging device according to claim 1, wherein the first wiring, the second wiring, and the third wiring are disposed in the pixel region.   The solid-state imaging device according to claim 1, wherein a width of the first wiring is larger than a width of the second wiring.   5. The solid-state imaging device according to claim 1, wherein the first semiconductor chip portion and the second semiconductor chip portion are bonded together via an adhesive layer.   The solid-state imaging device according to claim 1, further comprising a stress correction film between the first semiconductor chip unit and the second semiconductor chip unit.   The wiring provided in the first multilayer wiring layer and the wiring provided in the second multilayer wiring layer are electrically connected by a connection conductor penetrating the first semiconductor substrate. The solid-state imaging device according to any one of 1 to 6.   The solid-state imaging device according to claim 7, wherein the connection conductor is formed in a connection hole continuously provided from the first semiconductor substrate to a wiring provided in the second multilayer wiring layer.   The solid-state imaging device according to claim 8, further comprising an insulating layer covering a side wall of the connection hole. A solid-state imaging device, and a signal processing circuit for processing an output signal of the solid-state imaging device,
The solid-state imaging device
A first semiconductor chip portion having a first semiconductor substrate having a pixel region in which a plurality of pixels including photoelectric conversion elements are arranged, and a first multilayer wiring layer provided on the first semiconductor substrate;
A second semiconductor chip portion having a second semiconductor substrate on which a logic circuit is formed, and a second multilayer wiring layer provided on the second semiconductor substrate;
The first multilayer wiring layer is provided on a side opposite to a direction in which light enters the photoelectric conversion element with respect to the first semiconductor substrate,
The first multilayer wiring layer side of the first semiconductor chip part and the second multilayer wiring layer side of the second semiconductor chip part are bonded together,
The first multilayer wiring layer includes a first wiring layer and a second wiring layer;
The first wiring layer has a first wiring;
The second wiring layer includes a second wiring electrically connected to the transfer gate, and a third wiring spaced apart from the second wiring;
The first wiring, the second wiring, and the third wiring are arranged in parallel,
At the position where the first wiring, the second wiring, and the third wiring are arranged in parallel, at least a part of the first wiring is in a planar position with respect to the second wiring. It is arranged at a position where it overlaps at a plane position and an interval provided between the second wiring and the third wiring,
The position where the first wiring overlaps the second wiring at a planar position, and the distance between the second wiring and the third wiring and the planar position overlaps at least the pixel. Is placed at a position that overlaps with the plane position ,
An electronic device in which the third wiring is a dummy wiring .   The electronic device according to claim 10, wherein the first wiring layer and the second wiring layer are adjacent wiring layers.   The electronic device according to claim 10, wherein the first wiring, the second wiring, and the third wiring are arranged in the pixel region.   The electronic device according to claim 10, wherein a width of the first wiring is larger than a width of the second wiring.   The electronic device according to claim 10, wherein the first semiconductor chip portion and the second semiconductor chip portion are bonded together with an adhesive layer interposed therebetween.   The electronic device according to claim 10, further comprising a stress correction film between the first semiconductor chip portion and the second semiconductor chip portion.   The wiring provided in the first multilayer wiring layer and the wiring provided in the second multilayer wiring layer are electrically connected by a connection conductor penetrating the first semiconductor substrate. The electronic device according to any one of 10 to 15.   The electronic device according to claim 16, wherein the connection conductor is formed in a connection hole provided continuously from the first semiconductor substrate to the wiring provided in the second multilayer wiring layer.   The electronic device according to claim 17, further comprising an insulating layer covering a side wall of the connection hole.

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