JP6197873B2 - Information processing system, management apparatus, information processing method, and program - Google Patents

Description

  The present disclosure relates to an information processing system, a management apparatus, an information processing method, and a program.

  In an information processing apparatus such as a server that performs various types of information processing, an upper limit value of power consumption allowed for the information processing apparatus may be defined. The information processing apparatus includes a control unit for controlling power consumption, and controls the power consumption of the information processing apparatus so that the power consumption does not exceed the upper limit value.

  As a method of controlling the power consumption of the information processing apparatus, there is a method of controlling the operating frequency of a processor that is an arithmetic processing unit included in the information processing apparatus. The processor receives the clock generated by the clock generation circuit as an operation clock, and performs arithmetic processing based on the clock. When the operating frequency of the processor is increased, the processing capability of the processor is also improved. Therefore, for example, when it is necessary to improve the processing capacity of the processor due to an increase in the number of tasks waiting for processing in the processor, the clock generation circuit increases the frequency of the clock supplied to the processor. However, when the operating frequency of the processor increases, the power consumed by the processor also increases. Therefore, the power consumption control unit controls the frequency of the output clock of the clock generation circuit within a range where the power consumption does not exceed the upper limit value.

JP 2012-51300 A

  There may be a divergence between the power actually consumed by the information processing apparatus and the set upper limit value. For example, the upper limit value of power consumption set in the information processing apparatus is changed. When the power consumption of the information processing apparatus is less than the upper limit value and the processing capacity of the processor needs to be improved, the power consumption control unit changes the clock frequency using the upper limit value as a target value. Specifically, the frequency of the output clock of the clock generation circuit is changed and the power consumption is repeatedly monitored, and feedback control is performed so that the power consumption transitions to the target value. The transitional period until the power consumption transition is completed is a period in which the processing capability of the processor cannot be fully utilized, and is preferably shortened.

  When the power consumption of the information processing apparatus exceeds the upper limit value, the power consumption control unit sets the upper limit value as the target value and decreases the clock frequency so that the power consumption decreases to the target value. The transitional period until the transition of the power consumption is completed is a period in which the state where the power consumption exceeds the upper limit value is continued, and is preferably shortened.

  The technology disclosed in the present application aims to increase the transition speed of power consumption of the information processing apparatus and shorten the period during which the processing capacity of the processor cannot be fully utilized or the power consumption exceeds the upper limit. And

The disclosed information processing system includes a first information processing device including an arithmetic processing unit, a power consumption control unit that controls an operating frequency of the arithmetic processing unit, and a management device , and the management device stores a target value. In accordance with the first table, a first memory storing a first table that defines an added value indicating a larger value as the value obtained by subtracting the power consumption of the first information processing device from the target value is larger Determining an addition value corresponding to the difference between the target value and power consumption, calculating a control value by adding the addition value to the target value, and a setting unit notifying the power consumption control unit of the control value ; includes a power consumption controller may include a second storage unit for storing a control value, based on a difference between the control value and the power consumption, identifies the frequency change per unit time, frequency per unit of time the operating frequency is varied by a change amount, power consumption So as not to exceed the value stored in the second storage unit, that controls the operating frequency.

  The transition speed of the power consumption of the information processing apparatus can be increased, and the period during which the processing capability of the processor cannot be fully utilized or the period during which the power consumption exceeds the upper limit value can be shortened.

It is a figure which shows the hardware constitutions of the computer system in 1st Example. It is a functional block diagram of the power consumption control part in 1st Example. It is a figure which shows the example of the frequency change value amount table in 1st Example. It is a process flowchart of the power consumption control part in 1st Example. It is a graph which shows the transition behavior of the power consumption in 1st Example. It is a functional block diagram of the management apparatus in 1st Example. It is a figure which shows the example of the addition value table in 1st Example. It is a process flowchart of the management apparatus in 1st Example. It is a graph which shows the transition behavior of the power consumption in 1st Example. It is a functional block diagram of the power consumption control part in 2nd Example. It is a figure which shows the example of the frequency-voltage correspondence table in 2nd Example. It is a process flowchart of the power consumption control part in 2nd Example. It is a figure which shows the hardware constitutions of the computer system in 4th Example. It is a graph which shows the transition behavior of the power consumption in 4th Example. It is a functional block diagram of the management apparatus in 4th Example. It is a process flowchart of the management apparatus in 4th Example. It is a figure which shows the circuit structure of a PLL circuit. It is a figure which shows the circuit structure of a DC-DC converter.

<First embodiment>
In the first embodiment, when the power consumed by the information processing apparatus deviates from the upper limit value, the upper limit value is set as the target value, and differs from the target value according to the difference between the power consumption and the target value. By performing power consumption control using a control value having a value, the transition speed of power consumption is increased.

  FIG. 1 is a hardware configuration diagram of a computer system that performs information processing in the first embodiment. The computer system 1 includes a first information processing apparatus 100 and a management apparatus 300 that are connected to each other via a network 500. The first information processing apparatus 100 includes a processor 10, a memory 30, a network interface card (NIC) 40, a Phase Locked Loop (PLL) circuit 60, a DC-DC converter 70, and a power consumption control unit 80. . The processor 10 which is an arithmetic processing unit is connected to the memory 30 via a bus and can access the memory 30. The NIC 40 performs data transfer between the first information processing apparatus 100 and the management apparatus 300 via the network 500. The PLL circuit 60 is a clock generation circuit that generates a clock having a desired frequency and supplies it to the processor 10. The processor 10 performs arithmetic processing using the clock received from the PLL circuit 60. The DC-DC converter 70 is a power supply circuit and supplies power to the processor 10. Note that the DC-DC converter 70 may also supply power to hardware other than the processor 10, for example, the memory 30, the PLL circuit 60, and the power consumption control unit 80. The power consumption control unit 80 controls the power consumed by the first information processing apparatus 100.

  The power consumption control unit 80 includes a processor 110 and a memory 130. The processor 110 which is an arithmetic processing unit is connected to the memory 130 by wiring and can access the memory 130. Note that the power consumption control unit 80 may not include the memory 130. In this case, the processor 110 may store a program and data used for arithmetic processing in the memory 30. In FIG. 1, the power consumption control unit 80 is shown as being included in the first information processing apparatus 100, but the power consumption control unit 80 is disposed outside the first information processing apparatus 100 and is connected via the network 500. 1 The structure connected to the information processing apparatus 100 may be sufficient.

  The management apparatus 300 includes a processor 310, a memory 330, and a NIC 340. A processor 310 that is an arithmetic processing unit is connected to the memory 330 by wiring and can access the memory 330. The NIC 340 performs data transfer between the management apparatus 300 and the first information processing apparatus 100 via the network 500.

  The first information processing apparatus 100 is, for example, a server, and the management apparatus 300 is, for example, a management server. The processors 10, 110, and 310 are electronic circuit components such as a central processing unit (CPU), a micro-processing unit (MPU), a digital signal processor (DSP), and a field-programmable gate array (FPGA). , 330 are electronic circuit components such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and flash memory.

  In FIG. 1, the first information processing apparatus 100 is illustrated as including a memory 30, a NIC 40, a PLL circuit 60, a DC-DC converter 70, and a power consumption control unit 80 in addition to the processor 10. However, any configuration other than the processor 10 need not be included in the first information processing apparatus 100. For example, the PLL circuit 60, the DC-DC converter 70, and the power consumption control unit 80 may be provided outside the first information processing apparatus 100. The PLL circuit 60 may be built in the processor 10.

  2 to 5 described below will explain the function of the power consumption control unit 80 and the power consumption control method performed by the power consumption control unit 80. FIG. 6 to 9 show the control function and control flow of the management apparatus 300 for the power consumption control unit 80. FIG.

  FIG. 2 is a diagram illustrating functional blocks of the processor 110 included in the power consumption control unit 80 and information stored in the memory 130. The processor 110 implements the function of each block illustrated in FIG. 2 by executing a predetermined program stored in the memory 130, the memory 30, the memory 330, or the memory of another information processing apparatus. The processor 110 functions as a first upper limit storage unit 111, a power consumption measurement unit 112, a first measurement value storage unit 113, a timer unit 114, a calculation unit 115, a task manager 116, a determination unit 117, and a setting unit 118.

The first upper limit storage unit 111 stores an upper limit value of power consumption of the first information processing apparatus 100. The upper limit value is an example of a target value (target value) when performing power control of the first information processing apparatus 100. The value stored in the first upper limit storage unit 111 is given from the management device 300, for example. The power consumption measuring unit 112 measures the power consumed by the first information processing apparatus 100. Various methods can be applied as a method for measuring power consumption. For example, the power consumption may be measured by monitoring the output voltage and output current of the DC-DC converter 70. The power consumption measured in this case is a value including power consumed by other circuit elements to which the DC-DC converter 70 supplies power in addition to power consumed by the processor. For example, when the DC-DC converter 70 also supplies power to the PLL circuit 60, the power consumption is measured including the power consumed by the PLL circuit. As another method of measuring the power consumption, the power consumed by the processor 10 among the power consumption of the first information processing apparatus 100 may be measured, and the value may be used as the power consumption of the first information processing apparatus 100. The power P consumed by the processor 10 can be expressed by the following formula (1), for example.
Formula (1):

  In Equation (1), C is the total value of the capacitances of a plurality of elements included in the processor 10, V is the operating voltage of the processor 10, F is the operating frequency of the processor 10, and I is the processor 10 It is the total value of the electric current which flows in. The power consumption measuring unit 112 may calculate the power consumption using, for example, Expression (1). In this specification, the description “measurement of power consumption of the first information processing apparatus 100” includes both the measurement of power consumption of the entire first information processing apparatus 100 and the measurement of power consumption of the processor 10. Use as meaning. The power consumption measuring unit 112 measures power consumption at a fixed time interval or a time interval determined as a power consumption measurement interval described later.

  The first measured value storage unit 113 stores the power consumption value measured by the power consumption measurement unit 112. Since the power consumption measuring unit 112 measures power consumption every predetermined time, the measurement value storage unit 113 may store and save only the newly measured values.

  The timer unit 114 instructs the power consumption measurement unit 112 to measure the power consumption of the processor 10 at a fixed time interval or a time interval determined as a power consumption measurement interval described later. The measurement of power consumption by the processor 10 may be performed at regular intervals, or may be performed at time intervals defined in a frequency change amount table 131 described later.

  The calculation unit 115 performs various calculations necessary for controlling power consumption, for example, a process of subtracting the value stored in the first measured value storage unit 113 from the value stored in the first upper limit value storage unit 111. The task manager 116 manages the amount of tasks waiting for processing in the processor 10 and makes a request to improve the operating frequency as necessary. Based on the calculation result of the calculation unit 115, the determination unit 117 determines whether or not the measured power consumption value exceeds the upper limit value. Further, the determination unit 117 determines whether or not the operating frequency of the processor 10 should be changed based on the presence / absence of an operating frequency improvement request from the task manager 116 and the determination result of whether or not the power consumption exceeds the upper limit value. . Based on the determination result of the determination unit 117, the setting unit 118 instructs the PLL circuit 60 to change the frequency of the output clock in accordance with the description in a frequency change amount table 131 described later. Note that not all of the functions shown here need to be realized by the processor 110. For example, the first upper limit storage unit 111 and the first measured value storage unit 113 are dedicated registers provided outside the processor 110. May be used.

  The memory 130 stores a frequency change amount table 131. The contents of the frequency change amount table 131 are illustrated in FIG. The frequency change amount table 131 is a table that defines the correspondence between the difference between the upper limit value of the power consumption and the measured value and the frequency change amount of the clock output from the PLL circuit 60. In the example illustrated in FIG. 3, the frequency change amount table 131 further defines a correspondence relationship between the difference between the upper limit value of the power consumption and the measured value and the time interval at which the power consumption measurement unit 112 measures the power consumption. .

  The description from the first row to the third row of the frequency change amount table 131 indicates a case where the measured power consumption value is less than the upper limit value. For example, in the description of the first row of the frequency change amount table 131, if the value obtained by subtracting the measured value from the upper limit value of power consumption is 50 W or more, the frequency of the clock output from the PLL circuit 60 is increased by 200 MHz for 10 seconds. This means that the power consumption measuring unit 112 again measures the power consumption of the processor 10 later. The description in the third row of the frequency change amount table 131 indicates that if the value obtained by subtracting the measured value from the upper limit value of power consumption is 0 W or more and less than 20 W, the frequency of the clock output from the PLL circuit 60 is increased by 30 MHz. This means that the power consumption measuring unit 112 again measures the power consumption of the processor 10 after 10 seconds. As in the example shown in FIG. 3, the smaller the difference between the upper limit value of power consumption and the measured value, the smaller the frequency change amount is set.

  The descriptions in the fourth to sixth lines of the frequency change amount table 131 indicate a case where the measured power consumption value exceeds the upper limit value. The description in the sixth line of the frequency change amount table 131 is that if the value obtained by subtracting the measured value from the upper limit value of power consumption is less than −50 W, the frequency of the clock output from the PLL circuit 60 is decreased by 200 MHz for 10 seconds. This means that the power consumption measuring unit 112 again measures the power consumption of the processor 10 later. The description in the fourth row of the frequency change amount table 131 indicates that the frequency of the clock output from the PLL circuit 60 is reduced by 30 MHz if the value obtained by subtracting the measured value from the upper limit value of power consumption is less than 0 W and −20 W or more. It means that the power consumption measuring unit 112 again measures the power consumption of the processor 10 after 10 seconds. As in the example shown in FIG. 3, the absolute value of the frequency change amount is set to a smaller value as the absolute value of the difference between the upper limit value of the power consumption and the measured value is smaller. The specific numerical values shown in FIG. 3 are merely examples, and other numerical values may be used. Further, the frequency change amount table 131 is not necessarily stored in the memory 130, and may be stored in the memory 30 or other memory.

  FIG. 4 is a process flowchart of the processor 110 included in the power consumption control unit 80. The process of FIG. 4 is started by process 1000. In process 1001, the first upper limit storage unit 111 stores the upper limit value of power consumption of the first information processing apparatus 100. In processing 1002, the power consumption measuring unit 112 measures the power consumption of the first information processing apparatus 100. In process 1003, the first measurement value storage unit 113 stores the measurement value of power consumption. In process 1004, the determination unit 117 determines whether or not a completion notification indicating that the storage of the upper limit value in the first upper limit value storage unit 111 has been completed is received from the management apparatus 300, and the process 1004 is performed until the completion notification is received. repeat. If the determination unit 117 determines in step 1004 that a completion notification has been received, the process proceeds to step 1005. Details of the completion notification will be described later. In processing 1005, the calculation unit 115 calculates a difference value obtained by subtracting the value stored in the first measured value storage unit 113 from the value stored in the first upper limit value storage unit 111. In processing 1006, the determination unit 117 determines whether or not the measured power consumption value exceeds the upper limit value. When it is determined that the measured value exceeds the upper limit value, the process proceeds to process 1008, and when it is determined that the measured value does not exceed the upper limit value, the process proceeds to process 1007. In processing 1007, the determination unit 117 determines whether or not the task manager 116 makes a frequency increase request. If it is determined in process 1007 that the task manager 116 has made a frequency increase request, the process proceeds to process 1008. If it is determined that the task manager 116 has not made a frequency increase request, the process returns to process 1002.

  In process 1008, the setting unit 118 refers to the frequency change amount table 131 and acquires the frequency change amount corresponding to the difference value calculated in process 1005. In processing 1009, the setting unit 118 instructs the PLL circuit 60 to change the frequency of the output clock based on the frequency change amount acquired from the frequency change amount table 131. In processing 1010, the timer unit 114 determines whether or not a predetermined time has elapsed since the power consumption measurement unit 112 performed measurement in processing 1002, and returns to processing 1002 when the predetermined time has elapsed.

  FIG. 5 is a graph showing the transition behavior of the power consumption of the first information processing apparatus 100 when control using the frequency change amount table 131 shown in FIG. 3 is performed. In the graph shown in FIG. 5, the horizontal axis indicates time, and the vertical axis indicates measured power consumption. A case where 200 W is set in the first upper limit setting unit 111 as an upper limit value of power consumption is illustrated. At time T1, the measured value of the power consumption of the first information processing apparatus 100 indicates 130W. In this case, the difference between the upper limit value and the measured value is 70W. In the frequency change amount table 131, when the difference between the upper limit value and the measured value is 70 W, the frequency change amount is defined as 200 MHz. Therefore, the frequency of the output clock of the PLL circuit 60 is controlled to increase by 200 MHz. Further, in the frequency change amount table 131, when the difference between the upper limit value and the measured value is 70 W, the power consumption measurement interval is determined to be 10 seconds. Therefore, the first information is timed at time T2 10 seconds after time T1. The power consumption of the processing apparatus 100 is measured.

  Next, the measured value of the power consumption of the first information processing apparatus 100 at time T2 indicates 160W. In this case, the difference between the upper limit value and the measured value is 40W. In the frequency change amount table 131, when the difference between the upper limit value and the measured value is 40 W, the frequency change amount is defined as 100 MHz. Therefore, the frequency of the output clock of the PLL circuit 60 is controlled to increase by 100 MHz. Further, in the frequency change amount table 131, when the difference between the upper limit value and the measured value is 40 W, the power consumption measurement interval is determined to be 10 seconds. Therefore, the first information is timed at time T3 10 seconds after time T2. The power consumption of the processing apparatus 100 is measured.

  The power consumption of the first information processing apparatus 100 at times T3 and T4 is measured by the same procedure. At time T4, the measured power consumption value of the first information processing apparatus 100 is 190 W. In this case, the difference between the upper limit value and the measured value is 10W. In the frequency change amount table 131, when the difference between the upper limit value and the measured value is 10 W, the frequency change amount is defined as 30 MHz. Therefore, the frequency of the output clock of the PLL circuit 60 is controlled to increase by 30 MHz. Further, in the frequency change amount table 131, when the difference between the upper limit value and the measured value is 10 W, the power consumption measurement interval is determined to be 10 seconds. Therefore, the first information is timed at time T5 10 seconds after time T4. The power consumption of the processing apparatus 100 is measured. The power consumption of the first information processing apparatus 100 after time T6 is measured by the same procedure.

  In this way, the power consumption control unit 80 calculates the difference between the upper limit value of the power consumption of the first information processing apparatus 100 and the measured value. When the difference is large, the clock frequency is greatly changed, and when the difference is small, the clock frequency is changed. Make small changes.

  In the frequency change amount table 131 shown in FIG. 3, the power consumption measurement intervals are all defined as 10 seconds regardless of the difference between the upper limit value and the measurement value, but depending on the difference between the upper limit value and the measurement value. Different values may be specified. For example, when the absolute value of the difference between the upper limit value and the measurement value is 20 W or less, the power consumption measurement interval may be set to 20 seconds. By setting in this way, it is possible to set a wide measurement interval in the case where it is considered that the power consumption does not fluctuate in a large amount in a short period of time, and in order to measure the power consumption of the first information processing apparatus 100 The power consumption of the processor 110 used can be suppressed.

  Further, the frequency change amount table shown in FIG. 3 defines the frequency to be changed in one change, but the frequency change is not limited to such a discrete value. You may perform control which changes a frequency more continuously. In this case, the frequency change amount table 131 defines the frequency change amount per unit time. In addition, in this specification, when changing a frequency discretely like FIG. 3, the value which divided the frequency change amount by the power consumption measurement interval is handled as synonymous with the frequency change amount per unit time.

  So far, the function and control method of the power consumption control unit 80 have been described with reference to FIGS. 2 to 5. Next, functions and a control method of the management apparatus 300 for the power consumption control unit 80 will be described with reference to FIGS.

  FIG. 6 is a diagram illustrating information stored in the functional block of the processor 310 and the memory 330 included in the management apparatus 300. The processor 310 implements the function of each block illustrated in FIG. 6 by executing a predetermined program stored in the memory 330, the memory 30, the memory 130, or the memory of another processing device. The processor 310 functions as a second upper limit storage unit 311, a second measurement value storage unit 312, a calculation unit 313, an addition value acquisition unit 314, and a setting unit 315.

  The second upper limit storage unit 311 stores an upper limit value of power consumption of the first information processing apparatus 100. The value stored in the second upper limit storage unit 311 can be set from a user terminal connected to the management apparatus 300, for example. The second measurement value storage unit 312 receives and stores the measurement result from the power consumption measurement unit 112 of the processor 110. Since the power consumption measurement unit 112 measures power consumption at predetermined time intervals, the second measurement value storage unit 312 may store only the latest measurement value. The computing unit 313 performs computations necessary for processing performed by the management apparatus 300, for example, computation such as subtraction of a value stored in the second measured value storage unit 312 from a value stored in the second upper limit storage unit 311. The addition value acquisition unit 314 refers to an addition value table 331 described later, and acquires an addition value corresponding to the difference between the upper limit value of power consumption calculated by the calculation unit 313 and the measurement value. The technical significance of the added value will be described later. The setting unit 315 adds the addition value acquired by the addition value acquisition unit 314 to the upper limit value stored in the second upper limit value storage unit 311, and adds the added value to the first upper limit of the power consumption control unit 80. Stored in the value storage unit 111. In the present specification, the “original upper limit value” is used to mean a value stored in the second upper limit value storage unit 311 of the management apparatus 300. Further, in this specification, the “control value” is added to the original upper limit value stored in the second upper limit value storage unit 311 and added to the first upper limit value storage unit 111 of the power consumption control unit 80. Is used to mean a certain value.

  The memory 330 stores an addition value table 331. Here, the technical significance of the added value will be described using an example of the added value table 331 shown in FIG. The added value table 331 defines the correspondence between the difference between the upper limit value of power consumption and the measured value and the added value corresponding to the difference. For example, when the upper limit value is 200 W and the measured value is 130 W, the difference between the upper limit value and the measured value is 70 W. In the example of the addition value table 331 illustrated in FIG. 7, when the difference value is 70 W, the corresponding addition value is 50 W. In this case, 250 W obtained by adding the added value 50 W to the upper limit value 200 W is calculated as the control value. The control value is stored in the first upper limit storage unit 111 of the power consumption control unit 80. The processor 110 recognizes this control value stored in the first upper limit storage unit 111, which is different from the original upper limit value, as the upper limit value, and controls the power consumption of the first information processing apparatus 100.

  In the example of the addition value table 331 shown in FIG. 7, the absolute value of the addition value is set larger as the absolute value of the difference between the upper limit value and the measurement value is larger. By setting the addition value in this way, adding it to the original upper limit value, and storing it in the first upper limit storage unit 111, in a state where the difference between the upper limit value and the measured value is large, a difference larger than the actual difference It is possible to make the power consumption control unit 80 recognize as if there is. As a result, the frequency can be changed with a change amount equal to or greater than the change amount specified in the frequency change amount table 131. When the difference between the upper limit value and the measured value becomes smaller, the power consumption control unit 80 can control power consumption using the original upper limit value.

  FIG. 8 is a process flowchart of the processor 310 included in the management apparatus 300. The process of FIG. 8 starts with process 1100. In process 1101, the second upper limit storage unit 311 stores the upper limit value of the power consumption of the processor 10. As the upper limit value, a value input to the management apparatus 300 from an external user terminal may be used, or a value determined by the setting unit 315 based on a balance with power consumption of other information processing apparatuses may be used. In process 1102, the second measurement value storage unit 312 accesses the processor 110, acquires a power measurement value from the power consumption measurement unit 112 or the first measurement value storage unit 113, and stores the acquired measurement value. In processing 1103, the calculation unit 313 subtracts the value stored in the second measured value storage unit 312 from the value stored in the second upper limit value storage unit 311. In processing 1104, the addition value acquisition unit 314 accesses the addition value table 331 and acquires an addition value corresponding to the difference value calculated by the calculation unit 313. In processing 1105, the calculation unit 313 calculates the control value by adding the acquired addition value to the original upper limit value stored in the second upper limit value storage unit 311. In processing 1106, the setting unit 315 stores the control value calculated by the calculation unit 313 in the first upper limit value storage unit 111 of the power consumption control unit 80. In processing 1107, the setting unit 315 notifies the power consumption control unit 80 of a completion notification indicating that storage of the control value in the first upper limit value storage unit 111 is complete.

  Next, FIG. 9 is used to show what transition behavior the power consumption of the first information processing apparatus 100 shows by setting the control value calculated by the management apparatus 300 in the first upper limit storage unit 111. I will explain. FIG. 9 is a graph showing the transition behavior of the power consumption of the first information processing apparatus 100. The graph shown in FIG. 9 shows time on the horizontal axis and power consumption on the vertical axis, as in FIG. The case where 200 W is set as the upper limit value of power consumption in the second upper limit value setting unit 311 is illustrated. Note that the plots indicated by white circles are the power consumption when the control of FIG. 8 is performed by the management apparatus 300, and the plots indicated by black circles are the same values as the plots shown in FIG. To display.

  First, at time T1, the measured value of the power consumption of the first information processing apparatus 100 is 130W. In this case, the difference between the upper limit value and the measured value is 70W. In the added value table 331, when the difference between the upper limit value and the measured value is 70 W, the added value is defined as 50 W. Therefore, the control value is 250 W obtained by adding 50 W as the addition value to 200 W as the upper limit value. Then, the control value 250 W is stored in the first upper limit storage unit 111 of the power consumption control unit 80.

  The difference between 250 W stored in the first upper limit storage unit 111 and the measured value 130 W is 120 W. Therefore, in the frequency change amount table 131, control is performed so that the frequency of the output clock of the PLL circuit 60 is increased by 200 MHz defined as the frequency change amount when the difference between the upper limit value and the measured value is 120 W. Further, in the frequency change amount table 131, when the difference between the upper limit value and the measured value is 120 W, the power consumption measurement interval is determined to be 10 seconds. Therefore, the first information is timed at time T2 10 seconds after time T1. The power consumption of the processing apparatus 100 is measured.

  Next, at time T2, the measured value of the power consumption of the first information processing apparatus 100 is 160W. In this case, the difference between the upper limit value and the measured value is 40W. In the added value table 331, the added value when the difference between the upper limit value and the measured value is 40 W is defined as 20 W. Therefore, 220 W obtained by adding 20 W as the addition value to 200 W as the upper limit value becomes the control value. Then, the control value 220 W is stored in the first upper limit storage unit 111 of the power consumption control unit 80. The difference between 220W stored in the first upper limit storage unit 111 and the measured value 160W is 60W. Therefore, in the frequency change amount table 131, control is performed so that the frequency of the output clock of the PLL circuit 60 is increased by 200 MHz defined as the frequency change amount when the difference between the upper limit value and the measured value is 60 W. Further, in the frequency change amount table 131, when the difference between the upper limit value and the measured value is 60 W, the power consumption measurement interval is determined to be 10 seconds, and therefore the first information at the timing of time T3 10 seconds after time T2. The power consumption of the processing apparatus 100 is measured.

  Furthermore, at time T3, the measured value of the power consumption of the first information processing apparatus 100 is 190 W. In this case, the difference between the upper limit value and the measured value is 10W. In the added value table 331, when the difference between the upper limit value and the measured value is 10 W, the added value is defined as 0 W. Therefore, in this case, the upper limit value of 200 W becomes the control value as it is. Then, the control value 200W is stored in the first upper limit storage unit 111 of the power consumption control unit 80. Thereafter, the same control is repeated, and the power consumption at each time after time T4 is measured.

  Here, the value of the white circle that is controlled based on the control value calculated by the management apparatus 300 indicates the power consumption that is closer to the upper limit value after the time T3 than the value of the black circle shown in FIG. This is because the amount of increase in frequency from time T2 to time T3 is 100 MHz in the black circle, but is 200 MHz in the white circle. In other words, in the control of the white circle, the clock frequency can be sharply increased by using the control value set higher than the original upper limit value as the temporary upper limit value. When the measured power consumption value approaches the original upper limit value, the control value is returned to the original upper limit value to control the final power consumption to the original upper limit value. Thus, in the present embodiment, the upper limit value given to the power consumption control unit 80 is temporarily higher than the original upper limit value when the value obtained by subtracting the measured value from the upper limit value of power consumption is large. When the difference is small, it is possible to reduce the convergence time of the power consumption to the upper limit value by giving the original upper limit value.

  In FIG. 9, the case where the measured value of power consumption is less than the upper limit value has been described. Even when the measured value of power consumption exceeds the upper limit value, the convergence time to the upper limit value of power consumption is shortened by the control of the management apparatus 300 shown in FIG. 8 and the control of the power consumption control unit 80 shown in FIG. It becomes possible.

  In the first information processing apparatus 100, an upper limit value and a lower limit value of values that can be stored in the first upper limit storage unit 111 may be determined. For example, when the maximum power consumption is provided to prevent the hardware included in the first information processing apparatus 100 from being destroyed by overheating, or the minimum power consumption is required to ensure the reliability of the arithmetic processing by the processor 10. It may be provided. When the control value given from the management apparatus 300 exceeds the maximum power consumption defined in the first information processing apparatus 100, the maximum power consumption is stored in the first upper limit value storage unit 111. When the control value given from the management device 300 is lower than the minimum power consumption defined in the first information processing device 100, the minimum power consumption is stored in the first upper limit value storage unit 111.

  As described above, in this embodiment, a method of realizing a sharp change in power consumption by giving the control value obtained by adding the added value to the original upper limit value to the power consumption control unit 80 as a temporary upper limit value. explained. This method is particularly effective when it is difficult to change the contents of the frequency change amount table 131. For example, a user who uses a commercially available server may not be able to change the power consumption control policy defined internally by the server or the specified content of the frequency change amount that is a part thereof. In such a case, it is possible to change the power consumption at a higher speed by connecting the management apparatus 300 described in the present embodiment to the server and controlling the control value given to the upper limit storage unit of the server. It becomes. In addition, this embodiment is also effective for server management in which the upper limit value of power consumption is switched between daytime and nighttime when the power rate is different.

<Second embodiment>
In the first embodiment, the method of changing the operating frequency of the processor 10 in order to control the power consumption of the first information processing apparatus 100 has been described. In the second embodiment, a method of changing the operating voltage of the processor 10 in addition to changing the operating frequency of the processor 10 will be described.

  In the second embodiment, when the operating frequency of the processor 10 is increased, the output voltage of the DC-DC converter 70 that supplies power to the processor 10 is also increased. This is because when the processor 10 is operated at a high frequency, it is necessary to increase the operating speed of elements such as an inverter included in the processor 10, and for this purpose, it is necessary to increase the voltage applied to the elements such as the inverter. is there. Conversely, when the operating frequency of the processor 10 is decreased, the output voltage of the DC-DC converter 70 is also decreased. This is because if the operating frequency of the processor 10 is lowered, the operation of elements such as an inverter is maintained even if the voltage is lowered, and the power consumption of the processor 10 can be suppressed.

  FIG. 10 is a diagram illustrating functional blocks of the processor 110 included in the power consumption control unit 80 and information stored in the memory 130. Blocks having the same functions as those described in the first embodiment and information having the same contents are denoted by the same reference numerals, and the description thereof is omitted. The processor 110 implements the function of each block illustrated in FIG. 10 by executing processing based on a predetermined program stored in the memory 130, the memory 30, the memory 330, or the memory of another information processing apparatus. The processor 110 functions as a frequency monitor unit 119 and a voltage monitor unit 120 in addition to the functions described in the first embodiment. The frequency monitor unit 119 monitors the frequency of the clock output from the PLL circuit 60. The voltage monitor unit 120 monitors the output voltage of the DC-DC converter 70. In addition to the information described in the first embodiment, the memory 130 stores a frequency-voltage correspondence table 132. The frequency-voltage correspondence table 132 is a table showing a correspondence relationship between the operating frequency of the processor 10 and the operating voltage.

  FIG. 11 is a diagram illustrating an example of the frequency-voltage correspondence table 132. In the example shown in FIG. 11, for example, the description in the first row means that 1.8 V is required as the operating voltage when the operating frequency of the processor 10 is 3.0 GHz. As shown in the frequency-voltage correspondence table 132 of FIG. 11, it is specified that the operating voltage increases as the operating frequency increases. Here, in order to suppress the occurrence of an error in the arithmetic processing in the processor 10 due to the frequency change, when increasing the frequency, the PLL circuit 60 and the DC-DC converter 70 are configured to increase the voltage before increasing the frequency. Is controlled. When the frequency is lowered, the PLL circuit 60 and the DC-DC converter 70 are controlled so as to lower the voltage after the frequency is lowered.

  FIG. 12 is a process flowchart of the processor 110 in the second embodiment. The processing flow of the processor 110 in the second embodiment is the same as the processing flow of the processor 110 shown in FIG. 4 from the processing 1000 to the processing 1006 and from the processing 1009. Therefore, in FIG. 12, only the process flow after the process 1006 is shown.

  After the setting unit 118 determines the frequency change amount in the process 1006, the frequency monitor unit 119 acquires the current clock frequency in the process 2001. Further, in the process 2001, the calculation unit 115 adds a frequency change amount to the current clock frequency and specifies a newly set frequency. In processing 2002, the determination unit 118 determines whether the frequency change amount is a positive value or a negative value. If it is determined in process 2002 that the frequency change amount is positive, the process proceeds to process 2003, and if it is determined that the frequency change amount is negative, the process proceeds to process 2007.

  In processing 2003, the setting unit 118 refers to the frequency-voltage correspondence table 132 and acquires a voltage setting value corresponding to the new clock frequency. In processing 2004, the setting unit 118 sets the output voltage of the DC-DC converter 70. In processing 2005, the determination unit 117 repeatedly determines whether or not the output voltage has reached the set value based on the monitoring result of the voltage monitor unit 120 until the set value is reached. If it is determined in process 2005 that the output voltage has reached the set value, the process proceeds to process 2006. In processing 2006, the setting unit 118 sets a new clock frequency in the PLL circuit 60, and proceeds to processing 1009 in FIG.

  If it is determined in process 2002 that the frequency change amount is negative, the setting unit 118 decreases the clock frequency setting value of the PLL circuit 60 by the frequency change amount acquired in process 1006 in process 2007. In processing 2008, the determination unit 117 repeatedly determines whether or not the clock frequency has reached the set value based on the monitoring result of the frequency monitor unit 119 until the set value is reached. If it is determined in process 2008 that the clock frequency has reached the set value, the process proceeds to process 2009. In processing 2009, the setting unit 118 refers to the frequency-voltage correspondence table 132 and acquires a new voltage setting value. In processing 2010, the setting unit 118 sets a new voltage setting value in the DC-DC converter 70, and the process proceeds to processing 1009 in FIG.

  When the operating frequency of the processor 10 is thus increased, the output voltage of the PLL circuit 60 is increased after the output voltage of the DC-DC converter 70 is first increased. On the other hand, when the operating frequency of the processor 10 is lowered, the output voltage of the DC-DC converter 70 is lowered after the frequency of the output clock of the PLL circuit 60 is lowered first. Such control can reduce the power consumption of the processor 10 while suppressing the occurrence of errors in the processor 10.

<Third embodiment>
As described in the first embodiment and the second embodiment, the management apparatus 300 increases the transition speed of the power consumption of the first information processing apparatus 100 and shortens the period until the power consumption converges to the upper limit value. It has a function. When the rate of increase in power consumption is increased, a state where the power consumption temporarily exceeds the upper limit value, a so-called overshoot state may occur. Further, when the rate of decrease in power consumption is increased, a state where the power consumption temporarily falls below the upper limit value, a so-called undershoot state may occur. The added value table 331 described in the first and second embodiments is preferably created so as to suppress overshoot and undershoot while shortening the period until the power consumption converges to the upper limit value. . Here, an example of a procedure for creating the addition value table 331 using the first information processing apparatus 100 and the management apparatus 300 described in the first and second embodiments will be described. Note that “preventing power consumption from overshooting” does not mean that power consumption overshooting is completely eliminated, but reducing the possibility of overshooting or reducing the amount of overshooting. It means that it works. The same applies to “preventing power consumption from undershooting”.

  First, a fixed upper limit value is stored in the first upper limit value storage unit 111 of the power consumption control unit 80 from the setting unit 315 of the management apparatus 300, and the transition behavior of the power consumption of the first information processing apparatus 100 is confirmed. For example, in a state where the first information processing apparatus 100 is operating at a power consumption of 140 W, an upper limit value of, for example, 200 W is input to the first upper limit value storage unit 111, and the measurement of the power consumption measurement unit 112 is performed with the upper limit value fixed. Get the result. Assuming that the transition behavior of the power consumption obtained in this way has the same content as the graph shown in FIG. 5, the following description will be made with reference to FIG.

  The following can be seen from the transition behavior of the power consumption shown in FIG. The difference between the upper limit value of power consumption (200 W) and the measured value (130 W) at time T1 is 70 W, the difference between the upper limit value of power consumption and the measured value (160 W) at time T2 is 40 W, and from time T1 to time T2 The amount of increase in power consumption is 30W. From this, in the first information processing apparatus 100, when the difference between the upper limit value and the measured value is 70 W, it is predicted that the frequency change amount table 131 is determined so that the power consumption increases by 30 W. And even if the power consumption is increased by 30 W in the transition from time T2 to time T3, the power consumption still does not reach the upper limit value. Therefore, it can be seen that even when the difference value between the upper limit value and the measurement value is 40 W, the frequency may be changed by the same amount as when the difference between the upper limit value and the measurement value is 70 W. Therefore, it is possible to create an addition value table 331 that defines the addition value when the difference value between the upper limit value and the measurement value is 40 W as the same value as the difference value 70 W at time T1, that is, 30 W.

  Moreover, the following can also be seen from the graph of FIG. The difference between the upper limit value of power consumption and the measured value (175 W) at time T3 is 25 W, the difference between the upper limit value of power consumption and the measured value (190 W) at time T4 is 10 W, and the consumption from time T3 to time T4. The increase in power is 15W. From this, in the first information processing apparatus 100, when the difference between the upper limit value and the measured value is 25 W, it is predicted that the frequency change amount table 131 is determined so that the power consumption increases by 15 W. If the power consumption is increased by 15 W even at the transition from time T3 to time T4, it is predicted that the upper limit value will be exceeded. Therefore, it is possible to create an addition value table 331 that defines an addition value of 0 W when the difference value between the upper limit value and the measurement value is 10 W.

  As described above, the addition value table 331 can be created by acquiring in advance the transition behavior of the power consumption in a state where the fixed value is stored in the first upper limit storage unit 111. In order to further improve the accuracy of the added value table 331, a plurality of transition behaviors of power consumption obtained by storing a plurality of different values in the first upper limit storage unit 111 may be used. In addition to the transition behavior of power consumption, the transition behavior of the operating frequency or the transition behavior of the operating voltage of the first information processing apparatus 100 may be acquired together, and the addition value table 331 may be created based on the result. If the contents of the frequency change amount table 131 can be acquired by accessing the first information processing apparatus 100, the addition value table 331 is created based on the description contents of the frequency change amount table 131. Also good.

<Fourth embodiment>
In the first to third embodiments, the method for controlling the power consumption of the first information processing apparatus 100 has been described. However, the management apparatus 300 can also control power consumption including other information processing apparatuses. is there. Here, an example of a method for controlling power consumption of two information processing apparatuses will be described.

  FIG. 13 is a hardware configuration example of a computer system in the fourth embodiment. The same components as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. In the computer system 2 in the fourth embodiment, a second information processing apparatus 200 is further added to the configuration shown in FIG. The second information processing device 200 is connected to the first information processing device 100 and the management device 300 via the network 500. The internal configurations of the first information processing apparatus 100 and the management apparatus 300 are the same as the contents shown in FIG. The second information processing device 200 includes substantially the same internal configuration as the first information processing device 100.

  FIG. 14 is a graph showing the transition behavior of the power consumption of the first information processing apparatus 100 and the second information processing apparatus 200. FIG. 14 shows the transition behavior when each of the first information processing apparatus 100 and the second information processing apparatus 200 is not controlled by the management apparatus 300 and is controlled with the upper limit value of power consumption being constant 200 W. . In FIG. 14, black circles indicate power consumption of the first information processing device, and crosses indicate power consumption of the second information processing device. The second information processing apparatus 200 shows a rising trajectory that consumes more power than the first information processing apparatus 100. One of the causes for the difference between the two trajectories is the difference in the contents of the frequency change amount tables of the two information processing apparatuses. In the fourth embodiment, the change speed of the power consumption of the first information processing apparatus 100 having a slow increase speed is increased. When the power consumption of the first information processing apparatus 100 exceeds the power consumption of the second information processing apparatus 200, the change speed of the power consumption of the first information processing apparatus 100 is reduced. For example, when the power consumption of the first information processing apparatus 100 is lower than the power consumption of the second information processing apparatus 200 in a state where the power consumption increases, the first upper limit value storage unit 111 controls the higher than the original upper limit value. Store the value temporarily. When the power consumption of the first information processing apparatus 100 becomes higher than the power consumption of the second information processing apparatus 200, the original upper limit value is stored in the first upper limit value storage unit 111. By performing the control in this way, it is possible to control the power consumption of the first information processing apparatus 100 so as not to exceed the upper limit value while making the rising trajectory of the power consumption of the first information processing apparatus 100 steep.

  FIG. 15 is a diagram illustrating information stored in the functional block of the processor 310 and the memory 330 of the management apparatus 300 used in this embodiment. The same components as those shown in FIG. 6 are denoted by the same reference numerals, and description thereof is omitted. The function of the processor 310 illustrated in FIG. 15 is substantially the same as the function of the processor 310 illustrated in FIG. 6, but the second measured value storage unit corresponding to the first information processing apparatus 100 is used as a measured value storage unit. In addition to 312, the third measurement value storage unit 3122 corresponding to the second information processing apparatus 200 is provided. Moreover, it further has the determination part 316 which determines which of the value stored in the 2nd measured value storage part and the value stored in the 3rd measured value storage part is larger.

  FIG. 16 is a process flowchart of the processor 310 included in the management apparatus 300 according to the fourth embodiment. The same processing contents as those shown in FIG. 8 are denoted by the same reference numerals, and description thereof is omitted. After the processing 1101, in the processing 1201, the second measured value storage unit 312 stores the measured power consumption value of the first information processing apparatus 100. In processing 1202, the third measurement value storage unit 3122 stores the measurement value of the power consumption of the second information processing device 200. In processing 1203, the determination unit 316 determines which of the value stored in the second measurement value storage unit 312 and the value stored in the third measurement value storage unit 3122 is larger. If it is determined in process 1203 that the value stored in the second measurement value storage unit 312 is smaller than the value stored in the third measurement value storage unit 3122, the process proceeds to process 1103. In processing 1103 to processing 1106, a value obtained by adding the added value to the original upper limit value is stored in the first upper limit storage unit 111. On the other hand, when it is determined in the process 1203 that the value stored in the second measurement value storage unit 312 is larger than the value stored in the third measurement value storage unit 3122, the process proceeds to the process 1204. In process 1204, the setting unit 315 stores the original upper limit value in the first upper limit value storage unit 111 and returns to the process 1201.

  With such control, the power consumption of the first information processing device 100 exceeds the power consumption of the second information processing device 200 while controlling the first information processing device 100 to increase the rate of increase in power consumption. And reduce the ascent rate. Thereby, it is suppressed that the power consumption of the 1st information processing apparatus 100 overshoots.

  The fourth embodiment can be applied not only to the case of increasing the power consumption of a plurality of information processing apparatuses but also to the case of decreasing the power consumption of a plurality of information processing apparatuses. For example, among the two information processing apparatuses, the second information processing apparatus 200 that controls the first information processing apparatus 100, which has a slow power consumption decrease rate, to increase the decrease speed, while having a fast power consumption decrease speed. When the power consumption falls below the power consumption, the power consumption reduction rate is reduced. In this case, the determination content of the process 1203 in FIG. 16 is changed to “is lower than the power consumption of the second information processing apparatus?”. By controlling in this way, undershoot of power consumption is suppressed.

  Here, circuit configurations of the PLL circuit 60 and the DC-DC converter 70 that can be commonly applied in all the embodiments will be exemplified. FIG. 17 is a circuit block diagram of the PLL circuit 60. The PLL circuit 60 includes a phase comparator 61, a charge pump circuit 62, a low pass filter 63, a voltage controlled oscillator 64, a first frequency divider 65, a second frequency divider 66, and a reference clock receiving terminal 67. And a clock output terminal 68 and a frequency setting signal receiving terminal 69. The phase comparator 61 compares the phase of the reference clock received via the reference clock receiving terminal 67 with the clock received from the first frequency divider 65, and outputs a phase difference signal corresponding to the phase difference to the charge pump circuit 62. Output. The charge pump circuit 62 outputs a voltage signal having a voltage corresponding to the received phase difference signal to the low-pass filter 63. The low pass filter 63 removes a high frequency component of the received voltage signal and outputs a voltage control signal to the voltage controlled oscillator 64. The voltage controlled oscillator 64 generates a first clock having a frequency corresponding to the received voltage control signal and outputs the first clock to the first frequency divider 65 and the second frequency divider 66. The second frequency divider 66 outputs a second clock obtained by dividing the first clock by a predetermined number as an output clock of the PLL circuit 60 via the clock output terminal 68. The output clock is supplied to the processor 10. On the other hand, the first frequency divider 65 divides the received first clock by a predetermined number and supplies it to the phase comparator 61. The frequency of the first clock is lock-controlled by a loop composed of the phase comparator 61, the charge pump circuit 62, the low-pass filter 63, the voltage control oscillator 64, and the first frequency divider 65.

  The frequency dividing ratio of the first frequency divider 65 and the frequency dividing ratio of the second frequency divider 66 can be set by a frequency setting signal received via the frequency setting signal receiving terminal 69. For example, when the frequency division ratio of the first frequency divider 65 is set to 100 and the frequency division ratio of the second frequency divider 66 is set to 2, if the frequency of the reference clock is 10 MHz, the voltage-controlled oscillator 64 outputs 1 GHz. A second clock of 500 MHz is output from the second frequency divider 66 as an output clock of the PLL circuit 60. When the frequency division ratio setting of the first frequency divider 65 is changed, the frequency lock of the first clock is released, so that a certain time is required until the frequency is again locked to the frequency corresponding to the new set value. On the other hand, when changing the frequency division ratio setting of the second frequency divider 66 without changing the frequency division ratio setting of the first frequency divider 65, the frequency lock of the first clock is maintained. is there. Therefore, the shift to the frequency corresponding to the new set value can be performed in a shorter time than when the frequency division ratio setting of the first frequency divider 65 is changed. In the above example, when it is desired to change the frequency of the output clock, the frequency division ratio setting of the second frequency divider 66 is first changed as coarse adjustment, and then the frequency division of the first frequency divider 65 is finely adjusted. Control may be performed to change the ratio setting.

  FIG. 18 is a circuit block diagram of the DC-DC converter 70. The DC-DC converter 70 includes a power supply 71, a switch element 72, a duty ratio control circuit 73, an inductor 74, a diode 75, a capacitor 76, a variable resistance element 77, a differential increase circuit 78, and a reference potential. And a generation circuit 79. The switch element 72 is repeatedly turned on and off at a predetermined duty ratio controlled by the duty ratio control circuit 73. A voltage corresponding to the duty ratio is output from the DC-DC converter 70. The output voltage can be changed by controlling the variable resistance element 77 with a voltage setting signal received via the voltage setting signal receiving terminal 712.

DESCRIPTION OF SYMBOLS 1, 2 Computer system 100 1st information processing apparatus 200 2nd information processing apparatus 300 Management apparatus 500 Network 10, 110, 310 Processor 30, 130, 330 Memory 40, 340 NIC
60 PLL circuit 70 DC-DC converter 80 Power consumption control unit 111 First upper limit value storage unit 112 Power consumption measurement unit 113 First measurement value storage unit 114 Timer unit 115 Calculation unit 116 Task manager 117 Determination unit 118 Setting unit 119 Frequency monitor Unit 120 voltage monitor unit 311 second upper limit value storage unit 312 second measurement value storage unit 3122 third measurement value storage unit 313 calculation unit 314 addition value acquisition unit 315 setting unit 316 determination unit 131 frequency change amount table 132 frequency-voltage correspondence Table 331 Addition value table 61 Phase comparator 62 Charge pump circuit 63 Low pass filter 64 Voltage controlled oscillator 65 First frequency divider 66 Second frequency divider 67 Reference clock reception terminal 68 Clock output terminal 69 Frequency setting signal reception terminal 71 Power supply 72 switch Element 73 Duty ratio control circuit 74 Inductor 75 Diode 76 Capacitor 77 Variable resistance element 78 Differential amplifier circuit 79 Reference potential generation circuit 711 Output terminal 712 Voltage setting signal reception terminal

Claims (8)

A first information processing apparatus including an arithmetic processing unit;
A power consumption control unit for controlling the operating frequency of the arithmetic processing unit;
A management device ;
Have
The management device
A first storage for storing a target value;
A first memory storing a first table that defines an added value indicating a larger value as the value obtained by subtracting the power consumption of the first information processing apparatus from the target value is larger;
An arithmetic unit that determines the addition value corresponding to the difference between the target value and the power consumption according to the first table, and calculates a control value by adding the addition value to the target value;
A setting unit for notifying the control value to the power consumption control unit ;
Including
The power consumption control unit
A second storage unit for storing the control value;
Based on the difference between the control value and the power consumption, a frequency change amount per unit time is specified, the operating frequency is changed by the frequency change amount per unit time , and the power consumption is stored in the second storage unit. Controlling the operating frequency so as not to exceed the stored value;
An information processing system characterized by this.   The control device identifies the control value such that a value obtained by subtracting the target value from the control value increases as a value obtained by subtracting the power consumption from the target value increases. Information processing system described in 1.   The power consumption control unit specifies the frequency change amount per unit time such that the greater the value obtained by subtracting the power consumption from the control value, the greater the frequency change amount per unit time. The information processing system according to claim 1 or 2. The power consumption control unit has a frequency change amount per unit time such that the greater the value obtained by subtracting the power consumption from the value stored in the second storage unit, the greater the frequency change amount per unit time. The information processing system according to claim 3, further comprising a second memory storing a second table that defines The information processing system further includes a power supply device,
The information processing system according to claim 1, wherein the power consumption control unit measures the power output from the power supply apparatus as the power consumption. A management device connected to a power consumption control unit that controls an operating frequency of an arithmetic processing unit included in the first information processing device,
The management device
A first storage for storing a target value;
A first memory storing a first table that defines an added value indicating a larger value as the value obtained by subtracting the power consumption of the first information processing apparatus from the target value is larger;
An arithmetic unit that determines the addition value corresponding to the difference between the target value and the power consumption according to the first table, and calculates a control value by adding the addition value to the target value;
A setting unit for notifying the control value to the power consumption control unit;
Have
The management device, the power consumption control unit,
Storing the control value in the second storage unit;
Based on the difference between the control value and the power consumption, the amount of frequency change per unit time is specified,
Change the operating frequency by the amount of frequency change per unit time,
The operating frequency is controlled so that the power consumption does not exceed the value stored in the second storage unit.
A management device characterized by that. Information using an information processing system having a first information processing device including an arithmetic processing unit, a power consumption control unit that controls an operating frequency of the arithmetic processing unit, and a management device connected to the power consumption control unit A processing method,
By the management device,
The added value corresponding to the difference between the target value and the power consumption according to a first table that defines an added value indicating a larger value as the value obtained by subtracting the power consumption of the first information processing apparatus from the target value is larger. Decide
Calculating a control value by adding the added value to the target value;
Notifying the power consumption control unit of the control value,
By the power consumption control unit,
Storing the control value in the second storage unit;
Based on the difference between the control value and the power consumption, specify the amount of frequency change per unit time,
Change the operating frequency by the amount of frequency change per unit time,
Controlling the operating frequency so that the power consumption does not exceed the value stored in the second storage unit;
An information processing method characterized by the above. On the computer,
The larger the value obtained by subtracting the power consumption of the first information processing apparatus from the target value, the larger the added value corresponding to the difference between the target value and the power consumption according to the first table that defines the added value indicating a larger value. Process to determine,
A process of calculating a control value by adding the added value to the target value;
Notifying the power consumption control unit of the control value, causing the power consumption control unit to store the control value in a second storage unit, and changing the frequency per unit time based on the difference between the control value and the power consumption A process for controlling the operating frequency such that the amount is specified, the operating frequency is changed by the amount of frequency change per unit time, and the power consumption does not exceed the value stored in the second storage unit;
A program for running

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