JP6185508B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a normally-off semiconductor device using a III-V compound semiconductor.

  The III-V compound semiconductor is expected to be capable of controlling a large current with a high breakdown voltage because it has a large dielectric breakdown electric field, a saturated electron density, and the like. In particular, research on semiconductor devices using gallium nitride (GaN) is progressing, and HEMTs (High Electron Mobility Transistors) using heterostructures of n-AlGaN / p-GaN are known, and an example of such semiconductor devices Is described in Patent Document 1.

  This type of HEMT has a heterostructure consisting of a p-GaN layer and an n-AlGaN layer stacked on the p-GaN layer. The AlGaN layer contains Al in its semiconductor crystal and has a larger band gap than the GaN layer. A drain electrode, a gate electrode, and a source electrode are formed on the surface side of the n-AlGaN layer. The drain electrode and the source electrode are formed at positions sandwiching the gate electrode.

  In this type of HEMT, if no gate voltage is applied to the gate electrode, the potential well formed by the n-AlGaN layer and the p-GaN layer exists above the Fermi level, so that 2DEG ( (2 Dimensional Electron Gas) is not generated. Therefore, a normally-off operation is realized. On the other hand, when a predetermined on-voltage is applied to the gate electrode, 2DEG is generated in the potential well. Since the electrons move in the potential well, the HEMT is turned on.

JP 2003-59946 A

However, since the 2DEG electrons move along the p-type GaN layer in the semiconductor device, there is a problem that the moving electrons are scattered by impurities and the on-resistance is large. In order to reduce the on-resistance, it is necessary to lower the impurity concentration of the p-GaN layer. However, if the impurity concentration of the p-GaN layer is lowered, the 2DEG potential approaches the Fermi level, and even in the off state, 2DEG Is likely to occur, and the normally-off operation becomes unstable. That is, in the semiconductor device having the above-described configuration, there is a trade-off relationship between reducing the on-resistance and ensuring a stable normally-off operation.
An object of the present invention is to break this trade-off relationship. That is, an object of the present invention is to provide a semiconductor device that can guarantee a stable normally-off operation and can reduce on-resistance.

One of the semiconductor device embodying the present invention, the first and second layers and the surface layer are laminated, the gate electrode on the surface side of the surface layer is formed.
The first layer is made of a first type GaN compound semiconductor. The second layer is made of a second conductivity type second type GaN compound semiconductor. The surface layer is composed of a GaN-based compound semiconductor of the first conductivity type. The surface layer is preferably composed of a second type GaN compound semiconductor. Than the band gap of the first type GaN-based compound semiconductor is larger band gap of the second type GaN-based compound semiconductor. In this semiconductor device, the second layer and the surface layer are substantially depleted when the on-voltage is not applied to the gate electrode.
The first layer may be an intrinsic semiconductor layer substantially free of impurities, or may be a layer containing impurities of the first conductivity type or the second conductivity type.
Here, the gate electrode formed on the surface side of the surface layer faces the surface side of the surface layer directly (typically Schottky connection) or indirectly (typically with an insulating material interposed). Can be formed).

  According to the semiconductor device described above, the depletion layer extends from the junction interface between the second conductivity type second layer and the first conductivity type surface layer toward the second layer in a state where the on-voltage is not applied to the electrode. As a result, the second layer and the surface layer are substantially depleted, and carriers are not supplied from the second layer or the surface layer to the potential well formed by the first layer and the second layer, thereby realizing a stable normally-off operation. It is easy to be done. In order to stabilize the normally-off operation, it is not necessary to keep the impurity concentration of the first layer high, and both a stable normally-off operation and a low on-resistance can be obtained.

In one manufacturing method embodying the present invention, are stacked first and second layers and the surface layer is formed with a gate electrode on the surface side of the surface layer, not on voltage is applied to the gate electrode Sometimes, a semiconductor device is manufactured in which the second layer and the surface layer are substantially depleted . This manufacturing method, the first layer comprising a first type GaN-based compound semiconductor, the second type having a larger band gap than the band gap of the first type GaN-based compound semiconductor and a second conductivity type A second layer growth step of epitaxially growing a second layer made of a GaN-based compound semiconductor; and a surface layer growth step of epitaxially growing a surface layer made of a GaN-based compound semiconductor of the first conductivity type on the second layer. In the surface layer growth step, it is preferable to epitaxially grow a surface layer made of the second type GaN compound semiconductor.
By employing the above manufacturing method, it is possible to obtain a normally-off a is realized easily semiconductor device by the surface layer depletion layer extends to the second layer.

  According to the present invention, it is not necessary to keep the impurity concentration in the carrier movement region of the III-V compound semiconductor high in order to ensure a stable normally-off operation, and a semiconductor capable of obtaining both a stable normally-off operation and a low on-resistance. The device can be manufactured.

1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment. (a) The energy band figure when the semiconductor device of 1st Example is OFF is shown. (b) An energy band diagram when the semiconductor device of the first embodiment is on is shown. Sectional drawing of the principal part of the semiconductor device of 2nd Example is shown. (a) The energy band figure at the time of OFF of the semiconductor device of 2nd Example is shown. (b) An energy band diagram when the semiconductor device of the second embodiment is on is shown. Sectional drawing of the principal part of the semiconductor device of 3rd Example is shown. (a) The energy band figure at the time of OFF of the semiconductor device of 3rd Example is shown. (b) The energy band figure at the time of ON of the semiconductor device of 3rd Example is shown. Sectional drawing of the principal part of the modification of 3rd Example is shown.

First, main features of the embodiment will be described.
The III-V compound semiconductor is preferably a gallium nitride (GaN) -based compound. Since the gallium nitride compound has a large band gap, a high-frequency device capable of operating at a high temperature can be realized. Since gallium nitride compounds are III-V compound semiconductors, they have the characteristics of high output and high breakdown voltage.

Embodiments will be described in detail below with reference to the drawings.
First Embodiment FIG. 1 schematically shows a cross-sectional view of a main part of a semiconductor device according to a first embodiment.
A buffer layer 24 made of gallium nitride (GaN) is formed on a substrate 22 made of sapphire (Al ₂ O ₃ ). For the substrate 22, silicon carbide (SiC) or gallium nitride (GaN) may be used instead of sapphire. A p-GaN layer 32 (an example of a first layer), an SI (Semi Insulated) -GaN layer 62 (an example of an intermediate layer), and an AlGaN layer 34 (an example of a second layer) are stacked on the buffer layer 24. ing.
An SI (Semi Insulated) -GaN layer 62 is interposed between the p-GaN layer 32 and the AlGaN layer 34. The p-GaN layer 32 is doped with magnesium (Mg). The AlGaN layer 34 contains aluminum (Al) in its semiconductor crystal and has a larger band gap than the p-GaN layer 32 and the SI-GaN layer 62.
A gate electrode 44 having a laminated structure of nickel (Ni) and gold (Au) is formed in direct Schottky contact with the center of the paper surface on the surface side of the AlGaN layer 34. A drain electrode 42 and a source electrode 46 having a laminated structure of titanium (Ti) and aluminum (Al) are formed in ohmic contact with the AlGaN layer 34 in a positional relationship on the left and right sides of the paper with the gate electrode 44 interposed therebetween. . The SI-GaN layer 62 is substantially formed of an intrinsic semiconductor layer.

Next, the operation of this semiconductor device will be described with reference to an energy band diagram. FIG. 2 shows an energy band diagram corresponding to line II-II in the cross-sectional view of the main part of FIG. The numbers shown in this energy band diagram correspond to the numbers of each layer in the cross-sectional view of the main part shown in FIG.
FIG. 2A shows a state where no voltage is applied to the gate electrode 44, and FIG. 2B shows a state where a positive voltage is applied to the gate electrode 44.
As shown in FIG. 2A, since the band gap of the AlGaN layer 34 is larger than that of the p-GaN layer 32 and the SI-GaN layer 62, the AlGaN layer 34 and the SI-GaN layer are based on the band gap difference. A potential well 52 is formed on the SI-GaN layer 62 side of the junction interface 62. The potential level of the potential well 52 exists above the Fermi level (E _F ) when the gate electrode 44 is 0 V, and 2DEG is not generated. Therefore, when the gate electrode 44 is 0 V, no current flows between the drain electrode 42 and the source electrode 46 of this semiconductor device. That is, it operates as normally-off.

On the other hand, as shown in FIG. 2B, when a positive voltage is applied to the gate electrode 44, the potential well 52 exists below the Fermi level. 2DEG occurs. The 2DEG moves two-dimensionally along the potential well 52 and flows between the drain electrode 42 and the source electrode 46. As a result, the semiconductor device is turned on.
At this time, 2DEG electrons move along the SI-GaN layer 62 having a low impurity concentration. Therefore, the probability that electrons are scattered by impurities is small, and a state in which the mobility of electrons is large is realized.

In the semiconductor device described above, an insulating film made of, for example, silicon oxide (SiO ₂ ) may be interposed between the AlGaN layer 34 and the gate electrode 44. By interposing the insulating film, when a positive voltage is applied to the gate electrode 44, a phenomenon in which a current flows from the gate electrode 44 toward the AlGaN layer 34 can be prohibited, and a stable operation can be realized. it can.
The AlGaN layer 34 is preferably doped with silicon (Si) as an n-type impurity. When the AlGaN layer 34 is n-type, it functions as an electron supply layer, so that the on-resistance can be further reduced. However, the AlGaN layer 34 may not be p-type and may be SI (Semi Insulated).

Next, a method for manufacturing this semiconductor device will be described with reference to FIG.
First, a sapphire substrate 22 is prepared. A buffer layer 24 is formed on the sapphire substrate 22 with a film thickness of about 50 nm by metal organic vapor phase epitaxy (MOCVD) at a low temperature. At this time, trimethylgallium (TMGa) can be preferably used as the gallium source, and ammonia gas (NH ₃ ) can be preferably used as the nitrogen source.
Next, the p-GaN layer 32 is formed to a thickness of about 0.5 μm on the buffer layer 24 by metal organic vapor phase epitaxy. At this time, trimethylgallium (TMGa) as a gallium raw material, ammonia gas (NH ₃ ) as a nitrogen raw material, and cyclopentadienyl magnesium (CP2Mg) as a dopant material can be suitably used.
Next, the SI-GaN layer 62 is formed with a film thickness of about 10 nm (preferably 5 to 15 nm) on the p-GaN layer 32 by metal organic vapor phase epitaxy. At this time, trimethylgallium (TMGa) can be preferably used as the gallium source, and ammonia gas (NH ₃ ) can be preferably used as the nitrogen source. Further, it is preferable that the impurity concentration of the SI-GaN layer 62 is 1 × 10 ¹⁷ cm ⁻³ or less. The film thickness of the SI-GaN layer 62 is sufficient if it satisfies the range of the potential well to be formed. The width of the potential well varies depending on the material used, but the thickness of the SI-GaN layer 62 is preferably in the range of 5 to 15 nm.
Next, the AlGaN layer 34 is formed with a film thickness of about 25 nm on the SI-GaN layer 62 by metal organic vapor phase epitaxy. At this time, trimethylaluminum (TMAl) can be preferably used as the aluminum source, trimethylgallium (TMGa) as the gallium source, and ammonia gas (NH ₃ ) as the nitrogen source. In the process of forming the AlGaN layer 34, monosilane (SiH ₄ ) may be simultaneously used as an n-type impurity, and the AlGaN layer 34 may be doped with the n-type impurity.

Next, a process of forming various electrodes on the surface side of the AlGaN layer 34 will be described.
First, titanium (Ti) and aluminum (Al) are sequentially deposited on the AlGaN layer 34. Thereafter, the drain electrode 42 and the source electrode 46 are patterned using a photo process and an etching technique. After patterning, heat treatment is performed at 550 ° C. for 30 seconds by RTA (Rapid Thermal Anneal) method. Thereby, the contact resistance of the drain electrode 42 and the source electrode 46 with respect to the AlGaN layer 34 is reduced, and ohmic contact is realized.
Next, the gate electrode 44 is formed using a lift-off method. That is, after a resist film is formed in a place other than where the gate electrode 44 is to be formed, nickel (Ni) and gold (Au) are sequentially deposited. Thereafter, the nickel (Ni) and gold (Au) formed on the resist film together with the resist film are peeled off. Thereby, the gate electrode 44 is formed in a desired positional relationship.
The semiconductor device of the first embodiment can be formed through the above steps.

  According to the above manufacturing method, since there is no band gap between the p-GaN layer 32 and the SI-GaN layer 62 formed on the buffer layer 24, distortion due to lattice mismatch or the like does not occur in the layer. In particular, since the SI-GaN layer 62 is formed with a clean crystal structure, the mobility of 2DEG electrons moving along the SI-GaN layer 62 is increased. Therefore, it is easy to realize a semiconductor device with low on-resistance.

Second Embodiment FIG. 3 is a schematic cross-sectional view of a main part of a semiconductor device according to a second embodiment.
A buffer layer 124 made of gallium nitride (GaN) is formed on a sapphire (Al ₂ O ₃ ) substrate 122. As the substrate 122, silicon carbide (SiC) or gallium nitride (GaN) may be used instead of sapphire. A p-GaN layer 132 (an example of a first layer) and an n-AlGaN layer 34 (an example of a second layer) are stacked on the buffer layer 124.
The n-AlGaN layer 134 is doped with silicon (Si). The n-AlGaN layer 134 contains aluminum (Al) in its semiconductor crystal and has a larger band gap than the p-GaN layer 132.
A gate electrode 144 having a laminated structure of nickel (Ni) and gold (Au) is formed in direct Schottky contact with the center of the n-AlGaN layer 34 on the surface side. A drain electrode 142 and a source electrode 146 having a laminated structure of titanium (Ti) and aluminum (Al) are formed in ohmic contact with each other in a positional relationship on the left and right sides of the paper with the gate electrode 144 interposed therebetween.

The polarity of the p-GaN layer 132 at the interface where the n-AlGaN layer 134 of this semiconductor device is joined to the p-GaN layer 132 is the N plane (V group plane). Therefore, the n-AlGaN layer 134 formed on the p-GaN layer 132 has a Ga interface (group III surface) at the junction interface. As a result, the spontaneous polarization electric field of the n-AlGaN layer 134 is generated in a direction away from the bonding interface with the GaN layer 132 (in this example, upward in the drawing).
On the other hand, as is well known, since the n-AlGaN layer 134 has a lattice constant smaller than that of the GaN layer 132, tensile strain is generated in the n-AlGaN layer 134 due to lattice mismatch. Based on this tensile strain, a piezoelectric polarization electric field is generated in the n-AlGaN layer 134 in the direction opposite to the growth direction. That is, the piezoelectric polarization electric field of the n-AlGaN layer 134 is generated in a direction toward the bonding interface with the GaN layer 132 (downward in the drawing in this example). In the second embodiment, the directions of the piezoelectric polarization electric field and the spontaneous polarization electric field are reversed.

The strengths of the spontaneous polarization electric field and the piezoelectric polarization electric field vary depending on the composition ratio of aluminum (Al) contained in the n-AlGaN layer 134, but the spontaneous polarization electric field is usually larger than the piezoelectric polarization electric field.
Therefore, when the spontaneous polarization electric field is configured to be in the opposite direction to the piezo polarization electric field as in this embodiment, the direction of the polarization electric field in which both are superimposed coincides with the direction of the spontaneous polarization electric field. That is, the direction of the polarization electric field in the n-AlGaN layer 134 is generated in a direction away from the bonding interface with the GaN layer 132 (in this example, on the paper).

In this type of known semiconductor device, the spontaneous polarization electric field of the semiconductor layer corresponding to the n-AlGaN layer 134 is generated in the direction of the junction interface with the GaN layer 132 formed therebelow. . That is, the polarization directions of the spontaneous polarization electric field and the piezoelectric polarization electric field are the same, and both are generated toward the direction of the junction interface with the GaN layer 132. For this reason, the direction of the polarization electric field in which the spontaneous polarization electric field and the piezoelectric polarization electric field are superimposed is naturally generated toward the direction of the junction interface with the GaN layer 132. In the conventional semiconductor device of this type, the spontaneous polarization electric field is generated in the direction of the junction interface with the GaN layer 132 for the following reason.
First, in this type of conventional semiconductor device, the GaN layer 132 is formed by using a metal organic vapor phase epitaxy (MOCVD) method. When the GaN layer 132 is formed using the metal organic vapor phase epitaxial (MOCVD) method, the growth always ends on the Ga plane. Therefore, since the n-AlGaN layer 134 formed thereabove grows from the N plane, the spontaneous polarization electric field is inevitably generated in the direction of the junction interface with the GaN layer 132.
Secondly, in the conventional technical idea, the directions of the spontaneous polarization electric field and the piezoelectric polarization electric field are aligned, and both are generated toward the direction of the junction interface with the GaN layer 132, thereby deepening the potential well formed in the vicinity of the interface. And there was a tendency to improve the density of 2DEG. For these reasons, in this type of conventional semiconductor device, a spontaneous polarization electric field is generated in the direction of the junction interface with the GaN layer 132.
However, when this configuration is adopted, there is a problem that the operation becomes unstable when the semiconductor device is caused to function as normally-off. In this embodiment, by adopting an arrangement relationship different from the arrangement relationship between the spontaneous polarization electric field and the piezo polarization electric field, which has been conventionally employed, a semiconductor device that performs a stable normally-off operation has been successfully realized.

Next, the operation of the semiconductor device of the second embodiment will be described with reference to an energy band diagram. FIG. 4 shows an energy band diagram corresponding to the IV-IV line in the cross-sectional view of the main part of FIG. The numbers shown in this energy band diagram correspond to the numbers of each layer in the cross-sectional view of the main part shown in FIG.
4A shows a state where no voltage is applied to the gate electrode 144, and FIG. 4B shows a state where a positive voltage is applied to the gate electrode 144. FIG.
As shown in FIG. 4A, since the band gap of the n-AlGaN layer 134 is larger than that of the p-GaN layer 132, the energy band is bent so that the Fermi level is matched at the junction interface between the two layers. . In this example, it can be seen that the energy band in the n-AlGaN layer 134 is formed to be inclined upward from the gate electrode 144 side toward the bonding interface with the GaN layer 132. This is because the direction of the polarization electric field in the n-AlGaN layer 134 is generated in a direction away from the junction interface with the GaN layer 132. This suppresses the occurrence of a phenomenon in which electron carriers are supplied from the n-AlGaN layer 134 toward the vicinity of the bonding interface with the GaN layer 132. Therefore, since 2DEG cannot be generated in the vicinity of the junction interface, no current flows between the drain electrode 142 and the source electrode 146 when the gate electrode 144 is 0V. That is, it operates as normally-off.

  On the other hand, as shown in FIG. 4B, when a positive voltage is applied to the gate electrode 144, the potential well 152 is generated and the potential level is present below the Fermi level. Therefore, 2DEG is generated in the potential well 152. 2DEG electrons move two-dimensionally along the potential well 152 and flow between the drain electrode 142 and the source electrode 146. As a result, the semiconductor device is turned on.

Instead of the above configuration, the n-AlGaN layer 134 may be formed of an intrinsic semiconductor layer that does not substantially contain impurities.
Similarly, the p-GaN layer 132 may be formed of an intrinsic semiconductor layer that does not substantially contain impurities. A semiconductor device with low on-resistance can be realized.

  Most of the manufacturing method of the second embodiment can utilize the manufacturing technique of the first embodiment. However, when forming the GaN layer 132, it is preferable to use, for example, a molecular beam epitaxial (MBE) method instead of the metal organic vapor phase epitaxial (MOCVD) method. In the metal organic vapor phase epitaxy (MOCVD) method, as described above, the crystal growth ends on the Ga plane. On the other hand, when the molecular beam epitaxy (MBE) method is used, crystal growth can be terminated on the N plane by appropriately adjusting the manufacturing conditions. As a result, the semiconductor device of the second embodiment can be manufactured.

Third Example FIG. 5 is a schematic cross-sectional view of a main part of a semiconductor device according to a third example.
A buffer layer 224 made of gallium nitride (GaN) is formed on a sapphire (Al ₂ O ₃ ) substrate 222. As the substrate 222, silicon carbide (SiC) or gallium nitride (GaN) may be used instead of sapphire. A p-GaN layer 32 (an example of a first layer), an n-AlGaN layer 34 (an example of a second layer), and a p-AlGaN layer 235 (an example of a surface layer) are stacked on the buffer layer 24. .
The p-GaN layer 232 and the p-AlGaN layer 235 are doped with magnesium (Mg). The p-AlGaN layer 235 and the n-AlGaN layer 233 contain aluminum (Al) in their semiconductor crystals and have a larger band gap than the p-GaN layer 232.
A gate electrode 244 having a laminated structure of nickel (Ni) and gold (Au) is formed in direct Schottky contact with the center of the paper surface on the surface side of the p-AlGaN layer 235. A drain electrode 242 and a source electrode 246 having a laminated structure of titanium (Ti) and aluminum (Al) are formed in ohmic contact with each other in a positional relationship on the left and right sides of the paper with the gate electrode 244 interposed therebetween.
Note that the p-GaN layer 232 may be formed of an intrinsic semiconductor layer that does not substantially contain impurities. In this case, since the impurity scattering with respect to 2DEG which moves along this layer is suppressed, the mobility of 2DEG can be increased.

Next, the operation of the semiconductor device of the third embodiment will be described with reference to an energy band diagram. FIG. 6 shows an energy band diagram corresponding to the VI-VI line of the main part sectional view of FIG. The numbers shown in this energy band diagram correspond to the numbers of the respective layers in the cross-sectional view of the main part shown in FIG.
6A shows a state in which no voltage is applied to the gate electrode 244, and FIG. 5B shows a state in which a positive voltage is applied to the gate electrode 244.
As shown in FIG. 6A, when no voltage is applied to the gate electrode 244, a depletion layer extends from both the p-GaN layer 232 and the p-AlGaN layer 235 in the n-AlGaN layer 233. Formed. Therefore, as shown in the energy band in the n-AlGaN layer 233 in FIG. 6A, the energy band is inclined, and the lower limit of the conductor exists above the Fermi level. Accordingly, since 2DEG cannot be generated in the vicinity of the junction interface with the p-GaN layer 232, no current flows between the drain electrode 242 and the source electrode 246 of the semiconductor device when the gate electrode 244 is 0V. That is, it operates as normally-off.

  On the other hand, as shown in FIG. 6B, when a positive voltage is applied to the gate electrode 244, the potential well 252 is generated, and the potential level exists below the Fermi level. Therefore, 2DEG is generated in the potential well 252. 2DEG electrons move two-dimensionally along the potential well 252 and flow between the drain electrode 242 and the source electrode 246. As a result, the semiconductor device is turned on.

In the semiconductor device of this embodiment, the n-AlGaN layer 233 and the p-AlGaN layer 235 are depleted by joining the n-AlGaN layer 233 and the p-AlGaN layer 235. As a result, the potential well formed by the p-GaN layer 232 and the n-AlGaN layer 233 exists above the Fermi level, and an extremely stable normally-off operation is realized.
In order to substantially completely deplete the n-AlGaN layer 233, it is preferable that the n-AlGaN layer 233 and the p-AlGaN layer 235 are set so as to satisfy the following relational expression.
Xd <(2εN a Vd / (qN d (Na + Nd))) ^1/2 ... (1)
Xa <(2εN d Vd / (qN a (Na + Nd))) ^1/2 ... (2)
Here, Xd is the thickness of the n-AlGaN layer 233, Nd is the donor density of the n-AlGaN layer 233, Xa is the thickness of the p-AlGaN layer 235, and Na is the thickness of the p-AlGaN layer 235. The acceptor density, Vd is the diffusion potential formed by the n-AlGaN layer 233 and the p-AlGaN layer 235, ε is the dielectric constant of the GaN semiconductor crystal, and q is the absolute value of the electronic charge.

Next, an example of a modification of the semiconductor device of the third embodiment is shown. FIG. 7 schematically shows a cross-sectional view of relevant parts of a semiconductor device according to the modification. In addition, about the same component as 3rd Example, the same number is attached | subjected and the description is abbreviate | omitted.
Compared with the semiconductor device of FIG. 5, the features of this modification can be clearly understood. In this modification, n-AlGaN layers 236 and 238 (an example of the second layer) corresponding to the n-AlGaN layer 233 (an example of the second layer) and the p-AlGaN layer 235 (the surface layer) of the third embodiment, Repeated p-AlGaN layers 237 and 239 (upper layers) are stacked. Specifically, a first p-AlGaN layer 237 is formed on the first n-AlGaN layer 236, and a second n-AlGaN layer 238 and a second p-AlGaN layer 239 are further stacked thereon. Is formed.

By adopting a stacked structure as in this modification, it is promoted that the first n-AlGaN layer 236 and the second n-AlGaN layer 238 corresponding to the electron supply layer are substantially depleted. be able to. Therefore, it is easy to realize a stable normally-off operation.
In addition, since the impurity concentration of the second layer in the stacked structure can be made relatively high within the range in which normally-off is realized, the electron supply capability can be increased and the on-resistance can be reduced.
In addition, by adopting the stacked structure, even when a positive voltage is applied to the gate electrode 244, the pn junction in the stacked structure is reverse-biased and current flow from the gate electrode 244 can be prevented. It is easy to realize a stable operation of the semiconductor device.

  The semiconductor device manufacturing method according to the third embodiment can be realized by using the manufacturing technique according to the first embodiment in most of the methods.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

22: Substrate 24: Buffer layer 32: p-GaN layer (an example of the first layer)
34: AlGaN layer (example of second layer)
42: Drain electrode 44: Gate electrode 46: Source electrode 62: SI-GaN layer (an example of an intermediate layer)

Claims (2)

The first layer and the second layer and the surface layer is laminated, a semiconductor device that operates in a normally-off where a gate electrode is in contact with the surface of the surface layer,
The first layer is composed of a first type GaN-based compound semiconductor,
The second layer is composed of an n-type second type GaN compound semiconductor,
The surface layer is composed of a p-type GaN compound semiconductor,
The band gap of the second type GaN compound semiconductor is larger than the band gap of the first type GaN compound semiconductor,
When no on-voltage is applied to the gate electrode, the second layer and the surface layer are substantially depleted,
A semiconductor device satisfying the following expressions (1) and (2):
Xd <(2εNaVd / (qNd (Na + Nd))) ^1/2 ... (1)
Xa <(2εNdVd / (qNa (Na + Nd))) ^1/2 ... (2)
Here, Xd is the film thickness of the second layer, Nd is the donor density of the second layer, Xa is the film thickness of the surface layer, Na is the acceptor density of the surface layer, and Vd is the second layer. And ε is the dielectric constant of the GaN-based compound semiconductor, and q is the absolute value of the electronic charge. The first layer, the second layer, and the surface layer are stacked, the gate electrode is in contact with the surface of the surface layer, and when the on-voltage is not applied to the gate electrode, the second layer and the surface layer are substantially A method of manufacturing a semiconductor device that operates in a normally-off state that is depleted,
On the first layer made of the first type GaN-based compound semiconductor, the second type made of the second type GaN-based compound semiconductor that is n-type and has a band gap larger than the band gap of the first type GaN-based compound semiconductor. A second layer growth step of epitaxially growing the two layers;
A surface layer growth step of epitaxially growing a surface layer made of a p-type GaN-based compound semiconductor on the second layer;
A gate electrode forming step of forming a gate electrode on the surface of the surface layer;
A manufacturing method characterized by satisfying the following expressions (1) and (2):
Xd <(2εNaVd / (qNd (Na + Nd))) ^1/2 ... (1)
Xa <(2εNdVd / (qNa (Na + Nd))) ^1/2 ... (2)
Here, Xd is the film thickness of the second layer, Nd is the donor density of the second layer, Xa is the film thickness of the surface layer, Na is the acceptor density of the surface layer, and Vd is the second layer. And ε is the dielectric constant of the GaN-based compound semiconductor, and q is the absolute value of the electronic charge.

Images