JP6166954B2 - Semiconductor light emitting element array and method for manufacturing semiconductor light emitting element array - Google Patents

Description

  The present invention relates to a semiconductor light emitting element array including a plurality of semiconductor light emitting elements, and a method for manufacturing the same.

  A semiconductor light emitting device using a nitride semiconductor such as GaN can emit ultraviolet light or blue light, and can emit white light by using a phosphor. Such a semiconductor light emitting element is used for illumination, for example.

  The semiconductor light-emitting element includes, for example, an n-type GaN layer, a photo-semiconductor laminate in which a light-emitting GaN-based active layer and a p-type GaN layer are laminated, and a voltage applied to the photo-semiconductor laminate in contact with the n-type and p-type GaN layers. And an electrode to which can be applied. Semiconductor light emitting devices are classified into a counter electrode type, a flip chip type, a junction down type, a via type, and the like according to the structure and arrangement position of the electrodes.

  A sapphire substrate is generally used as a substrate for growing a GaN-based optical semiconductor stack. However, since the sapphire substrate has a relatively low thermal conductivity and poor heat dissipation, it is not suitable as a support substrate for a device to which a large current is input. Therefore, in recent years, after growing a GaN-based optical semiconductor stack on a sapphire substrate, the optical semiconductor stack is bonded to a silicon substrate that is advantageous for heat dissipation, and the sapphire substrate is removed by laser lift-off or polishing. It has been developed (for example, Patent Document 1).

  When a semiconductor light emitting element is used for illumination that requires high light output, for example, a vehicular lamp, a plurality of semiconductor light emitting elements are generally used connected in series or in parallel (semiconductor light emitting element array). In this case, a region where the semiconductor light emitting element is disposed is a light emitting region, and a region defined by a gap between the semiconductor light emitting elements is a non-light emitting region. There may be a significant light intensity distribution (brightness unevenness) between the light emitting region and the non-light emitting region.

JP 2010-056458 A

  An object of the present invention is to suppress luminance unevenness that may occur in a semiconductor light emitting element array including a plurality of semiconductor light emitting elements.

According to one aspect of the present invention, a support substrate and first to third elements disposed on the support substrate, having light reflectivity and electrical conductivity, and sequentially arranged in one direction with a gap therebetween. A light-reflecting conductive layer; a first lower semiconductor layer having a first conductivity type disposed above the first and second light-reflecting conductive layers; a first active layer having light emission; and the first conductivity type First upper semiconductor layers having different conductivity types from each other are sequentially stacked, the first upper semiconductor layer is electrically connected to the first light-reflecting conductive layer, and the first lower semiconductor layer is the second light A first semiconductor light emitting element electrically connected to the reflective conductive layer; and a second conductive type disposed above the second and third light reflective conductive layers and spaced apart from the first semiconductor light emitting element. 2 lower semiconductor layer, light-emitting second active layer, and a conductivity type different from the third conductivity type The second upper semiconductor layer is sequentially stacked, the second upper semiconductor layer is electrically connected to the second light reflecting conductive layer, and the second lower semiconductor layer is electrically connected to the third light reflecting conductive layer. A second semiconductor light emitting element to be connected, a conductive layer disposed on the support substrate, electrically connected to the first or third light-reflecting conductive layer and having electrical conductivity, and disposed on the conductive layer A power feeding layer including a light absorbing layer having a light absorbing property , wherein the second light reflecting conductive layer includes the support substrate, the first and second light reflecting conductive layers, and the first semiconductor. At least one ventilation groove that is continuous with the tubular first hollow region surrounded by the light emitting element and communicates with the outside is provided, and the third light-reflecting conductive layer includes the support substrate, the second and second A three-light-reflective conductive layer and a tubular second cavity region surrounded by the second semiconductor light-emitting element Contiguous with a ventilation groove communicating with the outside is provided at least one semiconductor light-emitting device array, is provided.

According to another aspect of the present invention, a) a step of forming a device structure, comprising: a1) a first semiconductor layer having a first conductivity type on a growth substrate surface, an active layer having a light emitting property, and A sub-process of sequentially growing a second semiconductor layer having a second conductivity type different from the first conductivity type to form an optical semiconductor stack; a2) a first element region in the optical semiconductor stack; A second element region separated from the element region, a first conductive member is formed in a region of the first element region away from the second element region, and a second element in the first element region is formed. Forming a second conductive member in a region close to the region with a gap from the first conductive member; forming a third conductive member in a region of the second element region close to the first element region; In a region of the two-element region away from the first element region, a fourth conductive member is provided with a gap from the third conductive member. A sub step of forming, a3) in the optical semiconductor multilayer, the etching, a step including a substep, the physical separation of the first and second element regions, b) the support substrate surface, the light reflectivity And the first to third light-reflecting conductive layers that are electrically conductive and are arranged in one direction in order with a gap between them , and the first light-reflecting conductive layer or the third light-reflecting conductive layer. Forming a power feeding layer connected to the substrate, and forming a support; c) the first and second conductive members and the first and second light-reflecting conductive layers are in contact with each other; 4 is a step of bonding the device structure and the support to form a bonded structure such that the four conductive members and the second and third light-reflecting conductive layers are in contact with each other, A gap between the first and second conductive members and the first And the gap between the second light-reflecting conductive layer and the first element region of the optical semiconductor stack, the first and second conductive members, the first and second light-reflecting conductive layers, and the support substrate An enclosed tubular first cavity region is defined, and the gap between the third and fourth conductive members in the second element region and the gap between the second and third light-reflecting conductive layers overlap, The second element region of the optical semiconductor stack, the third and fourth conductive members, the second and third light reflecting conductive layers, and the tubular second cavity region surrounded by the support substrate are defined. Bonding the device structure and the support; d) removing the growth substrate from the bonding structure to expose the first semiconductor layer of the optical semiconductor stack; and e) the growth substrate. The paste removed In Align structure, the feed layer resist film is formed in a region other than the forming region where has a step of forming a light-absorbing layer having a light absorbing property to the power feed layer exposed from the resist film, the In the sub-step a2) or the step b), the first or second conductive member or the first or second light-reflecting conductive layer is continuous with the first cavity region defined in the step c). In addition, at least one ventilation groove communicating with the outside is provided, and the second cavity region defined in the step c) is provided in the third or fourth conductive member or the second or third light reflecting conductive layer. And a method for manufacturing a semiconductor light-emitting element array , in which at least one ventilation groove communicating with the outside is provided.

  Luminance unevenness that may occur in the semiconductor light emitting element array can be suppressed.

and, FIG. 1A is a plan view showing a device structure according to the first embodiment, FIGS. 1B to 1G are cross-sectional views showing how the device structure is manufactured, and FIG. 1H shows an optical semiconductor stack, p It is a top view which shows a side electrode and an n side electrode. FIG. 2A is a plan view showing a support according to the first embodiment, and FIGS. 2B and 2C are cross-sectional views showing how the support is manufactured. , and, FIG. 3A is a plan view showing the LED array according to the first embodiment, FIGS. 3B to 3H are cross-sectional views showing how the LED array is manufactured, and FIG. 3I shows an optical semiconductor stack, an electrode layer, 2 is a plan view showing a fusion layer and the like. FIG. FIG. 4A is a plan view showing a device structure according to the second embodiment, and FIG. 4B is a cross-sectional view showing an LED array according to the second embodiment. FIG. 5A is a plan view showing a support according to the third embodiment, and FIG. 5B is a cross-sectional view showing an LED array according to the third embodiment.

  The structure of the semiconductor light emitting element array (LED array) according to the first embodiment and the manufacturing method thereof will be described below. The LED array includes, for example, a plurality of semiconductor light emitting elements (LED elements) having a via structure. In the embodiment, an LED array including two LED elements electrically connected in series will be described. However, there may be two or more LED elements, or they may be electrically connected in parallel.

  The LED array according to the first embodiment mainly includes a step of manufacturing a device structure in which a plurality of LED elements are formed on a growth substrate (FIGS. 1B to 1G), and a step of manufacturing a support (FIGS. 2B and 2B). 2C), manufacturing the bonded structure by bonding the device structure and the support, removing the growth substrate from the bonded structure (FIGS. 3B to 3D), and a plurality of LED elements It is manufactured through a process of forming wiring for supplying electric power (FIGS. 3E to 3G). The plurality of LED elements are assumed to have the same configuration. Moreover, the relative size of each component shown in the figure is different from the actual one.

  FIG. 1A is a plan view showing the device structure 102. The device structure 102 has a configuration in which, for example, two LED elements 101 (first and second LED elements 101a and 101b) are arranged on the growth substrate 11 with a gap Ge therebetween. The planar shape of the LED element 101 is, for example, a rectangular shape having a side of about 0.5 mm to 1 mm. The width of the gap Ge (the interval between the LED elements 101) is, for example, about 80 μm.

  The LED element 101 includes an optical semiconductor stack 20 (first and second element regions 20a and 20b) including an n-type semiconductor layer, an active layer (light emitting layer), and a p-type semiconductor layer, and an n-type semiconductor layer of the optical semiconductor stack 20 An n-side electrode layer 61 electrically connected to the first n-side electrode layer 61a disposed on the first element region 20a and a second n-side electrode layer 61b disposed on the second element region 20b; A p-side electrode layer 62 (disposed on the first p-side electrode layer 62a disposed on the first element region 20a and the second element region 20b) electrically connected to the p-type semiconductor layer of the optical semiconductor stack 20 Second p-side electrode layer 62b). The n-side electrode layer 61 and the p-side electrode layer 62 constitute an electrode layer 60. The n-side electrode layer 61 and the p-side electrode layer 62 are arranged with a gap Gc so as not to be electrically short-circuited with each other.

  1B to 1G are cross-sectional views showing how the device structure 102 is manufactured. Hereinafter, a method for manufacturing the device structure 101 will be described with reference to FIGS. 1B to 1G.

First, as shown in FIG. 1B, a growth substrate 11 made of a C-plane sapphire substrate is prepared, and a GaN-based semiconductor (Al _x In _y Ga _z N, x + y + z is formed by using a metal organic chemical vapor deposition (MOCVD) method. = 1) is formed. Specifically, first, the growth substrate 11 is thermally cleaned to grow the buffer layer 21 made of GaN. Subsequently, an n-type semiconductor layer 22 made of n-type GaN doped with Si or the like, an active layer (light emitting layer) 23 made of a multiple quantum well structure including a well layer (InGaN) and a barrier layer (GaN), Mg, etc. A p-type semiconductor layer 24 made of p-type GaN doped with is sequentially grown to form an optical semiconductor stack 20.

  The growth substrate 11 is a single crystal substrate having a lattice constant matching with the GaN crystal, and has an absorption edge wavelength of the GaN crystal so that the growth substrate can be peeled off in a laser lift-off process (see FIG. 3C) as a subsequent process. It is selected from those transparent to certain 362 nm light. In addition to sapphire, spinel, ZnO, or the like can be used.

  In the optical semiconductor stacked layer 20, a strain relaxation layer having a superlattice structure including an InGaN layer and a GaN layer may be grown between the n-type semiconductor layer 22 and the active layer. Furthermore, a clad layer made of p-type AlGaN may be grown between the active layer 23 and the p-type semiconductor layer 24.

  Thereafter, the first and second element regions 20 a and 20 b are partitioned in the optical semiconductor stack 20. Then, in the first and second element regions 20a and 20b, for example, indium tin oxide (10 nm) / Ag (100 nm) / TiW (250 nm) / Ti (50 nm) / by electron beam evaporation or sputtering. A multilayer film made of Pt (100 nm) / Au (1000 nm) / Ti (30 nm) is formed, and patterned by a photolithography method, a lift-off method, or the like to form a p-side electrode 30 having a desired shape. The p-side electrode 30 preferably contains a light reflective member, such as Ag or Al.

  At this time, the p-side electrode 30 is patterned including an opening 30h for forming the via 20d in the optical semiconductor stack 20 in a later step (FIG. 1C). The opening 30h is formed in a region away from the second element region 20b in the first element region 20a, and is formed in a region close to the first element region in the second element region 20b.

  Next, as shown in FIG. 1C, a region corresponding to the opening 30h of the p-side electrode 30 of the optical semiconductor stack 20 is etched by a dry etching method using a resist mask and chlorine gas, thereby forming a via 20d. . The via 20d is formed through the p-type semiconductor layer 24 and the active layer 23, and the n-type semiconductor layer 22 is exposed on the bottom surface of the via 20d. As a result, a via region 20n corresponding to the via 20d and a flat region 20p other than the via region 20n are defined in the first and second element regions 20a and 20b of the optical semiconductor stack 20. Here, a state where one via 20d is formed in each element region of the optical semiconductor stack 20 is shown, but in reality, a plurality of vias 20d are provided (see FIG. 1H).

Next, as illustrated in FIG. 1D, an insulating layer 40 is formed to cover the inner surface of the p-side electrode 30 and the via 20 d of the optical semiconductor stack 20. First, a 300 nm-thickness SiO ₂ film is formed on the p-side electrode 30 and in the via 20d by sputtering or the like. Subsequently, the SiO ₂ film located on a part of the upper surface of the p-side electrode 30 and the bottom surface of the via 20 d is etched by a dry etching method using a resist mask and a CF 4 / Ar mixed gas, thereby forming the insulating layer 40. At this time, the n-type semiconductor layer 23 is exposed on the bottom surface of the via 20d. A part of the p-side electrode 30 is also exposed. As the insulating layer 40, in addition to SiO _2, it can be used SiN.

Next, as illustrated in FIG. 1E, an n-side electrode 50 that contacts the n-type semiconductor layer 22 is formed in the via 20 d of the optical semiconductor stack 20. First, Ti (1 nm) / Ag (200 nm) / Ti (100 nm) / Pt (200 nm) are formed on the insulating layer 40 and in the region where the n-type semiconductor layer 22 in the via 20d is exposed by electron beam evaporation or sputtering. ) / Au (200 nm). Subsequently, the metal multilayer film is patterned by a lift-off method or the like to form a columnar n-side electrode 50. The member used for the n-side electrode 50 preferably has a low contact resistance, for example, 1 × 10 ⁻⁴ Ωcm ² or less, and preferably has light reflectivity, for example, Ag or Al. The n-side electrode 50 may be formed integrally with the electrode layer 60 in the step shown in FIG. 1F.

  Next, as illustrated in FIG. 1F, the electrode layer 60 is formed on the insulating layer 40 and the n-side electrode 50. First, Ti (1 nm) / Ag (200 nm) / Ti (100 nm) / Pt (200 nm) / Au (200 nm) / Ti are formed on the insulating layer 40 and the n-side electrode 50 by electron beam evaporation or sputtering. A metal multilayer film made of (50 nm) / Pt (100 nm) / Au (100 nm) is formed. Subsequently, the metal multilayer film is patterned by a lift-off method or the like to form the electrode layer 60. Note that the Au layer (bonding layer) 71 formed on the uppermost layer of the electrode layer 60 is a layer bonded to the fusion layer 70 (FIG. 2C) constituting the support 103 in the subsequent step (FIG. 3B). The electrode layer 60 preferably contains a light reflective member, such as Ag or Al.

  The electrode layer 60 includes an n-side conductive region 61 (a first n-side conductive region 61a disposed in the first element region and a second n disposed in the second element region) electrically connected to the n-side electrode 50. Side conductive region 61b), p-side conductive region 62 electrically connected to p-type electrode 30 (first p-side conductive region 62a disposed in the first element region, and second p disposed in the second element region). A side conductive region 62b). The n-side conductive region 61 and the p-side conductive region 62 are patterned with a gap Gc so as not to be electrically short-circuited (see FIG. 1A). The width of the gap Gc (the interval between the n-side conductive region 61 and the p-side conductive region 62) is, for example, about 10 μm.

  Next, as shown in FIG. 1G, a part of the optical semiconductor stack 20 (gap Ge between the first and second element regions 20a and 20b) is etched by a dry etching method using a resist mask and chlorine gas. First, the second element regions 20a and 20b are physically separated. The separated first and second element regions 20 a and 20 b have a forward taper shape in which their planar cross-sectional areas gradually increase toward the growth substrate 11.

  Thus, the LED element 101 (first and second LED elements 101a and 101b) is completed, and the device structure 102 is completed.

  FIG. 1H shows the overall planar shape of the optical semiconductor stack 20, the p-side electrode 30, and the n-side electrode 50. A via region 20n (or via 20d, FIG. 1C) formed in the optical semiconductor stack 20 (first and second element regions 20a and 20b) is, for example, circular and is formed so as to be surrounded by the flat region 20p. ing. Further, for example, five via regions 20n are provided so as to be distributed in the surface of the optical semiconductor laminate 20. The planar shape of the via region 20n is not limited to a circular shape, and may be an elliptical shape or a rectangular shape. Further, the number of via regions 20n is not limited to five, and may be larger.

  The size, shape, distribution density, and the like of the via region 20n (or flat region 20p) affect the light emission intensity, luminance unevenness, color unevenness, and the like of the LED array (or LED element). The size, shape, distribution density, and the like of the via region 20n (or flat region 20p) are desirably adjusted as appropriate according to the application of the LED array (or LED element).

  Further, the n-side electrode 50 (a region indicated by an oblique line pattern with a relatively narrow pitch in the figure) is, for example, a circular shape, and is formed at a position corresponding to the via region 20 n of the optical semiconductor stack 20.

  Further, the p-side electrode 30 (a region indicated by a hatched pattern with a relatively wide pitch in the drawing) looks into the n-side electrode 50 (or the via region 20n) at a position corresponding to the flat region 20p of the optical semiconductor stack 20. It is patterned including a circular opening 30h that can be formed. The planar shape of the opening 30h is not limited to a circular shape, and may be an elliptical shape or a rectangular shape.

  FIG. 2A is a plan view showing the support 103. The support 103 has a structure in which a fusion-bonding layer 70 containing light reflective and electrically conductive members, for example, Au, is formed on the support substrate 12. The fusion layer 70 includes a plurality of fusion regions (first to third fusion regions 70a to 70c) arranged in one direction with a gap Gj so as not to be electrically short-circuited with each other, and the first and first fusion layers. And a power feeding region 70p formed continuously with the three fusion regions 70a and 70c.

  2B and 2C are cross-sectional views showing how the support 103 is manufactured. Hereinafter, with reference to FIG. 2B and FIG. 2C, the manufacturing method of the support body 103 is demonstrated.

First, as shown in FIG. 2B, a support substrate 12 having an insulating film 12a formed on the surface is prepared. For the support substrate 12, a member having a thermal expansion coefficient close to that of sapphire (7.5 × 10 ⁻⁶ / K) or GaN (5.6 × 10 ⁻⁶ / K) is preferably used. For example, Si, Ge, Mo, CuW, AlN, etc. can be used. When a Si substrate is used as the support substrate 12, for example, the insulating film 12a made of SiO ₂ is formed by thermally oxidizing the surface of the Si substrate.

  Next, as shown in FIG. 2C, a metal multilayer film made of Ti / Ni / Au / Pt / AuSn (Sn: 20 wt%) is formed on the support substrate 12 (insulating film 12a) by sputtering or the like. The fused layer 70 is formed by patterning using a photolithography method, a lift-off method, or the like. In the fusion layer 70, the first to third fusion regions 70a to 70c are patterned with a gap Gj therebetween, and the power feeding region 70p is formed continuously with the first and third fusion regions 70a and 70c. Patterned as shown.

  Note that the width of the gap Gj (the interval between the first and second fusion regions or the interval between the second and third fusion regions) is the same as that of the n-side conductive region 61 and the p-side conductive region 62 in the device structure 102. It is about the same as the width of the gap Gc (see FIG. 1F). Further, members used for the fusion layer 70 (the uppermost film of the metal multilayer film) and the electrode layer 60 joining layer 71 (see FIG. 1F) to be joined to the fusion layer 70 in a later step (FIG. 3B) are: Metals including Au—Sn, Au—In, Pd—In, Cu—In, Cu—Sn, Ag—Sn, Ag—In, Ni—Sn, etc. capable of fusion bonding, or Au capable of diffusion bonding A metal containing can be used.

  Thus, the support body 103 is completed.

  FIG. 3A is a plan view showing the LED array 100. The LED array 100 is manufactured by pasting together a device structure that has already been manufactured and a support, and then removing the growth substrate.

  The LED array 100 has a configuration in which LED elements 101 (first and second LED elements 101a and 101b) are arranged on a support substrate 12 with a gap Ge between them. The support substrate 12 and the first and second LED elements 101a and 101b are physically coupled via the fusion layer 70 (and the bonding layer 71, see FIG. 1G). The first and second LED elements 101a and 101b are electrically connected in series, for example. From the gap Ge between the first and second LED elements 101a and 101b, the second fusion region 70b of the fusion layer 70 having light reflectivity formed on the support substrate 12 can be seen.

  At both ends of the support substrate 12, a power feeding region 70p of the fusion layer 70 for supplying power to the first and second LED elements 101a and 101b is exposed. The width W of the power supply region 70p is, for example, about 160 μm. A light absorption layer 73 containing a light-absorbing member, such as Ti, is formed in a part of the region on the power supply region 70p. In addition, a wiring 74 for connecting to an external power source is provided in a region on the power feeding region 70p where the light absorption layer 73 is not formed.

  3B and 3G are cross-sectional views showing how the LED array 100 is manufactured. Hereinafter, a method for manufacturing the LED array 100 will be described with reference to FIGS. 3B and 3G. 3B and 3G correspond to the IIIB-IIIB cross section in FIG. 3A.

  First, as shown in FIG. 3B, the device structure 102 and the support body 103 that have already been manufactured are assembled into the electrode layer 60 (first and second n-side conductive regions 61a and 61b, and first and second p-side conductive regions 62a, 62b) and the fusion layer 70 (first to third fusion regions 70a to 70c) are arranged so as to face each other, and held for 10 minutes while being heated to 300 ° C. while being pressurized at 3 MPa. Subsequently, the electrode layer 60 (the uppermost bonding layer 71) and the fusion layer 70 are fusion bonded to each other by cooling to room temperature. Thereby, the bonded structure 104 is formed.

  Note that the device structure 102 and the support 103 are bonded so that the gap Gc of the electrode layer 60 in the device structure 102 and the gap Gj of the fusion layer 70 in the support 103 overlap. Thereby, a cylindrical (or tubular) hollow region Sv surrounded by the LED element 101 (the optical semiconductor stack 20 and the electrode layer 60), the fusion layer 70, and the support substrate 12 is defined.

  Further, the n-side conductive region 61a of the first LED element 101a is in contact with and electrically connected to the first fusion region 70a of the fusion layer 70, and the p-side conductive region 62a of the first LED element 101a is fused. It is in contact with and electrically connected to the second fusion region 70 b of the adhesion layer 70. The n-side conductive region 61b of the second LED element 101b is in contact with and electrically connected to the second fusion region 70b of the fusion layer 70, and the p-side conductive region 62b of the second LED element 101b is fused. It is in contact with and electrically connected to the third fusion region 70 c of the adhesion layer 70. Thus, the first and second LED elements 101a and 101b are electrically connected in series.

Next, as shown in FIG. 3C, the bonded structure 104 is irradiated with KrF excimer laser light (wavelength: 248 nm, irradiation energy density: 800 to 900 mJ / cm ² ) from the growth substrate 11 side. Pyrolyze part. As a result, the growth substrate 11 and the optical semiconductor stack 20 are separated.

  Thereafter, Ga generated by thermal decomposition of the buffer layer 21 (GaN crystal) is removed with hot water or the like, and the surface of the optical semiconductor stack 20 with hydrochloric acid, sodium hydroxide, or the like (a part of the buffer layer 21 and the n-type semiconductor layer 22). Etch. As a result, the n-type semiconductor layer 22 of the optical semiconductor stack 20 is exposed. Note that the first and second element regions 20 a and 20 b have reverse tapered shapes in which their planar cross-sectional areas gradually decrease toward the support substrate 12.

  Next, as shown in FIG. 3D, a so-called microcone structure layer (MC layer) 22a is formed on the exposed n-type semiconductor layer 22 surface. By forming the MC layer 22a having a fine concavo-convex structure on the light emitting surface (the surface of the n-type semiconductor layer 22) of the optical semiconductor stack 20, the light extraction efficiency of the LED element (or LED array) can be improved. The MC layer 22a can be formed, for example, by wet etching the surface of the n-type semiconductor layer 22 with a TMAH (phenyltrimethylammonium hydroxide) aqueous solution (temperature of about 70 ° C., concentration of about 25%).

  Next, as shown in FIGS. 3E and 3F, the light absorption layer 73 is formed in a part of the power feeding region 70p of the fusion layer 70 by using a sputtering method, a lift-off method, or the like.

  First, as shown in FIG. 3E, a photoresist (for example, AZ5214 manufactured by Clariant) is applied to the entire surface of the support substrate 12 so as to cover the first and second LED elements 101a and 101b and the fusion layer 70, and the temperature is set to 90 ° C. or lower. Pre-baking is performed in the atmosphere for about 90 seconds using the hot plate. Subsequently, using ultraviolet light (UV light), the photoresist is exposed to a pattern with a first exposure amount of 17 mJ. The exposed photoresist is subjected to reversal baking for about 90 seconds in an atmosphere at 120 ° C. to thermally crosslink the exposed portion. Thereafter, the entire surface of the photoresist is irradiated with UV light with a reverse exposure amount of 600 mJ. Further, a desired photoresist pattern RP is formed by immersing in a developing solution for 130 seconds and performing development processing. Note that the conditions of such a photolithography process can be changed as appropriate.

  Subsequently, a sputtering method is used to form a Ti film 73a having a thickness of about 20 nm, and thereafter, the photoresist pattern RP (at the same time, the Ti film 73a formed thereon) is removed (lifted off) to obtain a figure. As shown in 3F, the light absorption layer 73 is formed in a part of the power feeding region 70p of the fusion layer 70. In the power supply region 70p, it is preferable not to form the absorption layer 73 in the region where the wiring 74 is formed, from the viewpoint of adhesion to the wiring 74 formed in a later step (FIG. 3G). Further, the light absorption layer 73 may be formed of Cr, Ni, TiN or the like in addition to Ti.

Next, as shown in FIG. 3G, a surface protective film 80 made of SiO ₂ or the like is formed on the first and second LED elements 101a and 101b by a chemical vapor deposition (CVD) method or the like. After that, the region where the light absorption layer 73 of the power supply region 70p is not formed and the terminal of the external power source PS are connected by wiring 74 made of Au or the like by wire bonding. Thus, the LED array 100 is completed.

  After that, as shown in FIG. 3H, a fluorescent layer 90 covering the LED array 100 may be formed. For example, the fluorescent layer 90 drops a resin containing phosphor fine particles 91 that emits yellow light on the entire surface of the support substrate 12 so as to cover the first and second LED elements 101a and 101b, and then cures the resin. Can be formed.

  By supplying power to the plurality of LED elements through the wiring connected to the power feeding region of the fusion layer, the optical semiconductor stack of each of the plurality of LED elements electrically connected in series (particularly the active layer thereof) Current is injected into the. As a result, the optical semiconductor stack (especially its active layer) emits light, and light is emitted from the optical semiconductor stack (especially its n-type semiconductor layer). In the case of the embodiment, since the optical semiconductor stack is composed of a GaN-based semiconductor, blue light or ultraviolet light is emitted. White light can be emitted from the LED array by forming a fluorescent layer that emits yellow light so as to cover the plurality of LED elements. Such an LED array 100 can be used for a vehicular lamp, for example.

  FIG. 3I shows the overall planar shape of the completed LED array. In the drawing, the optical semiconductor stack 20 (first and second element regions 20a and 20b) is indicated by a broken line. The electrode layer 60 (the first and second n-side conductive regions 61a and 61b and the p-side conductive region and the first and second p-side conductive regions 62a and 62b) is indicated by a diagonal pattern having a relatively wide pitch. The light absorption layer 73 in the power feeding region 70p of the fusion layer 70 is indicated by a hatched pattern with a relatively narrow pitch.

  By supplying power from the wiring 74, light is emitted from the optical semiconductor stack 20 (first and second element regions 20a and 20b). At this time, in the LED array 100 surface, the area where the first and second LED elements 101a and 101b are arranged becomes a light emitting area, and the area where the LED elements are not arranged, that is, the first and second LED elements 101a, 101a, The gap region 101b and both end regions of the LED array 100 are non-light emitting regions.

  Between the first and second LED elements 101a and 101b, the second fusion region 70b of the fusion layer 70 having light reflectivity and containing, for example, Au is exposed. The fusion layer 70 (second fusion region 70b) exposed from between the first and second LED elements 101a and 101b covers most of the gap region Rg defined between the first and second LED elements 101a and 101b. It is preferable to occupy. For example, the area of the fusion layer 70 (second fusion region 70b) exposed from between the first and second LED elements 101a and 101b is preferably 80% or more of the area of the gap region Rg.

  When the fusion layer 70 (second fusion region 70b) does not occupy most of the gap region Rg, the support substrate from the optical semiconductor stack 20 (first and second element regions 20a, 20b) to the gap region Rg. Most of the light emitted in the 12 directions is absorbed by the support substrate 12 made of Si or the like and is not reflected on the light emitting surface side of the LED array 100. For this reason, significant luminance unevenness may occur between the light emitting region (first and second LED elements 101a and 101b) and the gap region Rg. Further, when the LED array 100 is provided with the light emitting layer 90 (see FIG. 3H), the balance between the light emission from the optical semiconductor stack 20 (for example, blue light) and the fluorescence by the fluorescent layer 90 (for example, yellow light) is And the gap region, there is a possibility that significant color unevenness occurs.

  On the other hand, when the fusion layer 70 (second fusion region 70b) occupies most of the gap region Rg, most of the light emitted from the optical semiconductor stack 20 toward the support substrate 12 in the gap region Rg. Is reflected to the light emitting surface side of the LED array 100 by the fusion layer 70 having light reflectivity. That is, the second fusion region of the fusion layer 70 exposed from between the first and second element regions 20a and 20b reflects incident light from the two directions by the first and second element regions 20a and 20b. For this reason, luminance unevenness that may occur between the light emitting region and the gap region is reduced. Further, when the light emitting layer 90 is provided in the LED array 100, the color unevenness that may occur between the light emitting region and the gap region can be reduced.

  Even when the light-reflecting fusion layer occupies most of the gap region, the gap between the light-emitting region and the gap region can be reduced if the LED elements adjacent to each other are extremely wide. Remarkably uneven brightness can occur. Therefore, it is preferable that the interval between the LED elements adjacent to each other is 80 μm or less.

  In addition, at both ends of the support substrate 12, a power feeding region 70p of the fusion layer 70 is formed so as to be exposed from the first and second LED elements 101a and 101b. In a region other than the region where the wiring 74 of the power supply region 70p is formed, it is preferable to form a light absorption layer 73 having light absorption, for example, containing Ti or the like.

  When the light absorption layer 73 is not formed in the power feeding region 70p, most of the light emitted from the optical semiconductor stack 20 in the direction of the power feeding region 70p is reflected on the light emitting surface side of the LED array. However, the power feeding region 70p is formed at the end of the support substrate 12, and can only reflect incident light from one direction by the first or second element region 20a, 20b. For this reason, luminance unevenness (color unevenness when the light emitting layer 90 is provided) may occur between the light emitting regions (first and second LED elements 101a and 101b) and the gap region Rg and the power supply region 70p.

  On the other hand, when the light absorption layer 73 is formed in the power supply region 70p, most of the light emitted from the optical semiconductor stack 20 in the direction of the power supply region 70p is absorbed by the light absorption layer 73. Not reflected on the surface side. For this reason, in the light emission surface of the LED array 100, although the light emission area is reduced, the emitted light intensity can be made uniform.

  As described above, the light-reflecting fusion layer (second fusion region) exposed from the gap between the LED elements adjacent to each other occupies most of the gap area defined by the gap between the LED elements. Accordingly, it is possible to suppress luminance unevenness (or color unevenness) that may occur in the light exit surface of the LED array. Moreover, it becomes possible to make the emitted light intensity of the LED array uniform by forming a light absorption layer in the fusion layer (power feeding region) formed by being exposed from the LED element at both ends of the support substrate.

  According to further studies by the present inventors, the shape of the hollow region Sv surrounded by the LED element 101 (the optical semiconductor stack 20 and the electrode layer 60), the fusion layer 70, and the support substrate 12 is cylindrical (or thru). In the case of (tubular), it has been found that the light absorption layer 73 may not be satisfactorily patterned in the step shown in FIGS. 3E and 3F (light absorption layer patterning step). For example, the Ti film 73a is formed in the vicinity of the opening Op of the cavity region Sv, and the first and second fusion regions 70a and 70b or the second and third fusion regions 70b and 70c of the fusion layer 70 are formed. Has been found to be electrically short-circuited.

  This is because the photoresist pattern PR covering the LED element 101 blocks the opening Op of the cavity region Sv, and the air confined in the cavity region Sv expands by pre-baking or the like, thereby rupturing the photoresist pattern PR. It is thought that it is to make it. The inventors of the present invention have studied the shape of the cavity region that can satisfactorily pattern the light absorption layer.

  FIG. 4A is a plan view showing a device structure 102a according to the second embodiment. The device structure 102a according to the second embodiment has the same configuration as the device structure 102 according to the first embodiment except for the planar shape of the electrode layer 60.

  In the device structure 102a according to the second embodiment, the electrode layer 60 (p-side conductive region 62) formed on the optical semiconductor stack 20 (first and second element regions 20a, 20b) is continuous with the gap Gc. Then, patterning is performed so as to include a groove portion (venting groove) 63 a communicating with the outside of the electrode layer 60. The groove 63a is formed in a direction intersecting with the gap Ge. The electrode layer 60 including the groove 63a can be easily formed by changing the mask pattern used in the process shown in FIG. 1F. The width of the groove 63a is preferably 1 μm or more.

  FIG. 4B is a cross-sectional view showing an LED array 100a manufactured using the device structure 102a. By forming the LED array 100a using the device structure 102a including the separation groove 63a in the electrode layer 60, the ventilation groove 63 leading to the outside of the LED element 101 is formed in the cavity region Sv with the opening Op (see FIG. 3I). ) Can be provided.

  By providing the air groove 63 communicating with the outside of the LED element 101 in the cavity region Sv, the expansion pressure of the air confined in the cavity region Sv is dispersed in the light absorption layer patterning step (FIGS. 3E and 3F). It is possible to suppress the burst of the pattern PR. Thereby, it becomes possible to pattern the light absorption layer 73 satisfactorily.

  FIG. 5A is a plan view showing a support 103b according to a third embodiment. The support 103b according to the third embodiment has the same configuration as that of the support 103 according to the first embodiment except for the planar shape of the fusion layer 70.

  In the support 103b according to the third embodiment, the fusion layer 70 (second and third fusion regions 70b and 70c) formed on the support substrate 12 has a recess (ventilation groove) 75a that is continuous with the gap Gj. It is patterned to include. The fusion layer 70 including the recess 75a can be easily formed by changing the mask pattern used in the step shown in FIG. 2C. The width of the recess 75a is preferably 1 μm or more.

  FIG. 5B is a cross-sectional view showing an LED array 100b manufactured using the support 103b. By forming the LED array 100b using the support body 103b including the recess 75a in the fusion layer 70, the ventilation groove 75 communicating with the outside of the LED element 101 is formed in the hollow region Sv with the opening Op (see FIG. 3I). ) Can be provided. The ventilation groove 75 provided in the fusion layer 70 may be formed so as not to protrude from the LED element 101 in plan view from the viewpoint of alleviating luminance unevenness (or color unevenness) in the gap Ge of the LED element 101. Would be preferred.

  By providing the ventilation groove 75 communicating with the outside of the LED element 101 in the cavity region Sv, the expansion pressure of the air confined in the cavity region Sv is dispersed in the light absorption layer patterning step (FIGS. 3E and 3F). It is possible to suppress the burst of the pattern PR. Thereby, it becomes possible to pattern the light absorption layer 73 satisfactorily.

  In addition, you may form the ventilation groove | channel (a groove part and a dent part) which continues to a cavity area | region and leads to the exterior of both an electrode layer and a fusion | melting layer. Further, only one ventilation groove may be formed in the hollow region. However, from the viewpoint of dispersion of expansion pressure due to air confined in the cavity region, it may be desirable to form more ventilation grooves in the cavity region.

  As mentioned above, although this invention was demonstrated along the Example, this invention is not limited to these. For example, the LED elements constituting the LED array may not have a via structure. That is, it is not a structure in which a via is formed in the optical semiconductor stack and the n-type semiconductor layer and the fusion layer exposed in the via are electrically connected, but the n-side electrode is formed on the surface (upper surface) of the n-type semiconductor layer. It may be a structure (counter electrode structure) formed and provided with a member that electrically connects the n-side electrode and the fusion layer through the side surface of the optical semiconductor stack. It will be apparent to those skilled in the art that other various modifications, improvements, combinations, and the like are possible.

DESCRIPTION OF SYMBOLS 11 ... Growth substrate, 12 ... Support substrate, 12a ... Insulating film, 20 ... Optical semiconductor lamination | stacking, 1st, 2nd element area | region ... 20a, 20b, 20p ... Flat area | region (convex area | region, p-type semiconductor layer exposure area | region), 20n ... via region (recessed region, n-type semiconductor layer exposed region), 21 ... buffer layer, 22 ... n-type semiconductor layer, 22a ... microcone structure layer, 23 ... active layer (light-emitting layer), 24 ... p-type semiconductor 30 ... p-side electrode, 40 ... insulating layer, 50 ... n-side electrode, 60 ... electrode layer, 61 ... n-side conductive region, 62 ... p-side conductive region, 63 ... ventilation groove (groove), 70 ... fusion Layer, 70a ... first fusion region, 70b ... second fusion region, 70c ... third fusion region, 70p ... feed region, 71 ... bonding layer, 73 ... light absorption layer, 74 ... wiring, 75 ... ventilation groove (Recessed portion), 80 ... surface protective film, 90 ... phosphor layer, 91 ... phosphor fine particles, 100 ... LE Array, 101 ... LED element, 102 ... device structure, 103 ... support, 104 ... bonding structure, Gc, Ge, Gj ... gap, Rg ... gap region, Sv ... cavity region, PR ... photoresist.

Claims (2)

A support substrate;
First to third light-reflecting conductive layers disposed on the support substrate, having light reflectivity and electrical conductivity, and sequentially arranged in one direction with a gap between each other;
A first lower semiconductor layer having a first conductivity type, a first active layer having light emission properties, and a conductivity type different from the first conductivity type are disposed above the first and second light reflecting conductive layers. First upper semiconductor layers are sequentially stacked, the first upper semiconductor layer is electrically connected to the first light-reflecting conductive layer, and the first lower semiconductor layer is electrically connected to the second light-reflecting conductive layer. A first semiconductor light emitting element connected to
A second lower semiconductor layer having a second conductivity type, disposed above the second and third light-reflecting conductive layers and spaced apart from the first semiconductor light-emitting element; a second active layer having light emission; and A second upper semiconductor layer having a conductivity type different from the third conductivity type is sequentially stacked, and the second upper semiconductor layer is electrically connected to the second light-reflecting conductive layer, and the second lower semiconductor layer A second semiconductor light emitting device, wherein the layer is electrically connected to the third light-reflecting conductive layer;
A conductive layer disposed on the support substrate, electrically connected to the first or third light-reflecting conductive layer and having electrical conductivity, and light having light absorption disposed on the conductive layer A feeding layer including an absorption layer;
With
The second light reflecting conductive layer is continuous with the tubular first cavity region surrounded by the support substrate, the first and second light reflecting conductive layers, and the first semiconductor light emitting element, and communicates with the outside. Is provided with at least one,
The third light reflecting conductive layer is continuous with the tubular second cavity region surrounded by the support substrate, the second and third light reflecting conductive layers, and the second semiconductor light emitting element, and communicates with the outside. A semiconductor light-emitting element array in which at least one is provided . a) forming a device structure comprising the steps of:
a1) Growing a first semiconductor layer having a first conductivity type, an active layer having a light emitting property, and a second semiconductor layer having a second conductivity type different from the first conductivity type on the growth substrate surface in order. A sub-process for forming an optical semiconductor stack;
a2) A first element region and a second element region spaced apart from the first element region are partitioned in the optical semiconductor stack, and a second element region in the first element region is separated from the second element region. A first conductive member is formed, and a second conductive member is formed in a region of the first element region close to the second element region with a gap between the first conductive member and the second element region in the second element region; A third conductive member is formed in a region close to one element region, and a fourth conductive member is formed in a region of the second element region away from the first element region with a gap from the third conductive member. Sub-process,
a3) a sub-process of physically separating the first and second element regions by etching in the optical semiconductor stack;
A process including:
b) First to third light-reflecting conductive layers having light reflectivity and electric conductivity on the surface of the support substrate and arranged in one direction in order with a gap therebetween , and the first light-reflecting conductive layer or Forming a power supply layer electrically connected to the third light-reflecting conductive layer to form a support;
c) The first and second conductive members are in contact with the first and second light-reflecting conductive layers, respectively, and the third and fourth conductive members are in contact with the second and third light-reflecting conductive layers, respectively. And bonding the device structure and the support to form a bonded structure,
The gap between the first and second conductive members and the gap between the first and second light-reflecting conductive layers overlap to form a first element region of the optical semiconductor stack, the first and second conductive members, A tubular first cavity region surrounded by the first and second light-reflecting conductive layers and the support substrate is defined, and a gap between the third and fourth conductive members in the second element region; The gap between the third light-reflecting conductive layers overlaps and is surrounded by the second element region of the optical semiconductor stack, the third and fourth conductive members, the second and third light-reflecting conductive layers, and the support substrate. Bonding the device structure and the support so that a tubular second cavity region is defined;
d) removing the growth substrate from the bonded structure to expose the first semiconductor layer of the optical semiconductor stack;
e) In the bonded structure from which the growth substrate has been removed, a resist film is formed in a region other than the region where the power feeding layer is formed, and the power feeding layer exposed from the resist film has light absorption. Forming an absorbent layer;
Have
In the sub-step a2) or the step b),
The first or second conductive member or the first or second light-reflecting conductive layer has at least one ventilation groove that is continuous with the first cavity region defined in step c) and communicates with the outside. Provided,
The third or fourth conductive member or the second or third light-reflecting conductive layer has at least one ventilation groove that is continuous with the second cavity region defined in the step c) and communicates with the outside. A method for manufacturing a semiconductor light emitting element array.

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