JP6068031B2 - Time synchronization apparatus, time synchronization method, and time synchronization program - Google Patents

Description

  The present invention relates to a time synchronization apparatus, a time synchronization method, and a time synchronization program, and in particular, can achieve high-accuracy time synchronization by reducing frequency fluctuations in an output clock signal even in an asymmetric delay environment where a network is stopped. The present invention relates to a time synchronizer and the like.

  In wireless communication, higher accuracy is required for time synchronization between wireless base stations. In particular, in LTE (Long Term Evolution), which is spreading as a next-generation high-speed wireless communication standard, time synchronization between wireless base stations is generally required to be 50 ppb or less, but depending on customers, it is 1 ppb or less. In some cases, high-accuracy synchronization of 100 millionth of a second or less is required.

  A protocol for realizing such high-precision time synchronization is IEEE 1588v2 established by IEEE (Institute of Electrical and Electronic Engineers) described in Non-Patent Document 1. This protocol was developed on the assumption of a symmetric delay environment in which the uplink and downlink delay configurations are the same, so in an asymmetric delay environment where the uplink and downlink delay configurations are not identical, From the beginning, it has been a problem that accurate time synchronization is difficult.

  In order to satisfy the strict requirement of time synchronization accuracy of “1 ppb” or less in IEEE 1588v2, it is necessary to remove the phase fluctuation corresponding to the phase noise of the packet signal. This phase fluctuation is hereinafter referred to as packet jitter wander. A component having a frequency of 10 Hz or more is referred to as packet jitter, and a component having a frequency of less than 10 Hz is referred to as packet wander. However, since there is no need to particularly distinguish them, they are collectively referred to as packet jitter / wander.

  The removal of the packet jitter / wander can be broadly divided into two methods, ie, a software removal method at the clock signal generation stage or a removal method through an external PLL (Phase Locked Loop). There are different ways.

  Of these, the removal method using the former software has been proposed by various vendors. However, as studied by the ITU-T (International Telecommunication Union-Telecommunication Standardization Sector), it is required only by the clock signal generation software. It is generally difficult to satisfy the performance of “1 ppb” or less. For this reason, a clock device such as BC (Boundary Clock) or TC (Transparent Clock) is required between the master device and the slave device.

  On the other hand, since the method of removing by the latter external PLL only needs to suppress the generated packet jitter / wander, there is no need to newly install a device such as BC or TC, and the cost of the entire network is low. Can be suppressed.

  FIG. 6 is an explanatory diagram showing the configuration of the time synchronization apparatus 901 according to the existing technology. The time synchronizer 901 includes an IEEE 1588v2 protocol unit 910, an IEEE 1588v2 packet detection unit 920, and a digital PLL unit 930. The IEEE 1588v2 protocol unit 910 receives a clock signal and a received packet from the outside by communication conforming to the IEEE 1588v2 protocol, and generates a slave time according to this.

  More specifically, the IEEE 1588v2 protocol unit 910 includes a slave time timer function 911 that generates a slave time based on an external clock, a packet capture function 912 that captures a received packet, and a slave time that calculates and outputs a time offset. A time adder 914 that adjusts the slave time by adding a time offset to the slave time generated by the calculation function 913 and the slave time timer function 911 is included.

  The slave time calculation function 913 calculates a time offset based on each numerical value calculated from the received packet and the slave time by the packet capture function 912, and outputs this to the time adder 914. The output from the time adder 914 is output to the digital PLL unit 930 as a time signal (1 pps) before removing the frequency fluctuation component.

  The digital PLL unit 930 has a packet jitter / wander removal performance due to an asymmetric delay environment and has a holdover function described later, thereby removing a frequency fluctuation component from the time signal (1 pps) output from the time adder 14. Then, a time signal satisfying the required accuracy within 1 ppb is output. In addition, the phase noise cutoff frequency of the digital PLL unit 930 is 1 mHz.

  The digital PLL unit 930 has a general complete digital PLL configuration with a holdover function. That is, a phase comparator 931, a digital amplifier 932, a complete integrator 933, a holdover buffer 934, a selector 935, a D / A converter 936, a VC-OCXO 937, and a frequency divider 938 are included.

  The phase comparator 931 detects the phase difference between the time signal (1 pps) output from the time adder 914 and the reproduction signal divided by the frequency divider 938 from the output signal from the VC-OCXO 937 described later. The digital amplifier 932 amplifies the primary loop signal output from the phase comparator 931. The complete integrator 933 performs amplification and integration processing on the secondary loop signal output from the digital amplifier 932. The holdover buffer 934 realizes a holdover function by averaging the output data from the complete integrator 933.

  In response to an output from a sync message stop monitor function 921 of an IEEE 1588v2 packet detection unit 920, which will be described later, the selector 935 selects an output signal from either the complete integrator 933 or the holdover buffer 934 as a subsequent D / D. Select whether to output to the A converter function 936. The D / A converter 936 converts the digital signal selected by the selector 935 into a voltage signal (analog signal).

  A VC-OCXO 937 (Voltage Controlled / Oven Controlled Crystal Oscillator) converts the voltage signal output from the D / A converter 936 into a frequency signal. The frequency divider 938 divides the output signal from the VC-OCXO 937, and this is finally output to the outside as a time signal that satisfies the required accuracy within 1 ppb, and at the same time, also input to the phase comparator 931. .

  The IEEE 1588v2 packet detection unit 920 includes a sync message stop monitor function 921. The sync message stop monitor function 921 monitors the received packet to detect whether or not the sync message is included in the received packet, and the selector 935 completes the integrator based on the detection result. A control signal for determining which output signal from 933 and the holdover buffer 934 is selected is output.

  More specifically, the selector 935 selects the output signal from the complete integrator 933 in a normal state, but a sync message is detected for a predetermined time given to the received packet in advance. If not, the sync message stop monitor function 921 causes the selector 935 to select the output signal from the holdover buffer 934, and if the sync message is detected again, the output signal from the complete integrator 933 is detected. Select to return to the normal state.

  FIG. 7 shows a case where the time synchronizer 901 shown in FIG. 6 assumes an ideal delay environment in which there is no delay in both the uplink (slave → master direction) and the downlink (master → slave direction). 4 is a graph showing a delay distribution of each packet. Here, it is assumed that the packet transmission interval = 125 ms. In this graph, since neither the uplink nor the downlink has any delay, all packets are distributed in the delay time “0 s”.

  FIG. 8 is a graph showing the result of fast Fourier transform (FFT) of the time offset frequency component calculated in the IEEE 1588v2 protocol unit 910 in the ideal delay environment shown in FIG. Since the packet transmission interval = 125 ms, that is, the signal frequency = 8 Hz, the maximum frequency of the frequency component is theoretically 4 Hz. This frequency component corresponds to the phase noise of the packet, that is, packet jitter wander.

  9 outputs the packet jitter wander shown in FIG. 8 through the digital PLL unit 930 where the phase noise cutoff frequency = 1 mHz (= 0.001 Hz, so the DC loop gain = 2π × 1 mHz = 0.00628). 5 is a graph showing frequency components. Here, the frequency components shown in FIG. 9 are integrated. The integration conditions are: sampling frequency: 8 Hz, number of FFT points: 65536 (the same conditions apply to the integration performed thereafter in this specification). Thus, the phase noise component (phase fluctuation amount) is about 30 ns.

  From the following formulas 1 to 3, which are known functions, the frequency variation (ppm) is obtained as the following formulas 4 to 5.

  From these relationships, the amount of frequency fluctuation (ppm) obtained from FIG. 9 is 0.00628 × 30 ns≈0.19 ppb. This satisfies the requirement “1 ppb” or less. However, this is a number assuming the “ideal delay environment in which there is no delay in both the uplink and the downlink” as described above.

  10 to 11 show the time synchronizer 901 shown in FIG. 8 is a graph showing a delay distribution of each packet when a delay environment at the time of load change according to “Test Case 12” of 8261 (Non-Patent Document 2) is assumed.

  The “test case 12” is a test case recommended by ITU-T as a load model assuming a delay environment in an actual line. More specifically, the load in the master-to-slave direction is set to 80%, and the slave → The load in the master direction is 20%. FIG. 10 shows the delay distribution in the master → slave direction, and FIG. 11 shows the delay distribution in the slave → master direction.

  FIG. 12 shows the ITU-T GG shown in FIGS. 8 is a graph showing a result of fast Fourier transform (FFT) of a frequency component of a time offset calculated in the IEEE 1588v2 protocol unit 910 in a delay environment according to 8261 “test case 12”. FIG. 13 is a graph showing the results obtained by integrating the frequency components shown in FIG. 12 under the same conditions as in FIG. Thus, the phase noise component (phase fluctuation amount) is about 50 ns.

  From this and Equation 5 above, the frequency variation (ppm) is 0.00628 × 50 ns≈0.31 ppb. This also satisfies the requirement “1 ppb” or less. As described above, when the packet jitter / wander component is caused only by the asymmetric delay environment, if a PLL circuit (digital PLL unit 930) having a phase noise cut-off frequency of 1 mHz is mounted, the requirement “1 ppb” or less is reduced. Can be satisfied.

  There are following patent documents as technical documents related to this. Among them, Patent Document 1 describes a timing synchronization device that realizes highly accurate time synchronization by a GPS signal. Patent Document 2 describes a time synchronization system in which a time difference is calculated from a first delay amount from slave to master and a second delay amount in the opposite direction to synchronize the time.

  Patent Document 3 describes a time synchronization network that synchronizes time by comparing clocks on the transmission network side and the GPS side. Patent Document 4 describes a clock synchronization system in which it is possible to verify on the slave side whether or not time synchronization is accurately achieved. Patent Document 5 describes a timing system in which an error between a clock signal received from a time server on a client side is calculated and converged to zero. Non-Patent Document 1 describes the IEEE 1588v2 protocol as described above, and Non-Patent Document 2 describes the load model test case as described above.

JP 2012-004914 A JP 2011-135482 A JP 2010-278456 A JP 2011-029918 A Special table 2011-525308 gazette

IEEE P1588 TM / D1, “Draft Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems”, June, 2007. "Recommendation G.8261 / Y.1361 (04/08): Timing and synchronization aspects in packet networks", International Telecommunication Union-Telecommunication Standardization Sector, 12.March, 2009.

  14 to 15 show the time synchronizer 901 shown in FIG. 10 is a graph showing a delay distribution of each packet when a delay environment at the time of load change according to 8261 “test case 15” is assumed.

  “Test case 15” is also a test case recommended by ITU-T as a load model that assumes a delay environment in an actual line, similar to “test case 12” described above. This is a load model in which the load is 40%, the load in the slave-to-master direction is 30%, and the network is stopped (10 seconds or 100 seconds). FIG. 14 shows the delay distribution in the master-to-slave direction, and FIG. 15 shows the delay distribution in the slave-to-master direction.

  FIG. 16 shows the ITU-T GG shown in FIGS. 10 is a graph showing a result of fast Fourier transform (FFT) of a frequency component of a time offset calculated in the IEEE 1588v2 protocol unit 910 in a delay environment according to 8261 test case 15. FIG. 17 is a graph showing the results obtained by integrating the frequency components shown in FIG. 16 under the same conditions as in FIGS. Thus, the phase noise component (phase fluctuation amount) is about 4354 ns.

  From this and Equation 5 above, the frequency variation (ppm) is 0.00628 × 4354 ns≈27 ppb. This does not satisfy the requirement “1 ppb” or less. This ITU-TG In a network environment where the network is in a stopped state in addition to the asymmetric delay environment as in “Test Case 15” of 8261, the requirement of “1 ppb” or less cannot be satisfied only by mounting the PLL circuit.

  The holdover buffer 934 (holdover function) built in the digital PLL unit 930 can remove packet jitter / wander caused by an asymmetric delay environment in a normal case. However, if the sync message cannot be received for a certain period of time, the holdover function is activated. If the sync message is received after that, the holdover function is stopped immediately. At this time, the time offset value is recalculated inside the IEEE 1588v2 protocol unit 910.

  Since the recalculation is performed, the output signal varies and the output frequency also varies. This is a phenomenon in which the frequency fluctuation in the output clock signal cannot satisfy the requirement of “1 ppb” or less in the “network environment in which the network is stopped in addition to the asymmetric delay environment” as described above. It is the cause. The technology that can solve this problem is not described in any of Patent Documents 1 to 5 and Non-Patent Documents 1 and 2 described above.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a time synchronization apparatus and time synchronization capable of realizing high-accuracy time synchronization by reducing frequency fluctuations to 1 ppb or less even in a network environment where an asymmetric delay environment is present and the network is stopped. A method and a time synchronization program are provided.

In order to achieve the above object, a time synchronization apparatus according to the present invention is a time synchronization apparatus that generates a time signal according to a clock signal and a received packet received from the outside and synchronizes frequency timings between a plurality of bases, A packet receiver that receives a communication packet according to a specific communication protocol and generates the time signal according to the communication packet, and a frequency fluctuation component is removed from the time signal according to a sync message included in the received packet by the packet receiver. The PLL circuit unit and the received packet and the time offset value inside the received packet are constantly monitored, and the elapsed time that the sync message has not been detected in the received packet is equal to or greater than a predetermined time limit. A packet detection unit for determining whether or not the PLL circuit unit is constant Comprising a holdover function of removing a packet jitter and wander caused by asymmetric delays environment from the time signal at a timing, the packet detecting unit, the holdover of the PLL circuit when the elapsed time exceeds the time limit A sync message stop monitoring function that forcibly activates the function, and a threshold value is calculated by dividing a required value of frequency stability given in advance from the outside by a DC loop gain specific to the PLL circuit unit, When the sync message is detected again in the received packet in a state where the holdover function is activated, the time offset value is stabilized when the stability of the time offset value is equal to or less than the threshold value. And a time offset stability monitoring function for stopping the holdover function based on That, characterized in that.

In order to achieve the above object, a time synchronization method according to the present invention is a time synchronization apparatus that generates a time signal according to a clock signal and a received packet received from the outside, and synchronizes frequency timings between a plurality of locations. A packet receiver receives a communication packet according to a specific communication protocol, the packet receiver generates the time signal according to the communication packet, and the time signal according to a sync message included in the received packet by the packet receiver The PLL circuit unit removes frequency fluctuation components from the received packet and the time offset value in the received packet is constantly monitored, and the elapsed time elapsed since the sync message could not be detected in the received packet. The packet detection unit determines whether or not the time limit is not less than a predetermined time, When the overtime exceeds the time limit, the packet detection unit forcibly holds a holdover function for removing packet jitter and wander caused by an asymmetric delay environment from the time signal at a fixed timing provided in the PLL circuit. The packet detection unit divides the required frequency stability value given from the outside in advance by the DC loop gain specific to the PLL circuit unit, and the holdover function is activated. When the packet detection unit detects the sync message in the received packet again when the time offset value is less than or equal to the threshold value and the time offset value is stable, detection unit determines to stop the holdover function, characterized in that.

In order to achieve the above object, a time synchronization program according to the present invention is a time synchronization apparatus that generates a time signal according to a clock signal and a received packet received from the outside and synchronizes frequency timings between a plurality of bases. The time synchronizer receives a communication packet according to a specific communication protocol, generates a time signal according to the communication packet, and from the time signal according to a sync (Sync) message included in the received packet by the packet receiver. A PLL circuit that removes frequency fluctuation components, and a packet detector that constantly monitors the received packet and a time offset value inside the received packet, and a processor provided in the packet detector includes the received packet The sync message has not been detected. A procedure for determining whether or not the elapsed time is greater than or equal to a predetermined time limit; when the elapsed time exceeds the time limit, the PLL circuit includes an asymmetric delay environment from the time signal at a fixed timing A procedure for forcibly activating a holdover function for removing packet jitter and wander caused by divergence , a threshold value obtained by dividing a required value of frequency stability given from the outside in advance by a DC loop gain specific to the PLL circuit section A procedure for calculating, a procedure for determining whether or not the sync message is detected again in the received packet in a state where the holdover function is activated, and when the sync message is detected again , when the stability of the time offset value is equal to or less than the threshold value, the procedure determines that the time offset value is stabilized, and Serial time offset value is equal to or to execute a procedure for stopping the holdover function after determining that stable.

  As described above, the present invention stops the holdover function after the time offset value is stabilized when the sync message is detected again in the received packet with the holdover function activated. Thus, packet jitter and wander caused by recalculation of the time offset value can be greatly suppressed.

  Thereby, even in a network environment where the network is in an asymmetric delay environment, the time synchronization apparatus has an excellent feature that frequency fluctuation can be reduced to 1 ppb or less and high-accuracy time synchronization can be realized. A time synchronization method and a time synchronization program can be provided.

It is explanatory drawing shown about the structure of the time synchronizer which concerns on this embodiment. It is explanatory drawing which shows an example of the radio | wireless communications system using the time synchronizer shown in FIG. 2 is a flowchart showing operations of the time synchronization apparatus shown in FIG. 1, particularly, operations of a sync message stop monitoring function and a time offset stability monitoring function. 4 is a graph showing frequency components of an output signal from the IEEE 1588v2 protocol unit when the operation shown in FIG. 3 is performed by the time synchronization apparatus shown in FIG. 1. 6 is a graph showing frequency components of an output signal when an output signal from the IEEE 1588v2 protocol unit shown in FIG. 4 is passed through a digital PLL unit. It is explanatory drawing shown about the structure of the time synchronizer which concerns on the existing technique. In the time synchronizer shown in FIG. 6, the delay of each packet assuming an ideal delay environment in which there is no delay in either the uplink (slave → master direction) or the downlink (master → slave direction). It is a graph which shows distribution of. 8 is a graph showing the result of fast Fourier transform (FFT) on the time offset frequency component calculated in the IEEE 1588v2 protocol unit in the ideal delay environment shown in FIG. 7. FIG. 9 is a graph showing frequency components output from the packet jitter / wander shown in FIG. 8 through a digital PLL unit having a phase noise cutoff frequency = 1 mHz. FIG. In the time synchronizer shown in FIG. It is a graph which shows distribution of the delay of the direction of a master-> slave of each packet at the time of assuming the delay environment at the time of the load change according to 8261 test cases. In the time synchronizer shown in FIG. It is a graph which shows distribution of the delay of each packet in the slave-to-master direction when assuming a delay environment at the time of load fluctuation according to 8261 test cases. ITU-T GG shown in FIGS. 10 is a graph showing a result of fast Fourier transform (FFT) of a frequency component of a time offset calculated in the IEEE 1588v2 protocol unit in a delay environment according to 8261 test case 12. FIG. 13 is a graph showing the results obtained by integrating the frequency components shown in FIG. 12 under the same conditions as in FIG. In the time synchronizer shown in FIG. 10 is a graph showing a delay distribution in the master-to-slave direction of each packet when a delay environment at the time of load change according to 8261 test case 15 is assumed. In the time synchronizer shown in FIG. 8 is a graph showing a delay distribution in the slave-to-master direction of each packet when a delay environment at the time of load change according to 8261 test case 15 is assumed. ITU-T GG shown in FIGS. 10 is a graph showing a result of fast Fourier transform (FFT) of a frequency component of a time offset calculated in the IEEE 1588v2 protocol unit in a delay environment according to 8261 test case 15. It is a graph which shows the result obtained by integrating the frequency component shown in FIG. 16 on the same conditions as FIG. 9 and FIG.

(Embodiment)
Hereinafter, the configuration of an embodiment of the present invention will be described with reference to FIG.
First, the basic content of the present embodiment will be described, and then more specific content will be described.
The time synchronization apparatus 1 according to the present embodiment is a time synchronization apparatus that generates a time signal according to a clock signal and a received packet received from the outside and synchronizes frequency timings between a plurality of bases. The time synchronizer 1 receives a communication packet in accordance with a specific communication protocol (IEEE 1588v2) and generates a time signal according to the communication packet (IEEE 1588v2 protocol unit 10), and a sink ( (Sync) message, the PLL circuit unit (digital PLL unit 30) that removes frequency fluctuation components from the time signal, and the received packet is constantly monitored, and the elapsed time that the sync (Sync) message cannot be detected in the received packet. Has a packet detection unit (IEEE 1588v2 packet detection unit 20) for determining whether or not is equal to or longer than a predetermined time limit. The PLL circuit unit 30 includes a holdover function (holdover buffer 34) that removes packet jitter and wander caused by the asymmetric delay environment from the time signal.

  Furthermore, the packet detection unit 20 has a sync message stop monitoring function 21 that forcibly activates the holdover function of the PLL circuit when the elapsed time exceeds the time limit, and the holdover function is activated. When a sync message is detected again in the received packet, it is determined whether or not the time offset value in the received packet is stable, and the holdover function is activated after determining that the time offset value is stable. And a time offset stability monitoring function 22 for stopping.

  Further, when the time offset stability monitor function 22 detects the sync message again, and the stability of the time offset value falls below a predetermined threshold (stable time threshold), the time offset value is set. A time offset stability monitoring function 22 for determining that the time is stable is provided. The time offset stability monitoring function 22 calculates a threshold value by dividing a required value of frequency stability given from the outside in advance by a DC loop gain specific to the PLL circuit unit.

By providing the above configuration, the time synchronizer 1 can reduce the frequency fluctuation to 1 ppb or less and realize highly accurate time synchronization.
Hereinafter, this will be described in more detail.

  FIG. 1 is an explanatory diagram showing the configuration of the time synchronization apparatus 1 according to the present embodiment. The time synchronizer 1 includes an IEEE 1588v2 protocol unit 10, an IEEE 1588v2 packet detection unit 20, and a digital PLL unit 30.

  FIG. 2 is an explanatory diagram showing an example of a wireless communication system 100 using the time synchronization apparatus 1 shown in FIG. The wireless communication system 100 is configured by connecting a master device 110 and a plurality of slave devices 120, 130... Via a packet communication network 140. Each of the master device 110 and the slave devices 120, 130,... Is a ground station of a public wireless communication network, and communicates with a large number of terminal devices (not shown).

  Then, a clock signal and a received packet are transmitted from the master device 110 to each of the slave devices 120, 130... Via the packet communication network 140. Each of the slave devices 120, 130... Is equipped with the time synchronization device 1 shown in FIG. 1, thereby generating and outputting a time signal (slave time) synchronized with the master device 110.

  Returning to FIG. 1, the IEEE 1588v2 protocol unit 10 receives a clock signal and a received packet from the outside by communication conforming to the IEEE1588v2 protocol, and generates a slave time in response thereto. Although the IEEE 1588v2 protocol includes not only received packets but also transmitted packets, the present embodiment does not particularly depend on transmitted packets. Therefore, only elements related to received packets are illustrated in FIG. 1, and elements related to transmitted packets are illustrated. I will not do it.

  More specifically, the IEEE 1588v2 protocol unit 10 includes a slave time timer function 11 that generates a slave-side time based on an external clock, a packet capture function 12 that captures a received packet, and a slave time that calculates and outputs a time offset. The calculation function 13 and the time adder 14 that adjusts the slave time by adding the time offset to the slave time generated by the slave time timer function 11 are included. The output from the time adder 14 is output to the digital PLL unit 30 as a time signal (1 pps) before removing the frequency fluctuation component.

  Here, the slave time calculation function 13 is a numerical value calculated from the received packet and the slave time by the packet capture function 12, that is, a sync message transmission time t1, a sync message arrival time t2, and a sync (Sync). A time offset is calculated based on the delay request (Deley_Req) message sending time t3 at the time of message arrival and the delay request (Deley_Req) arrival time t4, and this time offset is calculated by the time adder 14 and the IEEE 1588v2 packet detector 20 described later. Output to the stability monitor function 22.

  The digital PLL unit 30 has a packet jitter / wander removal performance caused by an asymmetric delay environment and has a holdover function described later, thereby removing a frequency fluctuation component from the time signal (1 pps) output from the time adder 14. Then, a time signal satisfying the required accuracy within 1 ppb is output.

  The digital PLL section 30 has a general complete digital PLL configuration with a holdover function. That is, it includes a phase comparator 31, a digital amplifier 32, a complete integrator 33, a holdover buffer 34, a selector 35, a D / A converter 36, a VC-OCXO 37, and a frequency divider 38.

  The phase comparator 31 detects the phase difference between the time signal (1 pps) output from the time adder 14 and the reproduction signal divided by the frequency divider 38 from the output signal from the VC-OCXO 37 described later. The digital amplifier 32 amplifies the primary loop signal output from the phase comparator 31. The complete integrator 33 performs amplification and integration processing on the secondary loop signal output from the digital amplifier 32. The holdover buffer 34 averages the output data from the complete integrator 33 to realize a holdover function.

  The selector 35 selects the output signal from either the complete integrator 33 or the holdover buffer 34 in accordance with the output from the sync message stop monitor function 21 of the IEEE 1588v2 packet detector 20 described later. Select whether to output to the A converter function 36. The D / A converter 36 converts the digital signal selected by the selector 35 into a voltage signal (analog signal).

  A VC-OCXO 37 (Voltage Controlled / Oven Controlled Crystal Oscillator) converts the voltage signal output from the D / A converter 36 into a frequency signal. The frequency divider 38 divides the output signal from the VC-OCXO 37, and this is finally output to the outside as a time signal satisfying the required accuracy within 1 ppb, and at the same time, also input to the phase comparator 31 described above. .

  The IEEE 1588v2 packet detection unit 20 includes a sync message stop monitoring function 21 and a time offset stability monitoring function 22. The sync message stop monitor function 21 monitors the received packet to detect whether or not the sync message is included in the received packet, and the selector 35 performs a complete integrator according to the detection result. A control signal for determining which of the output signals from 33 and the holdover buffer 34 is selected is output.

  The time offset stability monitoring function 22 detects the stability of the time offset signal output from the slave time calculation function 13, more specifically, the amount of fluctuation per unit time of the time offset signal (it is a known technique in itself). The detected stability is compared with a threshold value described later, and the comparison result is output to the sync message stop monitor function 21.

  The time offset stability monitoring function 22 is preliminarily inputted with a required value of frequency stability from the outside. Since the numerical value of the direct current loop gain is given in advance as a specific numerical value to the digital PLL unit 30, if the required value is divided by the direct current loop gain according to the above-described equation 4, the "stable time" when the time offset becomes stable Therefore, this is set as a “stable time threshold”.

  FIG. 3 is a flowchart showing the operation of the time synchronization apparatus 1 shown in FIG. 1, particularly the operations of the sync message stop monitoring function 21 and the time offset stability monitoring function 22. While the communication operation is being performed, the sync message stop monitor function 21 monitors the received packet to detect whether or not the sync message is included in the received packet (step S201). If a sync message is included in the received packet, normal operation continues.

  If a sync message is not detected in the received packet for a predetermined time (Yes in step S201), the sync message stop monitor function 21 sends a signal from the holdover buffer 34 to the selector 35. Is output to the subsequent D / A converter function 36 (step S202). If the sync message stop monitoring function 21 detects the sync message from the received packet again (step S203), the control message from the time offset stability monitoring function 22 is waited for.

  A “stable time threshold value” that stabilizes the time offset by dividing the required stability value by the DC loop gain from the DC loop gain given in advance as a numerical value unique to the digital PLL unit 30 according to the aforementioned equations 4 to 5. Become. The time offset stability monitor function 22 detects the stability of the time offset signal output from the slave time calculation function 13 and compares it with this “stable time threshold” (step S204).

  If the stability of the time offset signal is equal to or lower than the “stability time threshold” (Yes in step S204), the time offset stability monitor function 22 sends a control signal to notify the sync message stop monitor function 21 to that effect. To emit. In response to this, the sync message stop monitor function 21 issues a control signal that causes the selector 35 to select the output signal from the complete integrator 33 to be output to the subsequent D / A converter function 36 ( Step S205). The process returns to step S201.

  The process in step S202 has a meaning of forcibly operating the holdover function when a sync message is not detected from the received packet. In the processing of steps S203 to S205, the holdover function is released after the time offset is sufficiently stabilized after the sync message is restored. The purpose of this operation is to prevent the time information from being temporarily unstable because the time offset calculation in the IEEE 1588v2 protocol cannot catch up when the sync message is restored.

  The “stable time threshold value” used for the determination is that the 1 pps frequency stability previously input from the outside to the time offset stability monitoring function 22 is “1 ppb” or less, and the digital PLL unit 30 has the phase noise cutoff frequency “ In the case of a 1 mHz PLL, when “1 ppb” is divided by the PLL loop gain “0.00628” of the PLL from the above equation 4, “stable time threshold = 1 ppb / 0.00628 = 159 ns Can be calculated.

  The time offset stability monitor function 22 forcibly operates the sync message stop monitor function 21 in step S202, and after the sync message is detected again and the time offset signal becomes stable, the holdover function. To cancel.

  FIG. 4 is a graph showing frequency components of an output signal from the IEEE 1588v2 protocol unit 10 when the operation shown in FIG. 3 is performed in the time synchronization apparatus 1 shown in FIG. FIG. 5 is a graph showing frequency components of the output signal when the output signal from the IEEE 1588v2 protocol unit 10 shown in FIG. 4 is passed through the digital PLL unit 30.

  The phase noise component calculated by integrating the frequency components in FIG. 5 is about 59 ns. That is, it is possible to calculate “frequency fluctuation amount = 0.00628 × 59 ns≈0.37 ppb” from Equation 5 described above. That is, the required 1 pps frequency stability “1 ppb or less” is satisfied.

  Here, for example, when the requirement item is not “1 ppb” but may be more general “50 ppb”, “stable time = 50 ppb / 0.00628≈8 μs” can be calculated in the same manner as described above. As described above, in this embodiment, it is possible to set a stable time corresponding to various customer requirements and operate according to the stable time. Further, even when the phase noise cutoff frequency of the digital PLL unit 30 is other than “1 mHz”, a DC loop gain, which is a numerical value unique to the digital PLL unit 30, is obtained from the above-described equations 4 to 5, and then Can be applied.

  The sync message stop monitoring function 21 and the time offset stability monitoring function 22 may be configured in hardware by a logic operation circuit or the like, or may be configured in software by a program operating on a microprocessor. May be.

(Overall operation of the embodiment)
Next, the overall operation of the above embodiment will be described.
The time synchronization method according to the present embodiment is a time synchronization apparatus 1 that generates a time signal in accordance with a clock signal and a received packet received from the outside and synchronizes frequency timings between a plurality of bases, according to a specific communication protocol. The packet receiver 10 receives a communication packet, the packet receiver generates a time signal according to the communication packet, and the PLL circuit unit 30 fluctuates in frequency from the time signal according to a sync message included in the received packet by the packet receiver. The component is removed, the received packet and the time offset value inside the received packet are constantly monitored, and the elapsed time that has passed since the sync message could not be detected in the received packet is longer than the time limit given in advance. Whether or not the packet detection unit 20 determines (step S201 in FIG. 3) and the elapsed time When the time limit is exceeded, a holdover function that removes packet jitter and wander caused by an asymmetric delay environment from a time signal is forcibly activated at a fixed timing, which is included in the PLL circuit of the packet detection unit (see FIG. 3). In step S202), it is determined whether or not the packet detection unit has detected the sync message in the received packet again with the holdover function activated (step S203 in FIG. 3), and the sync message. Is detected again, the packet detector determines whether or not the time offset value inside the received packet is stable (step S204 in FIG. 3), and after determining that the time offset value is stable, the packet detector Stops the holdover function (FIG. 3, step S205).

  Further, when the stability of the time offset value is equal to or less than a predetermined threshold value in the processing of FIG. 3 and step S204, it is determined that the time offset value is stable. The threshold value is calculated by dividing the required frequency stability value given from the outside in advance by the DC loop gain specific to the PLL circuit unit.

Here, each of the above-described operation steps may be programmed to be executable by a computer, and these may be executed by a processor included in the packet detection unit 20 that directly executes each of the steps. The program may be recorded on a non-temporary recording medium, such as a DVD, a CD, or a flash memory. In this case, the program is read from the recording medium by a computer and executed.
By this operation, this embodiment has the following effects.

  This embodiment is a PLL circuit with a holdover function that constantly monitors IEEE 1588v2 packets and has a packet jitter / wander elimination performance caused by an asymmetric delay environment when the Sync message is stopped. The holdover function is forcibly operated. . When the Sync message is detected again, the holdover function is stopped after the time offset value is stabilized. More specifically, the “stability time threshold” obtained by detecting the amount of fluctuation per unit time of the time offset signal as the stability, and dividing the detected stability by dividing the required value of the frequency stability by the DC loop gain. If the stability is equal to or less than the stable time threshold, it is determined that the time offset value is stable.

  Thereby, even in a network environment in which the present embodiment is an asymmetric delay environment and the network is stopped, the occurrence of packet jitter and wander due to recalculation of the time offset value is greatly suppressed, A required value of time synchronization accuracy of “1 ppb” or less can be realized.

  The present invention has been described with reference to the specific embodiments shown in the drawings. However, the present invention is not limited to the embodiments shown in the drawings, and any known hitherto provided that the effects of the present invention are achieved. Even if it is a structure, it is employable.

  Regarding the embodiment described above, the main points of the new technical contents are summarized as follows. In addition, although part or all of the said embodiment is summarized as follows as a novel technique, this invention is not necessarily limited to this.

(Supplementary Note 1) A time synchronization device that generates a time signal according to a clock signal and a received packet received from the outside, and synchronizes frequency timing between a plurality of bases,
A packet receiver that receives a communication packet according to a specific communication protocol and generates the time signal according to the communication packet;
A PLL circuit that removes frequency fluctuation components from the time signal in accordance with a sync message included in a packet received by the packet receiver;
Whether the received packet and the time offset value inside the received packet are constantly monitored, and whether the elapsed time that the sync message has not been detected in the received packet is equal to or greater than a predetermined time limit A packet detection unit for determining
A time synchronization apparatus, wherein the PLL circuit unit includes a holdover function for removing packet jitter and wander caused by an asymmetric delay environment from the time signal at a fixed timing.

(Supplementary Note 2) The packet detection unit includes:
A sync message stop monitoring function for forcibly starting the holdover function of the PLL circuit when the elapsed time exceeds the time limit;
When the sync message is detected again in the received packet with the holdover function activated, it is determined whether or not the time offset value is stable, and the time offset value is stable. The time synchronization apparatus according to claim 1, further comprising: a time offset stability monitoring function that stops the holdover function after determining that it has occurred.

(Supplementary Note 3) When the time offset stability monitor function detects the sync message again, and the stability of the time offset value falls below a predetermined threshold value, the time offset value is The time synchronizer according to appendix 2, wherein the time synchronizer is determined to be stable.

(Supplementary Note 4) The time offset stability monitoring function calculates the threshold value by dividing a required value of frequency stability given from outside in advance by a DC loop gain specific to the PLL circuit unit. The time synchronization apparatus according to appendix 3.

(Supplementary Note 5) In a time synchronization device that generates a time signal according to a clock signal and a received packet received from the outside, and synchronizes frequency timing between a plurality of bases,
The packet receiver receives a communication packet according to a specific communication protocol,
The packet receiver generates the time signal according to the communication packet,
The PLL circuit unit removes the frequency fluctuation component from the time signal according to the sync message included in the packet received by the packet reception unit,
Whether or not the elapsed time that has passed without being able to detect the sync message in the received packet by constantly monitoring the received packet and the time offset value inside the received packet is greater than or equal to a predetermined time limit Is determined by the packet detector,
When the elapsed time exceeds the time limit, the packet detector includes a holdover function for removing packet jitter and wander caused by an asymmetric delay environment from the time signal at a fixed timing, which is included in the PLL circuit. Start automatically
In the state where the holdover function is activated, the packet detector determines whether the sync (Sync) message is detected again in the received packet,
When the sync (Sync) message is detected again, the packet detector determines whether the time offset value inside the received packet is stable,
A time synchronization method, wherein the packet detection unit stops the holdover function after determining that the time offset value is stable.

(Additional remark 6) When the process which the said packet detection part determines whether the time offset value inside the said reception packet is stable, when the stability of the said time offset value becomes below a predetermined threshold value, the said The time synchronization method according to appendix 5, wherein the time offset value is determined to be stable.

(Supplementary Note 7) The process in which the packet detection unit determines whether or not the time offset value inside the received packet is stable is determined by using a frequency stability request value given from the outside in advance in the PLL circuit unit. The time synchronization method according to appendix 6, wherein the threshold value is calculated by dividing by a DC loop gain.

(Supplementary Note 8) In a time synchronization device that generates a time signal according to a clock signal and a received packet received from the outside, and synchronizes frequency timing between a plurality of bases,
The time synchronizer receives a communication packet according to a specific communication protocol, generates a time signal according to the communication packet, and from the time signal according to a sync (Sync) message included in the received packet by the packet receiver. A PLL circuit that removes a frequency fluctuation component, and a packet detector that constantly monitors the received packet and a time offset value inside the received packet;
In the processor provided in the packet detection unit,
A procedure for determining whether or not the elapsed time that has passed without being able to detect the sync (Sync) message in the received packet is equal to or greater than a predetermined time limit,
A procedure for forcibly starting a holdover function for removing packet jitter and wander caused by an asymmetric delay environment from the time signal at a fixed timing provided in the PLL circuit when the elapsed time exceeds the time limit ,
A procedure for determining whether the sync (Sync) message is detected again in the received packet in a state where the holdover function is activated,
A procedure for determining whether or not the time offset value inside the received packet is stable when the sync message is detected again.
And a time synchronization program for executing a procedure for stopping the holdover function after determining that the time offset value is stable.

  In addition to the LTE ground station described in the embodiment, the present invention can be used in applications that require highly accurate time synchronization, such as a GPS receiver.

DESCRIPTION OF SYMBOLS 1 Time synchronizer 10 IEEE1588v2 protocol part 11 Slave time timer function 12 Packet capture function 13 Slave time calculation function 14 Time adder 20 IEEE1588v2 packet detection part 21 Sync (Sync) message stop monitoring function 22 Time offset stability monitoring function 30 Digital PLL Unit 31 Phase comparator 32 Digital amplifier 33 Complete integrator 34 Holdover buffer 35 Selector 36 D / A converter 37 VC-OCXO
38 Frequency Divider 100 Wireless Communication System 110 Master Device 120, 130 Slave Device 140 Packet Communication Network

Claims (3)

A time synchronization device that generates a time signal according to a clock signal and a received packet received from the outside, and synchronizes frequency timing between a plurality of bases,
A packet receiver that receives a communication packet according to a specific communication protocol and generates the time signal according to the communication packet;
A PLL circuit that removes frequency fluctuation components from the time signal in accordance with a sync message included in a packet received by the packet receiver;
Whether the received packet and the time offset value inside the received packet are constantly monitored, and whether the elapsed time that the sync message has not been detected in the received packet is equal to or greater than a predetermined time limit A packet detection unit for determining
The PLL circuit unit has a holdover function for removing packet jitter and wander caused by an asymmetric delay environment from the time signal at a fixed timing ;
The packet detector is
A sync message stop monitoring function for forcibly starting the holdover function of the PLL circuit when the elapsed time exceeds the time limit;
A threshold value is calculated by dividing a required value of frequency stability given from the outside in advance by a DC loop gain specific to the PLL circuit unit, and the received packet is included in the received packet while the holdover function is activated. When a sync message is detected again, if the stability of the time offset value falls below the threshold value, the time offset stability monitoring function that determines that the time offset value is stable and stops the holdover function. When,
Having
A time synchronizer characterized by that . In a time synchronization device that generates a time signal according to a clock signal and a received packet received from the outside, and synchronizes frequency timing between a plurality of bases,
The packet receiver receives a communication packet according to a specific communication protocol,
The packet receiver generates the time signal according to the communication packet,
The PLL circuit unit removes the frequency fluctuation component from the time signal according to the sync message included in the packet received by the packet reception unit,
Whether or not the elapsed time that has passed without being able to detect the sync message in the received packet by constantly monitoring the received packet and the time offset value inside the received packet is greater than or equal to a predetermined time limit Is determined by the packet detector,
When the elapsed time exceeds the time limit, the packet detector includes a holdover function for removing packet jitter and wander caused by an asymmetric delay environment from the time signal at a fixed timing, which is included in the PLL circuit. Start automatically
A threshold value is calculated by dividing the required value of frequency stability given from the outside in advance by the packet detection unit by a DC loop gain specific to the PLL circuit unit,
When the holdover function is activated and the packet detection unit detects the sync message in the received packet again, and the stability of the time offset value is equal to or less than the threshold, the time The packet detector determines that the offset value is stable and stops the holdover function .
A time synchronization method characterized by the above. In a time synchronization device that generates a time signal according to a clock signal and a received packet received from the outside, and synchronizes frequency timing between a plurality of bases,
The time synchronizer receives a communication packet according to a specific communication protocol, generates a time signal according to the communication packet, and from the time signal according to a sync (Sync) message included in the received packet by the packet receiver. A PLL circuit that removes a frequency fluctuation component, and a packet detector that constantly monitors the received packet and a time offset value inside the received packet;
In the processor provided in the packet detection unit,
A procedure for determining whether or not the elapsed time that has passed without being able to detect the sync (Sync) message in the received packet is equal to or greater than a predetermined time limit,
A procedure for forcibly starting a holdover function for removing packet jitter and wander caused by an asymmetric delay environment from the time signal at a fixed timing provided in the PLL circuit when the elapsed time exceeds the time limit ,
A procedure for calculating a threshold value by dividing a required value of frequency stability given from the outside in advance by a DC loop gain specific to the PLL circuit unit,
A procedure for determining whether the sync (Sync) message is detected again in the received packet in a state where the holdover function is activated,
A procedure for determining that the time offset value is stable when the stability of the time offset value is equal to or less than the threshold when the sync (Sync) message is detected again.
And a procedure for stopping the holdover function after determining that the time offset value is stable ,
A time synchronization program characterized in that is executed.

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