JP6045247B2 - Image processing apparatus, control method thereof, and control program - Google Patents

Description

  The present invention relates to an image processing apparatus, a control method thereof, and a control program, and more particularly, to a technique for preventing a reduction in processing speed and reducing a circuit scale during image filter processing.

  In recent years, the number of pixels of a solid-state image sensor has increased significantly, and a high-definition still image can be taken using such a solid-state image sensor. Further, there are electronic cameras that can display and record not only still images but also high-definition moving images.

  When displaying and recording a moving image, it is necessary to secure a frame rate of at least about 24 to 30 frames / second in order to obtain a high resolution in the time axis direction. Also, high quality is required for moving images as well as still images.

  For example, there is a technique that performs false color generation processing in demosaicing (interpolation) in order to improve the quality of moving images (see Patent Document 1). In addition, there is a technique in which magnification chromatic aberration correction processing is performed to improve image quality (see Patent Document 2).

  In addition, there is a process for removing noise generated during sensitivity imaging, particularly noise removal for a wide dynamic range image (see Patent Document 3). In each of Patent Documents 1 to 3, various filter processing circuits including band pass filter processing or low pass filter processing are used.

  In addition, there is a technique in which the image memory capacity is reduced and the cost is reduced during the filtering process used when the image is reduced (see Patent Document 4). And in patent document 4, when the reference pixel which contains a filter tap with respect to the pixel used as a process target exists in the image at the time of a filter process, it is a dummy pixel of the same level as the pixel level of the pixel position in an image end (Hereinafter, provision of dummy pixels is referred to as pixel copy). As a result, in Patent Document 4, the peripheral area is simply expanded outward to reduce the deterioration of the image quality at the image edge and perform the filter processing.

  Then, the image data in the CCD-RAW format is converted into RGB image data by the image processing circuit according to the setting of the recording mode switch, and JPEG compression is performed by the JPEG circuit, or reversible by the data conversion circuit and the Huffman encoding / decoding circuit. Some have been compressed (see Patent Document 5). Here, a VALID signal and a STOP signal are defined, a pair of VALID signals and a STOP signal are added to the image data series, and the data is valid when the VALID signal is “1”. When the STOP signal is “1”, data input is blocked. That is, when the VALID signal is “1” and the STOP signal is “0”, data input processing is effectively performed.

JP 2002-300590 A JP 2008-15946 A JP 2008-15741 A JP 2002-150281 A JP 2001-61067 A

  By the way, it is assumed that a so-called raster scan method is used for pixel transfer during image processing. In this case, when the n-th order filter processing is performed in the horizontal direction and the vertical direction of the screen, information for pixels corresponding to the product of the number of horizontal pixels and “number of vertical lines−1” is temporarily stored in a memory or the like. There is a need. This inevitably increases the memory capacity.

  In order to prevent an increase in memory capacity, Patent Document 4 transfers data in units of blocks to reduce the amount of pixel copy at the time of filter processing. However, the sensor is not used for a temporary memory such as a DRAM. In other words, when data is directly received from a solid-state imaging device and is subjected to filter processing, data is not transferred in units of blocks, so a memory is required to perform n-th order filter processing data. In addition, the memory capacity increases.

  On the other hand, if pixel copying is performed using the relationship between the VALID signal and the STOP signal described in Patent Document 5, as described later, the processing efficiency is reduced due to the STOP signal, but the memory becomes unnecessary and the circuit scale is reduced. Can be reduced.

  However, when the frame rate of a moving image is increased, the frame rate is reduced due to the STOP signal.

  Accordingly, an object of the present invention is to provide an image processing apparatus, a control method thereof, and a control program that can suppress an increase in circuit scale without lowering the processing efficiency.

In order to achieve the above object, an image processing apparatus according to the present invention operates on a first clock, and image data obtained by analog-to-digital conversion of an output of an imaging sensor that captures an image of a subject is generated on the first clock. is input, the image data an image processing apparatus for image processing, writes the image data in accordance with said first of said second clock is switched to fast second clock than the clock in the memory the after writing for the second cutting conversion Ete the memory clock, the pixel data at the start end and termination end of the image data read out image data written in the memory prohibits input of said image data a memory control means for copying the image data, the image horizontally TAP filtering the output image data from said memory control means And having a physical means.

According to the control method of the present invention, image data obtained by analog-to-digital conversion of an output of an image sensor that operates with a first clock and images a subject is input with the first clock, and the image data is converted into an image. a control method for processing an image processing apparatus which includes a write steaming step to write the image data in accordance with said first of said switches to fast second clock than the clock the second clock to the memory, the first After the clock is switched to 2 and writing to the memory is performed, the input of the image data is prohibited, the image data written to the memory is read, and the pixel data is read at the start and end ends of the image data. this has a copy be away step, the absence steps to process horizontal TAP filter the image data obtained by the copying of the image data The features.

According to the control program of the present invention, image data obtained by analog-to-digital conversion of an output of an image sensor that operates with a first clock and images a subject is input with the first clock, and the image data is converted into an image. A control program used in an image processing apparatus for processing, wherein a computer provided in the image processing apparatus is switched to a second clock faster than the first clock, and the image data is transferred in accordance with the second clock. the image data read and write steaming step to write in the memory, after writing to the memory is switched to the second clock has been performed, the image data written by prohibiting the input of the image data in the memory and copying to Luz step the pixel data in the image data at the start end and termination end of, resulting et al by the copy And characterized in that the image data was performed and the automatic answering step to horizontal TAP filtering.

  According to the present invention, it is possible to suppress an increase in circuit scale without lowering the processing efficiency.

It is a figure which shows the structure of the image processing path | pass about an example of the image processing apparatus by the 1st Embodiment of this invention. FIG. 2 is a diagram illustrating an example of input image data and output image data of a copy circuit unit illustrated in FIG. 1. It is a block diagram which shows the structure about an example of an imaging device provided with the image processing apparatus shown in FIG. 4 is a timing chart for explaining the timing of image processing in the imaging apparatus shown in FIG. 3. 4 is a timing chart when pixel copying is performed after switching from a sensor clock to a processing clock in the imaging apparatus shown in FIG. 3. It is a figure which shows the structure of the image processing path | pass about an example of the image processing apparatus by the 2nd Embodiment of this invention. It is a figure which shows an example of the image data read from the memory shown in FIG. It is a figure which shows the structure of the image processing path | pass about an example of the conventional image processing apparatus. It is a figure for demonstrating an example of the filter process performed in the image development processing circuit shown in FIG. It is a figure which shows the concept of the pixel copy in the filter process shown in FIG. It is a figure for demonstrating the other example of the filter process performed with the image development processing circuit shown in FIG.

  Hereinafter, an example of an image processing apparatus according to an embodiment of the present invention will be described with reference to the drawings.

[First Embodiment]
First, before describing the image processing apparatus according to the first embodiment of the present invention, in order to facilitate understanding of the image processing apparatus according to the first embodiment of the present invention, the conventional image processing apparatus will be described with reference to the drawings. I will explain.

  Assume that a raster scan method is used as a pixel signal transfer method when performing image processing. Here, the raster scan method is to scan one pixel at a time from the left end pixel of the uppermost line of the screen toward the right end pixel, and when the scanning of one line is completed, from the left end to the right end of the line below the line. A scanning method that scans one pixel at a time. Then, scanning is performed until the bottom line of the screen is reached, and pixel signals (also referred to as pixel data) are sequentially output to a subsequent processing unit. For example, the raster scan method is used for outputting pixel signals in a solid-state imaging device such as a CCD image sensor.

  Here, it is assumed that n-th order filter processing is performed in the horizontal and vertical directions of the screen (that is, the image) in the subsequent processing unit (n is an integer of 2 or more). In this case, data for pixels corresponding to the product of the number of pixels in the horizontal direction and “number of vertical lines−1” is temporarily stored in the memory. Then, the filtering process is performed on the data held in the memory.

  For this reason, the memory capacity must be increased when performing the filtering process.

  FIG. 8 is a diagram showing a configuration of an image processing path for an example of a conventional image processing apparatus. The illustrated image processing apparatus is used in an imaging apparatus such as a digital camera, for example.

  The image processing apparatus includes a sensor I / F circuit 201. The sensor I / F circuit 201 captures pixel data as sensor data from an image sensor (hereinafter simply referred to as a sensor) such as a CCD, and performs sensor data replacement processing. And so on. The output of the sensor I / F circuit 201 is given as input data to the sensor correction circuit 202, and the sensor correction circuit 202 performs correction of pixel flaws and smear correction generated by the sensor on the input data.

  The output of the sensor correction circuit 202 is given to the development processing circuit 203 as input data. The development processing circuit 203 includes a filter processing circuit (not shown) and a memory such as a FIFO 204. In the illustrated image processing apparatus, during live view or the like, development processing is performed at high speed without storing input data in a temporary memory such as a DRAM.

  FIG. 9 is a diagram for explaining an example of the filter processing performed in the development processing circuit shown in FIG. Here, it is assumed that a memory is not provided for pixel copying, and pixel copying is performed by generating a STOP signal according to the relationship between the VALID signal and the STOP signal. In the illustrated example, it is assumed that the image size is 1920 × 1080 (pixel) in the so-called horizontal 5TAP (1, 2, 2, 2, 1) filter processing.

  FIG. 10 is a diagram showing the concept of pixel copy in the filter processing shown in FIG.

  In the horizontal 5TAP filter processing, when the reference pixel data is present outside the image 1001 for the pixel data to be processed, dummy pixel data at the same level as the pixel level at the image end (here, “0”). 1002 is added (pixel copy).

  In the example shown in FIG. 9, N (N = 5) flip-flops 401 are provided. These flip-flops 401 temporarily hold the input data (image data). Further, in the illustrated example, (N−2) bit shift calculators 404, (N−1) adders, and one bit shift calculator 406 are provided.

  Here, the output of the (n−1) -th flip-flop 401 is given to the (n−2) -th bit shift computing unit 404 (n is any integer from 3 to 5). The first adder 405 is supplied with the output of the first flip-flop 401 and the output of the first bit shift calculator 404.

  The second adder 405 is supplied with the output of the first adder 405 and the output of the second bit shift computing unit 404, and the third adder 405 receives the second addition. And the output of the third bit shift calculator 404 are provided. The fourth adder 405 is supplied with the output of the fifth flip-flop 401 and the output of the third adder 405.

  Here, as indicated by the time axis 402, time passes from the upper side to the lower side. The STOP signal 403 is a signal for stopping the input from the previous stage. The bit shift calculator 404 shifts the input by 1 bit to the left. The bit shift calculator 406 right 3 bits the output of the fourth adder 405.

  Each output of the flip-flop 401 is indicated by reference numeral 407, and the image data is sequentially input by the raster scan method, and “1”, “2”, “3”,. Assume that the pixel value to be incremented is input. The pixel value at the end of one line is set to “1919”. “X” represents an indefinite value.

  Here, when the pixel value “0” is input to the first flip-flop 401, a STOP signal = “1” is given to the preceding stage from a control unit (not shown). This prevents the pixel value “1” from being input from the previous stage. Then, the first flip-flop 401 holding “0” outputs the pixel value “0” to the second flip-flop 401 in the next cycle.

  Further, the pixel value “0” is held in the subsequent flip-flop 401 in the next cycle. Then, when the STOP signal is set to “0”, the pixel value “1” whose input is stopped in the previous stage is input from the next cycle, and thereafter, the pixel values that are not indefinite are held in all the flip-flops 401. 5TAP filter processing is sequentially performed.

  In the above description, the pixel copy is performed for the left end of the image, but the same processing is performed for the right end of the image. The pixel value at the right end is “1919”, and when the pixel value “1919” is input to the first flip-flop 401, a STOP signal = 1 is generated. Then, after two cycles, the STOP signal is canceled with STOP signal = 0.

  When processing as described above is performed, the processing efficiency is reduced by the STOP signal, but the memory becomes unnecessary and the circuit scale can be reduced.

  However, as described above, if the moving image has a high frame rate, the frame rate is lowered in the process described with reference to FIG.

  FIG. 11 is a diagram for explaining another example of the filter processing performed in the development processing circuit shown in FIG. Here, a memory such as a FIFO is used instead of the STOP signal. In FIG. 11, the same components as those in the example shown in FIG. The FIFO shown in FIG. 11 corresponds to the FIFO 204 shown in FIG.

  In the illustrated example, four FIFOs 503a to 503d are provided, and the FIFOs 503a and 503b are used for copying the rightmost pixel of the image. The FIFOs 503c and 503d are used for copying the leftmost pixel of the image.

  In the illustrated example, in order to hold two pixels of mirror pixels (pixels in which pixels of the original image reflected in the mirror are arranged as pixels around the image when a mirror is placed at the boundary portion around the image) A FIFO is used. Note that the vertical 5TAP filter processing requires two lines of line memory as in the case of the horizontal 5TAP.

  That is, when performing horizontal mTAP (m is an integer of 2 or more) filter processing, (m−1) FIFOs are required in total on the left and right, and when performing vertical mTAP filter processing, upper and lower ( m-1) line memory is required.

  Thus, the number of FIFOs increases as the number of TAPs increases both horizontally and vertically. That is, the circuit scale increases as the number of development processing circuits increases.

  FIG. 1 is a diagram showing the configuration of an image processing path for an example of an image processing apparatus according to the first embodiment of the present invention.

  The image processing apparatus includes a sensor I / F circuit 601. The sensor I / F circuit 601 captures pixel data from the sensor as sensor data, and performs sensor data replacement processing and the like. The output of the sensor I / F circuit 201 is given to the copy circuit unit 602 as input data.

  The copy circuit unit 602 includes a FIFO 603 that is a memory and a copy pixel addition circuit 604. A copy pixel addition circuit 604 is a circuit for adding copy pixel data used in a development processing circuit 606 and a development processing circuit 607 described later to input image data. A FIFO 603 is a memory in which input image data is written by the copy pixel addition circuit 604.

  The sensor correction circuit 605 receives the output of the copy circuit unit 602 as input data, and corrects pixel defects generated by the sensor, correction of smear, and the like on the input data. The development processing circuits 606 and 607 each perform horizontal TAP filter processing. In the illustrated example, it is assumed that the development processing circuits 606 and 607 perform horizontal 19TAP filter processing and horizontal 11TAP filter processing, respectively.

  FIG. 2 is a diagram illustrating an example of input image data and output image data of the copy circuit unit 602 illustrated in FIG. Here, it is assumed that the size of image data input from the sensor I / F circuit 601 to the copy circuit unit 602 is 1920 × 1080 (pixel).

  The copy circuit unit 602 adds nine copy pixels to the left and right for use in the horizontal 19TAP filter processing with respect to the size of the input image data of the copy circuit unit 602. Further, the copy circuit unit 602 adds 5 pixels to the left and right of the copy pixels used in the horizontal 11 TAP filter processing. As a result, the copy circuit unit 602 outputs image data having a size of 1948 × 1080 as output data.

  Referring to FIG. 1 again, the development processing circuit 606 receives the output of the copy circuit unit 602 and consumes copy pixels of 9 pixels on the left and right. As a result, the development processing circuit 606 outputs image data having a size of 1930 × 1080 as output data.

  Image data having a size of 1930 × 1080 is given to the development processing circuit 607 as input data. The development processing circuit 607 consumes five right and left copy pixels. As a result, the development processing circuit 607 outputs image data having a size of 1920 × 1080 as output data, and when all the filtering processes are completed, the image size becomes equivalent to the output of the sensor I / F circuit 601.

  Here, the frequency of the sensor clock (first clock) is 60 MHz, and the frequency of the processing clock (second clock) is 180 MHz. Also, as described above, pixel values incremented in the order of “1”, “2”, “3”, “4”,... From the pixel value “0” are input as sensor data. And

  At this time, when the input is controlled according to the STOP signal as described with reference to FIG. 9, considering only the filter processing at the left end of the image, the pixel value “0” is first taken in and then the development processing circuit 606. Then, a STOP signal = 1 for 9 cycles is output to perform pixel copy. Similarly, the development processing circuit 607 outputs a STOP signal = 1 for five cycles to perform pixel copying.

  On the other hand, as described with reference to FIG. 11, when the FIFO is provided as the memory, the development processing circuit 606 requires (19-1) / 2 = 9 FIFOs in consideration of only the filter processing at the left end of the image. Become. Similarly, the development processing circuit 607 requires (11-1) / 2 = 5 FIFOs. Therefore, the development processing circuits 606 and 607 require a total of 14 memories (FIFOs).

  FIG. 3 is a block diagram illustrating a configuration of an example of an imaging apparatus including the image processing apparatus illustrated in FIG. In FIG. 3, the same components as those shown in FIG. 1 are denoted by the same reference numerals. In FIG. 3, elements omitted in the copy circuit unit 602 shown in FIG. 1 are shown.

  The illustrated imaging apparatus includes an imaging lens unit (hereinafter referred to as an optical system) 101 having a plurality of lenses, and an optical image (that is, a subject image) is transmitted through the optical system 101 to a CCD solid-state imaging unit (imaging sensor). The image is formed on 102. Instead of using a CCD sensor as the solid-state image sensor, a CMOS sensor may be used.

  In the CCD solid-state imaging unit 102, a large number of sensors (that is, pixels) are arranged in a matrix of M rows × N columns in a plane perpendicular to the light emitted from the optical system 101 (here, M and N is an integer of 2 or more). The sensor matrix corresponds to a shooting screen. These sensors output in parallel electrical signals having a level corresponding to the amount of incident light.

  In the CCD solid-state imaging unit 102, each row from the first row to the Mth row of the sensor matrix is sequentially scanned in the horizontal direction by a scanning circuit (not shown). As a result, the output signal of each sensor is output to the AGC circuit 103 in series with a predetermined period T.

  An analog image signal, which is an output of the CCD solid-state imaging unit 102, is gain-adjusted by the AGC circuit 103 and then supplied to the A / D conversion unit 104. The A / D conversion unit 104 performs A / D conversion (analog-digital conversion) on the analog image signal and outputs the digital image signal (image data) to the sensor I / F circuit 601.

  The copy circuit unit 602 includes a RAM I / F unit 107, a selector 110, and a copy control unit 112 in addition to a copy pixel addition circuit (hereinafter simply referred to as a copy circuit) 604. The RAM I / F unit 107 includes a RAM 109 and a RAM control unit 108. The RAM 109 is a memory used in place of the FIFO 603 shown in FIG.

  In the illustrated example, the sensor I / F circuit 601 operates with a sensor clock of 60 MHz. The RAM control unit 108 performs a clock transfer process between the sensor clock and the processing clock, and writes image data to an available address in the RAM 109. When there is no more free address in the RAM 109, the RAM control unit 108 sends a STOP signal = 1 to the preceding sensor I / F circuit 105 to prohibit the input of image data.

  Sensor data input from the sensor I / F circuit 105 is sequentially written in the RAM 109. The sensor data input to the RAM 109 is selected by the selector unit 110 under the control of the copy control unit 112 and is output to the copy circuit 604 as selected sensor data. The copy circuit 111 outputs a VALID signal (valid signal) 115 and selection sensor data 114 to the sensor correction circuit 605.

  The sensor correction circuit 605 corrects pixel flaws (pixel defects) generated in the sensor, corrects smear, and the like, and outputs the output VALID 117 together with the corrected image data 118 to the development processing circuit 606 at the subsequent stage.

  The development processing circuit 606 consumes a predetermined pixel copy, and then deletes the consumption and outputs the VALID 120 and the image data 121 to the subsequent development processing circuit 607. Similarly, the development processing circuit 607 consumes the pixel copy and outputs the same 1920 × 1080 size data as the image data input from the sensor I / F circuit 601.

  FIG. 4 is a timing chart for explaining an example of image processing timing in the imaging apparatus shown in FIG.

  In FIG. 4, the sensor clock is 60 MHz and the processing clock is 180 MHz. Input data (output of the copy circuit 604) to the sensor correction circuit 605 is output together with the VALID signal with 14-pixel data for the copy added to the head thereof. Then, the STOP signal = 1 is output from the copy control unit 112 to the copy circuit 604 for 14 pixels.

  However, since the STOP signal is output in synchronization with the processing clock 180 MHz with respect to the sensor data input in synchronization with the sensor clock 60 MHz, 14 × (60/180) = 4.6666. It becomes. Therefore, the STOP signal for about 5 pixels is actually affected. That is, the minimum necessary memory amount is 5 pixels, and even if the delay for the I / F in the RAM is taken into consideration, the memory amount is 5 pixels + 1 or 2 pixels.

  FIG. 5 is a timing chart when pixel copying is performed after switching from the sensor clock to the processing clock in the imaging apparatus shown in FIG.

  As described above, the copy circuit 604 adds the copy pixel data used in the horizontal 19TAP filter processing to the left and right sides of the image (that is, the start end and the end end) for each image data having a size of 1920 × 1080. Furthermore, the copy circuit 604 adds copy pixel data used in the horizontal 11 TAP filter processing to the left and right of the image by 5 pixels, and outputs the image data of 1948 × 1080 size.

  As in FIG. 4, in order to perform the left side copy, the copy control unit 112 outputs a STOP signal = 1 for 14 pixels. At this time, since the input data is after the clock change, it is input in synchronization with the processing clock.

  Here, assuming that the first pixel value is “0” and pixel values that are incremented in the order of “1”, “2”, “3”, “4”,. In 5, the input data for 14 pixels is input to the STOP signal for 14 pixels. That is, the minimum necessary memory amount that does not output the STOP signal = 1 is 14 pixels, and even if the delay for the I / F of the RAM 109 is considered, the memory amount is 14 pixels + 1 or 2 pixels.

  That is, the optimum memory amount is obtained from the difference between the frequency of the fastest sensor clock and the slowest processing clock.

  As described above, according to the first embodiment of the present invention, paying attention to the clock frequency, pixel transfer is performed by changing the clock between the sensor clock having the slow clock frequency and the filter processing clock having the fast clock frequency. This reduces the amount of memory required for pixel copying. As a result, the circuit scale can be reduced without reducing the processing speed.

[Second Embodiment]
Next, an image processing apparatus according to the second embodiment of the present invention will be described.

  FIG. 6 is a diagram showing the configuration of an image processing path for an example of an image processing apparatus according to the second embodiment of the present invention. In FIG. 6, the same components as those shown in FIG. 1 are denoted by the same reference numerals.

  In FIG. 6, the image processing apparatus has a temporary memory 1001 such as a DRAM. A memory I / F 1002 is connected to the memory 1001. The memory I / F 1002 is connected to the development processing circuit 606.

  The memory 1 / F 1002 has first and second copy counters 1005 and 1006. The first copy counter 1005 is for generating the leftmost copy pixel of the image existing in the memory I / F 1002. The second copy counter 1006 is for generating the rightmost copy pixel of the image existing in the memory I / F 1002.

  The memory 1001 writes or reads image data at an address designated by the memory I / F 1002. The development processing circuit 606 requires 9 left and right copy pixels in the filter processing, and the development processing circuit 607 requires 5 left and right copy pixels in the filter processing. As a result, a total of 14 copy pixels are required.

  Here, when the start address and the image size are set, the memory I / F 1002 reads image data for the size from the memory 1001. Here, it is assumed that image data having a size of 1920 × 1080 (pixel) is read into the memory I / F 1002.

  As described above, since the horizontal size of the image data used in the development processing circuit 606 is 1948 pixels, the horizontal image size value (1948-1) = 1947 is set in the memory I / F 1002, and the first copy counter 1005 is set. (14-1) = 13 and (14-1) = 13 are set in the second copy counter 1006.

  Although not shown, the memory I / F 1002 includes a horizontal counter and a vertical counter, and when the memory I / F 1002 increments an address from a set start address, the horizontal counter is incremented.

  FIG. 7 is a diagram showing an example of image data read from the memory 1001 shown in FIG.

  The memory 1001 stores image data 110 having a size of 1920 × 1080. In the image data 1101, copy target pixel data 1102 exists at the left end, and copy target pixel data 1103 exists at the right end. Further, a copy area 1104 is defined on the left side, and a copy area 1105 is defined on the right side.

  Reference numeral 1106 represents a horizontal counter. When reading 1948 pixel data in the horizontal direction, the memory I / F 1002 increments the address from 0 to 1947 and reads the pixel data.

  Here, the memory I / F 1002 reads the same address without incrementing the address until the count value of the horizontal counter 1106 becomes equal to the set value of the first copy counter 1105 (that is, “13”). Run. When the count value of the horizontal counter 1106 becomes equal to the set value of the first copy counter 1105, the memory I / F 1002 increments the address.

  Further, when the count value of the horizontal counter 1106 becomes equal to (horizontal image size value−set value of the first copy counter 1105), that is, when 1947−13 = 1934, the memory I / F 1102 becomes the first one. The second copy counter 1106 is incremented. Then, the memory I / F 1102 continues incrementing until the second copy counter 1106 reaches a set value (that is, “13”). Until the second copy counter 1106 reaches the set value, the memory I / F 1102 reads the same address a plurality of times without incrementing the address.

  In this manner, the memory I / F 1102 reads the copy areas 1104 and 1105 and outputs the output as 1948 pixel image data.

  As a result, similarly to the first embodiment, a process equivalent to the process related to the copy pixel can be performed, and the processing speed does not decrease. Since the development processing circuits 606 and 607 do not require a memory, the circuit scale can be reduced.

  As mentioned above, although this invention was demonstrated based on embodiment, this invention is not limited to these embodiment, Various forms of the range which does not deviate from the summary of this invention are also contained in this invention. .

  For example, the function of the above embodiment may be used as a control method, and this control method may be executed by the image processing apparatus. In addition, a program having the functions of the above-described embodiments may be used as a control program, and the control program may be executed by a computer included in the image processing apparatus. The control program is recorded on a computer-readable recording medium, for example.

  The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various recording media, and the computer (or CPU, MPU, etc.) of the system or apparatus reads the program. To be executed.

102 CCD solid-state imaging unit 103 AGC circuit 104 A / D conversion unit 105 Sensor I / F circuit 108 RAM control unit 109 RAM
110 Selector 112 Copy Control Unit 602 Copy Circuit Unit 604 Copy Circuit

Claims (5)

An image processing apparatus that performs image processing on image data obtained by inputting image data obtained by analog-to-digital conversion of an output of an image sensor that operates with a first clock and images a subject. And
Writes the image data in the memory in response to said first of said switches to fast second clock than the clock the second clock, after writing to cut changeover Ete said memory to said second clock Memory control means for prohibiting input of the image data and reading out the image data written in the memory and copying pixel data to the image data at a start end and an end end of the image data;
An image processing apparatus comprising: image processing means for performing horizontal TAP filter processing on the image data output from the memory control means. The image processing apparatus according to claim 1 , wherein the second clock is a processing clock used when the image processing unit performs the horizontal TAP filter processing. Said memory control means, for the same address by performing a plurality of times reading process from the memory, according to claim 1 or 2, characterized in that copying the pixel data in the image data at the start end and termination end of the image data An image processing apparatus according to 1. Control of an image processing device that operates on a first clock and images image data obtained by analog-digital conversion of an output of an imaging sensor that captures an image of a subject and inputs the image data on the first clock. A method,
And write steaming step to write the image data in accordance with said first clock second switching clock of the second clock faster than the memory,
After switching to the second clock and writing to the memory, the input of the image data is prohibited, the image data written to the memory is read, and pixel data at the start and end ends of the image data and copying to Luz step to the image data,
Control method characterized by having a Luz step to horizontal TAP filter the image data obtained by said copying. Image data obtained by analog-to-digital conversion of an output of an image sensor that operates with a first clock and images a subject is input with the first clock, and is used in an image processing apparatus that performs image processing on the image data. A control program,
In the computer provided in the image processing apparatus,
And write steaming step to write the image data in accordance with said first clock second switching clock of the second clock faster than the memory,
After switching to the second clock and writing to the memory, the input of the image data is prohibited, the image data written to the memory is read, and pixel data at the start and end ends of the image data and copying to Luz step to the image data,
A control program, characterized in that to execute the automatic answering step to horizontal TAP filter the image data obtained by said copying.

Images