JP5904856B2 - プリント配線板、半導体パッケージ及びプリント回路板 - Google Patents
プリント配線板、半導体パッケージ及びプリント回路板 Download PDFInfo
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Description
図1は、本発明の第1実施形態に係るプリント回路板の概略構成を示す説明図である。プリント回路板500は、メイン基板400と、メイン基板400に実装された半導体パッケージ300とを備えている。半導体パッケージ300は、プリント配線板100と、プリント配線板100に実装された半導体素子(半導体チップ)200とを有している。本第1実施形態の半導体パッケージ300は、BGA(Ball Grid Array:ボールグリッドアレイ)パッケージである。メイン基板400はプリント配線板であり、表層に半導体パッケージ300が実装される。
次に、本発明の第2実施形態に係るプリント回路板について説明する。図5は、本発明の第2実施形態に係るプリント回路板の一部分を示す詳細図であり、図5(a)はプリント回路板の一部の上面図、図5(b)はプリント回路板の一部の正面図、図5(c)はプリント回路板の一部の側面図である。なお、この図5において、上記第1実施形態に係るプリント回路板と同様の構成については、同一符号を付しており、その詳細な説明は省略する。
次に、本発明の第3実施形態に係るプリント回路板について説明する。図8は、本発明の第3実施形態に係るプリント回路板の一部分を示す詳細図であり、図8(a)はプリント回路板の一部の上面図、図8(b)はプリント回路板の一部の正面図、図8(c)はプリント回路板の一部の側面図である。なお、この図8において、上記第1実施形態に係るプリント回路板と同様の構成については、同一符号を付しており、その詳細な説明は省略する。
次に、本発明の第4実施形態に係るプリント回路板について説明する。図10は、本発明の第4実施形態に係るプリント回路板の一部分を示す詳細図であり、図10(a)はプリント回路板の一部の上面図、図10(b)はプリント回路板の一部の正面図、図10(c)はプリント回路板の一部の側面図である。なお、この図10において、上記第1実施形態に係るプリント回路板と同様の構成については、同一符号を付しており、その詳細な説明は省略する。
Claims (7)
- 絶縁体を介して積層された複数の導体層を備えたプリント配線板において、
前記複数の導体層は、
第1の信号配線パターン及び第2の信号配線パターンが形成された第1の導体層と、
前記プリント配線板の一方の表面に位置し、前記第1の信号配線パターンに第1のヴィアを介して電気的に接続され、外部の第1の接続端子に接続される第1のパッドと、前記第2の信号配線パターンに、前記第1のヴィアに隣接する第2のヴィアを介して電気的に接続され、前記第1のパッドと隣接して配置された、外部の第2の接続端子に接続される第2のパッドと、が形成された第2の導体層と、
前記第1の導体層と前記第2の導体層との間に前記絶縁体を介して配置された第3の導体層と、を含んでおり、
前記第3の導体層には、前記第1のヴィアに電気的に接続された第1のヴィアパッドが形成されており、
前記第1のヴィアパッドの一部と前記第2のパッドの一部とは、前記絶縁体を介して互いに対向し、前記一方の表面に垂直な方向から見て重なり合って、容量結合により結合していることを特徴とするプリント配線板。 - 前記第1のヴィアパッドは、前記一方の表面に垂直な方向から見て、前記第1のパッドに対向しない形状に形成されていることを特徴とする請求項1に記載のプリント配線板。
- 前記第2の導体層には、前記第1のヴィアと前記第1のパッドとを電気的に接続する第3の信号配線パターンが形成されており、
前記第1のヴィアパッドは、前記一方の表面に垂直な方向から見て、前記第3の信号配線パターンに対向しない形状に形成されていることを特徴とする請求項2に記載のプリント配線板。 - 前記第3の導体層には、前記第2のヴィアに電気的に接続され、前記第1のヴィアパッドと間隔をあけて配置された第2のヴィアパッドが形成されていることを特徴とする請求項1乃至3のいずれか1項に記載のプリント配線板。
- 前記複数の導体層は、
前記第1の導体層と前記第3の導体層との間に前記絶縁体を介して配置された第4の導体層を更に含んでおり、
前記第4の導体層には、前記第2のヴィアに電気的に接続された第2のヴィアパッドが形成され、
前記第1のヴィアパッドの一部と前記第2のヴィアパッドの一部とは、前記絶縁体を介して互いに対向し、前記一方の表面に垂直な方向から見て互いに重なり合って、容量結合により結合していることを特徴とする請求項1乃至3のいずれか1項に記載のプリント配線板。 - 請求項1乃至5のいずれか1項に記載のプリント配線板と、
前記プリント配線板に実装され、前記第1の信号配線パターンに接続された第1の信号端子、及び前記第2の信号配線パターンに接続された第2の信号端子を有する半導体素子と、を備えたことを特徴とする半導体パッケージ。 - 請求項6に記載の半導体パッケージと、
前記半導体パッケージが実装され、前記第1のパッドが前記第1の接続端子で接続された第1のメイン基板側パッド、及び前記第2のパッドが前記第2の接続端子で接続された第2のメイン基板側パッドを有するメイン基板と、を備えたことを特徴とするプリント回路板。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012097572A JP5904856B2 (ja) | 2012-04-23 | 2012-04-23 | プリント配線板、半導体パッケージ及びプリント回路板 |
US13/862,038 US9192044B2 (en) | 2012-04-23 | 2013-04-12 | Printed wiring board, semiconductor package, and printed circuit board |
EP13164422.1A EP2658353A1 (en) | 2012-04-23 | 2013-04-19 | Printed wiring board, semiconductor package, and printed circuit board with semiconductor package |
CN201310142055.1A CN103379733B (zh) | 2012-04-23 | 2013-04-23 | 印刷布线板、半导体封装件和印刷电路板 |
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JP2012097572A JP5904856B2 (ja) | 2012-04-23 | 2012-04-23 | プリント配線板、半導体パッケージ及びプリント回路板 |
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JP2013225610A JP2013225610A (ja) | 2013-10-31 |
JP2013225610A5 JP2013225610A5 (ja) | 2015-06-18 |
JP5904856B2 true JP5904856B2 (ja) | 2016-04-20 |
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JP2012097572A Expired - Fee Related JP5904856B2 (ja) | 2012-04-23 | 2012-04-23 | プリント配線板、半導体パッケージ及びプリント回路板 |
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EP (1) | EP2658353A1 (ja) |
JP (1) | JP5904856B2 (ja) |
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JP6238567B2 (ja) | 2012-08-01 | 2017-11-29 | キヤノン株式会社 | 放電回路、電源装置及び画像形成装置 |
US9356525B2 (en) | 2012-08-31 | 2016-05-31 | Canon Kabushiki Kaisha | Power supply device and image forming apparatus |
US20140174812A1 (en) * | 2012-12-21 | 2014-06-26 | Raul Enriquez Shibayama | Method and Apparatus for Far End Crosstalk Reduction in Single Ended Signaling |
JP6036513B2 (ja) * | 2013-04-19 | 2016-11-30 | 株式会社デンソー | 車両用電子機器 |
US20150085458A1 (en) * | 2013-09-26 | 2015-03-26 | Raul Enriquez Shibayama | Reducing Far End Crosstalk in Single Ended Interconnects and Buses |
JP6384118B2 (ja) * | 2014-05-13 | 2018-09-05 | 日立化成株式会社 | 半導体装置の製造方法、半導体装置及び半導体装置製造用部材 |
KR102198858B1 (ko) | 2014-07-24 | 2021-01-05 | 삼성전자 주식회사 | 인터포저 기판을 갖는 반도체 패키지 적층 구조체 |
US9864826B2 (en) * | 2014-11-03 | 2018-01-09 | Toshiba Memory Corporation | Multilayer printed board and layout method for multilayer printed board |
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US9192044B2 (en) | 2015-11-17 |
JP2013225610A (ja) | 2013-10-31 |
CN103379733A (zh) | 2013-10-30 |
EP2658353A1 (en) | 2013-10-30 |
CN103379733B (zh) | 2016-06-01 |
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