JP5986036B2 - TRANSMISSION DEVICE, TRANSMISSION SYSTEM, RECEPTION DEVICE, AND TRANSMISSION METHOD - Google Patents

Description

  The present invention relates to, for example, a transmission device, a transmission system, a reception device, and a transmission method.

  In order to support the increase in traffic, it is required to increase the transmission capacity of the optical transmission apparatus. In order to expand the transmission capacity, studies are being made on multi-carrier transmission technology using a plurality of carriers, polarization multiplexing technology for multiplexing X polarization and Y polarization, and advanced modulation scheme technology. For example, two subcarriers (2-sub-carrier, hereinafter referred to as 2SC) are used, dual-polarization (hereinafter referred to as DP) is used, and BPSK (Binary Phase Shift Keying) modulation is performed. There is a transmission system called 2SC-DP-BPSK that uses this system. In 2SC-DP-BPSK, each of two carriers has an X polarization and a Y polarization, so that data is transmitted in two carriers × 2 polarization = 4, that is, four transmission lanes. As a method for transmitting a group of data in a plurality of lanes, for example, G.I. There is multi-lane transmission of OTUk (k = 3, 4) defined in 709 Annex C. G. In 709 Annex C, an OTUk multilane transmission method using 40 Gbit / s, 100 Gbit / s Ethernet (registered trademark) (hereinafter, 40 GbE and 100 GbE respectively) optical modules premised on multilane transmission is defined.

G. The operation principle of 709 Annex C will be described. First, using the FAS (Frame Alignment Signal) which is the head area of an OTU (Optical channel Transport Unit) frame shown in FIG. 19 as a mark, the OTU frame is divided into blocks of 16 bytes as shown in FIG. As shown in FIG. 20, since the OTU frame is 4080 bytes in one row, it is divided into 4,080 × 4/16 = 1020 (1020 = 2 ² × 3 × 5 × 17) blocks. Will do. After the division, in the case of OTU4, as shown in FIG. 21, the divided block is distributed to 20 logical lanes 0 to 19 (the vertical axis in FIG. 21 indicates the logical lane (Lane)) in a round robin manner. By doing so, multilane transmission can be performed. Further, when a block is distributed to a plurality of lanes, a method called lane rotation is used. The lane rotation is to change the lane where distribution is started for each frame. As a result, FAS is included in each logical lane, and FAS appears periodically. FIG. 22 shows an overhead configuration actually used for lane identification and skew detection. Referring to the FAS OH Byte (FAS OH Byte 1 to 6) in which a fixed bit pattern is stored, the head position of the frame is detected in each channel by determining whether or not the correct bit pattern is included. be able to.

Further, at the time of multi-lane transmission of OTU4, 240 numbers from 0 to 239 are sequentially assigned to the FAS OH Byte 6 by the distribution means on the transmission side and distributed to each logical lane. For example,
“FAS OH byte 6 =“ 0 ”” is assigned to logical lane 0.
“FAS OH byte 6 =“ 1 ”” is assigned to logical lane 1,
“FAS OH byte 6 =“ 2 ”” is assigned to logical lane 2,
...
“FAS OH byte 6 =“ 19 ”” is assigned to logical lane 19.
Next, return to logical lane 0 again.
“FAS OH byte 6 =“ 20 ”” is assigned to logical lane 0,
“FAS OH byte 6 =“ 21 ”” is assigned to logical lane 1,
“FAS OH byte 6 =“ 22 ”” is assigned to logical lane 2,
...
“FAS OH byte 6 =“ 239 ”” is assigned to logical lane 19. When a number is given up to 239, the number is assigned again after returning to 0 again. On the receiving side, the remainder of dividing the value of FAS OH Byte 6 received for each logical lane by the number of logical lanes 20 is the number for identifying each logical lane. Since the number of assigned numbers is 240 which is a multiple of the number of logical lanes 20 (0 to 239 as the assigned number), for example, logical lane 0 always has a remainder of 0 and logical lane 1 has a remainder. Is always 1, which makes it possible to detect logical lanes.
After distributing the OTUk frame to a plurality of logical lanes, multi-lane transmission is performed by bit-multiplexing the plurality of logical lanes as necessary to match the number of physical lanes actually used. For example, when OTU4 is transmitted in 4 physical lanes, OTU4 has 20 logical lanes. Therefore, as shown in FIG. 23, 4 logical lanes are generated by bit-multiplexing 20 logical lanes by 5 logical lanes and multilane transmission is performed. Is done.

"Interfaces for the Optical Transport Network (OTN)", February 2012, ITU-T Recommendation G.709 / Y.1331.

  Here, an example in which the above-described multi-lane transmission is applied to 100 Gbit / s transmission by 2SC-DP-BPSK will be described with reference to FIG. In the transmission device 50, the client signal reception unit 51 receives a client signal such as 100 GbE or OTU4. When the client signal is 100 GbE, mapping to the OTU4 frame is also performed. The error correction encoding unit 53 adds an error correction code to the signal output from the client signal receiving unit 51. The OTU4 signal to which the error correction code is added is divided into four signals by the distributing unit 52, that is, the X polarization of the first subcarrier (SC # 1X polarization) and the Y polarization of the first subcarrier ( SC # 1Y polarization) is distributed to signals corresponding to the X polarization (SC # 2X polarization) of the second subcarrier and the Y polarization (SC # 2Y polarization) of the second subcarrier. . With respect to this distributed signal, the G.P. The multi-lane transmission method of OTU4 specified by 709 Annex C is applied. In OTU4, 20 logical lanes are used, and the number of physical lanes is 4 physical lanes as shown in FIG. 23. Therefore, 4 logical lanes are generated by bit-multiplexing 5 logical lanes. The digital modulation unit / transmission unit / multiplexing unit 59 generates a transmission signal by modulating and multiplexing the four distributed signals in association with the subcarrier and the polarization, and transmits the signal through the optical transmission line 70. Transmit distance.

  In the receiving device 60, the demultiplexing unit / reception unit / digital demodulation unit 69 receives the transmission signal and outputs four physical lanes. The connecting portion 62 is a G.S. In accordance with the OTU4 multi-lane transmission method defined in 709 Annex C, a reorder that corrects the order of logical lanes after generating 20 logical lanes by performing 1: 5 bit separation for each of the four physical lanes, A deskew is performed to correct a transmission delay difference between logical lanes. Thereafter, the original OTU4 signal is reproduced from the 20 logical lanes and output to the error correction decoding unit 63. The error correction decoding unit 63 performs error correction using the redundant bits added by the error correction encoding unit 53. The client signal transmission unit 61 receives the signal output from the error correction decoding unit 63 and outputs a 100 GbE or OTU4 frame signal as a client signal.

  Here, attention is focused on the signal output from the distribution unit 52, that is, the signal before being supplied to the combining unit 62. As described above, the distribution unit 52 generates 20 logical lanes, and then bit-multiplexes 5 logical lanes to generate 4 physical lanes. The FAS byte described above is composed of fixed bit patterns called OA1 byte and OA2 byte. For example, OA1 has a bit pattern of “1111 0110”, OA2 has a bit pattern of “0010 1000”, and FAS is composed of 6 bytes of OA1, OA1, OA1, OA2, OA2, and OA2, as shown in FIG. (However, the FAS OH Byte 6 may be given a number indicating the order in the multi-lane transmission of the OTU 4 as described above). In the distribution unit 52, if the bit string including the FAS fixed pattern that is the mark of the head of the frame is bit-multiplexed with the bit strings of other logical lanes, each of the four physical lanes after the bit multiplexing is performed. In the signal, the FAS byte does not appear when the pattern is maintained. In the case of the OTU frame shown in FIG. 19, the structure of the frame is detected based on the repeated appearance of FAS bytes indicating the beginning of the frame at a fixed frame size (4 rows × 4080 columns = 16320 bytes). The frame structure cannot be detected from the individual signals of the four physical lanes. That is, the signal of each of the four physical lanes after being distributed no longer holds the frame structure. In addition to FAS, when detecting the structure of a frame using MFAS (Multi-Frame Alignment Signal) shown in FIG. 22, MFAS needs to appear repeatedly in addition to FAS. However, if bit multiplexing is performed as described above, MFAS cannot be detected. Therefore, FAS bytes appearing in the frame size period, or various signal processing performed by reconfiguring the frame by detecting the MFAS bytes in addition to the FAS bytes, for example, after error distribution codes etc. There is a problem that it cannot be performed before the coupling portion 62.

  The present invention has been made in view of such a problem, and in transmission of a signal having a frame structure, a transmission apparatus and a transmission system capable of performing signal processing using the frame structure at the subsequent stage of the distributing unit and the preceding stage of the combining unit. An object is to provide a receiving apparatus and a transmission method.

In order to solve the above problem, an aspect of the present invention includes a client signal receiving unit that receives a client signal and outputs a frame signal having a frame structure, and a byte of an overhead element used for detection of the frame structure of the frame signal. A plurality of blocks having the same size are generated by dividing the frame signal based on a value greater than or equal to a number, and when the number of generated blocks is an even number, the generated lane rotation is performed for each frame. The block is distributed to a plurality of lanes so that the block including the overhead element is included in each lane, and the generated block is performed without performing the lane rotation when the number of generated blocks is an odd number. the blocks as block including the overhead elements in each lane of Is distributed to a plurality of lanes, and the frame structure is detected based on the overhead elements included in the signals of each of the plurality of lanes distributed by the distribution unit, and each of the plurality of lanes is detected. A transmission apparatus comprising: a signal processing unit that performs signal processing on a signal; and a transmission unit that transmits signals included in the plurality of lanes.

One embodiment of the present invention is the above-described invention, wherein the signal processing unit includes a first error correction coding unit and a second error correction coding unit, and at least the second error correction coding unit. The encoding unit is disposed on the plurality of lanes to which the frame signal is distributed by the distributing unit, and the first error correction encoding unit and the second error correction encoding unit are respectively An error correction code having a different redundancy may be added to a given signal.

According to another aspect of the present invention, in the invention described above, the distribution unit is arranged for each of the first distribution unit and the plurality of lanes to which the frame signal is distributed by the first distribution unit. A plurality of second distribution units, wherein the first distribution unit is the number of bytes of overhead elements used to detect the frame structure of the signal for the frame signal output by the client signal reception unit. Block generation based on the above values and distribution to the plurality of lanes are performed, and the plurality of second distribution units are used to detect the frame structure of the signals for the signals included in the plurality of lanes. Block generation based on a value greater than or equal to the number of bytes of overhead elements and distribution to a plurality of lanes are performed, and the signal processing unit includes a plurality of blocks between the first distribution unit and the second distribution unit. A plurality of lanes are arranged, or a plurality of lanes are arranged in each of a plurality of lanes between the second distribution unit and the transmission unit, and the first distribution unit or the second distribution is arranged. For each of the plurality of lanes distributed by the unit, the frame structure is detected based on the overhead element included in the signal for each of the plurality of lanes, and the signal for each signal of the plurality of lanes is detected. Processing may be performed, and the transmission unit may transmit signals included in the plurality of lanes output from the second distribution unit or the signal processing unit.

According to another aspect of the present invention, in the invention described above, the signal processing unit is further disposed between the client signal receiving unit and the first distribution unit, and is output from the client signal receiving unit. The frame structure is detected based on the overhead element included in the signal to be processed and signal processing is performed on the frame signal, and the first distribution unit applies the frame signal output from the client signal reception unit to the frame signal. Instead, the frame signal output from the signal processing unit is divided into blocks based on a value greater than or equal to the number of bytes of overhead elements used to detect the frame structure of the signal and distributed to the plurality of lanes. Also good.

One aspect of the present invention is the above-described invention, wherein the distribution unit is configured to detect the frame structure when the distribution unit divides the frame signal to generate a plurality of blocks having the same size. If a value greater than or equal to the number of bytes of an element and a divisor of the frame size of the frame signal is selected, and the divisor does not exist or cannot be selected as a divisor that is divided into an appropriate size, adding data to the frame of the frame signal, you may select the divisor value of the size of the frame of the frame signal in which the data is added.

One embodiment of the present invention is based on a client signal receiving unit that receives a client signal and outputs a frame signal having a frame structure, and a value greater than or equal to the number of bytes of an overhead element used for detecting the frame structure of the frame signal. The frame signal is divided to generate a plurality of blocks having the same size, and when the number of generated blocks is an even number, the overhead element of the generated blocks is performed by performing lane rotation for each frame. When the number of generated blocks is an odd number, the overhead elements of the generated blocks are reduced without performing the lane rotation. min the block as the block is included in each lane in a plurality of lanes containing The frame structure is detected based on the overhead elements included in the signals of each of the plurality of lanes distributed by the distribution unit, and the transmission side for each signal of the plurality of lanes A transmission device comprising: a transmission-side signal processing unit that performs signal processing; a transmission unit that transmits signals included in the plurality of lanes; a reception unit that receives a signal transmitted from the transmission device; and the frame signal Receiving side signal processing corresponding to the transmitting side signal processing performed by the transmitting side signal processing unit, and outputting the received side signal processed signal for each lane, and a plurality of lanes based on the overhead elements included in the frame signal, divided, it detects the frame structure, and a coupling portion for coupling a signal which is divided into a plurality of lanes, the connection part Receiving a signal coupling to a transmission system comprising: the client signal transmitting unit that outputs a client signal, a receiving device comprising a, a.

One embodiment of the present invention is based on a client signal receiving unit that receives a client signal and outputs a frame signal having a frame structure, and a value greater than or equal to the number of bytes of an overhead element used for detecting the frame structure of the frame signal. The frame signal is divided to generate a plurality of blocks having the same size, and when the number of generated blocks is an even number, the overhead element of the generated blocks is performed by performing lane rotation for each frame. When the number of generated blocks is an odd number, the overhead elements of the generated blocks are reduced without performing the lane rotation. min the block as the block is included in each lane in a plurality of lanes containing The frame structure is detected based on the overhead elements included in the signals of each of the plurality of lanes distributed by the distribution unit, and the transmission side for each signal of the plurality of lanes A receiving apparatus in a transmission system comprising: a transmitting signal processing section that performs signal processing; a transmitting section that transmits signals included in the plurality of lanes; and a receiving apparatus. A receiving unit that receives a signal to be transmitted, and a reception side signal processing corresponding to the transmission side signal processing performed by the transmission side signal processing unit on the frame signal; a reception-side signal processing unit that outputs, based on the overhead elements included in the frame signal which is divided into a plurality of lanes, and detects the frame structure, wherein A coupling portion for coupling a signal which is divided into the number of lanes, receives a signal in which the coupling portion is coupled to a receiving device, characterized in that it comprises a client signal transmitting unit that outputs a client signal.

Another embodiment of the present invention outputs a frame signal having a frame structure receiving a client signal, the frame signal based on a value greater than or equal to the number of bytes of overhead elements used in the detection of the frame structure of the frame signal When a plurality of blocks having the same size are generated by dividing and the number of generated blocks is an even number, by performing lane rotation for each frame, each block including the overhead element is generated among the generated blocks. the blocks to be included in lane partitioned into a plurality of lanes, if the number of the generated said block is odd, without performing the lane rotation, blocks each lane including the overhead component of the generated said block The block is distributed to a plurality of lanes to be included in the plurality of lanes. The frame structure is detected based on the overhead element included in each signal of the signal, signal processing is performed on the signal of each of the plurality of lanes, and signals included in the plurality of lanes are transmitted. This is a transmission method characterized in that.

  According to the present invention, in the transmission of a signal having a frame structure, it is possible to perform signal processing using the frame structure at the subsequent stage of the distributing unit and the preceding stage of the combining unit.

1 is a block diagram showing a multicarrier optical transmission system according to a first embodiment of the present invention. It is a figure showing an example of block division to a frame of the embodiment. It is a block diagram which shows the modification of the multicarrier optical transmission system of the embodiment. It is a figure which shows the method of addition of the error correction code | cord | chord by the modification of the embodiment. It is a figure which shows the multicarrier optical transmission system by 2nd Embodiment of this invention. It is FIG. (1) which shows the method of adding the error correcting code by the same embodiment. It is FIG. (2) which shows the method of adding the error correcting code by the same embodiment. It is a figure which shows the multicarrier optical transmission system by 3rd Embodiment of this invention. It is a figure which shows the multicarrier optical transmission system by 4th Embodiment of this invention. It is a block diagram which shows the modification (the 1) of the multicarrier optical transmission system of the embodiment. It is a block diagram which shows the modification (the 2) of the multicarrier optical transmission system of the embodiment. It is a figure which shows the example of the chip | tip division | segmentation in the multicarrier optical transmission system of 1st Embodiment by 5th Embodiment of this invention. It is a figure which shows the example of the chip | tip division | segmentation in the modification of the multicarrier optical transmission system of 1st Embodiment by the embodiment. It is a figure which shows the example of the chip | tip division | segmentation in the multicarrier optical transmission system of 2nd Embodiment by the embodiment. It is a figure which shows the example of the chip | tip division | segmentation in the multicarrier optical transmission system of 3rd Embodiment by the embodiment. It is a figure which shows the example of the chip | tip division | segmentation in the multicarrier optical transmission system of 4th Embodiment by the embodiment. It is a figure which shows the example of the chip | tip division | segmentation in the modification (the 1) of the multicarrier optical transmission system of 4th Embodiment by the embodiment. It is a figure which shows the example of the chip | tip division | segmentation in the modification (the 2) of the multicarrier optical transmission system of 4th Embodiment by the embodiment. It is a figure which shows the structure of an OTU frame. It is a figure which shows the block division | segmentation with respect to an OTU frame. It is a figure which shows the logical lane production | generation in an OTU frame. It is a figure which shows FAS and MFAS of an OTU frame. It is a block diagram which shows a logical lane and physical lane generation. It is a block diagram which shows the multicarrier optical transmission system which performs a logical lane production | generation and a physical lane production | generation.

(First embodiment)
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic block diagram showing a configuration of a multicarrier optical transmission system 1 according to the first embodiment of the present invention. The multicarrier optical transmission system 1 includes a transmission device 10, a reception device 20, and an optical transmission path 40 that connects the transmission device 10 and the reception device 20. In the transmission device 10, the client signal reception unit 11 receives a client signal such as 100GbE or OTU4 from an externally connected device. Further, the client signal reception unit 11 outputs the received client signal as it is when it is an OTU4 frame, and maps and outputs it to the OTU4 frame when it is 100 GbE. The first distributor 12 divides the OTU4 frame signal output from the client signal receiver 11 into blocks. Here, when the first distribution unit 12 divides the signal into blocks, the first division unit 12 is a divisor value of the size of the OTU4 frame, and a functional unit that performs signal processing with reference to the signal after distribution is the OTU4 frame. A value equal to or greater than the number of bytes of overhead elements required for detecting the frame structure is selected as the size of the block to be divided. For example, in the case of an OTU4 frame, the frame size is 16320 bytes. The divisor of 16320 is 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 16, 17, 20, ..., 4080, 5440, 8160, 16320, and these values are blocks. Candidate for size. As an example of processing of the functional unit that performs signal processing with reference to the distributed signal, there is error correction encoding processing by the error correction encoding units 13a and 13b shown in FIG. 1, and only FAS bytes are used in the processing. When the frame structure is detected, a value of 6 bytes or more, which is the length of the FAS byte, is selected as the block size. The first distribution unit 12 divides the OTU4 frame signal into blocks based on the value selected as the block size.

  FIG. 2 shows an example of dividing into blocks. FIG. 2A shows one frame into 16320 byte blocks, FIG. 2B shows one frame into 4080 byte blocks, and FIG. FIG. 2D shows a state in which one frame is divided into 2040 byte blocks, FIG. 2D shows a state in which one frame is divided into 1020 byte blocks, and FIG. Also, the first distribution unit 12 distributes the block after being divided into blocks into two signals SC # 1 and SC # 2 corresponding to the subcarriers in a round robin manner. Here, when the number of blocks is an even number, the FAS at the head of the OTU4 frame is distributed to only one lane. Therefore, the lane rotation described above is performed for each frame so that the FAS is distributed to two lanes. Make a distribution. When the number of blocks is an odd number, the FAS is alternately distributed to the two lanes without performing lane rotation. The error correction encoding units 13a and 13b add an error correction code to each signal distributed by the first distribution unit 12. Here, the error correction encoders 13a and 13b have the redundancy of about 7% which is the same as RS (255, 239) or RS (255, 239) defined in the ITU-T recommendation of Non-Patent Document 1. The error correction code is added using another encoding method having another redundancy method different from that of RS (255, 239), for example, a redundancy property of about 20%.

  The second distributors 16a and 16b distribute the signal, to which the error correction code is added by the error correction encoders 13a and 13b, to two so as to correspond to the X polarization and the Y polarization. That is, the first distribution unit 12 distributes the SC # 1 and SC # 2 signals corresponding to the subcarriers, and the second distribution units 16a and 16b correspond to the X polarization and the Y polarization. As a result, it is distributed to four lanes of SC # 1X polarization, SC # 1Y polarization, SC # 2X polarization, and SC # 2Y polarization. Similarly to the first distributor 12, the second distributors 16a and 16b perform signal processing with reference to the frame size of the signals output by the error correction encoders 13a and 13b and the signals after distribution. The signal distribution is performed based on the number of bytes of overhead elements necessary to detect the frame structure required by the processing of the functional unit to be performed. For example, in the digital modulation processing by the digital modulation unit included in the digital modulation unit / transmission unit / multiplexing unit 19 connected to the second distribution units 16a and 16b, after detecting the frame structure, A training sequence for estimating chromatic dispersion or the like may be added. In this case, when the frame structure is detected using the FAS byte, a value of 6 bytes or more, which is the length of the FAS byte, is selected as the block size, and each of the second distribution units 16a and 16b distributes the signal. . In the digital modulation unit / transmission unit / multiplexing unit 19, the digital modulation unit includes SC # 1X polarization, SC # 1Y polarization, SC # 2X polarization, SC # distributed by the second distribution units 16a and 16b. Each signal of 2Y polarization is modulated by the 2SC-DP-BPSK method to multiplex the signal, the signal modulated by the transmission unit is transmitted, the signal is wavelength-multiplexed by the multiplexing unit, and the transmission signal Then, it is transmitted over a long distance through the optical transmission line 40.

  In the receiving device 20, the demultiplexing unit / receiving unit / digital demodulating unit 29 is configured such that the demultiplexing unit demultiplexes the optical signal, the receiving unit reads out the signal, and the digital demodulating unit demodulates the signal, thereby SC #. Four signals corresponding to 1X polarization, SC # 1Y polarization, SC # 2X polarization, and SC # 2Y polarization are output. The second coupling units 26a and 26b detect the FAS byte from the two signal blocks of X polarization and Y polarization, respectively. The second coupling units 26a and 26b reorder and deskew the two signal blocks using the detected FAS byte to reproduce and output the original signal. The error correction decoding units 23a and 23b perform error correction processing on the signals output from the second coupling units 26a and 26b, respectively. The first combining unit 22 detects the FAS byte from the two signal blocks output from the error correction decoding units 23a and 23b. Further, the first combining unit 22 reorders and deskews the two signal blocks using the detected FAS byte to reproduce and output the original OTU4 frame structure signal. The client signal transmission unit 21 outputs the OTU4 frame signal output from the first combining unit 22 as it is or after converting it into a 100 GbE signal.

  With the configuration of the first embodiment described above, the first distribution unit 12 and the second distribution units 16a and 16b distribute signals while maintaining the overhead elements necessary for frame structure detection, for example, the FAS byte area. To do. Thereby, the frame structure can be detected also in the signal after distribution output from the first distributor 12 and the second distributors 16a and 16b. Therefore, signal processing using a frame structure such as error correction coding processing can be performed after signal distribution. Thereby, for example, the circuit element for performing the signal processing can be divided and arranged after distribution, and the degree of freedom of arrangement of the circuit element can be increased, which cannot be realized by a single device due to the limitation of the circuit scale. It can be realized by dividing the function into a plurality of functions.

In the configuration of the first embodiment described above, the function unit that refers to the signal after the distribution by the first distribution unit 12 and the second distribution units 16a and 16b is not only the FAS byte but also the FAS byte. In some cases, the frame structure is detected with reference to both MFAS bytes. In this case, a value of 7 bytes or more, which is the length of FAS + MFAS bytes, is selected as the block size by the first distribution unit 12 and the second distribution units 16a and 16b. In addition, when the function unit that refers to the signal after distribution uses one line in the frame structure of 4 rows × 4080 columns in addition to the FAS byte and the MFAS byte, a value of 4080 bytes or more is a block size. Will be selected. When a value of 7 bytes or more, which is the length of FAS + MFAS bytes, is selected, the second combining units 26a and 26b and the first combining unit 22 in the receiving device 20 combine two signal blocks. In this case, the MFAS byte may be detected in addition to the FAS byte, and the original signal may be reproduced by reordering and deskewing the two signal blocks using the detected FAS byte and MFAS byte.
Further, in the second distribution units 16a and 16b, even if the first distribution unit 12 selects a value exceeding the block size used for dividing the block, a frame structure using an overhead element corresponding to the selected value Cannot be detected. For example, if the first distributor 12 selects 6 bytes, which are FAS bytes, as the block size, even if the second distributors 16a and 16b select 7 bytes of FAS + MFAS bytes as the block size, In the distribution unit 12, the MFAS byte pattern is not maintained for the signals after the distribution by the second distribution units 16a and 16b. Therefore, the value of the block size that can be selected in the second distribution units 16a and 16b is a value equal to or smaller than the block size selected in the first distribution unit 12. Therefore, the block size selected by the first distribution unit 12 is used to detect the frame structure required by the processing of the functional unit that performs signal processing with reference to the signals distributed by the second distribution units 16a and 16b. It is necessary to select it considering the number of bytes of necessary overhead elements.

In the configuration of the first embodiment, error correction encoding units 13a and 13b that perform error correction encoding, and a transmission path as signal processing function units that perform signal processing with reference to the distributed signal. The digital modulation unit of the digital modulation unit / transmission unit / multiplexing unit 19 to which a training sequence for estimating the chromatic dispersion of the signal is added has been described as an example. Signal processing using the frame structure includes processing such as scrambling, insertion and deletion of training sequences for digital signal processing, and access to overhead information, in addition to processing by these functional units.
In the configuration of the first embodiment, the OTU4 having a standard frame size of 16320 bytes has been described as a signal frame. However, the configuration of the present invention is not limited to the configuration of the embodiment, and for example, An OTU4V signal or the like having a frame size different from that of OTU4 may be applied. In this case as well, processing of a functional unit that is a divisor value of the frame size and performs signal processing with reference to the distributed signal A value equal to or greater than the number of bytes of overhead elements necessary to detect the frame structure required by is selected as the block size.

Further, as a modification of the first embodiment, a functional unit that performs error correction coding processing, such as the multicarrier optical transmission system 1a shown in FIG. 3, includes first error correction coding units 14a and 14b, The second error correction encoders 15a and 15b may be divided into a plurality of stages.
In the configuration of FIG. 3, the first error correction encoders 14a and 14b perform HD-FEC (Hard Decision-Forward Error Correction) with a redundancy of about 7%, and the second error correction encoders 15a and 15b 15b performs SD-FEC (Soft Decision Forward Error Correction) of about 13% redundancy. This makes it possible to perform error correction coding with a redundancy of about 20% in total. Specifically, for example, the processing is to form a frame having 4592 columns as shown in FIG. First, the first error correction encoders 14a and 14b add an error correction code having a redundancy of about 7% to the region of 3825 columns to 4080 columns of the frame. Then, the second error correction encoders 15a and 15b add an error correction code having a redundancy of about 13% to the 4081 column to 4592 column region of the frame. If the exact redundancy in this example is calculated, an error correction code of 4 × (4080-3824) bytes is added to 4 × 3824 bytes of data for FEC having a redundancy of about 7%. The degree is 4 × (4080-3824) / (4 × 3824) = 6.7%. Further, the FEC having a redundancy of about 13% adds an error correction code of 4 × (4592-4080) bytes to data of 4 × 3824 bytes, so that the redundancy is 4 × (4592-4080) / (4 × 3824) = 13.4%. When both are summed, the redundancy is 20.1%. Further, the size of the entire frame at this time is 4 × 4592 = 18368 bytes. Therefore, the second distributors 16a and 16b take into consideration the divisor of 18368, that is, 1, 2, 4, 7, while taking into account that the digital modulator / transmitter / multiplexer 19 detects the frame structure. The block size is selected from 8, 14, 16, 28, 32,..., 4592, 9184, 18368.

The receiving device 20a also includes two decoding units, the second error correction decoding units 25a and 25b, and the first error correction decoding units 24a and 24b so as to correspond to the configuration of the transmission device 10a. become.
In addition to the effects obtained by the configuration of the first embodiment shown in FIG. 1, by adding error correction processing in a plurality of stages and connecting error correction coding as in the modification of the first embodiment, the total Thus, it is possible to realize error correction performance with a high redundancy of about 20%. In addition, since the error correction coding functional unit is divided into two, it is possible to further increase the degree of freedom in the arrangement of circuit elements.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 5 is a schematic block diagram showing a multicarrier optical transmission system 2 according to the second embodiment of the present invention. Similarly to the multicarrier optical transmission system of the first embodiment, the multicarrier optical transmission system 2 performs 100 Gbit / s transmission by the 2SC-DP-BPSK method. In FIG. 5, the same components as those in the first embodiment are denoted by the same reference numerals, and hereinafter, configurations different from the multicarrier optical transmission system 1 a illustrated in FIG. 3, which is a modification of the first embodiment, will be described. The multicarrier optical transmission system 2 includes the first and second error correction encoding units and the error correction decoding unit as in the multicarrier optical transmission system 1a. The first distribution unit 12 is different from the first distribution unit 12 in that the first error correction decoding unit 24 is provided after the first combination unit 22. Also in the multicarrier optical transmission system 2, as in the multicarrier optical transmission system 1a, for example, the first error correction encoding unit 14 performs HD-FEC with a redundancy of about 7%, and the second The error correction encoders 15a and 15b perform SD-FEC with about 13% redundancy.

  Processing for adding an error correction code in the multicarrier optical transmission system 2 according to the second embodiment will be described. In FIG. 5, the client signal receiving unit 11 outputs the OTU frame shown in FIG. However, in the output signal, the error correction code is not yet written in the error correction code area of columns 3825 to 4080. The first error correction encoding unit 14 writes the error correction code in the error correction code areas of columns 3825 to 4080 of the OTU frame output from the client signal receiving unit 11. As shown in FIG. 6A, the first distribution unit 12 divides a frame of 4 rows × 4080 columns into 4080 bytes, that is, blocks each row as one block. Here, the divided blocks are referred to as 1-1, 1-2, 1-3, and 1-4 for the frame 1, and the same applies to the subsequent frames. -1, 2-2, 2-3, 2-4 and frame 3 are referred to as 3-1, 3-2, 3-3, 3-4. When output from the error correction encoding unit 14 to the first distribution unit 12, the transmission order of frames is first transmitted from the first byte to the 4080th byte in the first row, and then the second row. This is performed from the first byte to the 4080th byte, and this is repeated for each frame. The first distributor 12 distributes the signal having the frame structure shown in FIG. 6A to two lanes as shown in FIG. 6B according to the block. For example, for frame 1, blocks 1-1, 1-2, 1-3, and 1-4 are alternately distributed in the order of lane 1 and lane 2.

  When the distribution of the block of one frame is completed, the first distribution unit 12 performs distribution by changing the lane rotation, that is, changing the start lane of block distribution. For example, the blocks 2-1, 2-2, 2-3, 2-4 of the frame 2 are alternately distributed in the order of lane 2 and lane 1. As a result, in the blocks shown in FIGS. 6 (a) and 6 (b), the area of the overhead element at the head of the frame indicated by hatching appears in two lanes. For the block after distribution, paying attention to the signal of one lane, blocks 1-1, 1-3 surrounded by the broken line of lane 1 in FIG. When 2-2 and 2-4 are considered as a group, they can be viewed as signals having a frame structure as shown in FIG. The second error correction encoders 15a and 15b output the signal shown in FIG. 7A (reproduced from FIG. 6C) output from the first distributor 12 by 4 rows × 4080 columns. As shown in FIG. 7B, an area from 4081 to 4592 columns is added and an error correction code is written in this area.

With the configuration of the second embodiment, overhead elements necessary for detecting the frame structure in the first distribution unit 12 and the second distribution units 16a and 16b, for example, FAS and MFAS, as in the first embodiment. Distributes the signal while maintaining the byte area. Thereby, the frame structure can be detected also in the signal after distribution output from the first distributor 12 and the second distributors 16a and 16b. Therefore, signal processing using a frame structure such as error correction coding processing can be performed after signal distribution. Thereby, for example, the circuit element for performing the signal processing can be divided and arranged after distribution, and the degree of freedom of arrangement of the circuit element can be increased, which cannot be realized by a single device due to the limitation of the circuit scale. It can be realized by dividing the function into a plurality of functions.
In the configuration of the second embodiment, the first error correction encoding unit 14 is disposed before the first distribution unit 12, and the second error correction encoding unit is disposed after the first distribution unit 12. 15a and 15b are arranged. Then, the first error correction coding unit 14 performs HD-FEC with about 7% redundancy, and the second error correction coding units 15a and 15b perform SD-FEC with about 13% redundancy. Make it. By connecting the two error correction coding processes in this way, it is possible to realize a high redundancy performance of about 20% in total.
In the configuration of the second embodiment described above, in the receiving device 20b, the first error correction decoding unit 24 performs an error on the entire signal (in the above example, on the entire 100 Gbit / s signal). Perform correction processing. In contrast, the second error correction decoding units 25a and 25b perform error correction processing on the two branched signals (in the case of the above example, on the 50 Gbit / s signal). Therefore, even if the bit error rate of one of the two 50G signals is deteriorated, the first error correction decoding unit 24 further performs error correction together with a 100 Gbit / s signal in the subsequent stage. High error correction capability can be provided, and signal quality can be improved.

(Third embodiment)
Next, a third embodiment of the present invention will be described. FIG. 8 is a schematic block diagram showing a multicarrier optical transmission system 3 according to the third embodiment of the present invention. Similarly to the multicarrier optical transmission systems of the first and second embodiments, the multicarrier optical transmission system 3 performs 100 Gbit / s transmission by the 2SC-DP-BPSK method. In FIG. 8, the same components as those in the first and second embodiments are denoted by the same reference numerals, and the configuration different from the multicarrier optical transmission system 1a shown in FIG. 3, which is a modification of the first embodiment, will be described below. . Similarly to the multicarrier optical transmission system 1a, the multicarrier optical transmission system 3 includes the first and second error correction encoding units and the error correction decoding unit, but the second error correction encoding unit 15 -1, 15-2 and second error correction encoding units 15-3 and 15-4 are different from each other in that they are arranged after the second distribution units 16a and 16b, respectively. Also, in the receiving device 20c so as to correspond to the configuration of the transmitting device 10c, the second error correction decoding units 25-1, 25-2 and the second error correction decoding units 25-3, 25-4 are respectively It differs in that it is arranged in front of the second coupling parts 26a and 26b. Also in the configuration of the third embodiment, similarly to the multicarrier optical transmission system 1a, for example, the first error correction encoding units 14a and 14b perform HD-FEC with about 7% redundancy, The error correction encoding units 15-1, 15-2, 15-3, and 15-4 perform SD-FEC with about 13% redundancy.

  A procedure for adding an error correction code by dividing a signal into blocks in the multicarrier optical transmission system 3 according to the third embodiment will be described. First, the first distribution unit 12 divides a block into blocks having a block size of 4080 bytes and distributes the blocks to two lanes. This division processing is the same as the processing described with reference to FIGS. 6A and 6B described above. The signal shown in FIG. 6C is given to the first error correction encoding units 14a and 14b by the division processing. As described above, the blocks 1-1, 1-3, 2-2, and 2-4, which are the configuration of the first signal in FIG. 6C, have the same size as the signal for each frame in FIG. Since they have the same size, the 3825 to 4080 columns are error correction code areas. The first error correction encoders 14a and 14b write error correction codes in this area. For example, the second distribution units 16a and 16b select and divide and distribute 6 bytes or more, which is the size of the FAS byte, as the block size to be divided. By distributing in this way, in each lane distributed by the second distribution units 16a and 16b, the frame size is 4 × 4080 bytes, and a signal in which the FAS that is the head of the frame appears periodically appears. . The second error correction encoders 15-1, 15-2, 15-3, and 15-4 add an area of 4081 to 4592 columns to the signal, and about 13% redundancy is added to the area. Write the error correction code.

According to the configuration of the third embodiment, overhead elements necessary for detection of the frame structure in the first distributor 12 and the second distributors 16a and 16b, for example, FAS, as in the first and second embodiments. And the signal is distributed while maintaining the configuration of the byte area of MFAS. Thereby, the frame structure can be detected also in the signal after distribution output from the first distributor 12 and the second distributors 16a and 16b. Therefore, signal processing using a frame structure such as error correction coding processing can be performed after signal distribution. Thereby, for example, the circuit element for performing the signal processing can be divided and arranged after distribution. In the third embodiment, since the second error correction encoding unit is divided into four parts, a more flexible arrangement can be performed as compared with the multicarrier optical transmission system 1a. As the degree of freedom of arrangement increases in this way, it becomes possible to divide and realize a function that cannot be realized with a single device due to the limitation of the circuit scale.
In the configuration of the third embodiment, the first error correction coding units 14a and 14b are arranged after the first distribution unit 12, and the second error correction is performed after the second distribution units 16a and 16b. Encoding units 15-1 and 15-2 and second error correction encoding units 15-3 and 15-4 are arranged. Then, the first error correction encoders 14a and 14b perform HD-FEC with about 7% redundancy, and the second error correction encoders 15-1, 15-2, 15-3, 15- 4 to perform SD-FEC with about 13% redundancy. By connecting the two error correction coding processes in this way, it is possible to realize a high redundancy performance of about 20% in total.

  In the first, second, and third embodiments, the first distribution unit 12 and the second distribution units 16a and 16b each distribute two times. A larger number of distributions may be used. For example, in the case of N subcarriers instead of 2 subcarriers, the first distribution unit 12 performs N distribution. Further, for example, when using DP-QPSK (Quadrature Phase Shift Keying) or DP-16QAM (Quadrature Amplitude Modulation), which is another multi-level modulation method, instead of DP-BPSK, the second distributing unit The distribution number of 16a and 16b may be larger than two distributions.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. FIG. 9 is a schematic block diagram showing a multicarrier optical transmission system 4 according to the fourth embodiment of the present invention. Similarly to the multicarrier optical transmission systems of the first, second, and third embodiments, the multicarrier optical transmission system 4 performs 100 Gbit / s transmission by the 2SC-DP-BPSK method. In FIG. 9, the same components as those of the first, second, and third embodiments are denoted by the same reference numerals, and the configurations different from those of the multicarrier optical transmission system 1 of the first embodiment shown in FIG. 1 will be described below. . The multicarrier optical transmission system 1 includes a first distribution unit 12, two error correction encoding units 13 a and 13 b and two error correction code added to two lanes distributed by the first distribution unit 12. The second distributors 16a and 16b for further distributing the above are provided. On the other hand, the multicarrier optical transmission system 4 changes the arrangement of the first distribution unit 12, the error correction encoding units 13 a and 13 b, and the second distribution units 16 a and 16 b of the multicarrier optical transmission system 1 to the first distribution unit 12. The distribution unit 12, the second distribution units 16a and 16b, and the error correction coding units 13a and 13b are changed, and the first distribution unit 12 and the second distribution units 16a and 16b are combined into one. In this configuration, two error correction encoding units 13-1, 13-2, 13-3, and 13-4 are arranged. Also in the configuration of the receiving device 20d, four error correction decoding units 23-1, 23-2, 23-3, 23-23 are arranged after the demultiplexing unit / reception unit / digital demodulation unit 29 corresponding to the configuration of the transmission device 10d. 4 and a coupling unit 27 that couples the signals divided into four.

  The difference between the multicarrier optical transmission system 4 of the fourth embodiment and the multicarrier optical transmission system 1 of the first embodiment is the number of error correction coding units and the unit of processing. The multi-carrier optical transmission system 1 shown in FIG. 1 includes two error correction encoding units 13a and 13b, each of which processes a 50 Gbit / s signal. On the other hand, the multicarrier optical transmission system 4 shown in FIG. 9 includes four error correction encoding units 13-1, 13-2, 13-3, and 13-4, each of which has a signal of 25 Gbit / s. Process. In general, the higher the performance of the error correction coding unit and the higher the data rate to be processed, the larger the scale. Therefore, when realizing the same performance, the circuit scale becomes smaller as the processing data rate is lower. For example, when it is desired to use an error correction code with extremely high accuracy, two error correction codes are used as shown in FIG. 1 due to scale limitations when configuring an LSI (Large Scale Integration), FPGA (Field Programmable Gate Array), or the like. The units 13a and 13b may not be configured because the circuit scale becomes too large. Even in such a case, it is possible to configure with four error correction encoding units 13-1, 13-2, 13-3, and 13-4 as in the fourth embodiment.

The division and distribution processing by the distribution unit 17 is a two-stage distribution performed by the first distribution unit 12 and the second distribution units 16a and 16b of the first, second, and third embodiments. The process is performed in one stage. Also in the fourth embodiment, the value is a divisor of the frame and is equal to or greater than the number of bytes of overhead elements necessary to detect the frame structure required by the processing of the functional unit that references the signal after distribution. Will be selected as the block size. Further, when distributing, the distributing unit 17 distributes the lanes 1 to 4 in a round-robin manner, and performs lane rotation for the lanes 1 to 4 so that an overhead element periodically appears in each lane. Make a distribution.
As a result, the frame structure can also be detected in the post-distribution signal output from the distribution unit 17. Therefore, signal processing using a frame structure such as error correction coding processing can be performed after signal distribution, and circuit elements that perform the signal processing can be divided and arranged after distribution. In the third embodiment, since the error correction encoding unit is divided into four parts, it is possible to perform a more flexible arrangement than the multicarrier optical transmission system 1. As the degree of freedom in arrangement increases in this way, it becomes possible to divide and realize a function that cannot be realized with a single device due to the limitation of the circuit scale.

Also in the multicarrier optical transmission system 4 according to the fourth embodiment, an error correction encoding unit and an error correction decoding unit as shown in FIG. 10 may be divided into two. Also, as shown in FIG. 11, the first error correction encoding unit and the first error correction decoding unit, which are divided into two, are arranged before the distributing unit 17 and after the combining unit 27, respectively. It is good also as a simple structure. Also in the case of the configurations of FIGS. 10 and 11, as in the modifications of the first embodiment and the configurations of the second and third embodiments, about 7% in the first error correction encoding process. The redundancy HD-FEC is performed, and the SD-FEC having a redundancy of about 13% is performed in the second error correction encoding process. Further, in FIGS. 9, 10, and 11, the example in which the number of distributions is four has been described. However, the number of distributions is not limited to four distributions, and may be configured with a larger number of distributions.
Note that the redundancy and coding algorithm of the error correction code shown in the first to fourth embodiments are described as examples, and other redundancy and other algorithms may be applied.
In the first to fourth embodiments, the description has been made on the premise that a prescribed frame, for example, an OTU4 frame is applied. However, the configuration of the present invention is not limited to the embodiment. When there is no convenient divisor as a divisor of the frame length, the first distribution unit 12, the second distribution units 16a and 16b, and the distribution unit 17 may be applied to a frame having an arbitrary frame length. A method of adding a dummy byte to the frame as disclosed in Japanese Patent Application Laid-Open No. 2011-223454 may be applied to increase the frame length and select a convenient divisor. In this case, in the first coupling unit 22 on the receiving side, the second coupling units 26a and 26b, and the coupling unit 27, a process of deleting dummy bytes is performed after the frame is reproduced.

(Fifth embodiment)
Next, as a fifth embodiment of the present invention, an example of dividing each functional unit into chips in the configuration shown in the first to fourth embodiments will be described with reference to FIGS. In the first to fourth embodiments, a configuration is shown in which a plurality of error correction encoding units are provided after the distributing unit, and a plurality of error correction decoding units are provided before the combining unit. As described above, generally, the circuit scale of error correction processing is large, and the scale increases as the performance increases and the data rate to be processed increases. For this reason, it may be difficult to implement error correction code processing in a single LSI or FPGA due to restrictions on circuit scale. On the other hand, for example, as shown in FIG. 12, in the multicarrier optical transmission system 1 according to the first embodiment, the error correction coding process can be performed after the first distributor 12, It is possible to arrange the error correction encoding units 13a and 13b in two after the one distribution unit 12. By dividing the error correction coding functional unit into two, the bit rate processed by one functional unit can be lowered, and accordingly, the error correction coding circuit scale can be increased while maintaining the error correction performance. Can be small. Therefore, when configuring the transmission apparatus 10, high-performance error correction coding processing is realized as a form of two chips c1 and c2 each having an error correction coding function unit having an appropriate circuit scale. It becomes possible. The same applies to the error correction decoding units 23a and 23b of the receiving device 20, and can be realized as a form of two chips c3 and c4.

Similarly, in the case of the multicarrier optical transmission system 1a according to the modification of the first embodiment shown in FIG. 13, the transmitter 10a is divided into two chips c5 and c6, and the receiver 20a is chip c7. , C8 can be divided into two chips. In the case of the multicarrier optical transmission system 2 according to the second embodiment shown in FIG. 14, the transmitter 10b includes a chip c9 having two error correction encoding function units and one error correction encoding function unit. The receiving device 20b is divided into two chips, namely, a chip c11 having two error correction decoding function units and a chip c12 having one error correction decoding function unit. can do. In the case of the multicarrier optical transmission system 3 according to the third embodiment shown in FIG. 15, the transmitting device 10c is divided into two chips c13 and c14 each having three error correction coding functional units, and the receiving device 20c can also be realized by being divided into two chips of chips c15 and c16 each having three error correction decoding function units. In the case of the multicarrier optical transmission system 4 of the fourth embodiment shown in FIG. 16, the transmitter 10d is divided into four chips c17, c18, c19, and c20 each having one error correction coding function unit. Thus, the receiving device 20d can also be realized by being divided into four chips c21, c22, c23, and c24 each having one error correction decoding function unit. In the case of the multi-carrier optical transmission system 4a of the fourth embodiment shown in FIG. 17, the transmitter 10e is divided into four chips c25, c26, c27, and c28 each having two error correction coding functional units. Thus, the receiving device 20e can also be realized by being divided into four chips c29, c30, c31, and c32 each having two error correction decoding functional units. In the case of the multicarrier optical transmission system 4b of the fourth embodiment shown in FIG. 18, the transmitter 10f is divided into four chips c33, c34, c35, and c36 each having one error correction coding function unit. Thus, the receiving device 20f can also be realized by being divided into four chips c37, c38, c39, and c40 each having one error correction decoding function unit.
Note that the chip division examples shown in FIGS. 12 to 18 are examples, and may be arbitrarily divided according to the circuit scale and the like.
16, 17 and 18, the client signal receiver 11, the distributor 17, the client signal transmitter 21, the combiner 27, and the first error correction encoder 14 and the first error correction decoder in FIG. 18. 24 may be included in one of the divided chips, or may be divided as another chip, and may be arbitrarily combined to be divided into each chip so as to have an appropriate arrangement. Also good.

  You may make it implement | achieve the transmission apparatus and reception apparatus of the multicarrier optical transmission system in each embodiment mentioned above with a computer. In that case, a program for realizing this function may be recorded on a computer-readable recording medium, and the program recorded on this recording medium may be read into a computer system and executed. Here, the “computer system” includes an OS and hardware such as peripheral devices. The “computer-readable recording medium” refers to a storage device such as a flexible medium, a magneto-optical disk, a portable medium such as a ROM and a CD-ROM, and a hard disk incorporated in a computer system. Furthermore, the “computer-readable recording medium” dynamically holds a program for a short time like a communication line when transmitting a program via a network such as the Internet or a communication line such as a telephone line. In this case, a volatile memory inside a computer system serving as a server or a client in that case may be included and a program held for a certain period of time. Further, the program may be a program for realizing a part of the above-described functions, and may be a program capable of realizing the functions described above in combination with a program already recorded in a computer system. You may implement | achieve using programmable logic devices, such as FPGA (Field Programmable Gate Array).

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes designs and the like that do not depart from the gist of the present invention.

DESCRIPTION OF SYMBOLS 1 Multicarrier optical transmission system 10 Transmission apparatus 11 Client signal receiving part 12 First distribution part 13a Error correction encoding part 13b Error correction encoding part 16a Second distribution part 16b Second distribution part 19 Digital modulation part and transmission Unit / multiplexing unit 20 receiving device 21 client signal transmitting unit 22 first combining unit 23a error correction decoding unit 23b error correction decoding unit 26a second combining unit 26b second combining unit 29 demultiplexing unit / receiving unit / digital Demodulator 40 Optical transmission line

Claims (8)

A client signal receiving unit that receives the client signal and outputs a frame signal having a frame structure;
When the frame signal is divided based on a value greater than or equal to the number of bytes of overhead elements used to detect the frame structure of the frame signal to generate a plurality of blocks of the same size, and the number of generated blocks is an even number By performing lane rotation for each frame, the blocks are distributed to a plurality of lanes so that the blocks including the overhead element among the generated blocks are included in each lane, and the number of generated blocks is an odd number. In this case, without performing the lane rotation, a distribution unit that distributes the blocks to a plurality of lanes so that blocks including the overhead element among the generated blocks are included in each lane ;
A signal processing unit that detects the frame structure based on the overhead elements included in the signals of the plurality of lanes distributed by the distribution unit, and performs signal processing on the signals of the plurality of lanes When,
A transmission unit for transmitting signals included in the plurality of lanes;
A transmission device comprising: The signal processing unit includes a first error correction encoding unit and a second error correction encoding unit,
At least the second error correction coding unit is disposed on the plurality of lanes to which the frame signal is distributed by the distribution unit,
2. The first error correction encoding unit and the second error correction encoding unit add error correction codes having different redundancy to signals given to the first error correction encoding unit and the second error correction encoding unit, respectively. The transmitting device according to 1. The distribution unit includes a first distribution unit and a plurality of second distribution units arranged for each of the plurality of lanes to which the frame signal is distributed by the first distribution unit,
The first distribution unit generates a block based on a value greater than or equal to the number of bytes of an overhead element used for detection of a frame structure of the signal for the frame signal output from the client signal reception unit, and the plurality of lanes Distribution to
The plurality of second distribution units generate a block based on a value greater than or equal to the number of bytes of overhead elements used for detection of the frame structure of the signal for signals included in the plurality of lanes, Make a distribution,
A plurality of the signal processing units are arranged in each of a plurality of lanes between the first distribution unit and the second distribution unit, or between the second distribution unit and the transmission unit. A plurality of lanes are arranged in each of the plurality of lanes, and are included in the signal for each of the plurality of lanes with respect to each of the plurality of lanes distributed by the first distribution unit or the second distribution unit. Detecting the frame structure based on the overhead element, performing signal processing on each signal of the plurality of lanes;
The transmission device according to claim 1, wherein the transmission unit transmits signals included in the plurality of lanes output from the second distribution unit or the signal processing unit. The signal processing unit is further disposed between the client signal receiving unit and the first distribution unit, and the frame structure is based on the overhead element included in a signal output from the client signal receiving unit. Detect and perform signal processing on the frame signal;
Wherein the first distribution unit, the instead of the frame signal client signal receiving unit is outputted, the byte overhead elements used in the detection of the frame structure of the signal to the frame signal the signal processing unit outputs The transmission apparatus according to claim 3, wherein block division and distribution to the plurality of lanes based on a value greater than or equal to a number are performed. The distribution unit, when generating a plurality of blocks of the same size by dividing the frame signal, a frame of said frame signal to a number of bytes or more values overhead elements used in the detection of the frame structure Select a divisor value for size, and if the divisor does not exist or if a divisor that can be divided into appropriate sizes cannot be selected, data is added to the frame of the frame signal, and the data is added The transmission apparatus according to claim 1, wherein a value that is a divisor of a size of a frame of the frame signal that has been selected is selected. A client signal receiving unit that receives the client signal and outputs a frame signal having a frame structure;
When the frame signal is divided based on a value greater than or equal to the number of bytes of overhead elements used to detect the frame structure of the frame signal to generate a plurality of blocks of the same size, and the number of generated blocks is an even number By performing lane rotation for each frame, the blocks are distributed to a plurality of lanes so that the blocks including the overhead element among the generated blocks are included in each lane, and the number of generated blocks is an odd number. In this case, without performing the lane rotation, a distribution unit that distributes the blocks to a plurality of lanes so that blocks including the overhead element among the generated blocks are included in each lane ;
Transmission that detects the frame structure based on the overhead element included in the signal of each of the plurality of lanes distributed by the distribution unit, and performs transmission side signal processing on the signal of each of the plurality of lanes A side signal processing unit;
A transmission unit for transmitting signals included in the plurality of lanes;
A transmission device comprising:
A receiver for receiving a signal transmitted from the transmitter;
A reception-side signal processing unit that performs reception-side signal processing corresponding to transmission-side signal processing performed by the transmission-side signal processing unit on the frame signal, and outputs the signal subjected to the reception-side signal processing for each lane;
A coupling unit that detects the frame structure based on an overhead element included in the frame signal divided into a plurality of lanes, and combines the signals divided into the plurality of lanes;
A client signal transmission unit that receives a signal coupled by the coupling unit and outputs a client signal;
A receiving device comprising:
A transmission system comprising: And the client signal receiving unit for outputting a frame signal having a frame structure receiving a client signal, the same by dividing the frame signal based on a value greater than or equal to the number of bytes of overhead elements used in the detection of the frame structure of the frame signal When a plurality of blocks having a size are generated and the number of generated blocks is an even number, by performing lane rotation for each frame, a block including the overhead element among the generated blocks is included in each lane. When the number of generated blocks is an odd number, the blocks including the overhead element are included in each lane without performing the lane rotation. A distribution unit for distributing the block to a plurality of lanes, and the distribution Transmitter-side signal processing that detects the frame structure based on the overhead elements included in the signals of each of the plurality of lanes distributed by and performs transmission-side signal processing on the signals of the plurality of lanes A transmission device comprising: a transmission unit comprising: a transmission unit configured to transmit a signal included in the plurality of lanes; and a reception device,
A receiver for receiving a signal transmitted from the transmitter;
A reception-side signal processing unit that performs reception-side signal processing corresponding to transmission-side signal processing performed by the transmission-side signal processing unit on the frame signal, and outputs the signal subjected to the reception-side signal processing for each lane;
A coupling unit that detects the frame structure based on an overhead element included in the frame signal divided into a plurality of lanes, and combines the signals divided into the plurality of lanes;
A client signal transmission unit that receives a signal coupled by the coupling unit and outputs a client signal;
A receiving apparatus comprising: Receiving a client signal and outputting a frame signal having a frame structure;
Wherein by dividing the frame signal to generate a plurality of blocks of the same size based on the number of bytes or more values overhead elements used in the detection of the frame structure of the frame signal,
When the number of generated blocks is an even number, by performing lane rotation for each frame, the blocks are distributed to a plurality of lanes so that blocks including the overhead elements are included in each lane among the generated blocks. When the number of generated blocks is an odd number, the blocks are distributed to a plurality of lanes so that the blocks including the overhead element are included in each lane without performing the lane rotation. ,
Detecting the frame structure based on the overhead element included in each signal of the plurality of distributed lanes;
Signal processing is performed on each signal of the plurality of lanes,
A transmission method comprising: transmitting signals included in the plurality of lanes.

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