JP5983716B2 - III-V compound semiconductor photo detector - Google Patents

Description

  The present invention relates to a group III-V compound semiconductor light-receiving element and a method for manufacturing a group III-V compound semiconductor light-receiving element.

  Non-Patent Document 1 describes the production of a photodiode having a cutoff wavelength of 2.39 microns. The light receiving element includes a light receiving layer provided on the InP substrate and a p-type InGaAs window layer. The light receiving layer includes an InGaAs / GaAsSb type II quantum well structure. After the mesa etching, a SiO2 passivation film is formed on the p-type InGaAs window layer.

R. Sidhu, “Long-wavelength Photodiode on InP Using Lattice-Matched GaInAs-GaAsSb Type-II Quantum Wells” IEEE Photonics Technology Letters, Vol.17, No.12 (2005), pp.2715-2717

  According to the knowledge of the inventors, when an InGaAs window layer is used, dark current increases as compared to an InP window layer. Therefore, in an epitaxial film structure for a light receiving element having a light receiving layer on an InP substrate, an InP window layer is used as the uppermost layer of this film structure. In a front-illuminated photodiode having an epitaxial layer as an incident surface, the InP window layer does not absorb near infrared light that should reach the light receiving layer. In addition, the InP window layer is also effective in suppressing dark current, as already described.

  This epitaxial stack of photodiodes is grown by metal organic vapor phase epitaxy. The epitaxial stack includes a light receiving layer. When this light-receiving layer is made of a III-V compound semiconductor containing Sb as a group V constituent element, such as an InGaAs / GaAsSb type II type quantum well structure, in the growth of this epitaxial stack, III- containing Sb as a group V constituent element. After the V compound semiconductor layer is grown, crystal growth of the InP window layer is performed. Thereafter, an anode region is selectively formed in a part of the epitaxial stack to form a pn junction.

  In measuring the characteristics of the photodiode thus fabricated, the inventors encountered unexpected electrical characteristics (increased dark current). According to a further investigation of this unexpected characteristic, an InP window layer that originally exhibits n-type exhibits p-type conductivity. When the InP window layer exhibits p-type conductivity, a pn junction is formed even in a region other than the selectively formed anode region. Therefore, an increase in the pn junction region and surface leakage current due to exposure of the pn junction to the surface. There is a problem that dark current increases due to the increase. The inventors have found that there are the following cases in investigating this factor. For example, it has been found that antimony not supplied during the growth of the InP window layer is mixed in InP as impurities in an amount exceeding the background level. According to the study by the inventors, antimony contamination is unique to InP.

  The present invention has been made in view of such circumstances, and includes a light-receiving layer having a III-V compound semiconductor layer containing Sb as a group V constituent element and an n-type InP window layer, and a dark current. An object of the present invention is to provide a III-V compound semiconductor light-receiving device capable of reducing the above, and to provide a method for manufacturing a III-V compound semiconductor light-receiving device.

A III-V compound semiconductor light receiving element according to one aspect of the present invention includes (a) a semiconductor substrate having a main surface, (b) a light receiving layer provided on the main surface of the semiconductor substrate, and (c). A window layer provided on the light-receiving layer and having first and second portions; and (d) an anode region made of a p-type semiconductor reaching the light-receiving layer from the surface of the first portion of the window layer. With. The band gap of the III-V compound semiconductor layer is smaller than the band gap of the semiconductor substrate, the light receiving layer has a III-V group compound semiconductor layer containing at least antimony as a group V element, and the window layer includes An n-type dopant is added, and majority carriers in the second portion of the window layer are electrons.
In the group III-V compound semiconductor light-receiving device according to one aspect of the present invention, the window layer may be made of a material containing at least In and P.
Furthermore, in the III-V compound semiconductor light receiving element according to one aspect of the present invention, the window layer may be InP.
Furthermore, in the group III-V compound semiconductor light-receiving device according to one aspect of the present invention, the electron concentration in the second portion of the window layer may be 1 × 10 ¹⁶ cm ⁻³ or more.
A III-V compound semiconductor light receiving element according to one aspect of the present invention includes (a) a semiconductor substrate having a main surface, (b) a light receiving layer provided on the main surface of the semiconductor substrate, and (c). An InP layer provided on the light receiving layer and having first and second portions; and an anode region made of a p-type semiconductor extending from the surface of the first portion of the InP layer toward the light receiving layer. The band gap of the III-V compound semiconductor layer is smaller than the band gap of InP, the n-type dopant is added to the InP layer, and the majority carriers in the second portion of the InP layer are electrons. The electron concentration in the second portion of the InP layer is 1 × 10 ¹⁶ cm ⁻³ or more. The light receiving layer has a III-V compound semiconductor layer containing at least antimony as a group V element.

According to this group III-V compound semiconductor light-receiving element, the antimony supplied during the growth of the group III-V compound semiconductor layer of the light-receiving layer remains in the growth furnace (that is, the memory effect). The InP layer grown in this manner contains antimony as an impurity. According to the inventors' investigation, the antimony impurity in the InP layer generates holes. The n-type dopant added in the InP layer compensates for the generated carriers, and the majority carriers in the second portion of the InP layer are converted to electrons. Since the electron concentration is 1 × 10 ¹⁶ cm ⁻³ or more, the second portion of the InP layer exhibits sufficient n conductivity. For this reason, since regions other than the selectively formed anode region become n-conductive, it becomes possible to form a selective pn junction, thereby reducing dark current.

A III-V compound semiconductor light receiving element according to one aspect of the present invention includes (a) a semiconductor substrate having a main surface, (b) a light receiving layer provided on the main surface of the semiconductor substrate, and (c). A band gap of the III-V compound semiconductor layer is smaller than a band gap of InP, and a donor is added to the InP layer, and a donor of the InP layer is provided. The density is 1 × 10 ¹⁶ cm ⁻³ or more. The light receiving layer has a III-V compound semiconductor layer containing at least antimony as a group V element.

According to this group III-V compound semiconductor light-receiving element, the antimony supplied during the growth of the group III-V compound semiconductor layer of the light-receiving layer remains in the growth furnace (that is, the memory effect). The InP layer grown in this manner contains antimony as an impurity. According to the inventors' investigation, the antimony impurity in the InP layer generates holes. The donor in the InP layer compensates for this generated carrier, and the majority carriers in the second portion of the InP layer are converted to electrons. Since the donor density is 1 × 10 ¹⁶ cm ⁻³ or more, the second portion of the InP layer exhibits sufficient n conductivity. For this reason, since regions other than the selectively formed anode region become n-conductive, it becomes possible to form a selective pn junction, thereby reducing dark current.

In the group III-V compound semiconductor light-receiving device of the present invention, the donor density in the InP layer may be 1 × 10 ¹⁹ cm ⁻³ or less. In the III-V compound semiconductor photo detector of the present invention, the donor in the InP layer can be silicon.

  In the group III-V compound semiconductor light-receiving element of the present invention, the light-receiving layer may have a group III-V compound semiconductor layer containing at least antimony as a group V element. In the III-V compound semiconductor light receiving device of the present invention, the InP layer may contain antimony as an impurity.

In the group III-V compound semiconductor light-receiving element of the present invention, the electron concentration in the second portion of the InP layer may be 1 × 10 ¹⁹ cm ⁻³ or less.

According to the III-V compound semiconductor light-receiving element, when the second portion of the InP layer has an electron concentration not exceeding 1 × 10 ¹⁹ cm ⁻³ , appropriate characteristics can be given to the anode region.

In the III-V compound semiconductor light-receiving element of the present invention, the antimony concentration in the InP layer is 1 × 10 ¹⁷ cm ⁻³ or more, and the antimony concentration in the InP layer is 1 × 10 ¹⁹ cm ⁻³ or less. it can.

  According to this group III-V compound semiconductor light-receiving element, the concentration of mixed antimony in the InP layer is in the above range, and a part of the antimony impurity in this concentration range acts to provide holes. The addition of silicon compensates for the provided hole carriers, and further functions to convert majority carriers into electrons, and the regions other than the selectively formed anode region become n-conducting, thereby making it selective. Since it becomes possible to form a pn junction, dark current can be reduced.

  The III-V compound semiconductor light receiving element of the present invention may further include an InGaAs layer provided between the light receiving layer and the InP layer. The antimony concentration of the InP is higher than the antimony concentration of the InGaAs layer.

  According to the group III-V compound semiconductor light receiving element, the InGaAs layer is useful for adjusting the position of the anode region with respect to the light receiving layer. On the other hand, although this InGaAs layer also contains antimony as an impurity, the antimony concentration of the InP layer is higher than the antimony concentration of the InGaAs layer. Hence, the InGaAs layer can be undoped.

  The III-V compound semiconductor light receiving element of the present invention may further include a passivation film made of an insulator covering the surface of the second portion of the InP layer.

  According to the III-V compound semiconductor light-receiving element, dark current caused by the material of the window layer can be reduced, and surface leakage current can also be reduced.

  In the III-V compound semiconductor light-receiving element of the present invention, the light-receiving layer has at least one of a multiple quantum well structure including an InGaAs layer and a GaAsSb layer, and a multiple quantum well structure including a GaInNAs layer and a GaAsSb layer, The III-V compound semiconductor layer may include a GaAsSb layer.

  According to the group III-V compound semiconductor light-receiving element, a light-receiving layer having a desired wavelength sensitivity can be obtained.

  In the III-V compound semiconductor light receiving element of the present invention, the semiconductor substrate may be made of conductive InP, and the III-V compound semiconductor light receiving element may further include a cathode electrode provided on the back surface of the semiconductor substrate. .

  According to this group III-V compound semiconductor light-receiving element, the InP substrate can provide a light-receiving layer with good light-receiving sensitivity. Also, favorable light receiving characteristics can be provided by the anode region made of a p-type semiconductor selectively reaching the light receiving layer from the surface and the cathode of the InP substrate, which is selectively formed in the first portion of the InP layer.

Another aspect of the present invention is a method for producing a III-V compound semiconductor light-receiving element. The method includes (a) placing a substrate in a growth furnace, and (b) growing a semiconductor stack for the III-V compound semiconductor light receiving element in the growth furnace to form an epitaxial substrate; (C) after forming the semiconductor stack, removing the epitaxial substrate from the growth furnace; and (d) introducing a p-type dopant from the surface of the InP layer after removing the epitaxial substrate from the growth furnace. Forming an anode region made of a p-type semiconductor extending in the direction of the light receiving layer. In the step of growing the semiconductor stack, (b1) receiving light having an III-V compound semiconductor layer containing at least antimony as a group V constituent element by supplying a source gas containing an antimony source and a group V source to the growth furnace. A step of forming a layer on the main surface of the substrate; and (b2) after stopping the supply of the antimony raw material to the growth furnace, a raw material gas containing an n-type dopant, an indium raw material and a phosphorus raw material is supplied to the growth furnace. Forming an n-type conductive InP layer on the light receiving layer. The band gap of the III-V compound semiconductor layer is smaller than the band gap of InP, the InP layer contains antimony as an impurity, and the electron concentration in the InP layer is 1 × 10 ¹⁶ cm ⁻³ or more. The step of forming the light receiving layer on the main surface of the substrate includes a step of supplying a source gas containing an antimony source and a group V source to the growth furnace. The light receiving layer has a III-V compound semiconductor layer containing at least antimony as a group V element.

According to this method, although antimony is not supplied to the growth furnace when the InP layer is grown on the light receiving layer, the antimony supplied during the growth of the III-V compound semiconductor layer of the light receiving layer remains in the growth furnace. By doing this (that is, the memory effect), antimony is contained in the InP layer as an impurity. According to the inventors' investigation, the antimony impurity in the InP layer generates holes. The n-type dopant added in the InP layer compensates for this generated carrier, and the majority carriers in the second portion of the InP layer become electrons. Since the electron concentration is 1 × 10 ¹⁶ cm ⁻³ or more, the second portion of the InP layer exhibits sufficient n conductivity.

Another aspect of the present invention is a method for producing a III-V compound semiconductor light-receiving element. The method includes (a) placing a substrate in a growth furnace, and (b) growing a semiconductor stack for the III-V compound semiconductor light receiving element in the growth furnace to form an epitaxial substrate; (C) after forming the semiconductor stack, removing the epitaxial substrate from the growth furnace; and (d) introducing a p-type dopant from the surface of the InP layer after removing the epitaxial substrate from the growth furnace. Forming an anode region made of a p-type semiconductor extending in the direction of the light-receiving layer, and the step of growing the semiconductor stack includes forming a light-receiving layer on the main surface of the substrate, and n-type Including a step of supplying a source gas containing a dopant, an indium source material and a phosphorus source material to the growth furnace to form an n-type conductive InP layer on the light-receiving layer. The band gap of the object semiconductor layer is smaller than the band gap of InP, the donor density in the InP layer is 1 × ¹⁰ 16 ^{cm -3} or more. The step of forming the light receiving layer on the main surface of the substrate includes a step of supplying a source gas containing an antimony source and a group V source to the growth furnace. The light receiving layer has a III-V compound semiconductor layer containing at least antimony as a group V element.

According to this method, although antimony is not supplied to the growth furnace when the InP layer is grown on the light receiving layer, the antimony supplied during the growth of the III-V compound semiconductor layer of the light receiving layer remains in the growth furnace. By doing this (that is, the memory effect), antimony is contained in the InP layer as an impurity. According to the inventors' investigation, the antimony impurity in the InP layer generates holes. The donor in the InP layer compensates for this generated carrier, and the majority carriers in the second portion of the InP layer become electrons. Since the donor density is 1 × 10 ¹⁶ cm ⁻³ or more, the second portion of the InP layer exhibits sufficient n conductivity.

In the method according to the present invention, the donor density in the InP layer may be 1 × 10 ¹⁹ cm ⁻³ or less. In the method according to the present invention, the donor in the InP layer may be silicon.

  The method according to the present invention includes a step of supplying a source gas containing an antimony source and a group V source to the growth reactor, and the light receiving layer has a III-V group compound semiconductor layer containing at least antimony as a group V element. be able to. In the method according to the present invention, the InP layer may contain antimony as an impurity.

In the method according to the present invention, the electron concentration in the second portion of the InP layer may be 1 × 10 ¹⁹ cm ⁻³ or less.

According to this method, when the InP layer has an electron concentration not exceeding 1 × 10 ¹⁹ cm ⁻³ , an appropriate characteristic is given to the anode region without increasing the amount of p-type dopant for forming the anode region. be able to.

In the method according to the present invention, the antimony concentration in the InP layer may be 1 × 10 ¹⁷ cm ⁻³ or more, and the antimony concentration in the InP layer may be 1 × 10 ¹⁹ cm ⁻³ or less.

  According to this method, the mixed antimony concentration in the InP layer is in the above range, and a part of the antimony impurity in this concentration range acts to provide holes.

  The method according to the present invention further includes a step of supplying a source gas containing a group III source material and a group V source material to the growth furnace and growing an InGaAs layer on the light receiving layer before the InP layer is grown. Can do. The antimony concentration of the InGaAs layer is lower than the antimony concentration of the InP.

  According to this method, the InGaAs layer serves to adjust the position of the anode region with respect to the light receiving layer. On the other hand, although this InGaAs layer also contains antimony as an impurity, the antimony concentration of the InP layer is higher than the antimony concentration of the InGaAs layer. Therefore, the InGaAs layer is undoped.

  In the method according to the present invention, the light receiving layer has at least one of a multiple quantum well structure including an InGaAs layer and a GaAsSb layer, and a multiple quantum well structure including a GaInNAs layer and a GaAsSb layer, and the III-V compound The semiconductor layer can include a GaAsSb layer.

  According to this method, a light receiving layer having a desired wavelength sensitivity can be formed.

  In the method according to the present invention, the light receiving layer and the InP layer may be grown by metal organic vapor phase epitaxy. According to this method, although a light-receiving layer and an InP layer having good characteristics can be grown, an antimony memory effect is produced in the growth of InP.

  The above and other objects, features, and advantages of the present invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

  As described above, according to one aspect of the present invention, it is possible to reduce dark current by including a light-receiving layer having an III-V compound semiconductor layer containing Sb as a group V constituent element and an n-type InP window layer. A III-V compound semiconductor light receiving element is provided. According to another aspect of the present invention, a method for producing a III-V compound semiconductor light receiving element is provided.

FIG. 1 is a drawing showing the structure of a III-V compound semiconductor light receiving element according to the present embodiment. FIG. 2 is a drawing showing the main steps in the method for producing a III-V compound semiconductor light-receiving element according to the present embodiment. FIG. 3 is a drawing showing main steps in a method for producing a III-V compound semiconductor light-receiving element according to the present embodiment. FIG. 4 is a drawing showing the main steps in the method for producing the III-V compound semiconductor light receiving element according to the present embodiment. FIG. 5 shows the structure of two types of epitaxial substrates. FIG. 6 is a view showing Sb concentrations measured by secondary ion mass spectrometry for the second InGaAs layer and the InP window layer of the two types of epitaxial substrates shown in FIG. FIG. 7 is a drawing showing the structure of the photodiode shown in the first embodiment. FIG. 8 is a graph showing the relationship among silicon concentration, electron or hole concentration, and dark current in Example 1.

  The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Subsequently, embodiments of the III-V compound semiconductor light-receiving element and the epitaxial substrate of the present invention and methods for producing them will be described with reference to the accompanying drawings. Where possible, the same parts are denoted by the same reference numerals.

  FIG. 1 is a drawing showing a group III-V compound semiconductor light receiving element according to the present embodiment. The III-V compound semiconductor light receiving element is, for example, a photodiode. Referring to FIG. 1, an orthogonal coordinate system S is shown.

The III-V compound semiconductor light receiving element 11 includes a semiconductor substrate 13, a semiconductor stack 15, and an anode region 17. The semiconductor stack 15 is provided on the semiconductor substrate 13 and includes a light receiving layer 21 and an InP layer 23. The semiconductor layers (for example, the light receiving layer 21 and the InP layer 23) in the semiconductor stack 15 are stacked in the direction of the normal axis Ax of the main surface 13a of the semiconductor substrate 13. The semiconductor substrate 13 has a main surface 13a and a back surface 13b. The main surface 13a includes first and second areas 13c and 13d, and the second area 13d surrounds the first area 13c. The light receiving layer 21 is provided on the main surface 13 a of the semiconductor substrate 13 and is provided between the semiconductor substrate 13 and the InP layer 23. The light receiving layer 21 has a III-V group compound semiconductor layer containing at least antimony as a group V constituent element. The III-V compound semiconductor layer is made of, for example, GaAsSb. The light receiving layer 21 can have a bulk structure, a quantum well structure, or the like. The band gap E _absp of the group III-V compound semiconductor layer is smaller than the band gap E _{InP of InP} , and the group III-V compound semiconductor layer is incident from the main surface 15a of the semiconductor stack 15 and passes through the InP layer 23 to receive the light receiving layer. Electron / hole pairs are generated from the light that has reached 21. The light receiving layer 21 has first and second portions 21c and 21d, and the first and second portions 21c and 21d are provided on the first and second areas 13c and 13d, respectively. . The InP layer 23 is provided on the light receiving layer 21 and includes first and second portions 23c and 23d. The first and second portions 23c and 23d are provided on the first and second areas 13c and 13d, respectively. The first portion 21c is provided between the first portion 23c and the first area 13c. The second portion 21d is provided between the second portion 23d and the second area 13d. The anode region 17 is made of a p-type semiconductor that reaches the light receiving layer 21 from the surface of the first portion 23 c of the InP layer 23. A p-type dopant is added to the anode region 17. As the p-type dopant, for example, zinc (Zn) or the like is used.

In the III-V compound semiconductor light-receiving element 11, the InP layer 23 contains antimony as an impurity, and an n-type dopant is added to the InP layer 23. For example, silicon, sulfur, or the like can be used as the n-type dopant. The majority carriers in the second portion 23d of the InP layer 23 are electrons, and the electron concentration in the second portion 23d of the InP layer 23 is 1 × 10 ¹⁶ cm ⁻³ or more.

According to the group III-V compound semiconductor light-receiving element 11, the light-receiving layer 21 is caused by the residual antimony (that is, the memory effect) supplied to the growth reactor during the growth of the group III-V compound semiconductor layer of the light-receiving layer 21. The InP layer 23 grown on top contains antimony that is not supplied during the growth as an impurity. According to the inventors' investigation, the antimony impurity in the InP layer 23 generates holes. The generated carriers are compensated by the n-type dopant added to the InP layer 23. As a result, majority carriers in the second portion 23d of the InP layer 23 become electrons. Since the electron concentration is 1 × 10 ¹⁶ cm ⁻³ or more, the second portion 23 d of the InP layer 23 exhibits sufficient n conductivity.

According to the inventors' investigation, the antimony concentration in the InP layer 23 can be 1 × 10 ¹⁷ cm ⁻³ or more, and the antimony concentration in the InP layer 23 can be 1 × 10 ¹⁹ cm ⁻³ or less. The concentration of the mixed antimony in the InP layer 23 is in the above range, and at least a part of the antimony impurity in this concentration range acts to provide holes.

The electron concentration in the second portion 23d of the InP layer 23 can be 1 × 10 ¹⁹ cm ⁻³ or less. When the second portion 23d has an electron concentration of 1 × 10 ¹⁹ cm ⁻³ or less, the anode region 17 has appropriate electrical characteristics without increasing the amount of p-type dopant for forming the anode region. be able to. The silicon concentration of the InP layer 23 is, for example, 1 × 10 ¹⁶ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less.

  The light receiving layer 21 has at least one of a multiple quantum well structure including an InGaAs layer and a GaAsSb layer, and a multiple quantum well structure including a GaInNAs layer and a GaAsSb layer, and the III-V compound semiconductor layer includes a GaAsSb layer. Can do. According to the light receiving element 11, the light receiving layer 21 having a desired wavelength sensitivity can be obtained.

  In the III-V compound semiconductor light receiving element 11, the semiconductor stack 15 can further include an InGaAs layer 25. The InGaAs layer 25 is provided between the light receiving layer 21 and the InP layer 23. Antimony may be measured as an impurity in the InGaAs layer 25, and the antimony concentration of InP is higher than the antimony concentration of the InGaAs layer 25. The InGaAs layer 25 serves to adjust the position of the anode region 17 with respect to the light receiving layer 21. On the other hand, although the InGaAs layer 25 may also contain antimony as an impurity, the antimony concentration of the InP layer 23 is higher than the antimony concentration of the InGaAs layer 25. Therefore, the InGaAs layer 25 can be undoped. Further, the thickness of the InGaAs layer 25 may be larger than the thickness of the InP layer 23.

  The InGaAs layer 25 has first and second portions 25c and 25d, and the first and second portions 25c and 25d are provided on the first and second areas 13c and 13d, respectively. . The anode region 17 includes a first portion 25c and a first portion 23c, and is located on the first portion 21c. The bottom surface of the anode region 17 forms the pn junction 29a with the first portion 21c, and the side surface of the anode region 17 forms the pn junctions 29b and 29c with the second portion 25d and the second portion 23d.

In the III-V group compound semiconductor light receiving element 11, the semiconductor stack 15 can further include another InGaAs layer 27. The InGaAs layer 27 is provided between the light receiving layer 21 and the semiconductor substrate 13. The InGaAs layer 27 does not substantially contain antimony as an impurity. The band gap of the InGaAs layer 27 is larger than the band gap of the III-V group compound semiconductor layer of the light receiving layer 21. An n-type dopant is added to the InGaAs layer 27. As the n-type dopant, for example, silicon (Si) is used. The silicon concentration of the InGaAs layer 27 is, for example, 1 × 10 ¹⁶ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less. The InGaAs layer 27 has first and second portions 27c and 27d, and the first and second portions 27c and 27d are provided on the first and second areas 13c and 13d, respectively. . The InGaAs layer 27 is in contact with the InP semiconductor region.

  The semiconductor substrate 13 is preferably made of InP, for example. This InP exhibits conductivity. If necessary, a buffer layer can be provided on the main surface 13a of the semiconductor substrate 13, and this buffer layer is made of, for example, InP.

  The InP substrate can provide a light receiving layer with good light receiving sensitivity. Also, good light receiving characteristics can be provided by the anode region 17 made of a p-type semiconductor reaching the light receiving layer from the surface of the first portion 23c of the InP layer 23 and the cathode of the InP substrate. The receivable wavelength of the light receiving layer 21 can be 1.0 micrometer or more, and can be 3.0 micrometers or less.

  The III-V compound semiconductor light-receiving element 11 can include an anode electrode 33 that is in contact with the main surface 15 a of the semiconductor stack 15. The edge 33a of the anode electrode 33 is located inside a columnar virtual drawing that passes through the boundary of the first area 13c and extends in the direction of the normal axis Ax, and the pn junctions 29b and 29c are substantially on the side surfaces of the virtual drawing. Located along. In the coordinate system S having the Z axis on the axis Ax that passes through the center of the anode electrode 33, a reference plane that passes through the axis Ax is defined. On any reference plane, the X and Y coordinates of the edge 33a of the anode electrode 33 are smaller than the X and Y coordinates of the first area 13c.

  The III-V compound semiconductor light receiving element 11 can further include a cathode electrode 35 provided on the back surface 13 b of the semiconductor substrate 13. The cathode electrode 35 covers the back surface 13b of the semiconductor substrate 13 and makes contact with the back surface 13b.

  The III-V compound semiconductor light receiving element 11 can further include an insulating film 37 that covers the surface of the second portion 23d of the InP layer 23, and this insulating film 37 functions as a passivation film. The insulating film 37 has an opening 37 a, and the opening 37 a provides a path for the anode electrode 33 to contact the InP layer 23. According to the light receiving element 11, dark current due to the material of the window layer 23 can be reduced, and surface leakage current can also be reduced.

  The edge 37b of the opening 37a of the insulating film 37 is located inside the columnar virtual drawing that passes through the boundary of the first area 13c and extends in the direction of the normal axis Ax. In the reference plane, the X coordinate of the edge 33a of the anode electrode 33 can be between the X coordinate of the edge 37b of the opening 37a of the insulating film 37 and the X coordinate of the pn junctions 29b and 29c, respectively. Further, the Y coordinate of the edge 33a of the anode electrode 33 can be between the Y coordinate of the edge 37b of the opening 37a of the insulating film 37 and the Y coordinate of the pn junctions 29b and 29c, respectively.

  2, 3, and 4 are drawings showing main steps in a method for manufacturing a III-V compound semiconductor light-receiving element according to the present embodiment. A method for fabricating a III-V compound semiconductor light-receiving element will be described with reference to FIGS. In step S101, the substrate 41 is placed in the growth furnace 10a. The substrate 41 can be, for example, an InP substrate. In step S102, a semiconductor stacked layer Epi for a III-V compound semiconductor light receiving element is grown using the growth furnace 10a. Subsequent crystal growth is performed, for example, by metal organic vapor phase epitaxy. Gallium (Ga) raw material, indium (In) raw material, arsenic (As) raw material, phosphorus (P) raw material, and antimony (Sb raw material, respectively, TEGa, TMIn, TBAs, TBP, TMSb for metalorganic vapor phase growth For example, TeESi is used for n-type doping.

  First, in step S102-1, the first raw material is supplied to the growth reactor 10a, and the first InGaAs layer 43 is grown on the main surface 41a of the substrate 41. The first raw material G1 includes a gallium raw material, an indium raw material, and an arsenic raw material, and can include TeESi as an n-type dopant.

  Subsequently, in step S102-2, as shown in FIG. 2B, the second raw material G2 is supplied to the growth furnace 10a, and the light receiving layer 45 is grown on the main surface 41a of the substrate 41. The light receiving layer 45 includes a III-V group compound semiconductor layer containing at least antimony as a group V element. The band gap of this III-V compound semiconductor layer is smaller than the band gap of InP grown as a window layer in a later process. In this embodiment, the second raw material G2 includes, for example, a gallium raw material, an arsenic raw material, and an antimony raw material, and a single GaAsSb layer is grown on the main surface of the first InGaAs layer 43, for example. The GaAsSb layer is undoped, for example, and the majority carriers in this layer are electrons.

  The light receiving layer 45 may have at least one of a single or multiple quantum well structure including an InGaAs layer and a GaAsSb layer, and a single or multiple quantum well structure including a GaInNAs layer and a GaAsSb layer. With this structure, a light receiving layer having a desired wavelength sensitivity can be formed. The Sb-containing III-V compound semiconductor layer may include a GaAsSb layer.

The light-receiving layer 45 can have, for example, a type II type quantum well structure. At this time, In _X Ga _1-X As (0.38 ≦ X ≦ 0.68) and GaAs _1-Y Sb _Y (0. 36 ≦ Y ≦ 0.62) or Ga _{1 -U} In _U N _V As _1-V (0.4 ≦ U ≦ 0.8, 0 <V ≦ 0.2) and GaAs _1-Z Sb A pair of _Z (0.36 ≦ Z ≦ 0.62) is exemplified.

  If necessary, for example, after the supply of the gallium raw material and the antimony raw material is stopped, a process for interrupting the growth can be provided while the arsenic raw material is supplied to the growth reactor.

  In step S102-3, after stopping the supply of the antimony material to the growth furnace 10a, as shown in FIG. 3A, the third material G3 is supplied to the growth furnace 10a, and the second InGaAs layer is supplied. 47 is grown on the light-receiving layer 45. The third raw material G3 includes a gallium raw material, an indium raw material, and an arsenic raw material. The InGaAs layer 47 is undoped, for example, and majority carriers in this layer are electrons.

  In step S102-4, as shown in FIG. 3B, the antimony raw material is not supplied to the growth furnace 10a. The fourth raw material G4 is supplied to the growth furnace 10a, and the n-type conductive InP layer 49 is grown on the light receiving layer 45 and the second InGaAs layer 47. The fourth source gas G4 includes, for example, an n-type dopant, an indium source, and a phosphorus source.

The InP layer 49 includes antimony as an impurity and an n-type dopant (for example, silicon). The majority carriers in the InP layer 49 are electrons, and the electron concentration in the InP layer 49 is 1 × 10 ¹⁶ cm ⁻³ or more.

  Through these steps, the epitaxial substrate E is produced. After the InP layer 49 is formed on the substrate 41, the epitaxial substrate E is taken out from the growth furnace 10a in step S103.

  In step S104, an anode region 51 made of a p-type semiconductor is formed on the epitaxial substrate E. In this embodiment, the anode region 51 is formed by introducing a p-type dopant. The introduction of the p-type dopant uses, for example, thermal diffusion. After the epitaxial substrate E is taken out from the growth furnace 10a, an insulating film 53 is formed on the epitaxial substrate E. The insulating film 53 has an opening 53a aligned with the position of the anode region 51. A p-type dopant is introduced into the light receiving layer 45 from the surface 49a of the InP layer 49 in a zinc atmosphere using the heat treatment apparatus 10b. A reaching anode region 51 is formed. Zn introduced from the opening 53a by the heat treatment diffuses toward the substrate and also in the lateral direction. As a result, the anode region 51 extends below the insulating film 53. By this step, the substrate product P is produced. In the formation of the anode region 51 using thermal diffusion, if necessary, the thickness of the InGaAs layer 47 can be determined so as to adjust the position of the anode region 51 with respect to the light receiving layer 45.

  In S105, an electrode is formed on the substrate product P. For example, the anode electrode 55 that contacts the anode region 51 is formed, and the cathode electrode 57 that contacts the back surface of the substrate 41 is formed.

According to this method, antimony is not supplied to the growth reactor 10a when the InP layer 49 is grown on the light receiving layer 45, but is supplied when the Sb-containing III-V compound semiconductor layer of the light receiving layer 45 is grown. Antimony is mixed into the InP layer 49 as an impurity due to the antimony remaining in the growth furnace 10a (that is, the memory effect). According to the inventors' investigation, the antimony impurity in the InP layer 49 generates holes. The generated carriers are compensated by the n-type added dopant in the InP layer 49, and the majority carriers in the InP layer 49 are converted to electrons. Since the electron concentration is 1 × 10 ¹⁶ cm ⁻³ or more, the InP layer 49 exhibits sufficient n conductivity. Further, the electron concentration in the InP layer 49 can be 1 × 10 ¹⁹ cm ⁻³ or less. At this time, appropriate electrical characteristics can be imparted to the anode region 51 without increasing the amount of p-type dopant for forming the anode region 51.

According to the estimation of the inventors, the antimony concentration in the InP layer 49 is 1 × 10 ¹⁷ cm ⁻³ or more, and the antimony concentration is 1 × 10 ¹⁹ cm ⁻³ or less. The mixed antimony concentration in the InP layer 49 is in the above range, and a part of the antimony impurity in this concentration range acts to provide holes.

  On the other hand, the InGaAs layer 47 contains antimony as an impurity, and the antimony concentration of the InGaAs layer 47 is lower than the antimony concentration of the InP layer 49. Although the InGaAs layer 47 also contains antimony as an impurity, the antimony concentration of the InP layer 49 is higher than the antimony concentration of the InGaAs layer 47. Therefore, the InGaAs layer 47 can be undoped, and if necessary, a slight n-type dopant can be added.

  As described above, the growth from the light receiving layer 45 to the InP layer 49 is performed by metal organic vapor phase epitaxy. According to this method, although the light-receiving layer 45 and the InP layer 49 having good characteristics can be grown, the memory effect of antimony cannot be avoided in the growth of InP. However, the inventors have been able to avoid the problem of p-type conversion due to the antimony memory effect by adding an n-type dopant to InP.

FIG. 5 shows the structures of two types of epitaxial substrates. FIG. 5A uses a multiple quantum well structure including an InGaAs layer and a GaAsSb layer as a light receiving layer. FIG. 5B uses a GaAsSb layer as the light receiving layer. FIG. 6 shows Sb concentrations measured by secondary ion mass spectrometry for the second InGaAs layer and the InP window layer of the two types of epitaxial substrates shown in FIG. Referring to FIGS. 5A and 6, in the structure A, the InP window layer contains about 1 × 10 ¹⁸ cm ⁻³ of antimony. However, the antimony amount of the second InGaAs layer between the GaAsSb light-receiving layer and the InP window layer is less than 1 × 10 ¹⁶ cm ⁻³ below the detection limit of secondary ion mass spectrometry. When the carrier concentration of the InP window layer of structure A was determined by CV measurement, the hole concentration was 1 × 10 ¹⁶ cm ⁻³ . Referring to FIGS. 5B and 6, in the structure B, the InP window layer contains about 1 × 10 ¹⁹ cm ⁻³ of antimony. However, the antimony amount of the second InGaAs layer between the GaAsSb light-receiving layer and the InP window layer is less than 1 × 10 ¹⁶ cm ⁻³ below the detection limit of secondary ion mass spectrometry. When the carrier concentration of the InP window layer of structure B was determined by CV measurement, the hole concentration was 2 × 10 ¹⁷ cm ⁻³ .
As shown in FIGS. 5 and 6, the antimony profile Sb is once lowered in the second InGaAs layer, but when the InP layer is grown after the growth of the InGaAs layer, the antimony profile Sb is again raised in the InP layer.

Example 1
A photodiode having the structure shown in FIG. 7 was produced. An n-type InP substrate was prepared. On this InP substrate, TMIn (trimethylindium) and TBP (tertiary butylphosphine) were supplied to a growth reactor, and an n-type InP buffer layer was grown at a substrate temperature of 500 degrees Celsius. The thickness of the buffer layer is 10 nm, for example, and TeESi was used for n-type doping of the buffer layer. Next, TMIn (trimethylindium), TEGa (triethylgallium), and TBA (tertiary butylarsine) were supplied to the growth reactor on the n-type InP buffer layer to grow an n-type InGaAs layer at 500 degrees Celsius. The thickness of the InGaAs layer was 150 nm, for example. A light-receiving layer having a multiple quantum well structure was fabricated. In this embodiment, a light receiving layer having a multiple quantum well structure of (InGaAs / GaAsSb) is formed. The thickness of the InGaAs layer and the GaAsSb layer forming the unit quantum well structure was 5 nm, and 50 pairs (the number of repeating unit quantum wells) were grown. TMSb was used as the Sb raw material. Next, an InGaAs layer having a thickness of 1 μm was grown at 500 degrees Celsius on the light receiving layer as a diffusion concentration distribution adjusting layer when Zn diffusion was introduced. Finally, an n-type InP window layer having a thickness of 1 μm was grown at 500 degrees Celsius. Silicon was added to the n-type InP window layer, and as shown in FIG. 8, photodiodes A2 to A7 having different silicon concentrations were produced. Further, in place of the n-type InP window layer to which silicon was added, a photodiode A1 in which an InP window layer including silicon and not intentionally added with a dopant was grown was also produced.
With respect to the inventive examples A1 to A7, the concentration of silicon was measured by secondary ion mass spectrometry, and the carrier type and electron or hole concentration were measured by CV measurement.
In the present invention examples A2 to A7, the silicon concentration is 5 × 10 ¹⁵ (cm ⁻³ ) to 5 × 10 ¹⁹ (cm ⁻³ ), and in the present invention example A1, the silicon concentration is detected by secondary ion mass spectrometry. It was less than 1 × 10 ¹⁵ cm ⁻³ below the limit.
The carrier types of Invention Examples A1 and A2 were p-type, and the hole concentration was 1 × 10 ¹⁶ (cm ⁻³ ) for A1 and 5 × 10 ¹⁵ (cm ⁻³ ) for A2. On the other hand, the carrier types of Invention Examples A3 to A7 are n-type, and the electron concentration is 5 × 10 ¹⁵ (cm ⁻³ ) for A3, 1 × 10 ¹⁶ (cm ⁻³ ) for A4, and 1 × 10 ^{17 for} A5. ^(cm -3), the ^{A6 1 × 10 19 (cm -3} ), was A7 in ^{5 × 10 19 (cm -3)} .

  After an SiN film was grown on the surface of the InP window layers of Invention Examples A1 to A7, an opening was formed by patterning the SiN film. Thereafter, Zn was selectively diffused from the opening (InGaAs / GaAsSb) to form a p-type region in the light-receiving layer having a multiple quantum well structure. After selectively diffusing Zn to form an anode region, a p-side electrode made of AuZn was formed on the surface of the InP window layer, and an n-side electrode made of AuGeNi was formed on the back surface of the substrate.

  In another embodiment, a (GaInNAs / GaAsSb) light-receiving layer having a multiple quantum well structure was formed in place of the (InGaAs / GaAsSb) light-receiving layer. The thickness of the GaInNAs layer or GaAsSb layer forming the unit quantum well structure was 5 nm, and 50 pairs (the number of repetitions of the unit quantum well) were grown. TMSb was used as the Sb raw material.

The reverse current-voltage characteristics of the fabricated photodiode at room temperature were examined. The light receiving diameter of this photodiode is 100 micrometers. The leakage current at room temperature of the photodiodes of Examples A1 and A2 of the present invention was 20 microamperes at an applied voltage of minus 5 volts. The leakage current at room temperature of the photodiode of Invention Example A3 was 10 microamperes at an applied voltage of minus 5 volts. On the other hand, the leakage current at room temperature of the photodiodes of Invention Examples A4 to A6 was 2 microamperes at an applied voltage of minus 5 volts. The leakage current at room temperature of the photodiode of Example A7 of the present invention was 200 microamperes at an applied voltage of minus 5 volts.
Thus, by doping silicon into the InP window layer (electron concentration 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ ) and controlling the n-type, the dark current can be reduced by about one digit.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. The present invention is not limited to the specific configuration disclosed in the present embodiment. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

DESCRIPTION OF SYMBOLS 11 ... III-V compound semiconductor light receiving element, 13 ... Semiconductor substrate, 13a ... Semiconductor substrate main surface, 13b ... Semiconductor substrate back surface, 13c, 13d ... Area of semiconductor substrate main surface, 15 ... Semiconductor lamination, 15a ... Semiconductor lamination main Surface, 17 ... anode region, 21 ... light receiving layer, 21c, 21d ... light receiving layer portion, 23 ... InP layer, 23c, 23d ... InP layer portion, 25 ... InGaAs layer, 25c, 25d ... InGaAs layer portion, 29a 29b, 29c ... pn junction, 27 ... InGaAs layer, 27c, 27d ... part of InGaAs layer, 33 ... anode electrode, 35 ... cathode electrode, 37 ... insulating film

Claims (5)

A III-V compound semiconductor photo detector,
A semiconductor substrate having a main surface;
A light-receiving layer provided on the main surface of the semiconductor substrate;
A window layer provided on the light receiving layer and having first and second portions;
An anode region made of a p-type semiconductor reaching the light receiving layer from the surface of the first portion of the window layer;
A semiconductor layer comprising gallium, indium and arsenic and provided between the light receiving layer and the window layer;
With
The window layer is InP;
An n-type dopant is added to the window layer,
The window layer contains antimony as an impurity, the antimony concentration of the window layer is higher than the antimony concentration of the semiconductor layer, and majority carriers in the second portion of the window layer are electrons. A III-V compound semiconductor light-receiving element.   2. The III-V compound semiconductor light receiving element according to claim 1, wherein the light receiving layer includes a III-V compound semiconductor layer containing at least antimony as a group V element.   The III-V group compound semiconductor light receiving device according to claim 2, wherein a band gap of the III-V group compound semiconductor layer is smaller than a band gap of the semiconductor substrate. 4. The group III-V compound semiconductor according to claim 1 , wherein an electron concentration in the second portion of the window layer is 1 × 10 ¹⁶ cm ⁻³ or more. 5. Light receiving element. The light receiving layer, the semiconductor substrate uniformly and flatly provided on said main surface of said window layer the light receiving layer, uniformly and is flat provided that claims 1, wherein Item III-V compound semiconductor light-receiving element according to any one of Items 4 .

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