JP5948636B2 - Digital protection control device and substrate identification method - Google Patents

Description

  The present invention relates to a digital protection control device and a board identification method for protecting and controlling a power system.

  In general, in a plant such as a power plant or a substation, electric power supplied to an electric power system is protected and controlled by a digital protection control device.

  As a conventional digital protection control device, a second generation digital relay described in Non-Patent Document 1 is known. The second generation digital relay includes, for example, an analog input unit, a digital arithmetic processing unit, a settling unit, and an output unit.

  The analog input unit includes an analog filter for preventing aliasing errors, a sampling hold circuit, a multiplexer, an A / D converter, and a buffer, and converts an electrical signal representing the state of the power system into a digital electrical signal by sampling at high speed. And store it in the buffer.

  The digital arithmetic processing unit is further divided into a digital filter processing unit and a protection arithmetic unit. The digital filter processing unit performs a filtering process on the digital signal that has been digitally converted, and passes it to the protection calculation unit. The protection calculation unit executes a protection control calculation based on the filtered electric signal. The protection calculation unit executes the protection control calculation based on various set values related to the protection control calculation set in the setting unit, and outputs a control output or the like to the protection control target device via the output unit. The protection control calculation is generally performed at a cycle of an electrical angle of 30 °, and the sampling of the electrical signal is performed at a cycle Ts of an electrical angle of 3.75 ° or 7.5 °. By executing the filter processing in accordance with this period Ts, the accuracy of the sampling data is ensured.

By the way, in recent years, digital protection control devices have been increasingly combined, and digital protection control devices corresponding to various protection elements have been developed. In particular, power plants and substations are required to measure and monitor various elements of power, voltage levels and current levels.
However, since many analog inputs are required to calculate all protection elements, all the necessary analog input processing and calculation processing must be performed with a single unit-type digital protection controller. Is a difficult situation from the viewpoint of mounting space and computation time.

  Therefore, introduction of a digital protection control device that can perform measurement processing and monitoring by calculating a corresponding protection element by changing an analog input unit in the same device is being promoted. By using a plurality of such digital protection control devices, a method of measuring and monitoring all protection elements has come to be used.

  However, diversification of combinations of analog input units cannot be avoided in order to realize calculation of all required protection elements. In addition, the usage form of the digital protection control device varies depending on the plant. Conventionally, calculation elements have been manually set according to an analog input unit mounted on a digital protection control device. However, in this work, a setting failure occurs due to an artificial careless mistake, so a lot of labor was spent on work time such as confirmation of the setting.

  Therefore, as a method for recognizing a mounting board, that is, an input conversion board, an electronic board identification device is disclosed that simplifies the setting by automatically causing the control board to recognize the input conversion board mounted on the digital protection control device. (See Patent Document 1). The electronic board identification device described in Patent Document 1 has a storage element storing its own information in each electronic board, and transfers its own board-specific data to the board data storage RAM of the control board when the power is turned on. . Whether or not the target input conversion board is properly mounted is checked by checking the mounting by checking the board data written in the RAM based on the code unique to each board stored in the database in the control board. Identify. These processes are performed by a digital circuit.

JP 2001-67106 A

Second Generation Digital Relay Technical Committee, “Second Generation Digital Relay”, Electric Joint Research Group, Vol. 50, No. 1, 1994

  However, many input conversion boards of conventional digital protection control devices are not equipped with a digital circuit. Therefore, in order to realize the identification method described in Patent Document 1, a digital communication line for newly installing a digital circuit on the input conversion board and transmitting a digital signal between the input conversion board and the control board Need to be installed.

  The present invention has been made in view of such circumstances, and a digital circuit that can identify the type of input conversion board even when a digital circuit and a digital communication line are not mounted on the input conversion board in the digital protection control device. It is an object of the present invention to provide a protection control device and a substrate identification method.

In order to solve the above-described problems, the digital protection control device of the present invention is provided for each protection element, and performs input conversion processing on an analog signal of an input power system and outputs an analog signal after conversion. An input conversion board having a conversion section and an identification signal output section that outputs an identification signal that is an analog signal for identifying the own board is provided, and is supplied from the input conversion board via a communication line. an input unit that inputs and converts an analog signal into a digital signal, and a control unit for performing protective control of a power system to perform a predetermined protective control operation based on the digital signal, is converted into the digital signal the A control board having an arithmetic processing unit for identifying the type of the input conversion board based on the identification signal.

  Further, according to the board identification method of the digital protection control device of the present invention, the input conversion board provided in the digital protection control device is converted into an analog signal of the power system inputted from the outside via the input conversion unit provided for each protection element. A predetermined conversion process is performed and an analog signal after conversion is output, and an identification signal that is an analog signal for identifying its own board is output via the identification signal output unit. The control board included in the converter converts the analog signal supplied from the input conversion board into a digital signal through the input unit and inputs the digital signal, and performs a predetermined protection control calculation based on the digital signal through the control unit. And performing protection control of the power system, through the arithmetic processing unit, based on the identification signal converted into the digital signal, the input conversion board Identifying the kind.

  According to the present invention, the type of the input conversion board can be identified without newly installing a digital circuit and a digital communication line on the input conversion board in the digital protection control device. In addition, it is possible to simultaneously detect deterioration and failure of an analog circuit such as an analog filter and identify an input conversion board.

It is a block diagram which shows the structure of the digital protection control apparatus which concerns on the 1st Embodiment of this invention. It is a figure which shows an example of a structure of the signal output part for identification of the digital protection control apparatus which concerns on the said 1st Embodiment. It is a figure explaining the signal processing example of the digital protection control apparatus which concerns on the said 1st Embodiment. It is a figure which shows an example of the board | substrate information database stored in ROM of the digital protection control apparatus which concerns on the said 1st Embodiment. It is a block diagram which shows the structure of the digital protection control apparatus which concerns on the 2nd Embodiment of this invention. It is a figure explaining the signal processing example of the digital protection control apparatus which concerns on the said 2nd Embodiment. It is a figure which shows an example of the board | substrate information database stored in ROM of the digital protection control apparatus which concerns on the said 2nd Embodiment. It is a figure which shows an example of the board | substrate information database stored in ROM of the digital protection control apparatus which concerns on the said 2nd Embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing the configuration of the digital protection control apparatus according to the first embodiment of the present invention.

  As shown in FIG. 1, the digital protection control device 100 includes an input conversion board 1, a control board 2, a settling unit 3, a digital input / output unit 4, and a control power supply unit 5 that supplies power to each unit. It is prepared for. The input conversion board 1 is connected to the control board 2 through communication lines 13a, 13b,..., 13i and an identification communication line 32.

[Input conversion board 1]
The input conversion board 1 is provided for each protection element, and outputs an input conversion unit 10 that performs a predetermined conversion process on an analog signal of an input power system, and an identification signal that is an analog signal for identifying its own board. And an identification signal output unit 31.

The input conversion unit 10 converts an analog signal input from the outside (target to be protected) to the external input unit into an analog signal having a preset voltage level.
The input conversion unit 10 includes auxiliary transformers 11a, 11b,..., 11i that perform predetermined conversion processing on analog signals such as external currents and currents, and resistance circuits 12a, 12b,. And converting an input analog signal into a voltage signal. Each of the resistance circuits 12a, 12b,..., 12i provided corresponding to each channel (A to I in this example) of the input conversion unit 10 is connected to the control board 2 through the communication lines 13a, 13b,. ing.

  In the following description, the auxiliary transformers 11a, 11b,. In addition, the resistor circuits 12a, 12b,.

  The identification signal output unit 31 outputs an identification signal including board information (unique information) for identifying the board type of the input conversion board 1. Specifically, the identification signal output unit 31 uses a harmonic signal that is an integral multiple of the fundamental wave as the identification signal that is an analog signal. In the present embodiment, a twelfth harmonic (hereinafter referred to as f12 harmonic) signal that is an AC signal having a frequency 12 times the rated frequency is used as the harmonic signal. The identification signal output unit 31 outputs a pattern of time change between the f12 high frequency signal and a predetermined voltage level as an identification signal.

  The identification signal output unit 31 is connected to the control board 2 via an identification communication line 32 different from the communication lines 13a, 13b,..., 13i, and the identification signal is transmitted to the control board 2 through the identification communication line 32. Is transmitted.

  FIG. 2 is a diagram illustrating an example of the configuration of the identification signal output unit 31.

  As shown in FIG. 2, the identification signal output unit 31 includes an f12 harmonic generation unit 31a and a timing control unit 31b.

  The f12 harmonic generation unit 31a generates an f12 harmonic signal.

  The timing control unit 31b controls the output timing of the f12 harmonic signal generated by the f12 harmonic generation unit 31a, and outputs a time change pattern between the f12 high frequency signal and a predetermined voltage level. For example, the identification signal output unit 31 outputs an analog signal having a specific pattern in which an f12 harmonic with an amplitude of 0.1 V is superimposed / non-superimposed every millisecond.

  By the way, the conventional protective relay device includes an analog signal to the input stage of the control board in order to confirm the soundness of an analog circuit such as an analog filter and an A / D converter, or a signal cable that relays the analog signal. Some of them superimpose a harmonic signal and monitor the soundness of an analog circuit or a signal cable by the superimposed harmonic signal. As the harmonic signal, for example, an f12 harmonic that is an AC signal having a frequency 12 times the rated frequency is used. When f12 harmonics are used, when the calculation cycle of the protection calculation processing is set to an electrical angle of 30 °, the sampling timing becomes 0 (transmission zero point) in 12 cycles, which can be realized with a simple configuration. Specifically, in a conventional protective relay device, an f12 harmonic, which is an AC signal having a frequency 12 times the rated frequency, is applied to the analog circuit in order to detect failure / degradation of the analog circuit on the control board. It has a mechanism to check the soundness of the analog circuit by extracting the f12 harmonic after passing through the analog circuit and detecting the attenuation rate.

  The digital protection control apparatus 100 according to the present embodiment uses the f12 harmonic superposition mechanism that has been conventionally installed to confirm the soundness of the analog circuit as the identification signal generation unit of the identification signal output unit 31. However, the identification signal output unit 31 of the digital protection control device 100 is different from the f12 harmonic superposition mechanism of the conventional protection relay device in the following points. That is, the conventional protective relay device measures the attenuation rate of the f12 harmonic by applying the f12 harmonic in the input part of the control board or inside the control board. On the other hand, in the digital protection control device 100 of this embodiment, the application location of the f12 harmonic is applied not in the control board 2 but in the input conversion board 1. Further, the f12 harmonic generated in the input conversion board 1 is set at a predetermined timing as an identification signal for the input conversion board 1. In other words, in the digital protection control device 100 of the present embodiment, the timing for applying the f12 harmonic is set independently by the input conversion board 1. Further, the f12 harmonic generation unit 31a of the identification signal output unit 31 also serves as an f12 harmonic output for soundness determination of an analog circuit. As described above, the digital protection control device 100 according to the present embodiment uses the f12 harmonic superimposing mechanism of the conventional protection relay device as the identification signal output unit 31, thereby avoiding the addition of a new member and converting the input. The identification of the substrate 1 and the failure detection can be performed simultaneously.

[Control board 2]
Returning to FIG. 1, the control board 2 performs analog filter circuits 14 a, 14 b,..., 14 i, sampling hold circuits 15 a, 15 b,. A D converter 17, an arithmetic processing unit 24, an analog filter 33, and a sampling hold circuit 34 are provided. The analog filter circuits 14a, 14b,..., 14i, the sampling hold circuits 15a, 15b,..., 15i, the multiplexer 16, the A / D converter 17, the analog filter 33, and the sampling hold circuit 34 communicate from the input conversion board 1. An analog signal supplied via the line 13 and the identification signal line 32 is converted into a digital signal, and is input to input.

  The arithmetic processing unit 24 includes a harmonic removal digital filter 18, an f12 harmonic extraction digital filter 19, a buffer 20, a buffer 21, a CPU (Central Processing Unit) 22, and a ROM (Read Only Memory) 23. Each unit constituting the arithmetic processing unit 24 is connected to a system bus (BUS), and is connected to be communicable with each other through the system bus (BUS).

  In the following description, the analog filters 14a, 14b,. The sampling hold circuits 15a, 15b,..., 15i are referred to as sampling hold circuits 15 unless otherwise distinguished. In addition, the flow of signals through the channels (A to I) of the input conversion board 1 and the control board 2 is shown surrounded by a two-dot chain line in FIG.

  The analog filter 14 is a aliasing prevention filter that removes unnecessary harmonic components from the input analog signal and outputs the result to the sampling hold circuit 15. In the present embodiment, the analog filter 14 passes only a frequency component (including DC voltage) that is ½ or less of a sampling frequency (for example, an electrical angle of 30 °) and a voltage (analog signal) in a rated frequency band. The frequency component voltage (analog signal) is attenuated at a predetermined rate as noise.

  The sampling hold circuits 15a, 15b,..., 15i are connected to the input terminals of the respective channels of the multiplexer 16. The sampling hold circuit 15 samples and holds the supplied analog signal at every sampling interval, and outputs it to the multiplexer 16.

  The multiplexer 16 includes a plurality of input terminals (channels), selects one analog signal from the plurality of analog signals input to the plurality of input terminals, and outputs the selected analog signal to the A / D converter 17. That is, the multiplexer 16 selects and outputs one analog signal from the analog signals supplied from the input conversion board 1 via the corresponding communication line 13 for each input end (channel). The selection process of the multiplexer 16 is performed by time division, for example. The multiplexer 16 sequentially switches connections (channels) with the sampling hold circuits 15a, 15b,..., 15i in a time division manner, and switches a plurality of input analog signals. The multiplexer 16 of this embodiment corresponds to 16 channels as an example.

  The A / D converter 17 converts an analog signal supplied from the input conversion board 1 through the communication line 13 and the identification communication line 32 into a digital signal, and converts the harmonic removal digital filters 18 and f12 of the arithmetic processing unit 24. Output to the harmonic extraction digital filter 19.

  The harmonic removal digital filter 18 is a band-pass filter that passes only voltages in a predetermined rated frequency band and removes voltages and DC voltages in other frequency bands.

  The f12 harmonic extraction digital filter 19 is a band-pass filter that passes only voltages in the f12 harmonic frequency band and removes voltages and DC voltages in other frequency bands.

  The buffer 20 and the buffer 21 temporarily hold and output the data supplied from the harmonic removal digital filter 18 and the f12 harmonic extraction digital filter 19, respectively.

  The CPU 22 controls the entire control board 2 and executes the program stored in the ROM 23 to identify the board type of the input conversion board 1 connected to the control board 2. This identification timing is, for example, when the input conversion board 1 and the control board 2 are connected, but any timing may be used. Further, the CPU 22 can always check the operation including the operation time by using the f12 harmonic data stored in the buffer 21.

  In addition, the CPU 22 detects the function of the control unit that performs protection control processing for protecting the power system and the amplitude of the f12 harmonic stored in the buffer 21 to determine the soundness of the analog circuit such as the analog filter 14. Monitoring function. Note that the arithmetic processing unit for identifying the board type of the input conversion board 1 and the control unit for performing the protection control process may be separate circuits.

  The ROM 23 stores programs executed by the CPU 22 and various data. In the ROM 23, a board information database to be referred to when the digital protection control device 100 identifies the board type of the input conversion board 1 is constructed.

  The analog filter 33 and the sampling hold circuit 34 process the identification signal supplied from the identification signal output unit 31 of the input conversion board 1 via the identification communication line 32.

  The analog filter 33 has the same function as the analog filter circuit 14, attenuates unnecessary harmonic components from the input analog signal, and outputs the attenuated harmonic component to the sampling hold circuit 34.

  The sampling and holding circuit 34 has the same function as the sampling and holding circuit 15, samples and holds the supplied analog signal at every sampling interval, and outputs it to the multiplexer 16.

[Settling part 3]
The settling unit 3 sets a settling value that defines the operation of the external device 110 such as a relay in order to protect the power system and the power equipment. The settling unit 3 includes an operation unit 3a and a display unit 3b, and a monitor or the like sets the settling value using the operation unit 3a and the display unit 3b. The set value set by the settling unit 3 is stored in the ROM 23 via the system bus (BUS).

[Digital I / O unit 4]
Based on the control of the CPU 22, the digital input / output unit 4 controls the external device 110 such as a relay and acquires state information from the external device 110.

[Control power supply 5]
The control power supply unit 5 is a power supply that supplies power to each unit of the digital protection control device 100. For example, a DC-DC converter is applied to the control power supply unit 5. The control power supply unit 5 supplies a DC voltage of 5 V to each of the input conversion board 1, the control board 2 and the settling unit 3, and the digital input / output unit 4 has an input unit and an output unit (both not shown), respectively. Supply DC 5V and DC 15V.

Hereinafter, the operation of the digital protection control device 100 configured as described above will be described.
First, a signal processing example of the digital protection control device 100 will be described.

  FIG. 3 is a diagram for explaining an example of signal processing of the digital protection control device 100. In FIG. 3, a change in voltage output from the identification signal output unit 31 in the input conversion board 1 is also simply shown.

  The identification signal output unit 31 in the input conversion board 1 generates an identification signal (Sj1) that is an AC voltage and outputs it to the identification communication line 32. As an identification signal (Sj1), for example, it is assumed that an analog signal having a specific pattern in which an f12 harmonic with an amplitude of 0.1 V is superimposed / non-superimposed every millisecond is output.

  The identification signal (Sj1) (see FIG. 3a) is sent to the analog filter 33 in the control board 2 via the identification communication line 32. For example, the analog filter 33 passes only a frequency component (including a DC voltage) that is ½ or less of the sampling frequency and a voltage in the rated frequency band, and the other frequency component voltages are attenuated at a predetermined rate as noise (see FIG. 3b). The identification signal (Sj1) is an f12 harmonic of the fundamental wave, that is, an AC signal having a frequency 12 times the rated frequency. Therefore, the identification signal (Sj1) is attenuated to a predetermined ratio (for example, 50%) by the analog filter 33, and the amplitude is attenuated (here, the amplitude is 0.05 V), thereby obtaining the analog signal (Sj2). Become.

  The analog signal (Sj2) that has passed through the analog filter 33 is sampled by the sampling hold circuit 34 of each channel, and is supplied to the A / D converter 17 while the multiplexer 16 sequentially switches the channel.

  The A / D converter 17 converts the analog signal (Sj2) into a digital signal (Sj3) and outputs it (see FIG. 3c). In the waveforms of FIG. 3 and subsequent figures, for convenience of explanation, the digital signal is shown as an analog signal waveform, but it is actually a digital signal. In this example, the voltage value of the digital signal (Sj3) is an AC value having an amplitude of 0.05V. The digital signal (Sj3) is transferred to the harmonic removal digital filter 18 and the f12 harmonic extraction digital filter 19.

  The harmonic removal digital filter 18 passes only a voltage in a predetermined rated frequency band, and removes a voltage and a DC voltage in other frequency bands (see FIG. 3d). In this example, since the digital signal (Sj3) is an AC signal having a frequency 12 times the rated frequency, the digital signal (Sj4) is cut by the harmonic elimination digital filter 18 and the voltage value of the digital signal (Sj4) after passing is 0V. Become. The digital signal (Sj4) that has passed through the harmonic removal digital filter 18 is temporarily stored in the buffer 20.

  The f12 harmonic extraction digital filter 19 passes only the voltage in the rated frequency band 12 times the rated frequency, and removes the voltage and DC voltage in the other frequency bands. Since the digital signal (Sj3) is an AC signal having a frequency 12 times the rated frequency, the digital signal (Sj3) is not removed by the f12 harmonic extraction digital filter 19; (See FIG. 3e). The digital signal (Sj3) that has passed through the f12 harmonic extraction digital filter 19 is temporarily stored in the buffer 21.

  When the CPU 22 is notified that the digital signals from the harmonic removal digital filter 18 and the f12 harmonic extraction digital filter 19 have been prepared in the buffer 20 and the buffer 21, the CPU 22 reads out these data. The CPU 22 compares the time change pattern of the digital signal (Sj3) of the identification channel read from the buffer 21 with the board information database stored in the ROM 23 in the control board 2 to implement the input conversion implemented. The substrate type of the substrate 1 is determined. The details of the substrate information database will be described later with reference to FIG.

  In addition, the CPU 22 detects the amplitude of the f12 harmonic stored in the buffer 21 and determines the soundness of the analog circuit.

  FIG. 4 is a diagram showing an example of the board information database stored in the ROM 23.

  As shown in FIG. 4, the board information database stores a table 25 in which voltage level temporal change patterns and board types are associated with each other.

  In the example of FIG. 4, the table 25 of the board information database has a voltage level time change pattern that alternately repeats a frequency (amplitude 0.05 V) and a voltage 0 V that are 12 times the frequency rating every millisecond. Type of Substrate “Substrate A” Type of Substrate in Case of Having a Time-Varying Pattern of Voltage Level that Repeats Frequency (Amplitude 0.05V) and Voltage 0V Alternately at 12 Times of Frequency Rating Every 2 ms “Substrate B”, a type of substrate “Substrate C” having a voltage level time-varying pattern that alternately repeats a frequency (amplitude 0.05 V) and a voltage 0 V that are 12 times the frequency rating every 3 milliseconds, In addition, “no mounting board” in the case of no voltage level temporal change pattern is stored.

  The CPU 22 refers to the table 25 and determines the type of the input conversion board 1 that is the corresponding mounting board based on the temporal change pattern of the voltage level of the digital signal (Sj3) read from the buffer 21.

  For example, as shown in “Substrate A” in FIG. 4, the temporal change pattern of the voltage level of the digital signal (Sj3) read from the buffer 21 is 12 times the rating with an amplitude of 0.05 V per millisecond. When the frequency and the voltage 0V are alternately detected, the CPU 22 refers to the table 25 of the board information database and determines that the type of the mounting board, that is, the input conversion board 1 is the board A.

  Further, as shown in “Substrate B” in FIG. 4, the temporal change pattern of the voltage level of the digital signal (Sj3) read from the buffer 21 is 12 times the rating with an amplitude of 0.05 V every 2 milliseconds. If the frequency and the voltage of 0 V are alternately detected, the CPU 22 refers to the table 25 of the board information database and determines that the type of the input conversion board 1 is the board B.

  Further, as shown in “Substrate C” in FIG. 4, the time-varying pattern of the voltage level of the digital signal (Sj3) read from the buffer 21 is 12 times the rating with an amplitude of 0.05 V every 3 milliseconds. In this case, the CPU 22 determines that the type of the input conversion board 1 is the board C with reference to the table 25 of the board information database.

  Further, as shown in “no mounting” in FIG. 4, when there is no temporal change pattern of the voltage level of the digital signal (Sj3) read from the buffer 21, the CPU 22 refers to the table 25 of the board information database. Thus, it is determined that the input conversion board 1 is not mounted.

  As described above, the digital protection control device 100 according to the present embodiment is provided for each protection element, and includes an input conversion board having an input conversion unit 10 that performs a predetermined conversion process on an analog signal of an input power system. 1 and a control board 2 having an arithmetic processing unit 24 for identifying the type of the input conversion board 1 based on the identification signal converted into a digital signal. The input conversion board 1 is provided for each protection element, and outputs an input conversion unit 10 that performs a predetermined conversion process on an analog signal of an input power system, and an identification signal that is an analog signal for identifying its own board. And an identification signal output unit 31.

  As described above, the digital protection control device 100 is provided with the identification signal output unit 31 for outputting the identification signal which is an analog signal on the input conversion board 1, and also connects the input conversion board 1 and the control board 2 to the identification communication line 32. And the identification signal (analog signal) is transmitted from the input conversion board 1 to the control board 2. For example, f12 harmonics are transmitted from the input conversion board 1 to the control board 2 as an identification signal (analog signal). The CPU 22 of the control board 2 identifies the board type of the input conversion board 1 connected to the control board 2.

  With this configuration, the identification of the input conversion board mounted on the digital protection control device can be realized without newly installing a digital circuit and a digital communication line and using the same mechanism.

  For example, even when the input conversion board 1 is not mounted with a digital circuit and a digital communication line, the board information (unique information) included in the identification signal (analog signal) output by the identification signal output unit 31 is used. The type of the input conversion board 1 can be identified by analysis. That is, in the past, the input conversion board was identified by human manual work and visual confirmation in accordance with the analog input unit mounted on the digital protection control device, so there was a risk of mounting the input conversion board incorrectly. . In particular, when there are a plurality of input conversion boards, the risk of misplacement increases, and a lot of labor is spent on work time such as confirmation of settings. In this embodiment, even if the input conversion board 1 is an analog board, a digital circuit is not installed on the input conversion board 1 or a digital communication line is not installed between the input conversion board 1 and the control board 2. The conversion board (analog board) can be identified, and human error can be prevented in advance.

  In this embodiment, it is also possible to detect deterioration / failure of an analog circuit such as the analog filter 14. In this case, the identification signal output unit 31 outputs the pattern of time change between the f12 harmonic signal and the predetermined voltage level as the identification signal, thereby avoiding the addition of a new member and the input conversion board 1. Identification and fault detection can be performed simultaneously.

[Modification]
In the first embodiment, an identification signal output unit 31 that outputs an identification signal (analog signal) is provided on the input conversion board 1, and the input conversion board 1 and the control board 2 are separated from the communication line 13 for identification communication. The example in which the connection is made by the line 32 and the identification signal is transmitted from the input conversion board 1 to the control board 2 through the identification communication line 32 has been described. Hereinafter, an example in which the identification communication line 32 is not installed will be described.

In FIG. 1, the digital protection control device 100 is configured such that when there is a communication line 13 that is not used, that is, a channel is not assigned to a plurality of communication lines 13a, 13b,. 13 can also be used as an identification communication line.
When there is a communication line 13 to which no channel is assigned, the identification signal output unit 31 transmits the identification signal to the control board 2 using the communication line 13 to which no channel is assigned. Thereby, the unused communication line 13 can be used effectively, and there is an effect that it is not necessary to newly install the identification communication line 32.

(Second Embodiment)
The communication between the input conversion board 1 and the control board 2 requires many lines for transmitting analog signals, so the number of lines that can be installed for identifying the board type is limited.
Therefore, in the second embodiment, a technology for transmitting board information by establishing a smaller number of lines is established. The present embodiment is an example in which the identification communication line 32 is not used.

  FIG. 5 is a block diagram showing the configuration of the digital protection control apparatus according to the second embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals, and description of overlapping portions is omitted.

  As shown in FIG. 5, the digital protection control device 100A includes an input conversion board 1A, a control board 2, a settling unit 3, a digital input / output unit 4, and a control power supply unit 5 that supplies power to each unit. It is prepared for. The input conversion board 1A is connected to the control board 2 through communication lines 13a, 13b,.

[Input conversion board 1A]
The input conversion board 1A includes auxiliary transformers 11a, 11b,..., 11i and resistor circuits 12a, 12b,..., 12i, and an input conversion unit 10 that converts an input analog signal into an analog signal of an appropriate voltage level, .., 12i are arranged in the subsequent stage of the channel resistance circuits 12a, 12b,..., 12i, and the analog signals output from the resistance circuits 12a, 12b,. Adders 35a, 35b,..., 35i for adding signals, and identification signals (analog signals) that are alternating voltages are generated for each channel and supplied to the adders 35a, 35b,. A signal output unit 31A. In the following description, the adders 35a, 35b,..., 35i will be referred to as adders 35 unless otherwise distinguished.

  As described above, the digital protection control device 100A includes the identification signal output unit 31A that outputs the identification signal of each channel that identifies the channel, and the resistance circuits 12a, 12b,... Of each channel in the input conversion board 1A. , 12i is provided with adders 35a, 35b,..., 35i for adding the identification signals of the respective channels to the analog signals output from the resistor circuits 12a, 12b,. The configuration of the digital protection control device 100 shown in FIG.

  On the other hand, the arithmetic processing unit 24 of the control board 2 specifies each channel in the input conversion board 1A based on the identification signal of each channel transmitted from the input conversion board 1A, and converts each channel from the specified result. The substrate 1A is identified. That is, in the input conversion board 1A, each channel has a specific pattern, and the type of the input conversion board 1A can be identified by specifying each channel.

Hereinafter, an operation of the digital protection control device 100A configured as described above will be described.
First, a signal processing example of the digital protection control device 100A will be described.

FIG. 6 is a diagram for explaining an example of signal processing of the digital protection control apparatus 100A. In FIG. 6, the change of the voltage output from the signal output part 31A for identification in the input conversion board | substrate 1A is also shown simply.
The identification signal output unit 31A in the input conversion board 1A generates an identification signal (Sa1 to Si1) for each channel, which is an AC voltage, for each channel, and supplies it to the adders 35a, 35b,. To do.

The adders 35a, 35b,..., 35i use the supplied identification signals (Sa1 to Si1) for the respective channels, the auxiliary transformers 11a, 11b,..., 11i and the resistance circuits 12a, 12b,. Applied to the analog signal converted by. Here, as an identification signal (Sa1 to Si1) for each channel, for example, an analog signal having a specific pattern in which an f12 harmonic with an amplitude of 0.1 V is superimposed / non-superposed every 1 millisecond is output.
The analog signals to which the identification signals (Sa1 to Si1) of the respective channels are applied are sent to the analog filter circuits 14a, 14b,..., 14i of the control board 2 via the communication lines 13a, 13b,. (See FIG. 6a).

  In the analog filter circuits 14a, 14b,..., 14i, for example, only the frequency component (including DC voltage) of 1/2 or less of the sampling frequency and the voltage in the rated frequency band are allowed to pass, and the other frequency component voltages are specified as noise. (See FIG. 6b). In the case of this example, the identification signals (Sa1 to Si1) for each channel are f12 harmonics of the fundamental wave, that is, AC signals having a frequency 12 times the rated frequency. Therefore, the identification signals (Sa1 to Si1) of the respective channels are attenuated to a predetermined ratio (eg, 50% here) and the amplitude is attenuated (here, the amplitude is 0) by the analog filter circuits 14a, 14b,. .05V) and analog signals (Sa2 to Si2).

  The analog signals (Sa2 to Si2) that have passed through the analog filter circuits 14a, 14b,..., 14i are sampled by the sampling hold circuits 15a, 15b,. Supplied to the vessel 17.

  The A / D converter 17 converts the analog signal (Sa2 to Si2) into a digital signal (Sa3 to Si3) and outputs it to the buffer 20 and the buffer 21 (see FIG. 6c). In this example, the voltage value of the digital signal (Sa3 to Si3) is an AC value having an amplitude of 0.05V. The digital signal (Sa3 to Si3) is transferred to the harmonic removal digital filter 18 and the f12 harmonic extraction digital filter 19.

  The harmonic elimination digital filter 18 passes only a voltage in a predetermined rated frequency band, and removes a voltage and a DC voltage in other frequency bands (see FIG. 6d). In this example, since the digital signal (Sa3 to Si3) is an AC signal having a frequency 12 times the rated frequency, the voltage value of the digital signal (Sa4 to Si4) after being cut by the harmonic removal digital filter 18 and passing therethrough. Becomes 0V. The digital signal (Sa4 to Si4) that has passed through the harmonic removal digital filter 18 is temporarily stored in the buffer 20.

  The f12 harmonic extraction digital filter 19 passes only the voltage in the rated frequency band 12 times the rated frequency, and removes the voltage and DC voltage in the other frequency bands. In this example, since the digital signal (Sa3 to Si3) is an AC signal having a frequency 12 times the rated frequency, it is not removed by the f12 harmonic extraction digital filter 19, and the digital signal after passing (Sa3 to Si3) The maximum AC value is 0.05V (see FIG. 6e). The digital signal (Sj3 to Si3) that has passed through the f12 harmonic extraction digital filter 19 is temporarily stored in a buffer circuit (not shown) of the buffer 21.

  When the CPU 22 is notified that the digital signals (Sa4 to Si4, Sa3 to Si3) of each channel are prepared in the buffer 20 and the buffer 21, the CPU 22 reads out these data. The CPU 22 is implemented by collating the time change pattern of the digital signal (Sa3 to Si3) of each channel read from the buffer 21 with the board information database stored in the ROM 23 in the control board 2. The board type of the input conversion board 1A is determined.

  In addition, the CPU 22 detects the amplitude of the f12 harmonic stored in the buffer 21 and determines the soundness of the analog circuit of each channel.

  7 and 8 are diagrams showing an example of the board information database stored in the ROM 23 of FIG. FIG. 7 shows a temporal change pattern of the voltage level of each channel (A to I) of the substrate type “substrate A”, and FIG. 8 shows each channel (A to I) of the substrate type “substrate A”. The pattern of a time change of a voltage level is shown.

  As shown in FIGS. 7 and 8, the board information database stores a table 25 </ b> A in which combinations of voltage level temporal change patterns of the channels (A to I) and board types are associated with each other.

  7 and 8, in the board information database table 25A, each channel (A to I) has a frequency (amplitude 0.05V) and a voltage 0V that are 12 times the frequency rating every millisecond. The type of the board in the case of having a time-varying pattern of voltage level that alternately repeats “Board A”, only the channel B always has a frequency 12 times the frequency rating (amplitude 0.05 V), and other than the channel B Substrate type “Substrate B” having a time-varying voltage level pattern that alternately repeats a frequency (amplitude 0.05V) and a voltage 0V that are 12 times the frequency rating every millisecond, and so on. The time-varying pattern of the voltage level of the channel is always 12 times the frequency rating (amplitude 0.05V), and the voltage level of the other channels is 0.05V amplitude per millisecond. Stores “board C” (not shown) when 12 times the frequency and voltage 0 V are detected alternately, and “no mounting board” (not shown) when there is no voltage level temporal change pattern. Has been.

  The CPU 22 refers to the table 25A and determines the type of the input conversion board 1A, which is the corresponding mounting board, based on the temporal change pattern of the voltage level of the digital signal (Sa3 to Si3) read from the buffer 21. .

  For example, as shown in FIG. 7, the time of the voltage level in which all of the channels (A to I) alternately repeat a frequency (amplitude 0.05 V) and a voltage 0 V that are 12 times the frequency rating every 1 millisecond. When the pattern has a change pattern, the CPU 22 refers to the table 25 of the board information database and determines that the type of the mounting board, that is, the input conversion board 1A is the board A.

  Further, as shown in FIG. 8, only the channel B always has a frequency 12 times the frequency rating (amplitude 0.05V), and other than the channel B has a frequency 12 times the frequency rating (amplitude 0) every millisecond. .05V) and voltage 0V, the CPU 22 refers to the table 25A of the board information database and the type of the mounting board, that is, the input conversion board 1A is the board B. Is determined.

  Although not shown in the figure, the time-varying pattern of the voltage level of the corresponding channel is always 12 times the frequency rating (amplitude 0.05V), and the voltage levels of the other channels are 0.05V amplitude every 1 millisecond. If the frequency 12 times the rated value and the voltage 0 V are alternately detected, it is determined that the type of the input conversion board 1A is the board C. 7 and 8 are merely examples, and any time change pattern may be used as long as each channel can be specified.

  Although not shown, when there is no time-varying pattern of voltage levels of the digital signals (Sj3 to Si3) read from the buffer 21 in all the channels (A to I), the CPU 22 executes the board information database. With reference to the table 25A, it is determined that the input conversion board 1A is not mounted.

  In this way, the input conversion board type can be identified based on the temporal change pattern of the voltage level of each channel. Moreover, since the specific pattern of each channel and the type of the input conversion substrate 1A including each channel having the specific pattern are associated with each other in the substrate information database, each channel is identified from the specific result of the input conversion substrate 1A. Judgment can be made.

  As described above, in the digital protection control device 100A according to the second embodiment, the input conversion board 1A includes the identification signal output unit 31A that outputs the identification signal of each channel that identifies the channel, and the resistance of each channel. .., 12i include adders 35a, 35b,..., 35i that add the identification signals of the respective channels to the analog signals output from the resistor circuits 12a, 12b,. . The arithmetic processing unit 24 of the control board 2 specifies each channel in the input conversion board 1A based on the identification signal for each channel transmitted from the input conversion board 1A, and converts each channel from the specified result. The substrate 1A is identified.

  With this configuration, the same effect as that of the first embodiment, that is, even when the input conversion board 1A is not mounted with a digital circuit and a digital communication line, the signal output unit for identification is added without adding a communication line. The type of the input conversion board 1A can be identified by analyzing the board information (unique information) included in the identification signal (analog signal) output by 31A. As a result, the operation time for confirming the setting can be shortened and the input conversion board (analog board) can be identified without being installed, and human error can be prevented in advance.

  In the second embodiment, since each channel of the input conversion board 1A can be specified, the following effects can be obtained.

(1) By applying a voltage in each channel, the input conversion board 1A can be more accurately identified.
The input conversion board 1A performs level conversion on an input analog signal at a predetermined attenuation rate by a level converter (not shown). The conversion attenuation factor can be set individually for each channel. In general, the attenuation factor at the time of conversion is changed by changing the resistance multiplier included in each channel. For this reason, if the resistance multiplier changes, the attenuation factor value changes even when the same voltage is applied. Thereby, it is possible to specify how many channels of the substrate the attenuation rate is. The input conversion board 1A can be more accurately identified by confirming how the channels of the magnification are arranged on the input conversion board 1A. For example, it is possible to check that channel A has a conversion attenuation factor of 0.1 and channels B and C have a conversion magnification of 0.2. Further, the input conversion board having such a channel arrangement can be identified as the board A, for example.

  (2) Since more patterns can be set by applying a voltage in each channel, more input conversion boards 1A can be identified.

  (3) Since the time change pattern between the f12 harmonic signal and the predetermined voltage level is used as the identification signal, the voltage level is specially different from the aspect of creating the identification signal by changing the voltage level. Each pattern can be set without increasing or decreasing. That is, since the voltage application margin can be maintained with a predetermined margin, the input conversion board 1A can be identified even when the input conversion board 1A is in operation. Actually, it is difficult to assume a case where the input conversion board 1A is replaced when the input conversion board 1A is in operation, but there is an advantage that the input conversion board 1A can be always checked.

  The present invention is not limited to the above-described embodiments, and includes other modifications and application examples without departing from the gist of the present invention described in the claims.

  For example, the above-described exemplary embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of an embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of an embodiment. . Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each exemplary embodiment.

  Each of the above-described configurations, functions, processing units, processing means, and the like may be realized by hardware by designing a part or all of them with, for example, an integrated circuit. Further, as shown in FIGS. 1 and 5, the above-described configurations, functions, and the like may be realized by software for interpreting and executing a program that realizes each function by the processor. Information such as programs, tables, and files for realizing each function is stored in a memory, a hard disk, a recording device such as an SSD (Solid State Drive), an IC (Integrated Circuit) card, an SD (Secure Digital) card, an optical disk, etc. It can be held on a recording medium. Further, in this specification, the processing steps describing time-series processing are not limited to processing performed in time series according to the described order, but are not necessarily performed in time series, either in parallel or individually. The processing (for example, parallel processing or object processing) is also included.

  In addition, the control lines and information lines are those that are considered necessary for the explanation, and not all the control lines and information lines on the product are necessarily shown. Actually, it may be considered that almost all the components are connected to each other.

DESCRIPTION OF SYMBOLS 1,1A Input conversion board 2 Control board 4 Digital input / output part 11a-11i Auxiliary transformer 12a-12i Resistor circuit 13a-13i Communication line 14a-14i, 33 Analog filter (input part)
15a, 15b ..., 15i, 34 Sampling hold circuit (input unit)
16 Multiplexer (input unit)
17 A / D converter (input unit)
18 Harmonic Rejection Digital Filter 19 f12 Harmonic Extraction Digital Filter 20, 21 Buffer 22 CPU
23 ROM
24 arithmetic processing unit 25, 25A table 31, 31A identification signal output unit 31a f12 harmonic generation unit 31b timing control unit 32 identification communication line 35a-35i adder 100, 100A digital protection control device

Claims (11)

An input conversion unit that is provided for each protection element, performs a predetermined conversion process on the analog signal of the input power system, and outputs the converted analog signal;
An input conversion board having an identification signal output unit that outputs an identification signal that is an analog signal for identifying the own board;
An input unit that inputs and converts an analog signal supplied via the communication line from the input conversion substrate into a digital signal,
A control unit that executes a predetermined protection control calculation based on the digital signal to perform protection control of the power system;
A digital protection control device comprising: a control board having an arithmetic processing unit for identifying a type of the input conversion board based on the identification signal converted into the digital signal. 2. The digital protection control device according to claim 1, wherein the identification signal output unit outputs a temporal change pattern between a harmonic signal that is an integral multiple of the fundamental wave and a predetermined voltage level as the identification signal. . 3. The digital protection control device according to claim 2 , wherein the harmonic signal is an f12 high frequency signal which is an AC signal having a frequency 12 times the rated frequency. The input conversion unit has a plurality of channels for each protection element;
2. The digital protection control device according to claim 1, wherein the identification signal output unit outputs the identification signal that specifies each channel. The arithmetic processing unit is configured to identify each channel in the input conversion unit based on the identification signal corresponding to each channel transmitted from the input conversion substrate, and to use the identification result. 5. The digital protection control apparatus according to claim 4, wherein the identification is performed. It further comprises an identification communication line,
2. The digital protection control device according to claim 1, wherein the identification signal output unit transmits the identification signal to the control board using the identification communication line. The input conversion unit has a plurality of channels for each protection element;
2. The identification signal output unit transmits the identification signal to the control board using an unused communication line to which the channel is not assigned among the communication lines. Digital protection controller. The identification signal output unit outputs the identification signal for each protection element,
The input conversion board is:
The digital protection control device according to claim 1, further comprising a high frequency superimposing unit that superimposes the identification signal for each protection element on each of a plurality of analog signals output from the input conversion unit. The input converter is
An auxiliary transformer to which the analog signal is supplied;
A resistor circuit to which an analog signal output from the auxiliary transformer is supplied, and
The input conversion board is:
The identification signal for each protection element output from the identification signal output unit is added to the analog signal output from the resistance circuit for each protection element, and the added signal is supplied to the corresponding communication line. The digital protection control apparatus according to claim 1, further comprising an adder that performs the operation. The digital protection control device according to claim 1, wherein the control unit determines soundness of an analog circuit of a power system based on the identification signal transmitted from the input conversion board to the control board. The input conversion board provided in the digital protection control device
Through the input conversion unit provided for each protection element, it performs a predetermined conversion process on the analog signal of the power system input from the outside and outputs the converted analog signal,
Via the identification signal output unit, an identification signal that is an analog signal for identifying its own board is output,
A control board provided in the digital protection control device,
Via the input unit, the analog signal supplied from the input conversion board is converted into a digital signal and input,
Via the control unit, a predetermined protection control calculation is performed based on the digital signal to perform protection control of the power system,
A substrate identification method for a digital protection control device, wherein the type of the input conversion substrate is identified on the basis of the identification signal converted into the digital signal via an arithmetic processing unit.

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