JP5755782B2 - Nonvolatile resistance change element - Google Patents

Description

  Embodiments described herein relate generally to a nonvolatile variable resistance element.

  In recent years, development of a two-terminal nonvolatile resistance change element represented by ReRAM (Resistive Random Access Memory) has been actively conducted. Since this nonvolatile resistance change element is capable of low voltage operation, high speed switching and miniaturization, it is a promising candidate as a next generation mass storage device that replaces the floating gate type NAND flash memory. In particular, a nonvolatile variable resistance element using amorphous silicon as a variable resistance layer is promising from the viewpoints of low current operation, data retention characteristics, rewrite resistance, and miniaturization.

  As a mass storage device using this nonvolatile variable resistance element as a memory cell, a memory having a cross-point structure has been proposed. In such a cross-point type memory, a sneak current flows into a non-selected cell when writing, reading, and erasing a selected cell.

  When the sneak current occurs, power consumption increases in the mass storage device, and writing and erasing to the selected cell become difficult. Furthermore, since the disconnection of the wiring due to an increase in current is caused, the array itself cannot be established. For this reason, in the cross-point structure, it is essential to provide a rectifying function by combining a diode with a two-terminal nonvolatile resistance change element.

  However, combining a nonvolatile resistance change element and a diode increases the element size, which makes integration difficult. In order to solve these problems, a nonvolatile variable resistance element with a rectifying function is required, and development of the element is currently required.

  The nonvolatile variable resistance element is composed of, for example, a variable resistance layer, a metal electrode, and a semiconductor layer that is a counter electrode thereof. A conductive filament grows from the metal electrode and is short-circuited to the counter electrode, and the conductive filament is re-stored in the metal electrode. As a result, the resistance between the electrodes changes and switching characteristics are obtained. In the case of such a resistance change element, since the conductive filament is in direct contact with the semiconductor layer, recombination center formation occurs due to a change in Schottky characteristics due to a chemical reaction at the interface or diffusion of the conductive filament (metal) into the semiconductor layer. Variations in device characteristics, such as current variations due to

US Patent Application Publication No. 2009-0014707

  Provided is a nonvolatile variable resistance element that can reduce device characteristic deterioration and variation and has a rectifying function.

A nonvolatile resistance change element according to one embodiment is arranged to intersect a first wiring layer and the first wiring layer, and a second wiring layer in which an n-type semiconductor layer is disposed at least on the first wiring layer side A first electrode including a metal element, the first electrode being disposed between the first wiring layer and the second wiring layer at an intersection where the first wiring layer and the second wiring layer intersect each other, A resistance change layer disposed between an electrode and the second wiring layer and formed with a conductor portion made of the metal element included in the first electrode ; and the resistance change layer and the second wiring layer. And a first layer made of an insulating material , and the conductor portion is spaced apart from the second wiring layer.

It is a figure which shows the structure of the non-volatile resistance change element which concerns on embodiment, and its band diagram. It is a figure which shows the structure of the non-volatile resistance change element which concerns on embodiment, and its band diagram. It is a figure which shows the structure and its band figure of the non-volatile variable resistance element of a comparative example. It is a figure which shows the structure and its band figure of the non-volatile variable resistance element of a comparative example. It is sectional drawing which shows the structure of the non-volatile variable resistance element which concerns on 1st Embodiment. It is sectional drawing which shows the low resistance state and high resistance state of the non-volatile variable resistance element which concern on 1st Embodiment. It is a figure which shows the current-voltage characteristic in the non-volatile variable resistance element which concerns on 1st Embodiment. It is a figure which shows the current-voltage characteristic in the other non-volatile variable resistance element which concerns on 1st Embodiment. It is sectional drawing which shows the structure of the non-volatile variable resistance element which concerns on 2nd Embodiment. It is sectional drawing which shows the low resistance state and high resistance state of the non-volatile resistance change element which concerns on 2nd Embodiment. It is sectional drawing which shows the structure of the non-volatile variable resistance element which concerns on 3rd Embodiment. It is sectional drawing which shows the low resistance state and high resistance state of the non-volatile resistance change element which concerns on 3rd Embodiment. It is a figure which shows the structure of the memory cell array concerning 4th Embodiment. It is a top view which shows the voltage setting method at the time of the write-in of the selection cell in the memory cell array concerning 4th Embodiment. It is a top view which shows the voltage setting method at the time of the reading of the selection cell in the memory cell array concerning 4th Embodiment. It is a top view which shows the voltage setting method at the time of erasing of the selection cell in the memory cell array concerning 4th Embodiment.

  The nonvolatile variable resistance element according to the embodiment will be described below with reference to the drawings. In the following description, components having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

[Basic concept]
The nonvolatile resistance change element according to the embodiment includes a first electrode, a second electrode facing the first electrode, and a resistance change layer disposed between the first electrode and the second electrode. The first electrode includes a metal element, and the second electrode includes an n-type semiconductor. The resistance change layer is formed from a semiconductor layer.

  The resistance change layer has a conductor portion (hereinafter referred to as a filament) composed of a metal element included in the first electrode. The filament of the variable resistance layer is spaced from the second electrode.

  Further, a diffusion prevention layer may be disposed between the resistance change layer and the second electrode. The diffusion preventing layer prevents the filament from diffusing from the variable resistance layer to the second electrode. Thereby, separation is formed between the filament and the second electrode.

  In the resistance change layer, the resistance of the resistance change layer can be reversibly changed by inserting and removing the filament from the first electrode. The separation between the filament of the resistance change layer and the second electrode is formed by electrical control of the first electrode and the second electrode, or insertion of a diffusion prevention layer between the resistance change layer and the second electrode.

  The structure and band diagram of the nonvolatile variable resistance element (with the diffusion prevention layer) of the embodiment will be described below.

  1A and 2A show the structure of the nonvolatile variable resistance element according to the embodiment. FIG. 1A shows a high resistance state, and FIG. 2A shows a low resistance state.

  As shown in FIG. 1A and FIG. 2A, a resistance change layer 3 is disposed between the first electrode 1 and the second electrode 2, and between the resistance change layer 3 and the second electrode 2. The diffusion prevention layer 4 is disposed on the surface. In the high resistance state shown in FIG. 1A, no filament is formed in the resistance change layer 3, and the nonvolatile resistance change element is set in the high resistance state. In the low resistance state shown in FIG. 2A, the filament 3a reaching the diffusion prevention layer 4 from the first electrode 1 is formed in the resistance change layer 3, and the nonvolatile resistance change element is set in the low resistance state. Here, the first electrode 1 is made of metal, and the second electrode 2 is made of n-type silicon (Si).

  FIGS. 1B to 1E show band diagrams in the high resistance state shown in FIG. 1A, and FIGS. 2B to 2E show the band diagrams in FIG. The band figure in a low resistance state is shown.

  In the high resistance state in which the filament shown in FIG. 1A is not formed, when a positive voltage is applied to the first electrode 1 that is an ion supply source, the n-type Si of the second electrode 2 is in an accumulation state. (FIG. 1 (b)). Conversely, when a negative voltage is applied to the first electrode 1, a depletion layer is formed on the second electrode 2 (FIG. 1 (d)), and when a further negative high voltage is applied, an inversion state is established (FIG. 1 ( e)).

  Even in the low resistance state in which the filament 3a shown in FIG. 2 (a) is formed, when a negative voltage is applied to the first electrode 1, the metal constituting the filament 3a and the second electrode 2 are provided by having the diffusion prevention layer 4. The n-type Si is not directly bonded, and a depletion layer is formed as in the high resistance state (FIG. 2D). No current flows in the state where the depletion layer is formed. Therefore, by using a structure in which a depletion layer is formed even in a low resistance state, a rectifying effect can be obtained in which the current-voltage curve is asymmetric. Furthermore, when a negative high voltage is applied to the first electrode 1, an inversion state occurs, and a sufficient voltage is applied to the resistance change layer 3 to cause a reset operation to transition from the low resistance state to the high resistance state (FIG. 2E). ).

  On the other hand, the band diagram when the diffusion preventing layer is not disposed between the resistance change layer 3 and the second electrode 2 and no separation is formed between the filament 3a and the second electrode 2 is as follows.

  In the high resistance state in which the filament shown in FIG. 3A is not formed, when a positive voltage is applied to the first electrode 1 that is an ion supply source, the n-type Si of the second electrode 2 is in an accumulation state. (FIG. 3B). Conversely, when a negative voltage is applied to the first electrode 1, a depletion layer is formed on the second electrode 2 (FIG. 3 (d)), and is inverted when a negative high voltage is applied (FIG. 3 (e)). )).

  However, in the low resistance state in which the filament shown in FIG. 4A is formed, when a negative voltage is applied to the first electrode 1, the metal constituting the first electrode 1 (filament 3a) and the second electrode 2 are formed. It becomes a direct bond with n-type Si. In particular, when the work function of the metal of the first electrode 1 is smaller than the work function of n-type Si, ohmic contact is obtained, and even when a negative voltage is applied to the first electrode 1, no depletion layer is formed, and the rectifying effect is completely eliminated. It cannot be obtained (FIG. 4 (d)).

  The combination of using an n-type semiconductor for the second electrode and forming a separation between the filament of the variable resistance layer and the second electrode results in less deterioration and variation in device characteristics and rectification compared to the conventional structure. A nonvolatile resistance change element having a function can be formed.

[First Embodiment]
[1] Structure of Nonvolatile Resistance Change Element FIG. 5 is a cross-sectional view showing the structure of the nonvolatile resistance change element according to the first embodiment.

  As illustrated, the nonvolatile resistance change element 10 includes an upper electrode (first electrode) 1, a lower electrode (second electrode) 2, and a resistance change layer (semiconductor layer) 3. The resistance change layer 3 is disposed between the upper electrode 1 and the lower electrode 2. In the resistance change layer 3, a filament made of a metal element included in the upper electrode 1 is formed. The filament formed in the resistance change layer 3 is spaced from the lower electrode 2. In other words, the filament of the resistance change layer 3 is separated from the lower electrode 2.

  The upper electrode 1 is an electrode containing a metal. Materials applicable as the upper electrode 1 are, for example, Ag, Co, Ni, Ti, Cu, Al, Au, Fe, Cr, W, Hf, Ta, Pt, Ru, Zr, Ir, and their nitrides, carbides, Oxides, silicides, and the like. Furthermore, an alloy material containing the metals mentioned here may be used as the upper electrode 1.

The lower electrode 2 is formed from, for example, an n-type semiconductor layer. The n-type impurity concentration of the n-type semiconductor layer is desirably 1 × 10 ¹⁸ cm ⁻³ or less where depletion of the n-type semiconductor becomes significant. The resistance value of the lower electrode 2 is desirably 0.01Ω or more. Further, the lower electrode 2 may be made of silicon doped with a high concentration of impurities.

The resistance change layer 3 is formed from a semiconductor layer, for example. The semiconductor element included in the semiconductor layer can be selected from, for example, Si, Ge, SiGe, GaAs, InP, GaP, GaInAsP, GaN, and SiC. The resistance change layer 3 may be an amorphous semiconductor, a polycrystalline semiconductor, or a monocrystalline semiconductor. For example, amorphous silicon, polycrystalline silicon, or single crystal silicon can be used for the resistance change layer 3. Further, nitrogen (N) or oxygen (O) may be added to the semiconductor element included in the resistance change layer 3, for example, a silicon nitride film (SiN) or a silicon oxide film (SiO ₂ ). .

  The thickness of the resistance change layer 3 is typically 1 nm to 300 nm. Considering the miniaturization of the resistance change element 10, it is better that the film thickness is thinner, but if it is too thin, a uniform film cannot be obtained, and therefore 2 nm to 50 nm is more preferable. The optimum film thickness of the resistance change layer 3 is determined by the material of the resistance change layer and its resistance value.

  The lower electrode 2 is an electrode serving as a base when the variable resistance layer 3 is formed, and the upper electrode 1 is an electrode formed after the variable resistance layer 3 is formed.

[2] Method for Manufacturing Nonvolatile Resistance Change Element Next, a method for manufacturing the nonvolatile resistance change element shown in the first embodiment will be described.

First, phosphorus (P) ions are implanted into a semiconductor substrate, for example, a silicon single crystal substrate at an acceleration voltage of 30 keV and a dose of 4 × 10 ¹³ cm ⁻² . Thereafter, activation annealing is performed on the silicon substrate to form an n-type silicon layer as the lower electrode 2.

  Next, amorphous silicon as the resistance change layer 3 is deposited on the lower electrode 2 by chemical vapor deposition (CVD). In the present embodiment, amorphous silicon is formed at a film formation temperature of 250 ° C. using a plasma-enhanced chemical vapor deposition (PE-CVD) method.

  Next, Ag as the upper electrode 1 is formed on the resistance change layer 3 by sputtering, for example. Thus, the nonvolatile resistance change element 10 shown in FIG. 5 is manufactured.

[3] Characteristics of Nonvolatile Resistance Change Element The switching principle of the resistance change element 10 manufactured by the above-described manufacturing method will be described with reference to FIGS. 6 (a) and 6 (b).

  FIG. 6A is a cross-sectional view showing a low resistance state of the nonvolatile variable resistance element 10 shown in FIG.

  The growth process of the filament 3a formed in the resistance change layer 3 is as follows. A set voltage is applied to the upper electrode 1 by setting the upper electrode 1 to have a higher potential than the lower electrode 2. When a set voltage is applied to the upper electrode 1, the metal element in the upper electrode 1 is ionized, and the ionized metal element (metal ion) 3 b enters the resistance change layer 3 as shown in FIG. To do. At the same time, electrons are supplied to the resistance change layer 3 through the lower electrode 2.

  Then, in the resistance change layer 3, the metal ions 3 b and the electrons are combined to grow a filament 3 a made of the metal element of the upper electrode 1 in the resistance change layer 3. The filament 3 a grows in the resistance change layer 3 toward the lower electrode 2, but does not reach the lower electrode 2, and the filament 3 a is separated from the lower electrode 2. As a result, the resistance between the upper electrode 1 and the lower electrode 2 is reduced, so that the nonvolatile resistance change element 10 is set in a low resistance state.

  FIG. 6B is a cross-sectional view showing a high resistance state of the nonvolatile resistance change element 10 shown in FIG.

  The extinction process of the filament 3a formed in the resistance change layer 3 is as follows. A reset voltage is applied to the upper electrode 1 by setting the upper electrode 1 to have a lower potential than the lower electrode 2. When a reset voltage is applied to the upper electrode 1, holes are supplied to the resistance change layer 3 through the lower electrode 2, and the metal elements constituting the filament 3 a are ionized in the resistance change layer 3. And the metal element of the filament 3a is collect | recovered by the upper electrode 1, and the filament 3a in the resistance change layer 3 lose | disappears. Thereby, the nonvolatile variable resistance element 10 is reset to a high resistance state.

  The low resistance state and the high resistance state described above can be reversibly controlled by the polarity of voltage application. At this time, the high resistance state corresponds to the off state and the low resistance state corresponds to the on state. Then, when a certain voltage is applied, the current value flowing through the nonvolatile variable resistance element 10 is read, and the memory device can be operated as a memory by distinguishing between the on state and the off state. Further, since the transition between the high resistance state and the low resistance state occurs only when a voltage is applied, a nonvolatile memory can be realized.

  In addition, as shown in FIGS. 6A and 6B, the example in which the low resistance state and the high resistance state are formed by the growth and disappearance of the filament 3a in the resistance change layer 3 has been described. A low resistance state and a high resistance state may be formed by diffusing the metal element of the upper electrode 1 throughout the variable resistance layer 3.

  FIG. 7 is a diagram showing current-voltage characteristics in the nonvolatile resistance change element 10 shown in FIG. 5, and shows switching characteristics of the nonvolatile resistance change element 10.

  In the present embodiment, in order to provide a separation between the filament 3a and the lower electrode 2, electric control is performed by setting an upper limit current limit (compliance current) by DC measurement. Here, the compliance current was 500 nA. The control of the filament 3a is not limited to the upper limit current limitation, and may be pulse control. Examples of the pulse control method include a control method by optimizing the pulse width, the pulse time, and the number of applied pulses.

  As shown in FIG. 7, when the voltage applied to the upper electrode 1 of the nonvolatile variable resistance element is increased in the positive direction, the high resistance state is changed to the low resistance state. On the other hand, when the voltage applied to the upper electrode 1 is swept in the negative direction with respect to the non-volatile resistance change element in the low resistance state, there is a region where the current does not flow so much up to about 1 V. Decrease and transition from the low resistance state to the high resistance state.

  In the high resistance state, in the range where the voltage applied to the upper electrode 1 is somewhat larger than the reset voltage Vreset, current hardly flows with respect to the voltage. When the voltage applied to the upper electrode 1 is further swept in the positive direction from this state, the high resistance state transitions to the low resistance state.

  That is, the nonvolatile resistance change element can reversibly transition between the high resistance state and the low resistance state, and can store data for one bit.

  Further, from the current-voltage characteristics of FIG. 7, when the voltage is swept from 0 V to the reset voltage between the upper electrode 1 and the lower electrode 2, the amount of current change between 0 V and a voltage that is half the reset voltage. It can be seen that the maximum value of is smaller than the maximum value of the current change amount between the half of the reset voltage and the reset voltage.

  FIG. 8 is a diagram showing current-voltage characteristics in another nonvolatile variable resistance element.

  As shown, a filament is formed in the resistance change layer by sweeping a positive voltage from 0 V to the upper electrode, which is an ion supply source, and the nonvolatile resistance change element transitions from a high resistance state to a low resistance state ( Arrow A). At this time, in order to prevent the element change due to the resistance change element being in a low resistance state and a large current flowing, the current upper limit function of the measuring instrument was used so that the current did not flow beyond the set current.

  Next, sweeping was performed from a positive voltage to 0 V (arrow B). Further, after applying a negative voltage from 0 V (arrow C), sweeping from the negative voltage to 0 V was performed (arrow D). When a negative voltage is applied, since a depletion layer is formed in the lower electrode, the current flowing between the upper electrode and the lower electrode is suppressed. In this current-voltage curve, a reset operation in which a transition from the low resistance state to the high resistance state occurs in the state where the depletion layer is formed. Even in a nonvolatile resistance change element having such current-voltage characteristics, the resistance state of the element reversibly transitions between a high resistance state and a low resistance state, and 1-bit data can be stored.

  Further, from the current-voltage characteristics of FIG. 8, when the voltage is swept from 0 V to the reset voltage between the upper electrode 1 and the lower electrode 2, the current change between the voltage of 1/10 of the reset voltage and the reset voltage. It can be seen that the maximum value is within one digit.

  In the nonvolatile resistance change element of the present embodiment, there is a separation between the filament 3a and the lower electrode 2, and an n-type semiconductor is used for the lower electrode 2. By this combination, when a positive voltage is applied to the upper electrode 1, the n-type semiconductor is in an accumulation state, and conversely, when a negative voltage is applied to the upper electrode 1, a depletion layer is formed in the n-type semiconductor. Inverts when applied. The state of the n-type semiconductor that is the lower electrode 2 changes depending on the difference in voltage polarity and voltage magnitude. By incorporating this n-type semiconductor as an electrode into the nonvolatile variable resistance element itself, the current-voltage characteristic of the element itself is asymmetrical depending on the polarity, and a nonvolatile variable resistance element having a rectifying action is realized.

  In addition, the filament 3 a does not directly contact the lower electrode 2 and does not enter the lower electrode 2 in the on state. For this reason, it is possible to prevent metal from diffusing in the lower electrode 2, forming a recombination center, and increasing current when the negative voltage is applied to the upper electrode 1, thereby causing device degradation.

[Second Embodiment]
The nonvolatile resistance change element according to the second embodiment includes a diffusion prevention layer 4 between the resistance change layer 3 and the lower electrode 2. Other configurations are the same as those of the first embodiment.

[1] Structure of Nonvolatile Resistance Change Element FIG. 9 is a cross-sectional view showing the structure of the nonvolatile resistance change element according to the second embodiment.

  As shown in the figure, the nonvolatile resistance change element 20 includes an upper electrode (first electrode) 1, a lower electrode (second electrode) 2, a resistance change layer (semiconductor layer) 3, and a diffusion prevention layer (first layer). 4. The resistance change layer 3 is disposed between the upper electrode 1 and the lower electrode 2. The diffusion prevention layer 4 is disposed between the resistance change layer 3 and the lower electrode 2. In the resistance change layer 3, a filament made of a metal element included in the upper electrode 1 is formed. The diffusion preventing layer 4 prevents the filament from diffusing into the lower electrode 2. In other words, the diffusion prevention layer 4 is disposed between the resistance change layer 3 and the lower electrode 2 in order to provide a separation between the filament of the resistance change layer 3 and the lower electrode 2.

The diffusion prevention layer 4 is preferably formed of a material having a diffusion coefficient of the metal forming the filament smaller than that of the resistance change layer 3. In addition, it is preferable to use a material whose ease of movement in the ionized state of the metal is smaller than that of the resistance change layer 3. The diffusion preventing layer 4 is made of, for example, a material having a high dielectric constant (high-k). Further, for example, a silicon oxide film (SiO ₂ ), a silicon oxynitride film (SiON), or a silicon nitride film (SiN) is used for the diffusion prevention layer 4. For example, a silicon oxide film or a silicon nitride film may be used as a diffusion prevention layer for Ag, Ni, and Co.

  The resistance change layer 3 is formed from a semiconductor layer, for example. Examples of the material of the resistance change layer 3 include Si, Ge, SiGe, GaAs, InP, GaP, GaInAsP, GaN, SiC, and oxides, nitrides, oxynitrides, and carbides thereof. Furthermore, these may be either amorphous polycrystalline or single crystalline, and for example, amorphous silicon, polycrystalline silicon, or single crystalline silicon can be used. Since materials having the same composition are also used in the diffusion prevention layer 4 and the resistance change layer 3, the materials of the diffusion prevention layer 4 and the resistance change layer 3 are determined by a combination of both.

[2] Method for Manufacturing Nonvolatile Resistance Change Element Next, a method for manufacturing the nonvolatile resistance change element shown in the second embodiment will be described.

First, phosphorus (P) ions are implanted into a semiconductor substrate, for example, a silicon single crystal substrate at an acceleration voltage of 30 keV and a dose of 4 × 10 ¹³ cm ⁻² . Thereafter, activation annealing is performed on the silicon substrate to form an n-type silicon layer as the lower electrode 2.

  Next, a diffusion preventing layer 4, for example, a silicon nitride film is deposited on the lower electrode 2 by the CVD method. Further, amorphous silicon as the resistance change layer 3 is deposited on the diffusion prevention layer 4 by the CVD method. In the present embodiment, amorphous silicon is formed at a film formation temperature of 250 ° C. using a plasma-enhanced chemical vapor deposition (PE-CVD) method.

  Next, Ag as the upper electrode 1 is formed on the resistance change layer 3 by sputtering, for example. Thus, the nonvolatile resistance change element 10 shown in FIG. 9 is manufactured.

[3] Characteristics of Nonvolatile Resistance Change Element FIG. 10A is a cross-sectional view showing a low resistance state of the nonvolatile resistance change element 20 shown in FIG.

  Between the lower electrode 2 and the resistance change layer 3, the filament 3 a has a diffusion prevention layer 4 formed of a material that is less likely to move and diffuse than the resistance change layer 3. Thereby, when a set voltage is applied to the upper electrode 1, the growth of the filament 3 a stops at the interface between the diffusion prevention layer 4 and the resistance change layer 3 or inside the diffusion prevention layer 4. Thereby, even if an n-type semiconductor is used for the lower electrode 2 and the filament 3 a is formed on the resistance change layer 3, a separation can be provided between the filament 3 a and the lower electrode 2.

  By using an insulating material for the diffusion prevention layer 4, the filament 3 a, the diffusion prevention layer 4, and the lower electrode (n-type semiconductor) 2 have a MIS (Metal-Insulator-Silicon) structure. With this MIS structure, when a positive voltage is applied to the upper electrode 1, the n-type semiconductor that is the lower electrode 2 is in an accumulated state. On the other hand, when a negative voltage is applied to the upper electrode 1, the n-type semiconductor of the lower electrode 2 is depleted and inverts at an even higher negative voltage. Since almost no current flows in the depletion state, a difference occurs in the value of the current flowing between the upper electrode 1 and the lower electrode 2 between when the potential is applied to the upper electrode 1 and when the potential is applied to the lower electrode 2. A rectifying function is obtained without adding a diode to the change element 20.

  In the nonvolatile resistance change element of the present embodiment, the filament 3 a and the lower electrode 2 are thus separated by the diffusion prevention layer (insulator) 4, and an n-type semiconductor is used for the lower electrode 2. By this combination, when a positive voltage is applied to the upper electrode 1, the n-type semiconductor is in an accumulation state, and conversely, when a negative voltage is applied to the upper electrode 1, a depletion layer is formed in the n-type semiconductor. Inverts when applied. The state of the n-type semiconductor that is the lower electrode 2 changes depending on the difference in voltage polarity and voltage magnitude. By incorporating this n-type semiconductor as an electrode into the nonvolatile variable resistance element itself, the current-voltage characteristic of the element itself is asymmetrical depending on the polarity, and a nonvolatile variable resistance element having a rectifying action is realized.

[Third Embodiment]
The nonvolatile variable resistance element of the third embodiment includes two types of amorphous silicon having different film forming conditions as the variable resistance layer 3. Other configurations are the same as those of the first embodiment.

[1] Structure of Nonvolatile Resistance Change Element FIG. 11 is a cross-sectional view showing the structure of the nonvolatile resistance change element according to the third embodiment.

  As illustrated, the nonvolatile resistance change element 30 includes an upper electrode (first electrode) 1, a lower electrode (second electrode) 2, and a resistance change layer (semiconductor layer) 3. The resistance change layer 3 includes a first resistance change layer 3-1 and a second resistance change layer 3-2. The first and second resistance change layers 3-1 and 3-2 are provided on the lower electrode 2 between the lower electrode 2 and the upper electrode 1, on the first resistance change layer 3-1 and the second resistance change layer 3-3. They are stacked in the order of 2. In the second resistance change layer 3-2, a filament made of a metal element included in the upper electrode 1 is formed. The first resistance change layer 3-1 prevents the filament from diffusing into the lower electrode 2. In other words, the first resistance change layer 3-2 is provided between the second resistance change layer 3-2 and the lower electrode 2 in order to provide a gap between the filament of the second resistance change layer 3-2 and the lower electrode 2. 1 is arranged.

  In this example, an n-type Si layer is used as the lower electrode 2, two types of amorphous silicon having different film forming conditions are used as the resistance change layer 3, and Ag is used as the upper electrode 1.

[2] Method for Manufacturing Nonvolatile Resistance Change Element Next, a method for manufacturing the nonvolatile resistance change element shown in the present embodiment will be described.

First, phosphorus (P) ions are implanted into a semiconductor substrate, for example, a silicon single crystal substrate at an acceleration voltage of 30 keV and a dose of 4 × 10 ¹³ cm ⁻² . Thereafter, activation annealing is performed on the silicon substrate to form an n-type silicon layer as the lower electrode 2.

  Next, a first amorphous silicon layer as the first variable resistance layer 3-1 and a second amorphous silicon layer as the second variable resistance layer 3-2 are deposited on the lower electrode 2 by CVD. That is, the first amorphous silicon layer 3-1 is formed on the lower electrode 2 at a film forming temperature of 400 ° C. using LP-CVD (Low Pressure Chemical Vapor Deposition). Subsequently, a second amorphous silicon layer 3-2 is formed on the first amorphous silicon layer 3-1, using a PE-CVD method at a film formation temperature of 250 ° C.

  The first amorphous silicon layer 3-1 includes the same element as the second amorphous silicon layer 3-2, but is different in density, number of dangling bonds, or number of defects from the second amorphous silicon layer 3-2. Even if the same amorphous silicon is used, the switching characteristics of the variable resistance element 30 are different if the film quality differs depending on the film forming conditions. For example, the first amorphous silicon layer 3-1 preferably has a higher density, a larger number of dangling bonds, and a larger number of defects than the second amorphous silicon layer 3-2.

[3] Characteristics of Nonvolatile Resistance Change Element FIG. 12A is a sectional view showing a low resistance state of the nonvolatile resistance change element 30 shown in FIG. 11, and shows a state where a filament has grown. FIG. 12B shows a high resistance state of the nonvolatile variable resistance element 30 and shows a state where the filament disappears.

  As shown in FIG. 12A, during the growth of the filament 3a, the first amorphous silicon layer 3-1 functions as a diffusion preventing layer for the filament 3a. As a result, a gap can be provided between the filament 3a and the lower electrode 2. Thereby, the effect similar to 2nd Embodiment can be acquired.

[Fourth Embodiment]
In the fourth embodiment, a memory cell array to which the nonvolatile resistance change element of the embodiment is applied will be described.

  FIG. 13A is a plan view showing the configuration of the memory cell array according to the fourth embodiment. FIGS. 13B and 13C are cross-sectional views showing the structure of the cross point portion of the memory cell array shown in FIG.

  As shown in FIG. 13A, the memory cell array 11 is formed with a lower wiring 12 and an upper wiring 13 that intersects the lower wiring 12. The non-volatile resistance change element 10 (or 20, 30) shown in the first to third embodiments is arranged at a cross point portion between the lower wiring 12 and the upper wiring 13. That is, as shown in FIG. 13B, the nonvolatile resistance change element 10 (or 20, 30) is disposed between the lower electrode 12 and the upper electrode 13.

  FIG. 13C is a cross-sectional view showing another structure of the cross-point portion shown in FIG. 13A, and the cross-point portion may have a structure as shown in FIG. . The resistance change layer 3 (or the diffusion prevention layer 4 and the resistance change layer 3) is formed on the lower wiring 12, and the upper electrode 1 is formed on the resistance change layer 3. Furthermore, an upper wiring 13 is formed on the upper electrode 1. In this structure, the lower wiring 12 includes an n-type semiconductor layer, and a nonvolatile resistance change element 40 is configured by the lower wiring 12, the resistance change layer 3 (or the diffusion prevention layer 4 and the resistance change layer 3), and the upper electrode 1. The The nonvolatile resistance change element 40 has the same characteristics as the nonvolatile resistance change element described in the first to third embodiments.

  When an n-type semiconductor layer is used for the lower wiring 12, the thickness of the n-type semiconductor layer is made sufficiently thicker than the thickness of the depletion layer formed in the n-type semiconductor layer so that the conductivity of the lower wiring 12 is increased. Need to keep. For example, the thickness of the lower wiring 12 is preferably 50 nm or more.

  Further, the lower wiring 12 may have a laminated structure. Specifically, the lower wiring 12 in contact with the resistance change layer 3 (or the diffusion prevention layer 4) has a three-layer structure of a lower layer, an intermediate layer, and an upper layer, an n-type semiconductor layer is used for the lower layer and the upper layer, and a metal is used for the intermediate layer. Layers may be used. In this case, the resistivity of the n-type semiconductor layer and the metal layer differ by several digits, and most of the current flows through the metal layer. For this reason, even if the n-type semiconductor layer is completely depleted, a current can flow.

  In FIG. 13B, the upper wiring 13 and the lower wiring 12 cross each other, and the lower electrode (n-type semiconductor) 2 and the upper electrode 1 are formed at the cross point portion of the upper wiring 13 and the lower wiring 12. If so, the variable resistance layer and the diffusion prevention layer may be flat films on the entire surface. However, it is desirable that the thickness of the variable resistance layer and the diffusion prevention layer is smaller than the distance between the upper wirings 13 and the distance between the lower wirings 12.

  In FIG. 13C, if the upper wiring 13 and the lower wiring (n-type semiconductor) 12 intersect, and the upper electrode 1 is formed at the cross-point portion of the upper wiring 13 and the lower wiring 12, the resistance change The layer and the diffusion prevention layer may be a flat film on the entire surface. However, it is desirable that the thickness of the variable resistance layer and the diffusion prevention layer is smaller than the distance between the upper wirings 13 and the distance between the lower wirings 12.

  FIG. 14 is a plan view showing a voltage setting method when writing a selected cell in the memory cell array shown in FIG.

  As shown in FIG. 14, control units 14 and 15 for applying a potential to the lower wiring 12 and the upper wiring 13 are provided around the memory cell array 11. When writing to the selected cell 10, the set voltage Vset is applied to the upper wiring 13 connected to the selected cell 10, and a voltage ½ of the set voltage Vset is applied to the other upper wiring. On the other hand, 0 V is applied to the lower wiring 12 connected to the selected cell 10, and a voltage ½ of the set voltage Vset is applied to the other lower wiring 12.

  As a result, the set voltage Vset is applied to the selected cell 10 and writing is performed. On the other hand, a voltage that is ½ of the set voltage Vset is applied to the half-selected cells specified by the unselected lines and the selected lines of the upper wiring 13 and the lower wiring 12, and writing is prohibited. Further, 0 V is applied to the non-selected cells designated by the non-selected lines of the upper wiring 13 and the lower wiring 12, and writing is prohibited.

  FIG. 15 is a plan view showing a voltage setting method at the time of reading the selected cell in the memory cell array shown in FIG.

  As shown in FIG. 15, when reading from the selected cell 10, a voltage that is ½ of the read voltage Vread is applied to the upper wiring 13 connected to the selected cell 10, and 0 V is applied to the other upper wiring. . Further, a voltage “−½” of the read voltage Vread is applied to the lower wiring 12 connected to the selected cell 10, and 0 V is applied to the other lower wiring.

  As a result, the read voltage Vread is applied to the selected cell 10 and reading is performed. On the other hand, a half voltage of the read voltage Vread is applied to the half-selected cells designated by the non-selected line and the selected line of the upper wiring 13 and the lower wiring 12, and reading is prohibited. Further, 0V is applied to the non-selected cells designated by the non-selected lines of the upper wiring 13 and the lower wiring 12, and reading is prohibited.

  FIG. 16 is a plan view showing a voltage setting method when erasing selected cells in the memory cell array shown in FIG.

  As shown in FIG. 16, when erasing the selected cell 10, a reset voltage Vreset is applied to the upper wiring 13 connected to the selected cell 10, and a voltage ½ of the reset voltage Vreset is applied to the other upper wiring. Apply. Further, 0 V is applied to the lower wiring 12 connected to the selected cell 10, and a voltage ½ of the reset voltage Vreset is applied to the other lower wiring.

  As a result, the reset voltage Vreset is applied to the selected cell 10 and erasing is performed. On the other hand, a half voltage of the reset voltage Vreset is applied to the half-selected cells designated by the unselected lines and the selected lines of the upper wiring 13 and the lower wiring 12, and erasure is prohibited. Further, 0 V is applied to the non-selected cells designated by the non-selected lines of the upper wiring 13 and the lower wiring 12, and erasing is prohibited.

  When writing to, reading from, and erasing the selected cell 10, a sneak current is generated via the half-selected cell and the non-selected cell due to the potential difference between the selected line and the non-selected line of the upper wiring 13 and the lower wiring 12. However, since the nonvolatile variable resistance element of this embodiment has a rectifying function as shown in the first to third embodiments, such a sneak current can be prevented.

  Further, the present embodiment relates to the technology of a single memory cell, and does not depend on the connection method of the memory cell, and the present embodiment can be applied to any circuit.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Upper electrode (1st electrode), 2 ... Lower electrode (2nd electrode), 3 ... Resistance change layer, 3a ... Filament, 3b ... Metal ion, 3-1 ... 1st resistance change layer, 3-2 ... 1st 2 resistance change layer, 4 ... diffusion prevention layer, 10 ... nonvolatile resistance change element, 11 ... memory cell array, 12 ... lower wiring, 13 ... upper wiring, 14, 15 ... control unit, 20, 30, 40 ... nonvolatile resistance Change element.

Claims (8)

A first wiring layer;
A second wiring layer disposed so as to intersect the first wiring layer and having an n-type semiconductor layer disposed at least on the first wiring layer side;
A first electrode including a metal element, disposed between the first wiring layer and the second wiring layer at an intersection where the first wiring layer and the second wiring layer intersect;
A variable resistance layer disposed between the first electrode and the second wiring layer and having a conductor formed of the metal element included in the first electrode;
A first layer made of an insulating material and disposed between the resistance change layer and the second wiring layer;
The nonvolatile resistance change element, wherein the conductor portion is spaced apart from the second wiring layer. A reset operation for transitioning from a low resistance state to a high resistance state is performed by a reset voltage applied between the first electrode and the second wiring layer,
When the voltage is swept from 0 V to the reset voltage between the first electrode and the second wiring layer,
(1) The maximum value of the current change amount between one-tenth of the reset voltage and the reset voltage is within one digit,
(2) The maximum value of the current change amount between 0 V and a half voltage of the reset voltage is the maximum current change amount between the half voltage of the reset voltage and the reset voltage. In smaller than value,
2. The nonvolatile resistance change element according to claim 1 , wherein either of (1) and (2) is satisfied. It said first layer, a nonvolatile variable resistance element according to claim 1 or 2, characterized in that it comprises a material having a high dielectric constant. Said first layer, a silicon oxide film, a silicon oxynitride film, and a nonvolatile variable resistance element according to claim 1 or 2, characterized in that it comprises either a silicon nitride film. Wherein the first layer comprises the same material as the variable resistance layer, the density in comparison with the variable resistance layer, the number of dangling bonds, according to claim 1 or 2, characterized in that one of the number of defects is different Non-volatile resistance change element. The impurity concentration of the n-type semiconductor in which the second wiring layer includes the, 1 × 10 ¹⁸ cm ^-3 nonvolatile variable resistance element according to claim 1 or 2, characterized in that less. Wherein the resistance variable layer, amorphous silicon, polycrystalline silicon, silicon oxide, and a nonvolatile variable resistance element according to any one of claims 1 to 6, characterized in that it comprises any of silicon nitride. The metal element contained in the first electrode, Ag, Co, Ni, Ti , Cu, nonvolatile variable resistance element according to any one of claims 1 to 7, characterized in that either Al.

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