JP5634330B2 - Motor drive control program, drive control method, and drive control apparatus - Google Patents

Description

  The present invention relates to a motor drive control program, a drive control method, and a drive control apparatus, and more particularly to a drive control program, a drive control method, and a drive control apparatus for a brushless DC motor that performs position detection regardless of position detection elements such as Hall elements.

  When rotating the motor, it is necessary to detect the rotational position of the rotor and change the state of the drive signal in accordance with the rotational position of the rotor. In view of this, a general motor includes position detection means such as a Hall element to detect the rotational position of the motor and to change the state of the drive signal. However, the Hall element has a problem that accurate position detection cannot be performed under a high temperature environment (for example, an environmental temperature of 125 ° C. or more). Thus, in recent years, sensorless brushless DC motors are often used in applications that require high-speed and high-torque rotation, such as HDDs (Hard Disk Drives), blowers, and pumps. In a sensorless brushless DC motor, the rotational position of the motor can be detected without using position detecting means such as a Hall element, and the rotation can be controlled based on the detection result. When a sensorless brushless DC motor is used, it has many advantages in terms of durability in a high temperature environment.

  In this sensorless brushless DC motor, the rotational position of the motor can be detected using the induced voltage generated in the non-energized phase, and the energization of the armature winding current to be energized can be switched according to the detection timing. An example of such a sensorless brushless DC motor is disclosed in Patent Documents 1 and 2.

  In the example shown in Patent Document 1, a sensorless brushless DC motor is driven using a three-phase drive signal (U phase, V phase, W phase). In the example shown in FIGS. 1 and 2 of Patent Document 1, the voltage of the U-phase drive signal (voltage generated at the terminal R) and the reference voltage Vdc / 2 are compared by a comparator, and the voltage at the terminal R is the reference voltage. A zero-cross detection point that intersects Vdc / 2 is detected. Then, the state of the PWM signal for driving the motor by the microcomputer is changed to the next state according to the timing at which the zero cross detection point is detected.

  Further, in Patent Document 2, the voltage level of the non-energized phase drive signal and the center tap voltage are compared by a comparator, the up / down counter is operated according to the comparison result, and the true level is determined according to the value of the up / down counter. A method for calculating the zero cross point is disclosed. And in patent document 2, the timing which changes the state of a drive signal from the calculated zero cross point is calculated.

Japanese Patent Laid-Open No. 9-247984 US Pat. No. 7,235,939

  However, in general, when a drive signal and a reference voltage are compared in a sensorless brushless DC motor, the non-energized phase drive signal is attenuated by an input stage voltage dividing resistor or the like after the non-energized phase drive signal is attenuated by a comparator or the like. The magnitude of the drive signal is determined. At this time, the input stage voltage dividing resistor has a voltage dividing ratio error. The comparator that determines the magnitude of the non-energized phase drive signal has an error factor such as an input offset voltage and an input noise voltage. Furthermore, since a large induced voltage cannot be expected at the time of starting the motor rotating at a low rotation speed, the comparison potential difference between the voltage of the armature winding and the reference voltage becomes small. For this reason, in the technique described in Patent Document 1, a sufficient SN ratio cannot be secured between the induced voltage and the noise voltage in the low rotation region of the motor, and the comparison result becomes unstable. As a result, in the technique described in Patent Document 1, when the induced voltage crosses the reference voltage, the position detection signal is generated indefinitely several times, and it is difficult to accurately measure the position detection interval in the low rotation speed region. It is.

  In FIGS. 3 and 4 of Patent Document 2, the problem of an error caused by input noise to the comparator is obvious. However, in Patent Document 2, this error is included in the calculation result of the zero cross point by masking this noise. The effect of is not reflected. However, in Patent Document 2, as is clear from FIGS. 3, 4, 8, and related descriptions, there is a problem that the zero cross point cannot be calculated unless the cycle for changing the state of the drive signal is determined in advance. is there. That is, Patent Document 2 has a problem that it cannot cope with a change in the rotational speed of the motor. For example, the technique of Patent Document 2 cannot be used in applications where the rotational speed of the motor changes, such as when the rotational speed of the motor is controlled by changing the duty ratio of the PWM signal. Further, the motor must start rotating from a state where the rotational speed is zero, but the technique of Patent Document 2 cannot be used before the rotational speed reaches the maximum rotational speed. For this reason, Patent Document 2 has a problem that the controllability of the motor deteriorates particularly when the motor is rotating at a rotational speed other than the maximum rotational speed.

  Moreover, in patent document 1, the timing which changes the state of a PWM signal to the next state is switched according to the timing when the zero cross detection point was detected. Therefore, in patent document 1, when the zero cross detection point shifts, there exists a problem that the controllability of a motor deteriorates. In order to avoid the above problem, the comparator is generally provided with hysteresis. However, when the comparison result is stabilized by providing the comparator with a dead zone due to hysteresis, the voltage at the terminal R becomes equal to the reference voltage Vdc / The zero cross detection point intersecting with 2 is different from the actual zero cross detection point, and the controllability of the motor is deteriorated. When the induced voltage is within the hysteresis range, zero-cross detection cannot be performed, and thus a limit occurs in the low rotation speed. In other words, the technique described in Patent Document 1 cannot solve the problem that the controllability deteriorates when the sensorless brushless DC motor is controlled at a low rotational speed.

  One aspect of a motor drive control program according to the present invention includes an arithmetic core that changes the state of a PWM signal generated according to the rotational position of the motor, and an output interface that outputs the PWM signal to the motor via a driver circuit. A comparator that compares a comparison target detection signal selected from the three-phase drive signal generated by the driver circuit based on the PWM signal with a center tap voltage indicating a midpoint voltage of the three-phase drive signal. The motor drive control program executed by the arithmetic core in the above-described embodiment, the comparator integral value is increased or decreased based on the value of the output signal of the comparator, and the motor is activated in response to the comparator integral value reaching the initial count value. The rotational position of the PWM signal is detected and the state of the PWM signal is determined according to the detection result. To transition to the next state.

  One aspect of a motor drive control method according to the present invention includes a PWM signal generation circuit that changes the state of a PWM signal generated according to the rotational position of the motor, and an output that outputs the PWM signal to the motor via a driver circuit. An interface and a comparator for comparing a one-phase drive signal selected from the three-phase drive signal generated by the driver based on the PWM signal and a center tap voltage indicating a midpoint voltage of the three-phase drive signal; A motor drive control method using a motor drive device having a comparator integrated value is increased or decreased based on a value of an output signal of the comparator, and the motor is controlled in response to the comparator integrated value reaching a count initial value. It detects that the rotational position has changed, and changes the state of the PWM signal to the next state according to the detection result.

  One aspect of a motor drive control device according to the present invention includes a PWM signal generation circuit that transitions the state of a PWM signal generated according to the rotational position of the motor, and an output that outputs the PWM signal to the motor via a driver circuit. An interface and a comparator for comparing a one-phase drive signal selected from the three-phase drive signal generated by the driver based on the PWM signal and a center tap voltage indicating a midpoint voltage of the three-phase drive signal; The PWM signal generation circuit increases or decreases the comparator integral value based on the value of the output signal of the comparator, and the rotational position of the motor has changed in response to the comparator integral value reaching the initial count value. And the state of the PWM signal is changed to the next state according to the detection result.

  In the motor drive control program, the drive control method, and the drive control device according to the present invention, the rotational position of the motor is detected based on the comparator integrated value obtained by integrating the output result of the comparator to which the comparison target detection signal and the center tap voltage are input. To do. As a result, even when the comparator has an input offset, or even when measures against noise (for example, use of a comparator having hysteresis characteristics) are not taken, the characteristics of these comparators are given to the rotation detection timing of the motor. The influence can be suppressed.

  According to the motor drive control program, the drive control method, and the drive control apparatus according to the present invention, the controllability when the motor is controlled at a low rotational speed can be improved.

1 is a block diagram of a motor drive control device according to a first embodiment; FIG. 2 is a more detailed block diagram of the motor drive control device according to the first exemplary embodiment. 3 is a flowchart illustrating an operation procedure of the motor drive control device according to the first embodiment; It is a detailed flowchart of the variable initialization process of the flowchart shown in FIG. It is a detailed flowchart of the motor drive operation of the flowchart shown in FIG. It is a detailed flowchart of the rotation control process of the flowchart shown in FIG. It is a detailed flowchart of the constant current control process of the flowchart shown in FIG. It is a detailed flowchart of the flyback filter process of the flowchart shown in FIG. It is a detailed flowchart of the rotor position detection process of the flowchart shown in FIG. 10 is a detailed flowchart of the state control process of the flowchart shown in FIG. 9. It is a detailed flowchart of the constant rotational speed control process of the flowchart shown in FIG. It is a detailed flowchart of the state update process of the flowchart shown in FIG. FIG. 11 is a detailed flowchart of flyback adaptive filter update processing of the flowchart shown in FIG. 10. 7 is a detailed flowchart of a regulation loop arbitration process of the flowchart shown in FIG. 6. FIG. 7 is a detailed flowchart of PWM premodulation processing of the flowchart shown in FIG. 6. 3 is a timing chart illustrating an operation at the time of starting motor control of the motor drive control device according to the first embodiment; FIG. 6 is a block diagram of a driver circuit for explaining an operation of an alternate PWM method in a state 0 of the motor drive control device according to the first exemplary embodiment; FIG. 3 is a block diagram of a driver circuit for explaining an operation of an alternate PWM method in a state 1 of the motor drive control device according to the first exemplary embodiment; FIG. 5 is a block diagram of a driver circuit for explaining an operation of an alternate PWM method in a state 2 of the motor drive control device according to the first exemplary embodiment; FIG. 7 is a block diagram of a driver circuit for explaining an operation of an alternate PWM method in a state 3 of the motor drive control device according to the first exemplary embodiment; FIG. 6 is a block diagram of a driver circuit for explaining an operation of an alternate PWM method in a state 4 of the motor drive control device according to the first exemplary embodiment; FIG. 6 is a block diagram of a driver circuit for explaining an operation of an alternate PWM method in a state 5 of the motor drive control device according to the first exemplary embodiment; 4 is a graph for comparing input / output characteristics in the motor drive control device according to the first embodiment with and without a synchronous rectification operation. 6 is a timing chart for explaining a drive signal and a center tap voltage in a state 0 when a PWM signal having a duty ratio of 50% is generated in the motor drive control apparatus according to the first embodiment; 6 is a timing chart for explaining the operation of the motor drive control device in state 0 when a PWM signal with a duty ratio of 50% is generated in the motor drive control device according to the first embodiment; 6 is a timing chart for explaining a drive signal and a center tap voltage in states 0 to 5 when a PWM signal having a duty ratio of 50% is generated in the motor drive control apparatus according to the first embodiment; 6 is a timing chart for explaining the operation of the motor drive control device in state 0 to state 5 when a PWM signal with a duty ratio of 50% is generated in the motor drive control device according to the first embodiment; 6 is a timing chart for explaining a drive signal and a center tap voltage in states 0 to 5 when a PWM signal having a duty ratio of 100% is generated in the motor drive control apparatus according to the first embodiment; 6 is a timing chart for explaining the operation of the motor drive control device in state 0 to state 5 when a PWM signal with a duty ratio of 100% is generated in the motor drive control device according to the first embodiment; 6 is a timing chart for explaining a PWM signal generated when the duty ratio of the PWM signal determined in the motor drive control device according to the first embodiment exceeds the maximum duty ratio; 6 is a timing chart for explaining a PWM signal generated when the duty ratio of the PWM signal determined in the motor drive control device according to the first embodiment falls below a minimum duty ratio. 6 is a timing chart for explaining a PWM signal generated when the duty ratio of the PWM signal determined in the motor drive control apparatus according to the first embodiment is equal to or less than the maximum duty ratio and equal to or greater than the minimum duty ratio. FIG. 10 is a block diagram of a driver circuit for explaining an operation of an alternate PWM method in a state 0 of the motor drive control device according to the second exemplary embodiment; FIG. 6 is a block diagram of a driver circuit for explaining an operation of an alternate PWM method in a state 1 of a motor drive control device according to a second exemplary embodiment; FIG. 10 is a block diagram of a driver circuit for explaining an operation of an alternate PWM method in a state 2 of the motor drive control device according to the second exemplary embodiment; FIG. 10 is a block diagram of a driver circuit for explaining an operation of an alternate PWM method in a state 3 of the motor drive control device according to the second exemplary embodiment; FIG. 10 is a block diagram of a driver circuit for explaining an operation of an alternate PWM method in a state 4 of the motor drive control device according to the second exemplary embodiment; FIG. 10 is a block diagram of a driver circuit for explaining an operation of an alternate PWM method in a state 5 of the motor drive control device according to the second exemplary embodiment; 7 is a graph comparing the range of controllable motor rotation speeds with and without a regenerative braking operation in the motor drive control device according to the second embodiment. 10 is a timing chart for explaining a state 0 drive signal and a center tap voltage when a PWM signal having a duty ratio of 50% is generated in the motor drive control apparatus according to the second embodiment; 10 is a timing chart for explaining the operation of the drive signal and the center tap voltage in the state 0 to the state 5 when a PWM signal with a duty ratio of 50% is generated in the motor drive control device according to the second embodiment.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. First, FIG. 1 shows a block diagram of a motor drive control device 1 according to the first embodiment. As shown in FIG. 1, the motor drive control device 1 is a microcomputer. That is, the motor drive control device 1 according to the first embodiment realizes the motor drive operation by the motor drive control program executed on the microcomputer.

  In the block diagram shown in FIG. 1, the pre-driver circuit 2, the driver circuit 3, and the motor 4 are shown. The pre-driver circuit 2 performs level conversion of the PWM signal generated by the motor drive control device 1. The driver circuit 3 generates a drive signal of three phases (for example, a U phase, a V phase, and a W phase) according to the PWM signal input via the pre-driver circuit 2, and drives the motor 4 by the drive signal. . The motor 4 is a control target, and outputs a midpoint voltage (center tap voltage CT) of a three-phase drive signal. This center tap voltage may be taken out from the center tap voltage take-out terminal of the motor, or an artificial center tap voltage (artificially synthesized using a resistor network to which a three-phase drive signal is inputted ( Artificial center tap voltage). The center tap voltage used in the following description indicates the midpoint voltage of the three-phase drive signal regardless of the generation method.

  As shown in FIG. 1, the motor drive control device 1 includes, as hardware, an arithmetic core 10, a program memory 11, a RAM (Random Access Memory) 12, a GPIO (General Purpose Input / Output) 13, a selector 14, a comparator 15, An analog-digital converter 16 and a timer 17 are provided. In the motor drive control device 1, these blocks are connected to each other via a bus.

  The program memory 11 stores a motor drive control program. The program memory 11 includes a ROM (Read Only Memory), a flash memory, and the like. The arithmetic core 10 reads the motor drive control program from the program memory 11 and executes it. And the arithmetic core 10 produces | generates a PWM signal according to a motor drive control program. In addition, the arithmetic core 10 detects the rotation of the motor based on the output of the comparator 15 and changes the state of the PWM signal according to the detection result of the motor. Details of the operation of the arithmetic core 10 will be described later. The RAM 12 is a storage device that stores data used when the arithmetic core 10 executes a motor drive control program.

  The GPIO 13 is a general-purpose input / output device. The motor drive control device 1 receives a speed control signal and a PWM duty control signal from another circuit (not shown) via GPIO. The temperature control signal is generated according to the temperature of the device in which the motor drive control device 1 is incorporated. For example, when the motor controls the rotation of the fan, the PWM duty control signal instructs the motor drive control device 1 with a rotation speed instruction value indicating the rotation speed of the fan. Values indicated by the temperature control signal and the PWM duty control signal are given to the arithmetic core 10 via the GPIO 13. Further, the GPIO 13 outputs a notification signal having a frequency proportional to the rotation speed of the motor 4 (hereinafter referred to as a rotation speed notification signal) to another circuit (not shown). For example, the rotation speed notification signal is generated by the arithmetic core 10 and output via the GPIO 13. Further, in the motor drive control device 1, the PWM signal generated in the arithmetic core 10 is output to the pre-driver circuit 2 via the GPIO 13.

  The selector 14 outputs the non-driving phase selected from the three-phase signal as the comparison target detection signal SP based on the instruction from the arithmetic core 10. More specifically, when a sensorless brushless DC motor is used as the motor 4, the selector 14 selects a non-energized phase as the comparison target detection signal SP.

  The comparator 15 compares the comparison target detection signal SP with the center tap voltage, and sets the output signal to a logic level of either high level or low level. In the present embodiment, the comparator 15 sets the output signal to a high level when the center tap voltage CT is higher than the comparison target detection signal SP, and when the center tap voltage CT is lower than the comparison target detection signal SP. Sets the output signal to low level.

  In the example shown in FIG. 1, a current detection resistor Ri and a low-pass filter are provided on the source side of the driver circuit 3. The current detection resistor Ri converts the drive current of the motor 4 flowing through the driver circuit 3 into a voltage. The analog-digital converter 16 is a circuit that converts an analog value into a digital value. In the motor drive control device 1 according to the first embodiment, the analog / digital converter 16 converts the voltage value generated by the current detection resistor Ri into a digital value, and obtains a digital value corresponding to the magnitude of the drive current. The low-pass filter removes high-frequency noise of the voltage value generated by the current detection resistor R1, but is not shown in order to simplify the drawing.

  The timer 17 counts the operation clock of the microcomputer that operates as the motor drive control device 1, and outputs an interrupt request according to the count value. The interrupt request is given to the arithmetic core 10. The arithmetic core 10 performs a predefined operation according to the type of interrupt request that is input. In the motor drive control device 1 according to the first embodiment, the timer 17 is set with the first set value and the second set value. The timer 17 outputs a first interrupt signal in response to the count value reaching the first set value, and the second interrupt signal in response to the count value reaching the second set value. Is output. More specifically, in the motor drive control device 1, a value smaller than the on-time of the PWM signal (period during which the PWM signal is at a high level) is set as the first set value, and the second set value is A value corresponding to one period of the PWM signal is set. The first set value is used to specify the timing for switching the PWM signal from the on state to the off state, and is set to a value slightly smaller than the on time of the PWM signal. In the following description, the first interrupt request is referred to as a BEMF (back EMF) timer interrupt, and the second interrupt request is referred to as a periodic timer interrupt.

  In the motor drive control device 1 according to the first embodiment, the computation core 10 performs duty control and state control of a PWM signal that controls the drive of the motor by executing a motor drive control program. Therefore, FIG. 2 shows a block diagram of the motor drive control device 1 when the function realized by the arithmetic core 10 executing the motor drive control program is a functional block of the arithmetic core 10. The same components as those shown in the block diagram of FIG. 1 are denoted by the same reference numerals as those in FIG.

  As shown in FIG. 2, by executing the motor drive control program, the arithmetic core 10 includes a PWM demodulator 21, a PWM modulator 22, a constant current drive control unit 23, a rotor position detection unit 24, a rotation control unit 25, The rotation speed control unit 26 and the PWM duty control unit 27 are realized as functional blocks. In the motor drive control device 1 shown in FIG. 2, description of blocks that perform general processing such as initialization of set values and variables is omitted. The motor drive control device 1 performs a PWM pulse count process, and performs various processes based on the PWM pulse count value. However, the block for counting the PWM pulse count value is not shown in FIG. . The block functions omitted in this way are realized by general arithmetic processing of a microcomputer.

  The PWM demodulator 21 performs a demodulation process on the PWM signal. More specifically, the PWM demodulator 21 samples the output signal CMP_OUT of the comparator 15 and the drive current for driving the motor in response to the input of the BEMF timer interrupt. The value of the drive current is sampled in the constant current drive control unit 23 based on the PWM demodulator 21 giving a sampling instruction to the constant current drive control unit 23. Further, the PWM demodulator 21 updates the value of the first set value of the timer 17 in response to the input of the periodic timer interrupt. Then, the PWM demodulator 21 instructs the PWM modulator 22 to start the process in response to the completion of the output modulation process.

  The PWM modulator 22 switches the logic level of the PWM signal based on the processing start instruction from the PWM demodulator 21. At this time, the PWM modulator 22 determines whether to set the plurality of PWM signals to the high level or the low level based on the instruction value of the rotation control unit 25. The PWM signal output from the PWM modulator 22 is output to the pre-driver circuit 2 via the GPIO 13.

  The constant current drive control unit 23 performs a constant current drive control process. In the constant current drive control process, a feedback control value for driving the motor 4 at a constant current is generated.

  The rotor position detection unit 24 has a comparator integral value. The rotor position detection unit 24 performs a comparator integral value calculation process, a flyback filter process, a flyback adaptive filter update process, a rotor position detection process, and a state table update process. In the comparator integral value calculation process, the output values of the comparator 15 are integrated based on the output signal CMP_OUT of the comparator 15 sampled by the PWM demodulator 21. In the flyback filter process, the flyback pulse generated in the non-energized phase drive signal is filtered. During the application of this flyback filter, the comparator integral value is simply increased or decreased regardless of the output signal CMP_OUT of the comparator 15. In the flyback adaptive filter update process, the conditions of the flyback filter are updated. In the rotor position detection process, the rotor position detection process is performed, and the transition timing of the state of the PWM signal is instructed. In the state table update processing, update processing of the off-state table and the on-state table for determining the state of the PWM signal is performed.

  The rotation control unit 25 performs state control processing. More specifically, in the state control process, a rotation speed detection process, a stacking detection process, and a state update process are performed. In the rotation speed detection process, a process for detecting the rotation speed of the motor 4 is performed. In the stacking detection process, the rotor stack of the motor 4 is detected. In the state update process, the next state of the PWM signal state is determined, and whether or not the PWM signal is to be changed to the next state is determined.

  The rotation speed control unit 26 performs a constant rotation control process. In the constant rotation control process, an error between the current rotation speed of the motor 4 and a rotation speed instruction value given from the outside is calculated, and a feedback control value for controlling the motor 4 to a rotation speed according to the rotation speed instruction value. Is generated. The rotation speed instruction value includes a value based on a speed control signal derived from temperature control in addition to a value derived from a PWM duty control signal.

  The PWM duty control unit performs a regulation loop arbitration process and a PWM premodulation process. In the regulation loop arbitration process, a feedback control value generated by the constant current drive control unit 23 and a feedback control value generated by the rotation speed control unit 26 are used as feedback control values for determining the duty ratio of the next cycle of the PWM signal. Arbitration processing is performed for which one to use. In the PWM pre-modulation process, the on-time value of the next period of the PWM signal is determined based on the feedback control value determined in the regulation loop arbitration process. Further, in the PWM pre-modulation process, the determined on-time value is given to the PWM demodulator 21.

  Next, motor drive control using functions realized by the motor drive control program will be described in more detail. 3 to 15 are flowcharts showing the operation procedure of the motor drive control device 1. FIG. The operation of the motor drive control device 1 will be described in further detail with reference to FIGS.

  In FIG. 3, the flowchart which shows the whole operation | movement of the motor drive control apparatus 1 was shown. As shown in FIG. 3, when the main routine starts, the motor drive control program first performs variable initialization processing (step S1). Subsequently, the motor drive control program samples the voltage value of the power supply voltage supplied to the microcomputer 1 using the analog-digital converter 16 (step S2). Subsequently, the motor drive control program determines whether or not the voltage value of the sampled power supply voltage is larger than the minimum starting voltage (step S3). If it is determined in step S3 that the power supply voltage is equal to or lower than the minimum startup voltage, the process returns to the variable initialization process in step S1. On the other hand, when it is determined that the power supply voltage is higher than the minimum starting voltage, the timer interrupt to the arithmetic core 10 is permitted (step S4). Note that, as a power supply voltage for determining whether or not to permit activation, a power supply voltage having a high voltage value among the power supply voltage applied to the driver circuit 3 and the power supply voltage applied to the microcomputer 1 is used. In the present embodiment, it is preferable to monitor the power supply voltage of the driver circuit 3 in order to generate the power supply of the microcomputer 1 from the power supply of the driver circuit 3. In this case, the analog-to-digital converter 16 measures the power supply voltage of the driver circuit 3.

  Then, the motor drive control program waits for the occurrence of a timer interrupt, and performs motor drive operation processing due to the occurrence of the timer interrupt (steps S5 and S6). The motor drive control program determines whether or not the stack rotor detection flag STC_DET indicating the stack state of the rotor is TRUE at the time when the motor drive operation process is completed (step S7). If it is determined in step S7 that the stack rotor detection flag STC_DET is FALSE, that is, if it is determined that the motor is rotating, the generation of a timer interrupt is awaited again. On the other hand, if it is determined in step S7 that the stack rotor detection flag STC_DET is TRUE, that is, if it is determined that the motor is not rotating, the process returns to the variable initialization process in step S1.

  Next, the variable initialization process in step S1 will be described in detail. FIG. 4 is a flowchart showing a detailed operation procedure of the variable initialization process. As shown in FIG. 4, in the variable initialization process, first, a timer initialization process is performed (step S10). More specifically, in step S10, a first set value and a second set value for designating the length of one cycle of the PWM signal are stored in the register of the timer 17 based on the on-time period of the PWM signal.

  Next, the moving average state PWM pulse number ST_PWM_PLS_AVE and the PWM pulse number PWM_PLS [0] to PWM_LPLS [5] are set as the maximum pulse count number. The moving average state PWM pulse number ST_PWM_PLS_AVE indicates the average PWM pulse number of each state included in the six states when six states are used to rotate the motor once. The PWM pulse numbers PWM_PLS [0] to PWM_LPLS [5] are the number of pulses of the PWM signal that define the length of each period of the states 0 to 5. The maximum pulse count is, for example, the number of pulses of the PWM signal during one state when the motor 4 is operated at the minimum rotation speed, and is a preset value.

  Next, the value of the number FB_MASK of flyback pulse continuation PWM pulses at start-up is set (step S12). In step S12, a value of 1/6 of the number of 6-state PWM pulses corresponding to the maximum rotation speed of the motor 4 is set in the number of flyback pulse continuous PWM pulses FB_MASK. When the motor 4 starts to rotate in a no-load state, it may start to rotate at a high rotational speed, but by setting the flyback pulse continuous PWM pulse number FB_MASK at startup to such a value, Even if the motor 4 starts to rotate in a no-load state, it is possible to prevent the motor 4 from rotating in the direction opposite to the intended rotational direction due to the rotational position of the rotor being shifted from the state of the drive signal.

  Next, the constant current control instruction value CNST_CRNT_SET is set to a value one third of the maximum current value MAX_CRNT (step S13). The maximum current value MAX_CRNT is a value corresponding to the maximum current per predetermined time allowed for the transistors constituting the driver circuit 3. Normally, when generating a three-phase drive signal, the driver circuit 3 has three sets of drive stage circuits. Therefore, in order to rotate the motor once, the period in which the three sets of driving stage circuits are in a conductive state is one third of the time required to rotate the motor once. However, at the start of rotation, the motor is in a stopped state, and the time during which the drive stage circuit is in a conductive state is longer than when the motor is rotating. Therefore, when the constant current control instruction value CNST_CRNT_SET is set to the maximum current value MAX_CRNT at the start of rotation, the current flowing through each of the drive stage circuits may exceed the maximum current. Therefore, the constant current control instruction value CNST_CRNT_SET is set to a value one third of the maximum current value MAX_CRNT. As a result, even if the length of one state of the PWM signal becomes longer, it is possible to prevent a current exceeding the maximum current from flowing through the transistors constituting the drive stage circuit.

  Next, the stack rotor detection flag is set to FALSE (step S14). This is because the motor is in a stopped state before the motor starts rotating, so that the state is determined.

  Next, the rotational speed error integrated value ROT_ERR_INTG and the current error integrated value CRNT_ERR_INTG are initialized to a count initial value (for example, zero) (step S15). The rotation speed error integrated value ROT_ERR_INTG and the current error integrated value CRNT_ERR_INTG are undefined when initialization is not performed, and the motor drive control apparatus 1 may not operate normally when values before initialization are used. is there. Therefore, the value of the rotation speed error integrated value ROT_ERR_INTG and the current error integrated value CRNT_ERR_INTG at the start of the operation of the motor drive control device 1 is determined by setting the value to zero by this initialization process.

  Next, details of the motor drive operation process shown in step S6 of FIG. 3 will be described. FIG. 5 is a flowchart showing the operation procedure of the motor drive operation process. As shown in FIG. 5, the motor drive operation process includes a PWM demodulation process (step S20), a PWM modulation process (step S30), and a PWM signal setting process (step S40).

  The PWM demodulation process is a process executed by the PWM demodulator 21 of FIG. The PWM modulation process is a process executed by the PWM modulator 22 in FIG.

  In the PWM demodulation process, first, it is determined whether or not the input interrupt is a BEMF timer interrupt (step S21). If it is determined that the interrupt is a BEMF timer interrupt, the BEMF timer interrupt is cleared (step S22). Next, the output value of the output signal CMP_OUT of the comparator 15 is sampled. Next, the current value of the motor drive current is sampled from the analog-digital converter 16. The current value of the drive current is used by the constant current drive control unit 23. Next, upon completion of the PWM demodulation process, the PWM modulation process is started.

  In the PWM modulation process in which the interrupt is started in response to the BEMF timer interrupt, first, it is determined whether or not the on-time PWM_ON of the PWM signal is smaller than the cycle PWM_TRM of the PWM signal (step S31). If it is determined that the on-time PWM_ON of the PWM signal is smaller than the period PWM_TRM of the PWM signal, an off-state PWM signal is output to the GPIO 13 (step S32). In the motor drive control program, six PWM signals are generated when the motor 4 is a three-phase drive method. Which of the six PWM signals is set to the off state or the on state? Is determined according to the description in the state table. In the state table, designation of a PWM signal for switching between an on state and an off state for each state of the PWM signal, and designation of a high side off state or a low side off state as the off state are defined.

  Thereafter, the off-state side of the PWM signal is inverted (step S33). In step S33, the state table indicating the signal pattern of the PWM signal is switched between a high-side off state and a low-side off state. For example, when the off-state of the state table indicates high-side off in the current cycle of the PWM signal, the state table is updated so that the off-state of the state table indicates low-side off in the next cycle of the PWM signal. This step S33 is an operation of the alternate PWM method in which the motor drive control device 1 according to the first embodiment alternately switches between the high-side off state and the low-side off state as the off-state period of the PWM signal every PWM signal cycle. This is a process performed for this purpose. On the other hand, if it is determined in step S31 that the on-time PWM_ON of the PWM signal is equal to or longer than the period PWM_TRM of the PWM signal, the PWM signal is maintained in the on state (step S34).

  That is, when the PWM signal on-time PWM_ON is smaller than one cycle of the PWM signal, the motor drive control device 1 uses the BEMF timer interrupt as a trigger to sample the output signal CMP_OUT of the comparator 15 and the on-state of the PWM signal. Switch from off to off. Further, when the on-time PWM_ON is equal to or longer than one period of the PWM signal, the motor drive control device 1 samples the output signal CMP_OUT of the comparator 15 triggered by the occurrence of the BEMF timer interrupt. Does not switch to off-state.

  When the process of step S33 or step S34 is completed, the motor drive control program ends the motor drive control process.

  On the other hand, if it is determined in step S21 that the interrupt is not a BEMF timer interrupt, that is, if the interrupt is a periodic timer interrupt, the periodic timer interrupt is cleared (step S25). Next, the on-time PWM_ON of the PWM signal in the next cycle is updated with the value of the on-time PWM_ON of the PWM signal calculated in the current cycle of the PWM signal. Next, in response to the processing result of the PWM demodulation process, the PWM modulation process is started.

  In the PWM modulation process in which the interrupt is started in response to the BEMF timer interrupt, it is first determined whether or not the on-time PWM_ON of the PWM signal is greater than zero (step S35). That is, in step S35, it is determined whether or not the PWM signal to be generated has an on period. If it is determined in step S35 that the on-time PWM_ON of the PWM signal is greater than zero, the on-state PWM signal is output to the GPIO 13 (step S36). Next, the BEMF timer interrupt is permitted (step S37). On the other hand, if it is determined in step S35 that the on-time PWM_ON of the PWM signal is equal to or less than zero, the PWM signal maintaining the off state is output to the GPIO 13 (step S38). Thereafter, the off-state inversion of the PWM signal is performed similarly to step S33 (step S39). This off-state inversion processing is an alternate PWM method in which the motor drive control device 1 according to the first embodiment alternately switches between the high-side off-state and the low-side off-state as the off-state period of the PWM signal every PWM signal cycle. This is a process performed for the operation.

  When the process of step S37 or step S39 is completed, the motor drive control program performs a PWM signal setting process (step S40). When the PWM signal setting process is completed, the motor drive control process ends.

  Next, the PWM signal setting process in step S40 will be described. In the PWM signal setting process, a process for calculating the on-time PWM_ON of the PWM signal in the next cycle and a process for updating the state of the PWM signal are performed. FIG. 6 shows a detailed flowchart of the PWM signal setting process for performing these processes.

  As shown in FIG. 6, in the PWM signal setting process, first, the count-up process of the number of state PWM pulses ST_PWM_PLS is performed (step S41). This state PWM pulse number ST_PWM_PLS is a value indicating an elapsed time after the PWM signal transits to the current state. In the motor drive control program according to the first embodiment, the elapsed time of each state is calculated by counting the number of pulses of the PWM signal. The count-up process of the number of state PWM pulses ST_PWM_PLS is a process performed by the rotor position detection unit 24 in FIG.

  Next, the motor drive control program updates the value of the rotation speed instruction value ROT_SET (step S42). The rotation speed instruction value ROT_SET is given by, for example, a PWM duty control signal given from the outside of the motor drive control device 1. The update process of the rotation speed instruction value ROT_SET is a process performed by the rotation speed control unit 26 in FIG.

  Next, the motor drive control program performs a constant current control process (step S43). This constant current control process is a process for generating a feedback control value when the motor 4 is driven at a constant current. Details of the constant current control process will be described later. The constant current control process is a process performed by the constant current drive control unit 23 in FIG.

  Next, the motor drive control program compares the number of state PWM pulses PWM_PLS with the number of flyback pulse continued PWM pulses FB_MASK (step S44). When the state PWM pulse number PWM_PLS is smaller than the flyback pulse continuation PWM pulse number FB_MASK, the flyback pulse filter process is performed (step S45). On the other hand, when the state PWM pulse number PWM_PLS is equal to or greater than the flyback pulse continuous PWM pulse number FB_MASK, the rotor position detection process (step S49) is performed. Note that state control processing is also performed in the rotor position detection processing. The processing of steps S44 and S45 is performed by the rotor position detection unit 24 of FIG. 2, and the processing of step S49 is performed by the rotor position detection unit 24, the rotation control unit 25, and the rotation speed control unit 26. Details of the flyback filter process and the rotor position detection process will be described later.

  In a three-phase drive motor, a flyback pulse is generated in the non-energized phase drive signal immediately after the state transition of the PWM signal. During the period in which the fluff back pulse is generated, the voltage relationship between the center tap voltage CT and the comparison target detection signal SP (non-energized phase drive signal) has reached the timing when the rotor position switches the PWM signal state to the next state. In this case, the relationship between the comparison target detection signal SP and the center tap voltage CT is the same. Therefore, in the motor drive control program according to the first embodiment, the comparator integral value CMP_INTG is counted up or down regardless of the value of the output signal CMP_OUT of the comparator for a predetermined period after the state of the PWM signal transitions. In the first embodiment, this predetermined period is set in advance as a period of a predetermined ratio of one period during which the state of the PWM signal is maintained. In the example illustrated in FIG. 6, a variable of the number FB_MASK of flyback pulse continuous PWM pulses is provided as a variable that defines the predetermined period. Then, as the flyback pulse continuous PWM pulse number FB_MASK, a value of 1/6 of the 6-state PWM pulse number corresponding to the maximum rotation speed is set when the motor 4 is started, and after the motor 4 starts rotating, A quarter of the moving average state PWM pulse number ST_PWM_PLS_AVE is set.

  Next, when the process of step S45 or step S49 is completed, the motor drive control program performs a regulation loop arbitration process (step S46). In the regulation loop arbitration process, any one of the control feedback value calculated in the constant current control process (step S43) and the control feedback value generated based on the rotation speed of the motor 4 in the state control process in step S49. Based on the above, arbitration processing is performed to determine whether to set the duty ratio of the PWM signal of the next cycle. The regulation loop arbitration process is performed by the PWM duty control unit in FIG. Details of the regulation loop arbitration process will be described later.

  Next, the motor drive control program performs PWM pre-modulation processing (step S47). In the PWM pre-modulation process, the duty ratio of the PWM signal of the next period is determined based on the control feedback value determined in the regulation loop arbitration process, and the on-time PWM_ON of the PWM signal is determined based on the duty ratio. This PWM pre-modulation process is performed by the PWM duty control unit in FIG. Details of the PWM pre-modulation process will be described later.

  Next, the motor drive control program sets an on state and an off state of the PWM signal in the next cycle (step S48). The process of step S48 is a process of reading the PWM signal pattern of the state table corresponding to the state count value ST_CNT of the next cycle of the PWM signal among the 6 state tables. The pattern of the PWM signal is, for example, a driver circuit 3 that gives a PWM signal to the drive stage circuit of the driver circuit 3 that generates a drive signal to be a conductive phase in the updated state, and generates a drive signal of a phase to be a non-conductive phase. In this drive stage circuit, the PWM signal pattern for stopping the supply of the PWM signal is instructed. Further, the off-state set in step S48 is the off-state of the side selected in steps S33 and S39.

  Here, the constant current control process in step S43 will be described in more detail. FIG. 7 is a flowchart showing the detailed operation procedure of the constant current control process. As shown in FIG. 7, in the constant current control process, first, a current error CRNT_ERR between the constant current control instruction value CNST_CRNT_SET and the motor drive current MI sampled in step S24 of FIG. 5 is calculated (step S50). Next, the current error integrated value CRNT_ERR_INTG is added by updating the current error CRNT_ERR calculated in step S50 and the current error integrated value CRNT_ERR_INTG (step S51). Next, the current error integrated value CRNT_ERR_INTG calculated in step S51 is clamped (step S52). In the motor drive control program according to the first embodiment, the maximum value and the minimum value of CRNT_ERR_INTG are defined in advance. In the clamping process in step S52, the value of the rotational speed error integrated value ROT_ERR_INTG is a value between a predetermined maximum value and a minimum value, and is converted to a value that can be expressed by a predetermined bit width. The current error integrated value CRNT_ERR_INTG is a value corresponding to the control feedback value generated by the constant current drive control unit 23.

  Next, details of the flyback filter process in step S45 will be described. FIG. 8 is a flowchart showing the detailed operation procedure of the flyback filter process. As shown in FIG. 8, in the flyback filter process, first, the motor drive control program determines whether or not the rotation direction instruction flag FWD is TRUE (step S60). The rotation direction instruction flag FWD is a value for instructing whether to control the motor 4 in the forward rotation direction or in the reverse rotation direction, and is a value set by an external input signal. When the rotation direction instruction flag FWAD is TRUE, the motor drive control device 1 controls the motor 4 in the normal rotation direction, and when the rotation direction instruction flag FWAD is FALSE, the motor drive control device 1 sets the motor 4 in the reverse rotation direction. To control. In step S60, when it is determined that the rotation direction instruction flag FWD instructs to control the motor 4 in the normal rotation direction, the motor drive control program refers to the state count value ST_CNT and the value is an odd number. Or even number (step S61). This state count value ST_CNT is a value indicating which control state the PWM signal is in.

  In the motor drive control device 1 according to the first embodiment, when the state count value ST_CNT is an odd number, the voltage of the non-energized phase serving as the comparison target detection signal transitions from a small state to a large state with respect to the center tap voltage CT. . In the motor drive control device 1 according to the first embodiment, when the state count value ST_CNT is an even number, the voltage of the non-energized phase that is the comparison target detection signal is changed from a large state to a small state with respect to the center tap voltage CT. Transition. That is, if there is no flyback pulse, the output signal CMP_OUT of the comparator 15 transitions from 0 to 1 during the period in which the state count value ST_CNT is an odd number. If there is no flyback pulse, the output signal CMP_OUT of the comparator 15 transitions from 1 to 0 during the period in which the state count value ST_CNT is an even number. Therefore, if it is determined in step S61 that the state count value ST_CNT is an odd number, the motor drive control program subtracts 1 from the comparator integral value CMP_INTG (step S62). If it is determined in step S61 that the state count value ST_CNT is an even number, the motor drive control program adds 1 to the comparator integral value CMP_INTG (step S63). Then, when the process of step S62 or step S63 ends, the flyback filter process ends.

  On the other hand, when it is determined in step S60 that the rotation direction instruction flag FWD instructs to control the motor 4 in the reverse rotation direction, the motor drive control program refers to the state count value ST_CNT and the value is It is determined whether the number is an odd number or an even number (step S64). Here, when it is determined that the rotation direction instruction flag FWD instructs to control the motor 4 in the normal rotation direction, the drive current flowing through the rotor of the motor 4 is the reverse of that when the motor 4 is rotating in the normal direction. Therefore, the transition direction of the output signal of the comparator 15 when the state count value ST_CNT is an odd number is opposite to that when the motor 4 rotates in the forward rotation direction.

  Therefore, when it is determined in step S64 that the state count value ST_CNT is an odd number, the motor drive control program adds 1 to the comparator integral value CMP_INTG (step S65). If it is determined in step S64 that the state count value ST_CNT is an even number, the motor drive control program subtracts 1 from the comparator integral value CMP_INTG (step S66). Then, when the process of step S65 or step S66 ends, the flyback filter process ends.

  Next, details of the rotor position detection process in step S49 will be described. FIG. 9 is a flowchart showing the detailed operation procedure of the rotor position detection process. As shown in FIG. 9, the motor drive control program first determines whether or not the value of the output signal CMP_OUT of the comparator 15 sampled in step S23 of FIG. 5 is 1 (step S70). If the output signal CMP_OUT of the comparator 15 is 1 in step S70, the comparator integral value CMP_INTG is counted up. On the other hand, when the output signal CMP_OUT of the comparator 15 is 1, the comparator integral value CMP_INTG is counted down. That is, when the motor drive control program samples the value of the output signal CMP_OUT of the comparator 15 and determines that the voltage value of the comparison target detection signal (non-energized phase drive signal) is greater than the center tap voltage CT. Increases the comparator integral value, and decreases the comparator integral value when it is determined that the voltage value of the comparison target detection signal is smaller than the center tap voltage CT.

  Next, the motor drive control program determines whether or not the state PWM pulse number ST_PWM_PLS is larger than the maximum pulse count number MAXCNT (step S73). In this step S73, when the state PWM pulse number ST_PWM_PLS is larger than the maximum pulse count number, after performing the state control process (step S74), the effective startup flag STUP is set to FALSE (step S75), and zero is set to the zero cross count value ZC_CNT. Setting is made (step S76). Then, the rotor position detection process is terminated when the process of step S76 is completed. The maximum pulse count number of the motor drive control program defines the number of state PWM pulses in one state when the motor 4 is rotating at the minimum rotation speed. That is, in step S73, when the state PWM pulse number ST_PWM_PLS is larger than the maximum pulse count number, the motor 4 is either rotating at a rotation speed equal to or lower than the minimum rotation speed or stopped. Therefore, in this case, the effective startup flag STUP is set to FALSE, and the zero cross count value ZC_CNT that counts the number of times that the zero cross has occurred is reset to zero.

  On the other hand, when the state PWM pulse number ST_PWM_PLS is equal to or smaller than the maximum pulse count number in step S73, the motor drive control program determines whether or not the comparator integral value CMP_INTG is zero (step S77). If it is determined in step S77 that the comparator integral value CMP_INTG is zero, the motor drive control program performs state control processing (step S78). Then, 1 is added to the zero cross count value ZC_CNT (step S79). Next, the motor drive control program determines whether the zero cross count value is greater than 5 (step S80). When it is determined in step S80 that the zero cross count value ZC_CNT is larger than 5, the zero cross count value ZC_CNT is set to a value larger than 5 (for example, 6) (step S81). Further, the effective startup flag STUP is set to TRUE (step S82).

  In the motor drive control program according to the first embodiment, flyback filter processing (step S45) is performed in a predetermined period immediately after the start of each state of the PWM signal, and when the determination processing in step S77 is first performed, The comparator integral value CMP_INTG is a positive value or a negative value. Therefore, the fact that the comparator integral value CMP_INTG becomes zero means that a zero cross in which the voltage relationship between the comparison target detection signal SP and the center tap voltage CT is reversed has occurred. Therefore, as described above, the motor drive control program adds the zero cross count value ZC_CNT in this case. Then, in response to the zero cross count value ZC_CNT becoming a value of 5 or more, it is determined that the motor 4 has made one or more revolutions in electrical angle, and the effective startup flag STUP is set to TRUE.

  On the other hand, when it is determined in step S77 that the comparator integral value CMP_INTG has not reached zero, the motor drive control program determines whether or not the effective startup flag STUP is TRUE (step S83). If it is determined in step S83 that the effective startup flag STUP is FALSE, the motor drive control program determines that the rotor position cannot be detected, and ends the rotor position detection process.

  On the other hand, when it is determined in step S83 that the effective startup flag STUP is TRUE, it is determined whether or not the state PWM pulse number ST_PWM_PLS is larger than the moving average state PWM pulse number ST_PWM_PLS_AVE (step S84). If it is determined in step S84 that the state PWM pulse number ST_PWM_PLS is equal to or less than the moving average state PWM pulse number ST_PWM_PLS_AVE, the motor drive control program has yet passed the maximum allowable period during which one state of the PWM signal is maintained. It is determined that there is no rotor position detection process. On the other hand, when it is determined in step S84 that the state PWM pulse number ST_PWM_PLS is larger than the moving average state PWM pulse number ST_PWM_PLS_AVE, the motor drive control program performs the rotor position detection process after performing the state control process (step S85). Exit.

  The state control processing (steps S74, S78, S85) performed in the rotor position detection processing is the same processing routine. This state control process is a process for transitioning the PWM signal to the next state. That is, in the motor drive control program according to the first embodiment, when the rotational speed of the motor 4 is equal to or lower than the minimum rotational speed (YES branch of step S73), the rotor integral value CMP_INTG becomes zero according to the comparator integral value CMP_INTG becoming zero. If the position is detected (YES branch of step S77), and the position of the rotor is not detected while the motor 4 is rotating, the duration of the current state of the PWM signal is the number of moving average state PWM pulses. When the length indicated by ST_PWM_PLS_AVE has been reached (YES in step S84), the state of the PWM signal is changed to the next state. In the state control process, it is not necessary to update every cycle of the PWM signal, but a variable that needs to be updated is calculated at a predetermined frequency.

  Subsequently, the details of the state control processing in steps S74, S78, and S85 will be described. FIG. 10 is a flowchart showing the detailed operation procedure of the state control process. As shown in FIG. 10, in the state control process, the motor drive control program performs a rotation speed detection process (step S90). In this rotational speed detection process, the motor drive control program sets the number of state PWM pulses ST_PWM_PLS updated in step S41 of FIG. 6 to the number of PWM pulses PWM_PLS [ST_CNT] indicating the length of the period during which the PWM signal has maintained the current state. Substitute (step S90a). Then, the PWM pulse numbers PWM_PLS [0] to PWM_PLS [6] calculated in each of the six states are added to calculate the 6-state total PWM pulse number TTL_ST_PWM_PLS (step S90b). Next, the moving average state PWM pulse number ST_PWM_PLS_AVE is calculated by dividing the 6-state total PWM pulse number TTL_ST_PWM_PLS by 6 which is the number of states (step S90c). Here, the 6-state total PWM pulse number TTL_ST_PWM_PLS is a total value of PWM signal pulses generated while the motor 4 makes one electrical rotation, and indicates the time during which the motor 4 makes one electrical rotation. That is, the rotational speed of the motor 4 can be known from the 6-state total PWM pulse number TTL_ST_PWM_PLS. The rotation speed detection process in step S90 is performed by the rotation control unit 25 in FIG.

  Next, the motor drive control program performs stacking detection processing (step S91). In the stacking detection process, it is determined whether or not the 6-state total PWM pulse number TTL_ST_PWM_PLS is smaller than the stack rotor detection set value STC_DET_SET (step S91a). The stack rotor detection set value STC_DET_SET is a value corresponding to a rotational speed sufficiently higher than the maximum rotational speed of the motor 4, and is a value set in advance. Here, the rotation speed sufficiently higher than the maximum rotation speed is a rotation speed that is electrically possible although it is not less than a limit speed determined by the mechanical structure of the motor. For example, when the limit speed determined from the mechanical structure of the motor 4 is 7000 rpm, a value corresponding to a rotational speed of 8000 to 10000 rpm is set as the stack rotor detection setting value STC_DET_SET. When the motor 4 is in a stacked state, the motor 4 is not mechanically rotated even when a PWM signal is applied, and the comparator integral value CMP_INTG reaches zero in an extremely short time. Therefore, when the motor 4 is in a stacked state, the rotor is not mechanically rotated, but the rotating magnetic field of the stator is in an electrically rotating state exceeding the rotational speed of the rotor. For this reason, the period during which one state of the PWM signal continues is shortened, and the 6-state total PWM pulse number TTL_ST_PWM_PLS becomes smaller than the stack rotor detection set value STC_DET_SET. Therefore, the stack state of the motor 4 can be detected by detecting that the 6-state total PWM pulse number TTL_ST_PWM_PLS is smaller than the stack rotor detection set value STC_DET_SET. Note that the 6-state total PWM pulse number TTL_ST_PWM_PLS is the stack rotor detection set value unless the motor 4 is rotating and is driven without loss and no load, or unless the motor is driven by external power. The state is not smaller than STC_DET_SET.

  When the motor drive control program determines in step S91a that the motor 4 is in a stacked state, the motor drive control program sets the stack rotor detection flag STC_DET to TRUE (step S91b). Further, when it is determined in step S91a that the motor 4 is not in the stack state, the motor drive control program sets the stack rotor detection flag STC_DET to FALSE (step S91c). The stacking detection process in step S91 is performed by the rotation control unit 25 in FIG.

  Then, in response to the completion of the stacking detection process (step S91), the motor drive control program executes the constant rotation speed control process (step S92), the state update process (step S93), the flyback pulse adaptive filter update process (step S94) is performed. Further, after the flyback pulse adaptive filter update process (step S94), the motor drive control program performs a reset process of the comparator integral value CMP_INTG and the number of state PWM pulses ST_PWM_PLS (step S95). Further, the detection signal phase selected by the selector 14 is switched based on the state count value ST_CNT in the next state in accordance with the updated state of the PWM signal.

  Here, the constant rotation speed control process (step S92), the state update process (step S93), and the flyback pulse adaptive filter update process (step S94) will be described in more detail. The constant rotation speed control process (step S92) is a process performed by the rotation speed control unit 26, and the state update process (step S93) and the flyback pulse adaptive filter update process are performed by the rotor position detection unit 24. Process.

  First, FIG. 11 is a flowchart showing a detailed operation procedure of the constant rotation speed control process in step S92. As shown in FIG. 11, in the constant rotation speed control process, the motor drive control program calculates a rotation speed error ROT_ERR by subtracting the rotation speed instruction value ROT_SET from the 6-state total PWM pulse number TTL_ST_PWM_PLS (step S100). Next, the motor drive control program performs stacking prevention acceleration / deceleration limiting processing using the rotation speed error ROT_ERR (step S101).

  In the stacking prevention acceleration / deceleration limiting process, first, the maximum allowable acceleration MAX_ALW_ACL is calculated by multiplying the moving average state PWM pulse number ST_PWM_PLS_AVE and the acceleration coefficient a (step S101a). Next, the maximum allowable deceleration MAX_ALW_DCL is calculated by multiplying the moving average state PWM pulse number ST_PWM_PLS_AVE and the deceleration coefficient b (step S101b).

  Next, the motor drive control program performs a comparison process between the rotation speed error ROT_ERR and the maximum allowable acceleration MAX_ALW_ACL (step S101c). If the rotational speed error ROT_ERR is larger than the maximum allowable acceleration MAX_ALW_ACL in step S101c, the rotational speed error ROT_ERR is updated with the maximum allowable acceleration MAX_ALW_ACL (step S101d). On the other hand, if the rotational speed error ROT_ERR is equal to or smaller than the maximum allowable acceleration MAX_ALW_ACL in step S101c, the rotational speed error ROT_ERR is not updated.

  Next, the motor drive control program performs a comparison process between the rotation speed error ROT_ERR and the maximum allowable deceleration MAX_ALW_DCL (step S101e). If the rotational speed error ROT_ERR is smaller than the maximum allowable deceleration MAX_ALW_DCL in step S101e, the rotational speed error ROT_ERR is updated with the maximum allowable deceleration MAX_ALW_DCL (step S101f). On the other hand, if the rotational speed error ROT_ERR is greater than or equal to the maximum allowable deceleration MAX_ALW_DCL in step S101e, the rotational speed error ROT_ERR is not updated.

  Next, the motor drive control program adds the rotational speed error ROT_ERR to the rotational speed error integrated value ROT_ERR_INTG to update the rotational speed error integrated value ROT_ERR_INTG (step S102). Thereafter, the motor drive control program performs a clamp process of the updated rotational speed error integrated value ROT_ERR_INTG (step S103). In this clamping process, the rotation speed error integrated value ROT_ERR_INTG is converted to a value between a predetermined maximum value and a minimum value, which can be expressed by a predetermined bit width. The rotational speed error integrated value ROT_ERR_INTG is a value corresponding to a control feedback value generated by the rotational speed control unit 26.

  Next, the state update process in step S93 will be described in detail. FIG. 12 is a flowchart showing a detailed operation procedure of the state update process. As shown in FIG. 12, in the state update process, first, the rotation direction of the motor 4 is determined with reference to the rotation direction instruction flag FWD (step S110). If the rotation direction instruction flag FWD is TRUE in step S110, 1 is added to the state count value ST_CNT (step S111). Thereafter, it is determined whether or not the updated state count value ST_CNT is greater than 5 (step S112). If it is determined in step S112 that the state count value ST_CNT is greater than 5, the state count value ST_CNT is reset to zero, and the state update process ends (step S113).

  On the other hand, if the rotation direction instruction flag FWD is FALSE in step S110, 1 is subtracted from the state count value ST_CNT (step S114). Thereafter, it is determined whether or not the updated state count value ST_CNT is smaller than 0 (step S115). If it is determined in step S115 that the state count value ST_CNT is smaller than 0, the state count value ST_CNT is reset to 5 and the state update process is terminated (step S116).

  Next, the flyback pulse adaptive filter update process in step S94 will be described in detail. FIG. 13 is a flowchart showing a detailed operation procedure of the flyback pulse adaptive filter update process. As shown in FIG. 13, in the flyback pulse adaptive filter update process, the motor drive control program determines whether or not the effective startup flag STUP is TRUE (step S120). If it is determined in step S120 that the effective startup flag STUP is FALSE, it is determined that the motor 4 is not rotating effectively, and the process is terminated without updating the flyback pulse adaptive filter.

  On the other hand, if it is determined in step S120 that the effective startup flag STUP is TRUE, the constant current control instruction value CNST_CRNT is set to the maximum current value MAX_CRNT (step S121). Next, the motor drive control program sets the flyback pulse continuation pulse number FB_MASK to a quarter of the moving average state PWM pulse number ST_PWM_PLS_AVE (step S122). Thereafter, the motor drive control program compares the updated flyback pulse continuation pulse number FB_MASK with the minimum value MIN_FB_MASK of the flyback pulse continuation pulse number (step S123). If the number of flyback pulse continuation pulses FB_MASK is equal to or greater than the minimum value MIN_FB_MASK of the number of flyback pulse continuation pulses, the process ends. On the other hand, when the flyback pulse duration pulse number FB_MASK is smaller than the minimum flyback pulse duration pulse value MIN_FB_MASK, the flyback pulse duration pulse number FB_MASK is set to the minimum flyback pulse duration pulse value MIN_FB_MASK, and the processing ends. (Step S124).

  Next, the regulation loop arbitration process in step S46 of FIG. 6 will be described in detail. FIG. 14 is a flowchart showing a detailed operation procedure of the regulation loop arbitration process. This regulation loop arbitration process is performed by the PWM duty control unit 27 of FIG.

  As shown in FIG. 14, in the regulation loop arbitration process, the motor drive control program performs a comparison process between the rotational speed error integrated value ROT_ERR_INTG and the current error integrated value CRNT_ERR_INTG (step S130).

  If it is determined in step S130 that the rotational speed error integrated value ROT_ERR_INTG is smaller than the current error integrated value CRNT_ERR_INTG, the current error integrated value CRNT_ERR_INTG is updated with the rotational speed error integrated value ROT_ERR_INTG (step S131). . Thereafter, the motor drive control program sets the rotation speed error integrated value ROT_ERR_INTG to the on-time PWM_ON of the PWM signal, and then ends the regulation loop arbitration process (step S132).

  On the other hand, when it is determined in step S130 that the rotational speed error integrated value ROT_ERR_INTG is equal to or greater than the current error integrated value CRNT_ERR_INTG, the value of the rotational speed error integrated value ROT_ERR_INTG is updated with the value of the current error integrated value CRNT_ERR_INTG (step S133). . Thereafter, the motor drive control program sets the current error integrated value CRNT_ERR_INTG to the on-time PWM_ON of the PWM signal, and then ends the regulation loop arbitration process (step S134).

  By performing such regulation loop arbitration processing, when the control loop is switched between the constant current control system and the constant rotation control system, the control loop used after switching at the time of switching starts control from the saturated state. Can be prevented. And since the control loop immediately after switching does not start control from a saturated state, switching of a control loop can be performed smoothly.

  Next, the PWM premodulation process in step S47 of FIG. 6 will be described in detail. FIG. 15 is a flowchart showing the detailed operation procedure of the PWM premodulation process. The PWM pre-modulation process is performed by the PWM duty control unit 27 in FIG.

  As shown in FIG. 15, in the PWM pre-modulation process, the motor drive control program first adds the carry-over PWM on-time CRY_PWM_ON to the on-time PWM_ON of the PWM signal determined in the regulation loop arbitration process in step S46 (step S46). S140). At this time, the carry-over PWM on-time CRY_PWM_ON to be added is a value calculated when determining the on-time of the PWM signal in the current cycle. Next, the motor drive control program performs a comparison process between the on-time PWM_ON of the PWM signal calculated in step S140 and the maximum duty set value MAX_DUTY (step S141). The maximum duty setting value MAX_DUTY is set based on a restriction on the pulse width that can be generated by the motor drive control device 1.

  If it is determined in step S141 that the on-time PWM_ON of the PWM signal is larger than the maximum duty set value MAX_DUTY, a value obtained by subtracting the PWM cycle PWM_TRM from the on-time PWM_ON of the PWM signal is set to the carry-over PWM on-time CRY_PWM_ON (step S141). S142). Thereafter, the PWM cycle PWM_TRM is set as the on-time PWM_ON of the PWM signal (step S143). That is, when the on-time PWM_ON of the PWM signal is generated by the process of step S142, the PWM signal of the next cycle is not in the off state.

  On the other hand, when it is determined in step S141 that the on-time PWM_ON of the PWM signal is smaller than the maximum duty set value MAX_DUTY, a comparison process between the on-time PWM_ON of the PWM signal and the minimum duty set value MIN_DUTY is performed (step S144). If it is determined in step S144 that the on-time PWM_ON of the PWM signal is smaller than the minimum duty set value MIN_DUTY, the on-time PWM_ON of the PWM signal is set as the carry-over PWM on-time CRY_PWM_ON (step S145). Thereafter, the on-time PWM_ON of the PWM signal is set to zero (step S146). That is, when the on-time PWM_ON of the PWM signal is generated by the process of step S146, the PWM signal of the next period is not in the on state.

  On the other hand, if it is determined in step S144 that the on-time PWM_ON of the PWM signal is greater than or equal to the minimum duty set value MIN_DUTY, zero is set as the carry-over PWM on-time CRY_PWM_ON (step S147). That is, when the on-time PWM_ON of the PWM signal is generated by the process of step S147, the PWM signal of the next period has an on-state having a length corresponding to the value of the on-time PWM_ON of the PWM signal.

  In the above description, the operation by the motor drive control device 1, that is, the motor drive control program has been described. Below, a specific waveform is shown and operation | movement of the motor drive control apparatus 1 is demonstrated.

  First, FIG. 16 shows a timing chart for explaining the initial behavior of motor drive control in which the motor drive control device 1 changes the motor 4 from the stopped state to the rotated state. In the timing chart shown in FIG. 16, a state signal is shown as a signal that switches between a high level and a low level each time the state of the PWM signal changes. The period during which the state signal is at a high level indicates that the driving phase of the stator is odd-numbered, that is, the PWM signal is in an odd-numbered state. , Indicates that the PWM signal is in an even-numbered state. In addition, a 6-state signal is shown as a signal that switches between a high level and a low level every time the PWM signal passes through 6 states. In FIG. 16, an effective start-up flag STUP is shown to indicate the rotation state of the rotor. Note that the timing chart shown in FIG. 16 shows an example in which the rotation starts from a state where the rotor is stationary at a position corresponding to the state 0 as an example of the operation for starting the rotation.

  First, the motor drive device 1 according to the first embodiment starts motor control in a state in which the current error integrated value CRNT_ERR_INTG and the rotation speed error integrated value ROT_REE_INTG are reset to zero in the variable initialization process (step S1). For this reason, the motor drive device 1 according to the first embodiment starts motor control with the state of the PWM signal for controlling the motor as state 0, but the drive current at the start of this control is zero. For this reason, as shown in FIG. 16, in the state 0 immediately after the drive control is started, the rotor of the motor 4 does not generate rotational torque and remains stopped. Further, since the rotor is not rotating, no zero cross occurs between the non-energized phase drive signal and the center tap voltage CT. In the example shown in FIG. 16, the phase of the rotor is delayed from the position of the stator to be driven (hereinafter referred to as an excitation stator), and zero crossing does not occur. Therefore, the comparator integral value CMP_INTG Never reaches zero. In the first state 0, the motor drive control device 1 changes the state of the PWM signal from the state 0 to the state 1 in response to the comparator integral value CMP_INTG reaching the maximum pulse count value MAXCNT (FIG. 9). In step S74 and subsequent steps). The state where the comparator integral value CMP_INTG reaches the maximum pulse count value MAXCNT in this way is hereinafter referred to as timeout detection. The motor drive control device 1 continues the startup process of the motor 4 while increasing the drive current each time the state of the PWM signal is changed.

  Here, a procedure for increasing the drive current when the motor 4 is started will be described. First, in the initial state 0, the rotation speed instruction value ROT_SET is maintained at zero, whereas the drive current MI is zero, so the error between the drive current MI and the constant current control set value CONST_CRNT_SET is the maximum drive current. Matches. Therefore, in the initial state 0, the current error integrated value CRNT_ERR_INTG is maintained at zero by the regulation loop arbitration process (step S46 and the process of FIG. 14).

  Subsequently, when the state of the PWM signal transits from the state 0 to the state 1 due to the timeout detection, the motor drive control device 1 performs the processing of step S92 and FIG. 11 and performs the rotation speed instruction as the value of the rotation speed error value ROT_INTG. A value obtained by limiting the value ROT_SET with the maximum allowable acceleration MAX_ALW_ACL is set. On the other hand, in the state 1, an error value between the drive current MI and the constant current control set value CONST_CRNT_SET is calculated as the current error integrated value CRNT_INTG with respect to the drive current MI. At this time, in the first state 1, the drive current MI is initially zero, and the current error integrated value CRNT_INTG matches the maximum drive current. Therefore, in the rotary motor drive control device 1, the value of the rotational speed error integrated value ROT_INTG is substituted into the current error integrated value CRNT_INTG by the regulation loop arbitration process (step S46 and the process of FIG. 14). That is, the amount of increase in drive current that increases when the state of the PWM signal changes becomes a value limited by the maximum allowable acceleration ROT_ALW_ACL.

  As described above, the increase amount of the drive current when the state of the PWM signal is changed becomes a value limited by the maximum allowable acceleration ROT_ALW_ACL. A state smaller than the error integral value CRNT_ERR_INTG continues. That is, during the period until the rotation of the motor 4 is started, the drive current that is increased every time the state of the PWM signal changes is limited by the maximum allowable acceleration ROT_ALW_ACL, and the drive current gradually increases.

  Thus, the motor drive control device 1 gradually increases the drive torque applied to the rotor. Then, when the driving torque applied to the rotor exceeds the stationary torque of the rotor, the rotation of the rotor is started. However, even if the rotor rotates, the rotation of the motor does not continue unless the rotation frequency and rotation phase of the rotor match the drive frequency and drive phase of the excitation stator.

  For example, when the driving torque is insufficient, a state where the rotor does not rotate occurs. Even if the drive torque is sufficient and the rotor rotates, the drive torque applied to the rotor will be in an inappropriate state if the excitation stator drive phase and the rotor rotation phase do not match. The rotor rotates in the reverse direction or the position passing through the drive target position of the excited stator in the next state, and the motor does not continue to rotate. In addition, when the drive frequency of the excitation stator and the rotational frequency of the rotor do not coincide with each other, an appropriate drive torque cannot be continuously applied to the rotor, so that the rotation of the motor does not continue.

  As described above, in order to keep the rotation of the motor 4, it is necessary to make a sufficient driving torque and the driving frequency and driving phase of the excitation stator coincide with the rotating frequency and rotation phase of the rotor. Therefore, in the motor drive control device 1 according to the first embodiment, the drive current is gradually increased every time the state of the PWM signal is changed, and the drive frequency and the drive phase of the excitation stator are changed by changing the state of the PWM signal. Search for a state that matches the rotational frequency and rotational phase of the rotor. More specifically, the motor drive control device 1 according to the first embodiment uses the flyback pulse filter process, the comparator integral value CMP_INTG, and the maximum pulse count number MAXCNT to drive and drive the excitation stator. The state in which the phase matches the rotational frequency and rotational phase of the rotor is searched.

  First, immediately after the state of the PWM signal is changed, the motor drive control device 1 increases the comparator integral value CMP_INTG by flyback pulse filter processing (steps S44, S45 in FIG. 6 and the processing in FIG. 8), or Decrease. After the flyback pulse filter processing, if the driving torque is equal to or greater than the static torque and the rotational phase difference of the rotor with respect to the excitation stator driving phase is less than ± 30 °, the rotor rotates and zero crossing occurs. There is a possibility that it can be detected. Therefore, if it can be detected that the comparator integral value CMP_INTG has reached zero before the timeout detection period has elapsed (period in which the state PWM pulse number ST_PWM_PLS is equal to or less than the maximum pulse count value MAXCNT), the motor drive control device 1 determines that a zero cross has occurred. Judgment is made and the PWM signal is shifted to the next state.

  However, if the state after the completion of the flyback pulse filter processing is a state in which the rotational phase of the rotor has advanced by 30 ° or more with respect to the drive phase of the excitation stator, the comparator Since the output has a logic level opposite to the expected logic level, the comparator integral value CMP_INTG reaches zero before the timeout detection period elapses. That is, in such a case, the motor drive control device 1 determines that a zero cross has occurred before the completion of the flyback pulse filter processing, and transitions the state of the PWM signal to a state without waiting for the timeout detection period to elapse. Let A state corresponding to such an operation is, for example, a state indicated by “state transition based on comparator integrated value” in FIG. In the motor drive control device 1, in the variable initialization process (step S1 in FIG. 3 and the process in FIG. 4), the number FB_MASK of flyback pulse continuation PWM pulses until the effective startup flag STUP is switched from FALSE to TRUE is set. Since it is set to a small value (for example, 1/6 of the number of 6-state PWM pulses corresponding to the maximum rotation speed), a period of a state in which it is determined that a zero cross has occurred before the completion of the full-back pulse filter processing will be described later. Compared to the case where state transition based on timeout detection is performed, the time is extremely short.

  In addition, if the state after the flyback pulse filter processing is a state where the rotor rotation phase is delayed by 30 ° or more with respect to the drive phase of the excitation stator, the output of the comparator is output when the flyback pulse filter processing is completed. Therefore, the absolute value of the comparator integral value CMP_INTG increases. However, when the rotation phase of the rotor is delayed by 30 ° or more with respect to the drive phase of the excitation stator, an appropriate load torque cannot be applied to the rotor, so the rotor does not rotate. Therefore, even if the timeout detection period elapses, the output of the comparator is not inverted, and the absolute value of the comparator integral value CMP_INTG does not start to decrease. That is, in such a case, the motor drive control device 1 waits for the occurrence of zero crossing until time-out detection is performed, and transitions the state of the PWM signal to the state when the time-out detection period elapses. The state corresponding to such an operation is, for example, a state indicated by “state transition based on timeout detection” in FIG.

  Even after the flyback pulse filter processing is finished, even if zero crossing actually occurs, the rotor further rotates before the comparator integral value CMP_INTG reaches zero, and the rotational phase of the rotor corresponds to the current state. When the position of the rotational phase corresponding to a state different from the rotational phase is reached, the timeout detection period may elapse before the comparator integral value CMPCMP_INTG reaches zero. Therefore, even in such a case, the motor drive control device 1 changes the state of the PWM signal based on the timeout detection.

  Thus, in the motor drive control device 1, when it is determined that the occurrence of zero crossing has already occurred, the PWM signal is immediately shifted to the next state. Further, when there is a possibility of occurrence of zero crossing, the motor drive control device 1 waits for the comparator integral value CMP_INTG to reach zero during the timeout detection period. If the comparator integral value CMP_INTG does not reach zero during the time-out detection period, the motor drive control device 1 determines that the rotation frequency of the rotor is slower than the drive frequency with the time-out detection period as one cycle, and detects time-out. As the period elapses, the PWM signal is shifted to the next state. Further, when the motor drive control device 1 can detect that the comparator integral value CMP_INTG has reached zero during the timeout detection period, the motor drive control device 1 determines that the rotational frequency of the rotor is faster than the drive frequency with the timeout detection period as one cycle. In response to the comparator integral value CMP_INTG reaching zero, the state of the PWM signal is changed to the next state.

  Then, when the state transition (step S78 in FIG. 9) corresponding to the fact that the comparator integral value CMP_INTG has reached zero has occurred six times in succession, the motor drive control device 1 sets the effective start-up flag STUP to FALSE. Is switched from TRUE to TRUE (step S82). As described above, the state transition corresponding to the fact that the comparator integral value CMP_INTG has reached zero has continuously occurred six times, that is, the rotation frequency and rotation phase of the rotor, the drive frequency and drive phase of the excitation stator, , Means a match. In the period immediately before the effective startup flag STUP becomes TRUE (zero cross detection unbalanced rotation in FIG. 16), the motor is in an acceleration state and before the state PWM pulse number ST_PWM_PLS reaches the moving average state PWM pulse number ST_PWM_PLS_AVE. The state where the comparator integral value CMP_INTG reaches zero continues. Therefore, in the period immediately before the effective startup flag STUP becomes TRUE, one period of each state is gradually shortened. In addition, in the zero cross detection unbalanced rotation state, the length between the states is not uniform, but it can be determined that the rotor and the excitation stator are in a stable rotation state in which the frequency and the phase are the same.

  After the effective startup flag STUP is switched to TRUE, the motor drive control device 1 increases the constant current control instruction value CNST_CRNT_SET from one third of the maximum current value MAX_CRNT to the maximum current value MAX_CRNT (FIG. 14). Together with steps S120 and S121), the flyback pulse continuation PWM pulse number FB_MASK is set to a quarter of the moving average state PWM pulse number ST_PWM_PLS_AVE. Then, the motor drive control device 1 increases the rotation speed of the motor 4 to the rotation speed instruction value ROT_SET by constant current control.

  In the motor drive control device 1 according to the first embodiment, it is possible to prevent the motor 4 from continuing the reverse rotation state by starting the motor 4 by the above processing.

  First, the motor drive control device 1 starts the start-up control with the drive current for driving the motor 4 set to zero. Then, the motor drive control device 1 advances the state transition while gradually increasing the drive current. This prevents sudden application of a driving torque that is much larger than the stationary torque of the rotor. In this way, by gradually increasing the drive current, even if the phase relationship between the rotor and the excitation stator is a relationship that causes the rotor to rotate backward (unintentional rotation direction), the rotor is excessive in the reverse rotation direction. To prevent it from rotating.

  Further, in the motor drive control device 1, if it is determined from the output state of the comparator 15 that a zero cross has occurred before the flyback pulse filter processing ends, the PWM is immediately performed without waiting for the timeout detection period to elapse. Transition the signal state to the next state. At this time, in the period in which the effective startup flag STUP is FALSE, the motor drive control device 1 sets the value of the flyback pulse continuous PWM pulse number FB_MASK to a small value so that the drive torque in the reverse rotation direction is applied to the rotor. To shorten. On the other hand, when the occurrence of zero crossing can be expected after completion of the flyback pulse filter processing, the motor drive control device 1 waits for the comparator integral value CMP_INTG to reach zero until the timeout detection period elapses. In other words, in the motor drive control device 1, in a state where the drive torque of the forward rotation (intended rotation direction) is applied to the rotor, the motor drive control device 1 waits as much as possible for the rotation phase of the rotor to reach the rotation position of the next state, and rotates backward to the rotor. In the state where the drive torque is applied, the period during which the drive torque is applied to the rotor is shortened.

  In addition, the motor drive control device 1 determines that the motor 4 has entered a normal rotation state in response to six consecutive occurrences of the PWM signal state transition in response to the comparator integral value CMP_INTG reaching zero. (The effective startup flag STUP is set to TRUE). For example, when the state transition of the PWM signal corresponding to the fact that the comparator integral value CMP_INTG has reached zero does not occur continuously six times, the rotational frequency and rotational phase of the rotor and the driving of the excitation stator in any of the driving phases The frequency and drive phase are inconsistent. When the drive current is increased to the maximum current value in such a state, the intended drive torque is not applied to the rotor in the mismatched drive phase, and there is a possibility that the rotation stops or reversely rotates. On the other hand, the state in which the state transition of the PWM signal corresponding to the fact that the comparator integral value CMP_INTG has reached zero continuously occurs six times is the rotation frequency and rotation phase of the rotor, and the drive frequency and drive phase of the excitation stator. Means that they match. Therefore, by determining that the state transition of the PWM signal corresponding to the comparator integral value CMP_INTG reaching zero has occurred six times continuously, it is determined that the motor 4 has entered an effective rotation state. It is possible to prevent an excessive driving torque in the reverse rotation direction from being applied to the motor 4 and to prevent the motor 4 from continuing in a reverse rotation state.

  Next, the operation of the motor drive control program after the motor 4 is rotated will be described. The motor drive control program according to the first embodiment controls the motor 4 by an alternate PWM method that switches between a high-side off state and a low-side off state as an off state for each cycle of the PWM signal. First, an alternate PWM method performed by the motor drive control program will be described. The motor drive control program determines the ratio between the on state and the off state of the PWM signal based on the duty ratio. Then, the motor drive control program gives a drive current from the power source to the motor 4 when the PWM signal is in an on state. Further, the motor drive control program consumes the current flowing in the coil of the motor 4 by the transistor in the driver circuit 3 and the parasitic resistance of the coil when the PWM signal is in the off state.

  In this off state, when only one of the high side off state and the low side off state is adopted, the voltage level of the center tap voltage CT and the drive signal of the non-conduction phase is either the power supply voltage side or the ground voltage side. Biased toward A problem arises in that the zero cross point at which the voltage relationship between the center tap voltage CT and the drive signal of the non-energized phase is reversed due to this voltage level deviation shifts forward or backward in time. On the other hand, the motor drive control program according to the first embodiment adopts the alternate PWM method, so that the voltage level of the center tap voltage CT and the drive signal of the non-conduction phase is set to either the power supply voltage side or the ground voltage side. Prevents bias. Specifically, in the motor drive control program according to the first embodiment, the cycle in which the voltage level of the center tap voltage CT and the drive signal of the non-energized phase is biased toward the power supply voltage side and the cycle in which the voltage level is biased toward the ground voltage side are PWM signal cycles. It is repeated every time and it is prevented from being biased to one side. Further, the voltage level of the input center tap voltage CT and the comparison target detection signal SP (non-energized phase drive signal) has a vertical deviation for each period of the PWM signal, so that the comparator of the motor drive control device 1 Even if 15 has an input offset, the error due to the input offset is canceled at the stage of calculating the comparator integral value CMP_INTG. That is, the motor drive control program according to the first embodiment can improve the accuracy of the state transition timing of the PWM signal based on the comparator integral value CMP_INTG by adopting the alternate PWM method.

  The motor 4 is a three-phase drive motor and is controlled by a six-state PWM signal. When performing the operation by the alternate PWM method, which of the transistors constituting the driver circuit 3 is turned on differs depending on the state in order to perform the rotation operation. 17 to 22 show circuit diagrams of the driver circuit 3 for explaining the on-state and off-state control states of the states 0 to 5.

  Here, before describing the control states of the on-state and off-state driver circuits, the circuit of the driver circuit 3 will be described with reference to FIGS. As illustrated in FIGS. 17 to 22, the driver circuit 3 includes three sets of drive stage circuits in order to generate three drive signals of U phase, V phase, and W phase. In the example shown in FIGS. 17 to 22, in the three sets of driving stage circuits, a high-side transistor is formed by a PMOS transistor, and a low-side transistor is formed by an NMOS transistor.

  As shown in FIGS. 17 to 22, in the driving stage circuit that generates the U-phase driving signal, the high-side transistor PU and the low-side transistor NU are connected in series between the power supply wiring and the ground wiring. The PWM signal UH is input to the gate of the high side transistor PU, and the PWM signal UL is input to the gate of the low side transistor NU. In a drive stage circuit that generates a V-phase drive signal, a high side transistor PV and a low side transistor NV are connected in series between a power supply line and a ground line. The PWM signal VH is input to the gate of the high side transistor PV, and the PWM signal VL is input to the gate of the low side transistor NV. In a drive stage circuit that generates a W-phase drive signal, a high-side transistor PW and a low-side transistor NW are connected in series between a power supply line and a ground line. The PWM signal WH is input to the gate of the high side transistor PW, and the PWM signal WL is input to the gate of the low side transistor NW.

  Next, the control state of the on-state and off-state driver circuits will be described. FIG. 17 is a circuit diagram showing the control state of the on-state and off-state driver circuit 3 in state 0. As shown in FIG. 17, in the on-state of state 0, the high-side transistor PU and the low-side transistor NV are turned on. Then, a drive current flows from the U-phase coil LU of the motor 4 to the V-phase coil LV. In the high-side off state, all the high-side transistors are turned off, and the low-side transistor NU of the drive stage circuit to which the high-side transistor PU that is on in the on-state belongs, and the low-side transistor that is on in the on-state NV is turned on. The flyback current flowing in the coils LU and LV is consumed by the low side transistors NU and NV. In the low-side off state, all the low-side transistors are turned off, and the high-side transistor PV of the drive stage circuit to which the high-side transistor PU that is on in the on-state and the low-side transistor NV that is on in the on-state belongs. Are turned on. The flyback current flowing in the coils LU and LV is consumed by the high side transistors PU and PV.

  FIG. 18 is a circuit diagram showing the control state of the on-state and off-state driver circuit 3 in state 1. As shown in FIG. 18, in the on state of state 1, the high side transistor PU and the low side transistor NW are in the on state. A drive current flows from the U-phase coil LU of the motor 4 to the W-phase coil LW. In the high-side off state, all the high-side transistors are turned off, and the low-side transistor NU of the drive stage circuit to which the high-side transistor PU that is on in the on-state belongs, and the low-side transistor that is on in the on-state NW is turned on. The flyback current flowing in the coils LU and LW is consumed by the low side transistors NU and NW. In the low-side off state, all the low-side transistors are turned off, and the high-side transistor PW of the drive stage circuit to which the high-side transistor PU that is on in the on-state and the low-side transistor NW that is on in the on-state belongs. Are turned on. The flyback current flowing in the coils LU and LW is consumed by the high side transistors PU and PW.

  FIG. 19 is a circuit diagram illustrating a control state of the on-state and off-state driver circuit 3 in the state 2. As shown in FIG. 19, in the on state of state 2, the high side transistor PV and the low side transistor NW are in the on state. Then, a drive current flows from the V-phase coil LV of the motor 4 to the W-phase coil LW. In the high-side off state, all the high-side transistors are turned off, and the low-side transistor NV of the drive stage circuit to which the high-side transistor PV that is on in the on-state belongs, and the low-side transistor that is on in the on-state NW is turned on. The flyback current flowing in the coils LV and LW is consumed by the low side transistors NV and NW. In the low-side off state, all the low-side transistors are turned off, and the high-side transistor PW of the drive stage circuit to which the high-side transistor PV that is on in the on-state and the low-side transistor NW that is on in the on-state belongs. Are turned on. The flyback current flowing in the coils LV and LW is consumed by the high side transistors PV and PW.

  FIG. 20 is a circuit diagram showing the control state of the on-state and off-state driver circuit 3 in state 3. As shown in FIG. 20, in the on state of state 3, the high side transistor PV and the low side transistor NU are in the on state. A drive current flows from the V-phase coil LV of the motor 4 to the U-phase coil LU. In the high-side off state, all the high-side transistors are turned off, and the low-side transistor NV of the drive stage circuit to which the high-side transistor PV that is on in the on-state belongs, and the low-side transistor that is on in the on-state NU is turned on. The flyback current flowing in the coils LV and LU is consumed by the low side transistors NV and NU. In the low-side off state, all the low-side transistors are turned off, and the high-side transistor PU of the drive stage circuit to which the high-side transistor PV that is on in the on-state and the low-side transistor NU that is on in the on-state belongs. Are turned on. The flyback current flowing in the coils LU and LV is consumed by the high side transistors PU and PV.

  FIG. 21 is a circuit diagram showing the control state of the on-state and off-state driver circuit 3 in state 4. As shown in FIG. 21, in the on state of state 4, the high side transistor PW and the low side transistor NU are in the on state. A drive current flows from the W-phase coil LW of the motor 4 to the U-phase coil LU. In the high-side off state, all the high-side transistors are turned off, and the low-side transistor NW of the drive stage circuit to which the high-side transistor PW that was on in the on-state belongs, and the low-side transistor that was on in the on-state NU is turned on. The flyback current flowing in the coils LU and LW is consumed by the low side transistors NU and NW. In the low-side off state, all the low-side transistors are turned off, and the high-side transistor PU of the drive stage circuit to which the high-side transistor PW that is on in the on-state and the low-side transistor NU that is on in the on-state belongs. Are turned on. The flyback current flowing in the coils LU and LW is consumed by the high side transistors PU and PW.

  FIG. 22 is a circuit diagram showing the control state of the on-state and off-state driver circuit 3 in state 5. As shown in FIG. 22, in the on state of state 5, the high side transistor PW and the low side transistor NV are turned on. Then, a drive current flows from the W-phase coil LW of the motor 4 to the V-phase coil LV. In the high-side off state, all the high-side transistors are turned off, and the low-side transistor NW of the drive stage circuit to which the high-side transistor PW that was on in the on-state belongs, and the low-side transistor that was on in the on-state NV is turned on. The flyback current flowing in the coils LV and LW is consumed by the low side transistors NV and NW. In the low-side off state, all the low-side transistors are turned off, and the high-side transistor PV of the drive stage circuit to which the high-side transistor PW that is on in the on-state and the low-side transistor NV that is on in the on-state belongs. Are turned on. The flyback current flowing in the coils LV and LW is consumed by the high side transistors PV and PW.

  Note that the operation of turning on the opposite transistor paired with the turned off transistor in the off state is called a synchronous rectification operation. That is, the operation of the alternate PWM method in the motor drive control program according to the first embodiment includes a synchronous rectification operation. By performing such synchronous rectification operation, conventionally, the flyback current consumed by the body diode of the off-state transistor can be consumed by the on-state transistor, and the power efficiency can be improved. . Therefore, FIG. 23 shows a graph comparing input / output characteristics with and without the synchronous rectification operation. As shown in FIG. 23, it is understood that when the synchronous rectification operation is performed, the output (rotation speed × torque) when the input power is small is lower than when the synchronous rectification operation is not performed. It can also be seen that when the input power range is the same, the output range is wider when the synchronous rectification operation is performed.

  From the above description, the motor drive control program according to the first embodiment controls the off-state state of the PWM signal by the alternate PWM method. As the off-state control, in addition to the alternate PWM method, it is conceivable to control only one of the high-side off state and the low-side off state. However, when only one of the high side off state and the low side off state is performed as the off state, the voltage level of the center tap voltage CT and the drive signal of the non-conducting phase is set to either the power supply voltage side or the ground voltage side. Biased. Further, when the rotation speed of the motor 4 is low, the gradient of the potential change of the non-energized phase that is in the high impedance state becomes gentle. Therefore, when only one of the high-side off-state and the low-side off-state is performed as the off-state, the voltage relationship between the center tap voltage CT and the drive signal of the non-energized phase is reversed while the rotation speed of the motor 4 is low. There is a problem that the deviation of the zero cross timing becomes remarkable and the deviation of the zero cross point becomes remarkable.

  However, in the motor drive control program according to the first embodiment, by adopting the alternate PWM method, the shift direction of the voltage level of the center tap voltage CT and the drive signal of the non-energized phase is increased or decreased for each period of the PWM signal. Thereby, even when the comparator 15 has an input offset, the deviation of the comparator integral value CMP_INTG caused by the input offset is canceled by the fluctuation in the deviation direction of the voltage level of the center tap voltage CT and the drive signal of the non-conduction phase. Is done. In addition, the comparator 15 may make an erroneous determination due to the influence of input noise, but by adopting the alternate PWM method, the vertical fluctuation of the center tap voltage CT and the voltage level of the drive signal of the non-conduction phase is changed to the input noise. Offset. Therefore, when the motor drive control program according to the first embodiment is used, it is not necessary for the comparator 15 to have hysteresis characteristics. Thereby, in the motor drive control program according to the first embodiment, even if the rotation speed of the motor 4 is slow and the inclination between the center tap voltage CT and the drive signal of the non-energized phase is gradual, the input offset of the comparator 15 In addition, it is not affected by the deviation of the zero cross detection timing due to the hysteresis characteristic. In the motor drive control program according to the first embodiment, the state of the PWM signal can be transitioned with high accuracy by the comparator integral value CMP_INTG. That is, the motor drive control program according to the first embodiment can improve the controllability of the motor in the low rotation speed region. Further, the motor drive control program according to the first embodiment can improve the controllability of the motor in a wide rotation speed range by increasing the controllability on the low rotation speed side.

  Such an operation by the alternate PWM method is performed in a state where the duty ratio of the PWM signal is less than 100%. Thus, the operation of the motor drive control program will be described by taking as an example a state where the duty ratio of the PWM signal in which the operation by the alternate PWM method is performed is 50%. In the following description, since the PWM signal generated based on the operation of the motor drive control program is output from the motor drive control device 1, the operation of the motor drive control device 1 is performed as the operation of the motor drive control program. Will be explained.

  Here, in order to explain in more detail the waveform of the PWM signal, the waveform of the drive signal that drives the motor 4, and the operation of the motor drive control device 1 according to the drive signal, the operation state of the state 0 is taken as an example for the motor. The operation of the drive control device 1 will be described.

  First, FIG. 24 shows a timing chart of the PWM signal generated by the motor drive control device 1, the drive signal of the motor 4 generated according to the PWM signal, and the center tap voltage CT of the motor 4. As shown in FIG. 24, the motor drive control device 1 generates a reference PWM signal with a duty ratio of 50%. Then, the motor drive control device 1 generates six PWM signals UH, UL, VH, VL, WH, WL for generating a three-phase drive signal based on the reference PWM signal.

  State 0 is a state in which a drive current flows from the U phase toward the V phase. In state 0, the W-phase drive signal is in a high impedance state (Z state). Therefore, in the state 0, the motor drive control device 1 sets the PWM signals UH and UL to the low level in the on-state (high level period) of the reference PWM signal. In state 0, the motor drive control device 1 sets the PWM signals VH and VL to the high level in the on-state of the reference PWM signal. Further, in the state 0, the motor drive control device 1 sets the PWM signal WH to the high level and the PWM signal WL to the low level in the on-state of the reference PWM signal. As a result, during the on-time of the reference PWM signal, the U-phase drive signal is at a high level and the V-phase drive signal is at a low level. A drive current flows from the U phase to the V phase. Further, since the W-phase drive signal is in a high impedance state, the voltage value is between the U-phase drive signal and the V-phase drive signal. The voltage value of the W-phase drive signal gradually decreases according to the rotational position of the rotor.

  Further, in the first embodiment, in order to perform the operation by the alternate PWM method, the reference PWM signal has the high side off state and the low side off state as the off state. As shown in FIG. 24, the motor drive control device 1 according to the first embodiment switches between the high-side off state and the low-side off state for each cycle of the PWM signal.

  Therefore, first, PWM signals UH, UL, VH, VL, WH, WL in the high-side off state in state 0 will be described. In state 0, a drive current is passed from the U phase to the V phase, and the W phase drive signal is in a high impedance state. Therefore, in the high-side off state of state 0, the motor drive control device 1 sets the PWM signals UH and UL to the high level in the off state (low level period) of the reference PWM signal. Further, in the high-side off state in the state 0, the motor drive control device 1 sets the PWM signals VH and VL to the high level in the off state of the reference PWM signal. Further, in the high-side off state of state 0, the motor drive control device 1 sets the PWM signal WH to the high level and the PWM signal WL to the low level in the off state of the reference PWM signal. As a result, during the off time of the reference PWM signal, the U-phase drive signal, the V-phase drive signal, and the W-phase drive signal are at a low level. A current flows between the U phase and the V phase.

  Next, PWM signals UH, UL, VH, VL, WH, and WL during the low-side off state in state 0 will be described. In state 0, a drive current is passed from the U phase to the V phase, and the W phase drive signal is in a high impedance state. Therefore, in the low-side off state of the state 0, the motor drive control device 1 sets the PWM signals UH and UL to the low level in the off state (low level period) of the reference PWM signal. In the low-side off state of state 0, the motor drive control device 1 sets the PWM signals VH and VL to the low level in the off state of the reference PWM signal. Further, in the low-side off state of state 0, the motor drive control device 1 sets the PWM signal WH to the high level and the PWM signal WL to the low level in the off-state of the reference PWM signal. As a result, during the off time of the reference PWM signal, the U-phase drive signal, the V-phase drive signal, and the W-phase drive signal are at a high level. A current flows between the U phase and the V phase.

  As described above, the motor drive control device 1 switches between the on state and the off state for each cycle of the PWM signal. Furthermore, the motor drive control device 1 switches the control state in the off state between a high side off state and a low side off state for each period of the PWM signal. By performing such control, the motor drive control device 1 causes a drive current to flow from the U phase to the V phase in the on state. The voltage of the non-conducting phase (W-phase drive signal in state 0) that enters the high impedance state changes from the high level to the low level. This voltage change in the non-energized phase changes according to the rotational position of the rotor. Immediately after the state of the PWM signal is changed, a flyback pulse is generated in the non-energized phase. The center tap voltage CT is generated based on voltage values of U-phase, V-phase, and W-phase drive signals. At this time, since the U-phase drive signal is at a high level and the V-phase drive signal is at a low level in the on-state, the center tap voltage CT varies depending on the voltage of the non-energized W-phase drive signal. Indicates.

  Next, the PWM signal control process of the motor drive control device 1 in the state 0 will be described. FIG. 25 is a timing chart for explaining the operation of the motor drive control device 1 in the state 0 when a PWM signal having a duty ratio of 50% is generated. As shown in FIG. 25, when the duty ratio of the PWM signal is 50%, the motor drive control device 1 switches the PWM signal from the on state to the off state in response to the occurrence of the BEMF timer interrupt. This operation corresponds to the operation in step S32 in FIG. The motor drive control device 1 switches the PWM signal from the off state to the on state in response to the PWM cycle interrupt. This operation corresponds to the operation in step S36 in FIG. Note that the motor drive control device 1 updates the duty ratio of the PWM signal for each period of the PWM signal in one state, but in FIG. 25, for the sake of simplicity, the duty ratio of the PWM signal is over the entire period. Was 50%.

  In state 0, the non-energized phase is a W-phase drive signal. Therefore, the motor drive control device 1 selects the W-phase drive signal as the comparison target detection signal SP. That is, the comparison target detection signal SP and the center tap voltage CT are input to the comparator 15 of the motor drive control device 1 as the W-phase drive signal. The comparator 15 sets the output signal CMP_OUT to a high level when the comparison target detection signal SP is higher than the center tap voltage CT, and sets the output signal CMP_OUT to a low level when the comparison target detection signal SP is lower than the center tap voltage CT. And

  The motor drive control device 1 samples the value of the output signal CMP_OUT of the comparator 15 when the BEMF interrupt occurs. This operation corresponds to the operation in step S23 of FIG. In the example shown in FIG. 25, the output signal CMP_OUT sampled by the PWM demodulator 21 is shown as the output signal CMP_OUT of the comparator 15.

  In the example shown in FIG. 25, the output signal CMP_OUT of the comparator 15 erroneously determines the voltage relationship between the comparison target detection signal SP and the center tap voltage CT (for example, the output signal of the comparator 15 has a pulse waveform). Period) exists. This phenomenon occurs due to noise input to the comparator 15 or the operation of the alternate PWM method.

  Further, the motor drive control device 1 increases or decreases the comparator integral value based on the value of the sampled output signal CMP_OUT of the comparator 15. More specifically, the motor drive control device 1 determines the comparison target detection signal SP and the center tap voltage CT in a period during which flyback pulse filter processing is performed (for example, a period indicated by the number of continuous PWM pulses FB_MASK). The comparator integral value CMP_INTG is increased regardless of the voltage relationship with. This operation corresponds to the operation in step S44 in FIG. 6 and step S63 in FIG. In addition, when the period during which the flyback pulse filter processing is performed ends, the motor drive control device 1 increases the comparator integral value CMP_INTG when the output signal CMP_OUT of the comparator 15 is at a high level, and the output signal CMP_OUT of the comparator 15 is low. If it is at the level, the comparator integral value CMP_INTG is decreased. This operation corresponds to the operation of steps S70 to S72 in FIG.

  Further, the motor drive control device 1 increases the number of state PWM pulses ST_PWM_PLS every time a PWM cycle timer interrupt occurs. This operation corresponds to the operation in step S41 in FIG. When either one of the first condition and the second condition is satisfied, the motor drive control device 1 changes the state of the PWM signal to the next state. Here, the first condition is that the state PWM pulse number ST_PWM_PLS [0] in the current state (for example, state 0) has reached the moving average state PWM pulse number ST_PWM_PLS_AVE. Note that the moving average state PWM pulse number ST_PWM_PLS_AVE includes a state PWM pulse number ST_PWM_PLS [0] in the previous state (for example, state 0) and a state PWM pulse number ST_PWM_PLS [5] in five states before the previous state. This is a value obtained by dividing the total value of ~ ST_PWM_PLS [1] by 6 which is the number of states. The second condition is that the comparator integral value CMP_INTG has reached a count initial value (for example, zero). The state transition that occurs in response to the first condition corresponds to the operations in steps S84 and S85 in FIG. The transition of the condition that occurs according to the second condition corresponds to the operations of Step S77 and Step S78 in FIG. In the example shown in FIG. 25, an example is shown in which the state transition of the PWM signal is performed in response to the fact that the comparator integral value CMP_INTG has reached zero, that is, the second condition has been satisfied.

  Next, an operation during a period in which the motor drive control device 1 rotates the motor 4 once will be described. The motor drive control device 1 changes the state of the PWM signal six times while rotating the motor 4 once. FIG. 26 shows a timing chart for explaining the drive signals and the center tap voltage in the state 0 to the state 5 when the motor drive control device 1 generates a PWM signal having a duty ratio of 50%. Note that the signal waveforms of the PWM signals UH, UL, VH, VL, WH, WL are equivalent to the signal waveforms of the state 0 described in FIG. 24 and correspond to the state transitions. A detailed description of the waveform is omitted.

  As shown in FIG. 26, in the state 0, the motor drive control device 1 sets the PWM signal WH to the high level and the PWM signal WL to the low level, thereby setting the W-phase drive signal to the non-energized phase. On the other hand, the motor drive control device 1 controls the PWM signals UH, UL, VH, and VL to flow a drive current from the U phase to the V phase in the on state, and outputs the U phase and V phase drive signals in the off state. High side off state or low side off state. As a result, the center tap voltage CT causes a voltage fluctuation corresponding to the voltage fluctuation of the W-phase drive signal.

  Further, in the state 1, the motor drive control device 1 sets the PWM signal VH to the high level and the PWM signal VL to the low level, thereby setting the V-phase drive signal to the non-conduction phase. On the other hand, the motor drive control device 1 controls the PWM signals UH, UL, WH, WL to flow a drive current from the U phase to the W phase in the on state, and outputs the U phase and W phase drive signals in the off state. High side off state or low side off state. As a result, the center tap voltage CT causes a voltage fluctuation corresponding to the voltage fluctuation of the V-phase drive signal.

  Further, in the state 2, the motor drive control device 1 sets the PWM signal UH to the high level and the PWM signal UL to the low level, thereby setting the U-phase drive signal to the non-energized phase. On the other hand, the motor drive control device 1 controls the PWM signals VH, VL, WH, WL to flow a drive current from the V phase to the W phase in the on state, and outputs the V phase and W phase drive signals in the off state. High side off state or low side off state. As a result, the center tap voltage CT causes a voltage fluctuation corresponding to the voltage fluctuation of the U-phase drive signal.

  Further, in the state 3, the motor drive control device 1 sets the PWM signal WH to the high level and the PWM signal WL to the low level to set the W-phase drive signal to the non-energized phase. On the other hand, the motor drive control device 1 controls the PWM signals UH, UL, VH, and VL to flow a drive current from the V phase to the U phase in the on state, and outputs the V phase and U phase drive signals in the off state. High side off state or low side off state. As a result, the center tap voltage CT causes a voltage fluctuation corresponding to the voltage fluctuation of the W-phase drive signal.

  Further, in the state 4, the motor drive control device 1 sets the PWM signal VH to the high level and the PWM signal VL to the low level, thereby setting the V-phase drive signal to the non-conduction phase. On the other hand, the motor drive control device 1 controls the PWM signals UH, UL, WH, WL to flow a drive current from the W phase to the U phase in the on state, and outputs the W phase and U phase drive signals in the off state. High side off state or low side off state. As a result, the center tap voltage CT causes a voltage fluctuation corresponding to the voltage fluctuation of the V-phase drive signal.

  Further, in the state 5, the motor drive control device 1 sets the PWM signal UH to the high level and the PWM signal UL to the low level to set the U-phase drive signal to the non-energized phase. On the other hand, the motor drive control device 1 controls the PWM signals VH, VL, WH, WL to flow a drive current from the W phase to the V phase in the on state, and outputs the W phase and V phase drive signals in the off state. High side off state or low side off state. As a result, the center tap voltage CT causes a voltage fluctuation corresponding to the voltage fluctuation of the U-phase drive signal.

  Subsequently, FIG. 27 shows a timing chart for explaining the operation of the motor drive control device 1 in the state 0 to the state 5 when the motor drive control device 1 generates a PWM signal having a duty ratio of 50%. The operations related to the flyback pulse filter, the comparator integral value CMP_INTG, and the number of state PWM pulses ST_PWM_PLS are the same as the operations in the state 0 described with reference to FIG. To do.

  As shown in FIG. 27, the motor drive control device 1 selects the W-phase drive signal as the comparison target detection signal SP in the state 0, and selects the V-phase drive signal as the comparison target detection signal SP in the state 1. A U-phase drive signal is selected as the comparison target detection signal SP in the state 2, a W-phase drive signal is selected as the comparison target detection signal SP in the state 3, and a V-phase drive signal is selected as the comparison target detection signal SP in the state 4. And the U-phase drive signal is selected as the comparison target detection signal SP in the state 5. In each state, the comparison target detection signal SP and the center tap voltage CT are compared by the comparator 15.

  Then, a comparator integral value CMP_INTG is calculated based on the value of the output signal CMP_OUT of the comparator 15. At this time, the comparator integral value CMP_INTG shows a fluctuation that decreases after increasing in the even-numbered state, and shows a fluctuation that increases after decreasing in the odd-numbered state. In the example shown in FIG. 27, in any state, there is a state in which the comparator 15 erroneously determines the voltage relationship between the two input signals. However, the motor drive control device 1 can detect the rotor position by detecting a zero cross between the comparison target detection signal SP and the center tap voltage CT when the comparator integral value CMP_INTG becomes zero.

  Further, the motor drive control device 1 calculates the moving average state PWM pulse number ST_PWM_PLS_AVE used in the next state from the total value of the current state and the number of state PWM pulses ST_PWM_PLS in five states before the current state. Then, the motor drive control device 1 satisfies that either the state PWM pulse number ST_PWM_PLS has reached the moving average state PWM pulse number ST_PWM_PLS_AVE or the comparator integral value CMP_INTG has reached zero. In response to this, the state of the PWM signal is changed.

  Next, the operation of the motor drive control device 1 when the duty ratio of the PWM signal is 100% will be described. FIG. 28 is a timing chart for explaining the drive signals and the center tap voltage in the state 0 to the state 5 when a PWM signal having a duty ratio of 100% is generated. As shown in FIG. 28, in the state 0, the motor drive control device 1 brings the high-side transistor PU and the low-side transistor NV serving as the path of the drive current into a conductive state. Therefore, the motor drive control device 1 sets only the PWM signal UH and the PWM signal VL to the on state, and sets the other PWM signals to the off state. As a result, a potential variation according to the rotor position occurs in the W-phase drive signal that is the non-energized phase.

  In the state 1, the motor drive control device 1 brings the high-side transistor PU and the low-side transistor NW, which are driving current paths, into a conductive state. Therefore, the motor drive control device 1 sets only the PWM signal UH and the PWM signal WL to the on state, and sets the other PWM signals to the off state. As a result, a potential variation in accordance with the rotor position occurs in the V-phase drive signal that is a non-energized phase.

  In the state 2, the motor drive control device 1 brings the high-side transistor PV and the low-side transistor NW, which are driving current paths, into a conductive state. Therefore, the motor drive control device 1 sets only the PWM signal VH and the PWM signal WL to the on state, and sets the other PWM signals to the off state. As a result, a potential fluctuation according to the rotor position occurs in the U-phase drive signal that is a non-conduction phase.

  In the state 3, the motor drive control device 1 brings the high-side transistor PV and the low-side transistor NU serving as the drive current path into a conductive state. Therefore, the motor drive control device 1 sets only the PWM signal VH and the PWM signal UL to the on state, and sets the other PWM signals to the off state. As a result, a potential variation according to the rotor position occurs in the W-phase drive signal that is the non-energized phase.

  In state 4, the motor drive control device 1 brings the high-side transistor PW and the low-side transistor NU, which serve as the path of the drive current, into a conductive state. Therefore, the motor drive control device 1 sets only the PWM signal WH and the PWM signal UL to the on state, and sets the other PWM signals to the off state. As a result, a potential variation in accordance with the rotor position occurs in the V-phase drive signal that is a non-energized phase.

  In the state 5, the motor drive control device 1 brings the high-side transistor PW and the low-side transistor NV serving as a drive current path into a conductive state. Therefore, the motor drive control device 1 sets only the PWM signal WH and the PWM signal VL to the on state, and sets the other PWM signals to the off state. As a result, a potential fluctuation according to the rotor position occurs in the U-phase drive signal that is a non-conduction phase.

  Subsequently, FIG. 29 shows a timing chart for explaining the operation of the motor drive control device 1 in the state 0 to the state 5 when the motor drive control device 1 generates a PWM signal having a duty ratio of 100%. The operations related to the flyback pulse filter, the comparator integral value CMP_INTG, and the number of state PWM pulses ST_PWM_PLS are the same as the operations in the state 0 described with reference to FIG. To do.

  As shown in FIG. 29, the motor drive control device 1 selects the W-phase drive signal as the comparison target detection signal SP in the state 0, and selects the V-phase drive signal as the comparison target detection signal SP in the state 1. A U-phase drive signal is selected as the comparison target detection signal SP in the state 2, a W-phase drive signal is selected as the comparison target detection signal SP in the state 3, and a V-phase drive signal is selected as the comparison target detection signal SP in the state 4. And the U-phase drive signal is selected as the comparison target detection signal SP in the state 5. In each state, the comparison target detection signal SP and the center tap voltage CT are compared by the comparator 15.

  Then, a comparator integral value CMP_INTG is calculated based on the value of the output signal CMP_OUT of the comparator 15. At this time, the comparator integral value CMP_INTG shows a fluctuation that decreases after increasing in the even-numbered state, and shows a fluctuation that increases after decreasing in the odd-numbered state. In the example shown in FIG. 29, in any state, the comparator 15 correctly determines the voltage relationship between the two input signals without causing erroneous determination. This is because the rotation speed of the motor 4 is high and the time of one state is short (that is, the number of state PWM pulses ST_PWMPLS is small), so that the gradient of potential change in the non-conduction phase is large. Therefore, a period in which the potential difference between the two signals input to the comparator 15 is small is small. For this reason, when the rotation speed of the motor 4 is high, the probability that the comparator 15 erroneously determines the voltage relationship of the input signal is small. Further, since the gradient of the potential change in the non-energized phase is large, the influence of the input offset of the comparator 15 on the comparator integral value CMP_INTG is reduced. In the motor drive control device 1, a zero cross between the comparison target detection signal SP and the center tap voltage CT is detected when the comparator integral value CMP_INTG becomes zero. The position detection accuracy can be maintained.

  Further, the motor drive control device 1 calculates the moving average state PWM pulse number ST_PWM_PLS_AVE used in the next state from the total value of the current state and the number of state PWM pulses ST_PWM_PLS in five states before the current state. Then, the motor drive control device 1 satisfies that either the state PWM pulse number ST_PWM_PLS has reached the moving average state PWM pulse number ST_PWM_PLS_AVE or the comparator integral value CMP_INTG has reached zero. In response to this, the state of the PWM signal is changed.

  Next, a method for generating a PWM signal in the motor drive control device 1 according to the first embodiment will be described with reference to specific waveforms. That is, the PWM premodulation process shown in FIG. 15 in the motor drive control device 1 according to the first embodiment will be described here. The motor drive control device 1 determines the duty ratio of the PWM signal based on the on-time PWM_ON of the PWM signal determined in the regulation loop arbitration process of FIG.

  First, FIG. 30 shows a timing chart showing the procedure for determining the on-time PWM of the PWM signal when the duty ratio of the PWM signal determined in the regulation loop arbitration process is larger than the maximum duty set value. As shown in FIG. 30, in this case, in the original PWM signal generated based on the duty ratio of the PWM signal determined by the regulation loop arbitration process, the on-time PWM_ON of the PWM signal becomes longer than the maximum duty set value MAX_DUTY. Therefore, a value obtained by subtracting the PWM signal cycle PWM_TRM from the PWM signal on-time PWM_ON is calculated as a carry-on on-time CRY_PWM_ON. Then, the same value as the PWM signal period PWM_TRM is set as the on-time PWM_ON of the PWM signal having the period TRM1. In this case, the motor drive control device 1 generates the BEMF timer interrupt of the cycle TRM1 slightly before the cycle timer interrupt. Then, in the cycle TRM2 next to the cycle TRM1, the on-time PWM_ON of the PWM signal in the cycle TRM2 is calculated by adding the carry-on on-time CRY_PWM_ON calculated in the cycle TRM1 to the on-time PWM_ON of the PWM signal.

  By determining the on-time PWM_ON of the PWM signal as shown in FIG. 30, it is possible to generate a PWM signal having a duty ratio larger than the maximum duty ratio determined by the limit of the hardware. This process corresponds to the process of steps S140 to S142 in FIG.

  Next, FIG. 31 shows a timing chart showing the procedure for determining the on-time PWM of the PWM signal when the duty ratio of the PWM signal determined in the regulation loop arbitration process is smaller than the minimum duty set value. As shown in FIG. 31, in this case, in the original PWM signal generated based on the duty ratio of the PWM signal determined by the regulation loop arbitration process, the on-time PWM_ON of the PWM signal becomes shorter than the minimum duty set value MIN_DUTY. Therefore, the on-time PWM_ON of the PWM signal is calculated as the carry-on on-time CRY_PWM_ON. Then, zero is set as the on-time PWM_ON of the PWM signal of the cycle TRM2. In this case, the motor drive control device 1 does not generate a BEMF timer interrupt because there is no on-time in the cycle TRM2. Then, in the period TRM3 next to the period TRM2, the on-time PWM_ON of the PWM signal in the period TRM2 is calculated by adding the carry-on on-time CRY_PWM_ON calculated in the period TRM2 to the on-time PWM_ON of the PWM signal.

  By determining the on-time PWM_ON of the PWM signal as shown in FIG. 31, it is possible to generate a PWM signal having a duty ratio smaller than the minimum duty ratio determined by the hardware limit. This process corresponds to the processes in steps S143 to S145 in FIG.

  Subsequently, FIG. 32 is a timing chart showing the procedure for determining the on-time PWM of the PWM signal when the duty ratio of the PWM signal determined in the regulation loop arbitration process is not less than the minimum duty set value and not more than the maximum duty set value. Show. As shown in FIG. 32, in this case, the original PWM signal generated based on the duty ratio of the PWM signal determined by the regulation loop arbitration process has an on-time PWM_ON of the PWM signal longer than the minimum duty set value MIN_DUTY, and , Becomes shorter than the maximum duty set value. Therefore, the motor drive control device 1 sets the carry-on on-time CRY_PWM_ON to zero and generates a PWM signal having the same on-time as the original PWM signal. This process corresponds to the process in step S146 of FIG.

  From the above description, in the motor drive control program and the motor drive control apparatus 1 according to the first embodiment, the rotor position is detected based on the comparator integral value CMP_INTG. Then, the state of the PWM signal is changed based on the rotor position detection result. Here, the comparator 15 generally has misjudgment factors such as input offset and input noise. However, in the comparator integral value CMP_INTG, even if an erroneous determination occurs in the comparator 15, the erroneous determination components are canceled out by a plurality of erroneous determination components that are converted into alternating current by generating the PWM signal in the alternate PWM method. The Therefore, by detecting the rotor position based on the comparator integral value CMP_INTG, the rotor position can be detected with high accuracy regardless of the erroneous determination factor of the comparator 15. In particular, when the motor 4 is rotating at a low speed, the voltage change in the non-energized phase is gradual, and the frequency of erroneous determination increases. However, by detecting the rotor position based on the comparator integral value CMP_INTG, even if the rotational speed of the motor 4 is low, the rotor position detection accuracy is not lowered. For this reason, the motor drive control program and the motor drive control device 1 according to the first embodiment can perform highly accurate rotor position detection regardless of the rotation speed of the motor 4. Controllability can be improved.

  Further, in the conventional motor driving method, there is a problem that it is difficult to eliminate the time difference between a plurality of states used while the motor is rotated once. For example, in a conventional motor driving method, a zero cross between the center tap voltage CT and the drive signal or a zero cross between the reference voltage and the drive signal is detected using a comparator, and the state transition timing of the PWM signal is determined based on the detection result. It was calculated. For example, when the zero cross between the center tap voltage CT and the drive signal is detected using a comparator, the detection timing of the zero cross is shifted between the odd-numbered state and the even-numbered state due to the input offset voltage of the comparator, There is a time difference between the states. In addition, when a zero cross between the reference voltage and the drive signal is detected using a comparator, the deviation in the detection timing of the zero cross can be eliminated by dynamically changing the reference voltage for each state. There is a problem that it is difficult to converge to a stable state due to recursive behavior. When there is a time difference between states, the average power increases in a relatively long state, and the average power decreases in a relatively short state. When such a phenomenon occurs, the rotational torque and rotational speed during one rotation of the motor become unstable, causing a problem that a beat is generated. Further, when there is a time difference between the states, the maximum rotational torque or the maximum rotational speed is generated in a relatively long state, but in the relatively short state, the maximum rotational torque or the maximum rotational speed cannot be generated. That is, there is a problem that the maximum rotation torque or maximum rotation speed cannot be generated through one rotation, and the average maximum torque or maximum rotation speed generated through one rotation decreases.

  However, in the motor drive control program and the motor drive control apparatus 1 according to the first embodiment, the moving average state PWM pulse number ST_PWM_PLS_AVE used in the next state is calculated from the total value of the six states including the current state. In the motor drive control program and the motor drive control device 1 according to the first embodiment, when the state PWM pulse number ST_PWM_PLS reaches the moving average state PWM pulse number ST_PWM_PLS_AVE, the comparator integral value CMP_INTG does not reach zero. Transition the PWM signal to the next state. By forcibly changing the state of the PWM signal in this way, even when the time until the comparator integral value CMP_INTG reaches zero is longer than the average value of the six previous states, the state of the PWM signal is changed. The time difference between states can be eliminated. That is, in the motor drive control program and the motor drive control device 1 according to the first embodiment, the period of a relatively long state is forcibly shortened only by the control based on the comparator integral value CMP_INTG. Only the control based on the value CMP_INTG is used to lengthen the period of the relatively short state. In this way, by eliminating the time difference between the states, the motor drive control program and the motor drive control device 1 according to the first embodiment can stably drive the motor to a lower speed. In addition, in the motor drive control program and the motor drive control device 1 according to the first embodiment, it is possible to maintain a constant rotational torque or rotational speed through one rotation, and thus it is possible to prevent the occurrence of beats. Further, in the motor drive control program and the motor drive control device 1 according to the first embodiment, the time difference between the states can be eliminated, so that the maximum rotation torque or the maximum rotation speed can be exhibited through one rotation, and the rotation efficiency of the motor Can be improved.

  Further, by performing the operation by the alternate PWM method, the motor drive control program and the motor drive control device 1 according to the first embodiment reduce the influence of the input offset and the input noise of the comparator 15 on the comparator integral value CMP_INTG. Can do. Thereby, the motor drive control program and the motor drive control device 1 according to the first embodiment can further improve the accuracy of the state transition timing of the PWM signal when the motor 4 rotates at a low speed. Note that the alternate PWM method operation of the motor drive control program and the motor drive control device 1 according to the first embodiment includes a synchronous rectification operation, and has an effect of improving power efficiency.

  Further, in the motor drive control program and the motor drive control device 1 according to the first embodiment, even if the duty ratio of the PWM signal exceeds the maximum duty ratio or the minimum duty ratio on hardware, a plurality of cycles One pulse is generated using the PWM signal. As a result, the motor drive control program and the motor drive control apparatus 1 according to the first embodiment can generate a PWM signal having a duty ratio that exceeds the limit of the maximum duty ratio or the minimum duty ratio on hardware. Since the setting range of the duty ratio of the PWM signal is wide, the motor drive control program and the motor drive control device 1 according to the first embodiment expand the control range of the motor 4 as compared with the conventional general motor control device. be able to.

  In the motor drive control program and the motor drive control device 1 according to the first embodiment, stacking of the rotor can be prevented. When the acceleration amount of the rotor is too high, stacking occurs when the rotational speed of the rotor exceeds the speed control and overshoots and the phase difference between the rotor rotation and the stator rotating magnetic field is 180 °. If a signal having a phase difference of 180 ° is negatively fed back with a gain of 1 or more, abnormal oscillation (rotor stack) may be caused. The same applies to deceleration. However, in the motor drive control program and the motor drive control device 1 according to the first embodiment, as shown in step S101 of FIG. 11, the maximum allowable acceleration or the maximum allowable reduction obtained by multiplying the current rotational speed by a coefficient. Limit the amount of negative feedback of speed error according to speed. That is, in the motor drive control program and the motor drive control device 1 according to the first embodiment, the acceleration or deceleration is limited to a certain level. That is, in the motor drive control program and the motor drive control device 1 according to the first embodiment, the negative feedback amount is limited by limiting the acceleration / deceleration, and the overshoot / undershoot of the rotation speed is prevented from the control speed. be able to. That is, in the motor drive control program and the motor drive control device 1 according to the first embodiment, it is possible to remove the cause of the rotor stacking and prevent the rotor from stacking.

  Furthermore, in the motor drive control program and the motor drive control device 1 according to the first embodiment, it is possible to prevent the motor from being twisted due to the stacking of the rotor. Prevention of a roaring sound after the occurrence of stacking is performed by a speed control loop. During stacking, a rotating magnetic field is generated beyond the original rotational speed range (the state changes rapidly in a short time). At this time, the speed control loop tries to reduce the rotational speed by reducing the PWM duty (this is equivalent to rotating the rotor without loss, so the rotational speed of the rotating magnetic field during stacking actually decreases. As a result, the PWM duty approaches zero as much as possible, resulting in a decrease in driving power and squealing noise.

  Further, in the motor drive control program and the motor drive control apparatus 1 according to the first embodiment, it is detected that stacking has occurred in response to the 6-state total PWM pulse number TTL_ST_PWM_PLS being smaller than the stack rotor detection set value. To do. In the motor drive control program and the motor drive control apparatus 1 according to the first embodiment, when stacking of the motor 4 is detected, the control can be restarted from the initial state again (step S7 in FIG. 3). Thereby, in the motor drive control program and the motor drive control apparatus 1 according to the first embodiment, the motor 4 can be made to escape from the stacking state.

  Further, in the motor drive control program and the motor drive control device 1 according to the first exemplary embodiment, only the timer interrupt (in the above description, the BEMF timer interrupt and the periodic timer interrupt) is used to switch the PWM signal between the on state and the off state and the PWM signal. Change the cycle. More specifically, in the motor drive control program and the motor drive control device 1 according to the first embodiment, the duty of the PWM signal of the next cycle is generated in response to the occurrence of a cycle timer interrupt that shifts the cycle of the PWM signal to the next cycle. It is determined whether to determine the ratio and change the state. In the motor drive control program and the motor drive control device 1 according to the first embodiment, the value of the output signal CMP_OUT of the comparator 15 is sampled and the PWM signal is switched from the on state to the off state in response to the BEMF timer interrupt. Do. As described above, in the motor drive control program and the motor drive control device 1 according to the first embodiment, it is possible to reduce the computing ability required for the computing core 10 by setting only the interrupt factor as the interrupt factor. That is, since a computing core with high computing capability is not required, the motor drive control program and the motor drive control device 1 according to the first embodiment can be executed or realized in more microcomputers.

  Further, in the motor drive control program and the motor drive control apparatus 1 according to the first embodiment, the output signal CMP_OUT of the comparator 15 is sampled in response to the BEMF timer interrupt. That is, the motor drive control program and the motor drive control device 1 according to the first embodiment can always sample the output signal CMP_OUT of the comparator 15 at the time closest to the on-state of the PWM signal. In general, the end of the on-state of the PWM signal is the time when the values of the center tap voltage CT and the comparison target detection signal SP are most stable. By sampling the output signal CMP_OUT of the comparator 15 at this timing, more accurate accuracy can be obtained. High zero cross detection is possible.

  Here, in the motor drive control program and the motor drive control apparatus 1 according to the first embodiment, the output signal CMP_OUT of the comparator 15 is sampled in response to the BEMF timer interrupt, which corresponds to the operation of the PWM demodulation process. . In this way, by sampling the output signal CMP_OUT of the comparator 15 by the PWM demodulation process, the motor drive control program and the motor drive control device 1 according to the first embodiment perform band notch filtering on the pulse of the PWM signal by digital sampling. Because it does not need an analog filter. This is because the timing at which the BEMF timer interrupt occurs is immediately before the end of the on-state of the PWM signal, and therefore the influence of the pulse generated in the off-state of the PWM signal does not affect the value to be sampled. For this reason, according to the motor drive control program and the motor drive control apparatus 1 according to the first embodiment, it is not necessary to provide an analog filter or the like for filtering the pulse of the PWM signal. It is possible to reduce the area.

  In the motor drive control program and the motor drive control device 1 according to the first embodiment, the selector 14 selects a drive signal that is a non-conduction phase among the three drive signals as the comparison target drive signal SP, and the single comparator compares the drive signal SP. A comparison process between the comparison target drive signal SP and the center tap voltage CT is performed. That is, in the motor drive control program and the motor drive control device 1 according to the first embodiment, no channel error occurs in the comparison operation for the three-phase drive signals. For this reason, according to the motor drive control program and the motor drive control device 1 according to the first embodiment, it is possible to improve the comparison accuracy between the comparison target drive signal SP and the center tap voltage CT.

  In the conventional motor control method, the PWM signal is switched from the on state to the off state in accordance with the monitoring result of the drive current. For example, in the conventional motor control method, the PWM signal is shifted from the on state to the off state in response to the drive current exceeding the reference current value. At this time, in a general control loop, a predetermined delay time is generated after the drive current is monitored and the monitoring result is reflected in the output. When PWM generation is performed, the minimum duty ratio of the PWM signal is determined by this delay time.

  Here, when performing constant current drive control, the average input current is reduced while keeping the pulse input current constant when the load torque increases. At this time, since the average output drive current is constant, it is possible to prevent the rotor permanent magnet from being demagnetized. In addition, if the static torque of the load is heavier than the driving torque that can be covered with a constant driving current, the motor 4 cannot be started. Also, if the rotor is mechanically constrained, the current limit will not function if a current with a pulse width shorter than the minimum duty ratio cannot be generated. If the current limit does not work, the power MOSFET may burn out. If this state continues, there is a problem that the permanent magnet is demagnetized due to the temperature rise of the rotor.

  Further, when the PWM signal is turned off based on the monitoring result of the drive current, when the turn-off timing of the power MOSFET due to current limitation occurs depends on the load state. For this reason, another problem arises in which it is uncertain at what timing the voltage value of the drive signal of the non-energized phase is sampled. As a result, as soon as the constant current drive control becomes active, it becomes impossible to continue the sensorless rotation control, and if the rotation of the motor 4 cannot be detected, the sequence of temporarily stopping the drive and restarting it after a while Required.

  On the other hand, in the motor drive control program and the constant current drive control in the motor drive control device 1 according to the first embodiment, the pulse input current increases when the load torque increases, but the average input current can be kept constant. Is possible. The motor drive control program and the motor drive control device 1 according to the first embodiment increase the average output drive current and rotate the motor 4 with constant power. Thereby, in the motor drive control program and the motor drive control apparatus 1 according to the first embodiment, it is possible to rotate the rotor even when heavy static torque becomes a load.

  Further, when the motor 4 is mechanically restricted and a current having a pulse width shorter than the minimum duty ratio is requested, the motor drive control program and the motor drive control device 1 according to the first embodiment have a PWM premodulator of 0%. By inserting a duty skip pulse, control is performed so that the average input current is held constant as a result. Thereby, the possibility that the power MOSFET is burned out can be prevented.

  Further, in the design in which the PWM demodulator 21 drives the PWM modulator 22, it is determinative when the power MOSFET is turned off. Can be sampled at an appropriate timing, and rotation can be continued.

Embodiment 2
In the second embodiment, a modified example of the operation of the alternate PWM method described in the first embodiment will be described. FIG. 33 to FIG. 38 are diagrams for explaining the operation of the alternate PWM method based on the PWM signal generated by the motor drive control program according to the second embodiment. 33 to 38 correspond to the circuit diagrams of FIGS. 17 to 22. In FIGS. 33 to 38, components corresponding to FIGS. 17 to 22 are denoted by the same reference numerals and description thereof is omitted. To do.

  FIG. 33 is a block diagram of a driver circuit for explaining the operation of the alternate PWM method in the state 0 of the motor drive control device according to the second embodiment. As shown in FIG. 33, in the second embodiment, the low side transistor NW is turned on in addition to the low side transistors NU and NV in the high side off state of the state 0. In the second embodiment, the high side transistor PW is turned on in addition to the high side transistors PU and PV in the low side off state of the state 0.

  FIG. 34 is a block diagram of a driver circuit for explaining the operation of the alternate PWM method in the state 1 of the motor drive control apparatus according to the second embodiment. As shown in FIG. 34, in the second embodiment, the low side transistor NV is turned on in addition to the low side transistors NU and NW in the high side off state of state 1. In the second embodiment, in the low-side off state of state 1, the high-side transistor PV is turned on in addition to the high-side transistors PU and PW.

  FIG. 35 is a block diagram of a driver circuit for explaining the operation of the alternate PWM method in the state 2 of the motor drive control apparatus according to the second embodiment. As shown in FIG. 35, in the second embodiment, the low-side transistor NU is turned on in addition to the low-side transistors NV and NW in the high-side off state of state 2. In the second embodiment, in the low-side off state of state 2, the high-side transistor PU is turned on in addition to the high-side transistors PV and PW.

  FIG. 36 is a block diagram of a driver circuit for explaining the operation of the alternate PWM method in the state 3 of the motor drive control device according to the second embodiment. As shown in FIG. 36, in the second embodiment, the low side transistor NW is turned on in addition to the low side transistors NV and NU in the high side off state of the state 3. In the second embodiment, the high side transistor PW is turned on in addition to the high side transistors PV and PU in the low side off state of the state 3.

  FIG. 37 is a block diagram of a driver circuit for explaining the operation of the alternate PWM method in the state 4 of the motor drive control apparatus according to the second embodiment. As shown in FIG. 37, in the second embodiment, the low-side transistor NV is turned on in addition to the low-side transistors NW and NU in the high-side off state of state 4. In the second embodiment, the high side transistor PV is turned on in addition to the high side transistors PW and PU in the low side off state of the state 4.

  FIG. 38 is a block diagram of the driver circuit for explaining the operation of the alternate PWM method in the state 5 of the motor drive control apparatus according to the second embodiment. As shown in FIG. 37, in the second embodiment, the low-side transistor NU is turned on in addition to the low-side transistors NV and NW in the high-side off state of state 5. In the second embodiment, in the low-side off state of state 5, the high-side transistor PU is turned on in addition to the high-side transistors PV and PW.

  By performing such an operation of the alternate PWM method, in the first embodiment, the flyback current consumed by the body diode of the transistor of the drive stage circuit corresponding to the non-energized phase that is in the OFF state is changed to the ON state. It can be consumed in the transistor. Such an operation functions as a regenerative brake for the rotor. Therefore, FIG. 39 shows a graph comparing the input / output characteristics with and without the regenerative braking operation. As shown in FIG. 39, it can be seen that when the regenerative braking operation is performed, the rotation speed when the input power is small is lower than when the regenerative braking operation is not performed. In addition, when the range of the input power is the same, it can be seen that the rotation speed range of the motor 4 is wider when the regenerative braking operation is performed.

  Here, a description will be given of a PWM signal when an alternate PWM system operation involving a regenerative braking operation is performed. FIG. 40 is a timing chart for explaining the state 0 drive signal and the center tap voltage when a PWM signal with a duty ratio of 50% is generated in the motor drive control apparatus according to the second embodiment. As shown in FIG. 40, when the regenerative braking operation is performed, a pulse is also given to the PWM signals WH and WL corresponding to the W-phase drive signal that is the non-energized phase in the state 0. More specifically, the PWM signal WH is at a low level during the low side off-state period, and is maintained at a high level during other periods. Further, the PWM signal WL is at a high level during the high-side off-state period, and is maintained at a low level during other periods. Thereby, the regenerative braking operation is performed in the high-side off-state period and the low-side off-state period.

  Subsequently, FIG. 41 is a timing chart for explaining the operation of the drive signal and the center tap voltage in the state 0 to the state 5 when the PWM signal having the duty ratio of 50% is generated in the motor drive control device according to the second embodiment. Show. As shown in FIG. 41, in the state 1 to the state 5, similarly to the state 0, the pulse for the regenerative braking operation is given to the PWM signal corresponding to the drive signal that is in the non-energized phase.

  From the above description, according to the motor drive control program according to the second embodiment, all the low-side transistors are turned on in the high-side off-state period, and all the high-side transistors are turned on in the low-side off-state period. Thereby, the motor drive control program according to the second embodiment performs the regenerative braking operation in the high side off-state period and the low side off-state period. Since the regenerative braking operation suppresses the rotation speed of the motor 4, the motor 4 can be rotated at a lower rotation speed with respect to the same input power. At this time, the effectiveness of the regenerative brake increases as the duty ratio of the PWM signal decreases. That is, by performing the regenerative braking operation, the rotation speed of the motor 4 becomes lower on the low speed side and is equivalent to the case where there is no regenerative braking operation on the high speed side. Therefore, according to the motor drive control program according to the second embodiment, the control range of the rotation speed of the motor 4 can be expanded with respect to the same input power range.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, the present invention includes the following inventions from another viewpoint.

(Appendix 1)
An arithmetic core that transitions the state of the PWM signal generated according to the rotational position of the motor;
An output interface for outputting the PWM signal to the motor via a driver circuit;
A comparator that compares a comparison target detection signal selected from the three-phase drive signal generated by the driver circuit based on the PWM signal with a center tap voltage of the motor, and the motor that is executed by the arithmetic core in the processor. A drive control program comprising:
The PWM signal count number obtained by counting the number of pulses of the PWM signal in the current state of the PWM signal is an average PWM signal pulse number indicating the average number of pulses of the PWM signal in each state that has been changed during one rotation of the motor. Detecting that the rotational position of the motor has transitioned in response to reaching,
A motor drive control program for changing the state of the PWM signal to the next state according to the detection result.

(Appendix 2)
When the output of the comparator indicates that the center tap voltage is lower than the comparison target detection signal, the comparator integral value is counted up, and the output of the comparator is higher than the comparison target detection signal. Count down the comparator integral,
When the PWM signal count number obtained by counting the number of pulses of the PWM signal in the current state of the PWM signal reaches the initial count value before the average PWM signal pulse number, the comparator integral value Detecting that the rotational position of the motor has changed based on
The motor drive control program according to appendix 1, wherein the state of the PWM signal is changed to the next state according to the detection result.

(Appendix 3)
An arithmetic core that transitions the state of the PWM signal generated according to the rotational position of the motor;
An output interface for outputting the PWM signal to the motor via a driver circuit;
A comparator that compares a comparison target detection signal selected from the three-phase drive signal generated by the driver circuit based on the PWM signal with a center tap voltage of the motor, and the motor that is executed by the arithmetic core in the processor. A drive control program comprising:
A duty ratio of the PWM signal is calculated from a current error indicating an error between a drive current flowing through the driver and a current instruction value or a rotation error indicating an error between the rotation speed of the motor and the rotation speed instruction value;
When the pulse width of the PWM signal calculated from the duty ratio is less than the minimum pulse width, one ON pulse is generated by adding the ON periods of the PWM signals having a plurality of cycles, and exceeds the maximum pulse width A motor drive control program for generating one off pulse by adding off periods of the PWM signals having a plurality of cycles.

(Appendix 4)
An arithmetic core that transitions the state of the PWM signal generated according to the rotational position of the motor;
An output interface for outputting the PWM signal to the motor via a driver circuit;
A comparator that compares a comparison target detection signal selected from the three-phase drive signal generated by the driver circuit based on the PWM signal with a center tap voltage of the motor, and the motor that is executed by the arithmetic core in the processor. A drive control program comprising:
When a rotation error indicating an error between the rotation speed of the motor and a rotation speed instruction value exceeds a preset maximum allowable acceleration, the rotation error is the maximum allowable acceleration,
When the rotation error is smaller than a preset maximum allowable deceleration, the rotation error is the maximum allowable deceleration,
Calculate the duty ratio of the PWM signal based on the rotation error,
A motor drive control program for generating the PWM signal having the duty ratio.

(Appendix 5)
An arithmetic core that transitions the state of the PWM signal generated according to the rotational position of the motor;
An output interface for outputting the PWM signal to the motor via a driver circuit;
A comparator that compares a comparison target detection signal selected from the three-phase drive signal generated by the driver circuit based on the PWM signal with a center tap voltage of the motor, and the motor that is executed by the arithmetic core in the processor. A drive control program comprising:
The stop state of the motor in response to the total number of PWM signal pulses indicating the number of pulses of the PWM signal in a plurality of states used during a period of one rotation of the motor being smaller than a preset rotor stack detection value Drive control program for detecting motor.

(Appendix 6)
The motor drive control program according to appendix 5, wherein the rotor stack detection value is set with the number of pulses of the PWM signal generated during a period in which the motor makes one rotation at a maximum rotation speed defined for the motor.

(Appendix 7)
There are three sets of drive stage circuits in which a high side transistor and a low side transistor are connected in series between a power supply line and a ground line, and the high side transistor and the low side of the two selected sets of drive stage circuits A calculation core that outputs a PWM signal to a driver circuit that is controlled to be in a conductive state exclusively with a transistor, and changes the state of the PWM signal according to the rotational position of the motor;
A processor having a comparator for comparing a comparison target detection signal output from the non-selected drive stage circuit among the three-phase drive signals generated by the driver circuit based on the PWM signal and a center tap voltage of the motor; A motor drive control program executed by the arithmetic core,
By the PWM signal,
An on state in which a high-side transistor of one set of driving stage circuits among the three sets of driving stage circuits is turned on and a low-side transistor of another set of driving stage circuits is turned on. State and
A high-side off-state in which the low-side transistor of the driving stage circuit in which the high-side transistor is conductive in the on-state is in a conductive state and the low-side transistor in the other set of driving stage circuits is in a conductive state;
Controlling the high-side transistor of the set of driving stage circuits to a conductive state, and the low-side off state of bringing the low-side transistor of the driving stage circuit to a conductive state in the on-state into a conductive state;
A motor drive control program that switches between the high-side off state and the low-side off state for each generation cycle of the PWM signal.

(Appendix 8)
The PWM signal is
In the high-side off-state drive, the low-side transistor of the driving stage circuit in which both the high-side transistor and the low-side transistor are turned off in the on-state is made conductive.
The motor drive control program according to appendix 7, wherein the low-side off-state drive generates the high-side transistor of the drive stage circuit in which both the high-side transistor and the low-side transistor are turned off in the on-state. .

(Appendix 9)
A driver having three sets of driving stage circuits in which a high-side transistor and a low-side transistor are connected in series between the power supply wiring and the ground wiring, and the high-side transistor and the low-side transistor are exclusively controlled to be conductive. An arithmetic core that outputs a PWM signal to the circuit and changes the state of the PWM signal according to the rotational position of the motor;
A motor executed by the arithmetic core in a processor having a comparator that compares a one-phase drive signal selected from three-phase drive signals generated by the driver circuit based on the PWM signal with a center tap voltage of the motor A drive control program for
By the PWM signal, the driver circuit is controlled to an on state in which a current is supplied to the motor and an off state in which the supply of the current to the motor is stopped,
The PWM signal includes a high-side off-state drive that circulates a current that flows to the motor via a ground wiring in the off-state, and a low-side off-state drive that circulates a current that flows to the motor via a power supply wiring. A motor drive control program that is switched every PWM signal generation cycle.

(Appendix 10)
An arithmetic core that transitions the state of the PWM signal generated according to the rotational position of the motor;
An output interface for outputting the PWM signal to the motor via a driver circuit;
A comparator for comparing the comparison target detection signal selected from the three-phase drive signal generated by the driver circuit based on the PWM signal and the center tap voltage of the motor;
A motor drive control program executed by the arithmetic core in a processor having a timer that outputs first and second timer interrupt requests to the arithmetic core according to first and second set values,
Update the first set value with a value corresponding to the on-time period of the PWM signal calculated according to the rotation state of the motor,
In response to a first timer interrupt request generated based on the first set value, the PWM signal is turned off to instruct to stop the drive current from the on state to instruct the supply of the drive current to the motor. Transition to the state,
A motor drive control program for shifting the PWM signal from the off state to the on state in accordance with the second set value.

(Appendix 11)
The motor drive control program according to appendix 10, wherein when the on-time period of the PWM signal is longer than a period of one cycle of the PWM signal, the arithmetic core maintains the PWM signal in an on state.

(Appendix 12)
An arithmetic core that transitions the state of the PWM signal generated according to the rotational position of the motor;
An output interface for outputting the PWM signal to the motor via a driver circuit;
In a processor comprising: a comparison target detection signal selected from a three-phase drive signal generated by the driver circuit based on the PWM signal; and a comparator that compares a center tap voltage indicating a midpoint voltage of the three-phase drive signal. A motor drive control program executed by the arithmetic core,
Increase or decrease the comparator integral value according to the value of the output signal of the comparator,
When the comparator integral value reaches the initial count value during a timeout detection period that defines the maximum period during which one state of the PWM signal continues, the PWM integral value reaches the initial count value in response to the fact that the comparator integral value has reached the initial count value. When the signal state is changed to the next state and the comparator integration value does not reach the initial count value during the timeout detection period, the PWM signal state is changed to the next state as the timeout detection period elapses. Let
The initial value of the drive current for driving the motor is zero,
The drive current is gradually increased every time the state of the PWM signal is changed,
A motor drive control program for determining that the motor has entered an effective rotational state in response to six consecutive transitions of the state of the PWM signal in response to the comparator integrated value reaching the initial count value.

(Appendix 13)
The motor drive control program further includes:
A fly that monotonously increases or decreases the integrated value of the comparator monotonically regardless of the value of the output signal of the comparator during the period until the number of pulses of the PWM signal generated after the state transition reaches the number of continuous pulses of the flyback pulse filter. Perform back pulse filter processing.
13. The motor drive control program according to supplementary note 12, wherein the number of continuous pulses of the hulaback pulse filter before the motor enters an effective rotation state is set smaller than that after the motor enters an effective rotation state.

NU, NV, VW: Low side transistor, PU, PV, PW: High side transistor, Ri: Current detection resistor, SP: Comparison target detection signal, 1: Motor drive control device, 2: Pre-driver circuit, 3: Driver circuit, 4: motor, 10: arithmetic core, 10: arithmetic core, 11: program memory, 12: RAM, 13: output interface, 14: selector, 15: comparator, 16: analog-digital converter, 17: timer, 21: PWM Demodulator 22: PWM modulator 23: Constant current drive controller 24: Rotor position detector 25: Rotation controller 26: Rotational speed controller 27: PWM duty controller

Claims (7)

An arithmetic core that transitions the state of the PWM signal generated according to the rotational position of the motor;
An output interface for outputting the PWM signal to the motor via a driver circuit;
A comparison target detection signal selected from the three-phase drive signal generated by the driver circuit based on the PWM signal and a center tap voltage indicating a midpoint voltage of the three-phase drive signal, or a ground potential from each phase winding terminal A comparator for comparing an artifical center tap voltage synthesized by a voltage dividing resistor network connected to a motor drive control program executed by the arithmetic core in a processor,
Increase or decrease the comparator integral value based on the value of the output signal of the comparator,
Detecting that the rotational position of the motor has transitioned in response to the comparator integral value reaching the initial count value,
A motor drive control program for changing the state of the PWM signal to the next state according to the detection result.   2. The motor drive control program according to claim 1, wherein the comparator integrated value is counted up or down regardless of an output result of the comparator during a predetermined period after the state of the PWM signal transitions.   3. The motor drive control program according to claim 2, wherein the predetermined period is preset as a period of a predetermined ratio of one period during which the state of the PWM signal is maintained.   The motor drive control program according to any one of claims 1 to 3, wherein the comparison target detection signal to be selected is switched in response to detection of a transition of the rotational position of the motor. The driver circuit has three sets of drive stage circuits in which a high side transistor and a low side transistor are connected in series between a power supply line and a ground line, and two sets of the drive stages selected by the PWM signal. The high-side transistor and the low-side transistor of the circuit are controlled to be exclusively conductive;
5. The motor drive control according to claim 1, wherein the comparison target detection signal is a drive signal generated at an output node of a non-selected drive stage circuit among the three sets of drive stage circuits. 6. program. A PWM signal generation circuit that transitions the state of the PWM signal generated according to the rotational position of the motor;
An output interface for outputting the PWM signal to the motor via a driver circuit;
One-phase drive signal selected from the three-phase drive signal generated by the driver circuit based on the PWM signal and the center tap voltage indicating the midpoint voltage of the three-phase drive signal, or grounded from each phase winding terminal A motor driving control method using a motor driving device comprising: a comparator for comparing an artificial center tap voltage synthesized by a voltage dividing resistor network connected to a potential;
Increase or decrease the comparator integral value based on the value of the output signal of the comparator,
Detecting that the rotational position of the motor has transitioned in response to the comparator integral value reaching the initial count value,
A motor drive control method for changing the state of the PWM signal to the next state according to the detection result. A PWM signal generation circuit that transitions the state of the PWM signal generated according to the rotational position of the motor;
An output interface for outputting the PWM signal to the motor via a driver circuit;
One-phase drive signal selected from the three-phase drive signal generated by the driver circuit based on the PWM signal and the center tap voltage indicating the midpoint voltage of the three-phase drive signal, or grounded from each phase winding terminal A comparator for comparing the artifical center tap voltage synthesized by the voltage dividing resistor network connected to the potential;
The PWM signal generation circuit includes:
Increase or decrease the comparator integral value based on the value of the output signal of the comparator,
Detecting that the rotational position of the motor has transitioned in response to the comparator integral value reaching the initial count value,
A motor drive control device that changes the state of the PWM signal to the next state in accordance with the detection result.

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