JP5609523B2 - Receiver circuit - Google Patents

Description

  The present disclosure generally relates to an electronic circuit, and more particularly to a receiving circuit that equalizes a received signal.

  In a signal transmission system, when the transmission line length is long or the signal data rate is high, the signal waveform transmitted from the transmitter is deteriorated by intersymbol interference due to the influence of the frequency characteristics of the transmission line. If the signal waveform is greatly degraded, the signal may not be received correctly. Therefore, it is preferable to provide an equalization circuit in the transmitter and the receiver and perform processing such as timing extraction after removing the intersymbol interference component. In the output obtained by the equalization processing, signal deterioration is reduced to such an extent that a waveform substantially the same as the transmission waveform is restored, and a correct signal can be received. When the characteristics of the transmission line change with time, it is common to apply an adaptive equalization method and dynamically optimize the equalization process following the characteristic variation.

  The adaptive equalization circuit generally includes an equalization circuit, an error calculation circuit, and an adaptive equalization control circuit. The equalization circuit receives a signal waveform deteriorated due to the transmission line, and outputs a signal waveform with reduced signal deterioration by performing equalization processing. The frequency characteristic between the input and output of the equalization circuit is variable and is controlled by the output of the adaptive equalization control circuit. The error calculation circuit calculates an error between the output waveform of the equalization circuit and the ideal waveform. For example, the 0/1 determination result of the equalizer circuit output is set to the ideal waveform signal level, and the difference between this signal level and the signal level of the equalizer circuit output is output from the error calculation circuit as an error. The adaptive equalization control circuit updates the current equalization coefficient so that the integrated value of this error becomes zero. In this way, by adjusting the equalization coefficient, it is possible to realize characteristics of the equalization circuit appropriate for the transmission line.

  In the adaptive equalization circuit as described above, a high-accuracy digital operation with a wide bit width is required to calculate the error amount. As a result, there is a problem that the circuit area and power consumption increase.

JP-A-2005-303607

  In view of the above, a receiving circuit that can realize adaptive equalization processing with a small circuit area and power consumption without requiring a digital operation with a wide bit width is desired.

  The reception circuit performs an equalization process according to the equalization coefficient on the reception signal and outputs an equalized signal, and 0 according to the magnitude relationship between the equalized signal and the first threshold value. And a first signal having a signal value of 1 and a second signal having a signal value of 0 and 1 corresponding to a magnitude relationship between the equalized signal and a second threshold value. An error calculation circuit for calculating a difference between the number of appearances of a predetermined 0 and 1 pattern appearing in the signal and the number of appearances of the predetermined 0 and 1 pattern appearing in the second signal, and according to the difference And an adaptive equalization control circuit for adjusting the equalization coefficient.

  According to at least one embodiment of the present disclosure, the equalization coefficient is adjusted based on the number of occurrences of predetermined 0 and 1 patterns. Therefore, adaptive equalization processing can be realized with a small circuit area and power consumption without requiring high-precision digital computation with a wide bit width.

It is a figure which shows an example of a structure of an adaptive equalization circuit. It is a figure which shows typically the eye pattern of the signal after an equalization process. It is a figure which shows typically the difference of the counter value of the pattern counter shown in FIG. It is a figure for demonstrating adjustment of an equalization coefficient. It is a figure which shows a data pattern and its power spectrum. It is a figure which shows another example of a structure of an adaptive equalization circuit. It is a figure which shows an example of a structure of the counter of FIG. 6, and an adaptive equalization control circuit. It is a figure which shows the structure which uses not the maximum value 7 but the last convergence value as an equalization coefficient. It is a figure which shows an example of a structure of the equalization circuit of FIG. It is a figure which shows an example of a structure of the band pass filter shown in FIG. FIG. 10 is a diagram illustrating an example of a configuration of a variable gain amplifier illustrated in FIG. 9. FIG. 12 is a diagram illustrating an example of a configuration of a circuit that generates signals C1 <0> to C1 <7> illustrated in FIG. 11. It is a figure which shows another example of a structure of an adaptive equalization circuit. It is a figure which shows another example of a structure of an adaptive equalization circuit. It is a figure which shows an example of a structure of a signal transmission system.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a diagram illustrating an example of a configuration of an adaptive equalization circuit. The adaptive equalization circuit 10 shown in FIG. 1 includes an equalization circuit 11, an error calculation circuit 12, an adaptive equalization control circuit 13, and a pattern setting unit 14. The error calculation circuit 12 includes a plurality of error calculation units having the same configuration, and one error calculation unit includes a first threshold value holding circuit 21, a second threshold value holding circuit 22, determination circuits 23 and 24, pattern counters 25 and 26, And a subtraction circuit 27. Note that in FIG. 1 and the subsequent similar drawings, the boundary between each functional block shown in each box and other functional blocks basically indicates a functional boundary, and separation of physical position, It does not necessarily correspond to separation of electrical signals, separation of control logic, and the like. Each functional block may be one hardware module that is physically separated from other blocks to some extent, or represents one function in a hardware module that is physically integrated with another block. It may be.

  The equalization circuit 11 performs an equalization process according to the equalization coefficient on the received signal and outputs an equalized signal. This equalization coefficient is set by the adaptive equalization control circuit 13. The error calculation circuit 12 obtains a first signal having signal values of 0 and 1 corresponding to the magnitude relationship between the equalized signal and the first threshold, and further, the equalized signal and the second threshold A second signal having signal values of 0 and 1 corresponding to the magnitude relationship of is obtained. Here, the first threshold value is a threshold value held by the first threshold value holding circuit 21 (for example, this signal level “0” when the center of fluctuation of the signal level after equalization is 0). The determination circuit 23 compares the equalized signal with the first threshold value to determine a data value of 0 or 1. That is, the determination circuit 23 outputs 1 if the equalized signal is larger than the first threshold value, and outputs 0 if the equalized signal is smaller than the first threshold value. The second threshold is a threshold Vth held by the second threshold holding circuit 22 and is a variable threshold whose value is adjusted by the adaptive equalization control circuit 13. The determination circuit 24 compares the equalized signal with the second threshold value to determine a data value of 0 or 1. That is, the determination circuit 24 outputs 1 if the equalized signal is larger than the first threshold value, and outputs 0 if the equalized signal is smaller than the first threshold value.

The error calculation circuit 12 further calculates a difference between the number of appearances of the predetermined 0 and 1 patterns appearing in the first signal and the number of appearances of the predetermined 0 and 1 patterns appearing in the second signal. Specifically, for example, when a pattern of 0 and 1 of the highest frequency f _N which is “1010” or “0101” appears in the first signal, the pattern counter 25 detects this pattern and increases the count value by one. Let Similarly, when the 0 and 1 patterns of the maximum frequency f _N that are “1010” or “0101” appear in the second signal, the pattern counter 26 detects this pattern and increments the count value by 1. Let The subtraction circuit 27 subtracts the count value of the pattern counter 26 from the count value of the pattern counter 25 to generate a difference between the count values. The pattern counters 25 and 26 may be reset at a predetermined cycle. In addition, the pattern to be counted by the pattern counters 25 and 26 may be set by the pattern setting unit 14.

The error calculation circuit 12 includes a plurality of error calculation units having the same configuration, and one error calculation unit calculates the difference with respect to one predetermined 0 and 1 pattern. Another error calculation unit calculates the difference with respect to another predetermined 0 and 1 pattern. For example, one error calculation unit counts the number of occurrences of patterns of 0 and 1 having the highest frequency f _N and calculates the difference, and the other error calculation unit calculates 0 and 1 of the frequency f _N / 2 that is half that frequency. The difference may be calculated by counting the number of occurrences of the pattern. The pattern of the highest frequency f _N is “1010” or “0101”, and the pattern of the half frequency f _N / 2 is “1100” or “0011” or “0110” or “1001”. Thus the error calculation circuit 12 includes a plurality of different patterns as the predetermined 0 and 1 of the pattern (the pattern of the frequency f _N, the pattern of the frequency f _{N /} 2, ···) using a corresponding plurality of different patterns Thus, a plurality of differences may be obtained.

The adaptive equalization control circuit 13 adjusts the equalization coefficient according to the calculated difference. Specifically, the adaptive equalization control circuit 13, "1010" or "0101" in which on the basis of the calculated difference with respect to the pattern of the frequency f _N, etc. of the component of the frequency f _N corresponding to the pattern The conversion factor may be adjusted. Similarly, the adaptive equalization control circuit 13 responds to this pattern based on the difference calculated for the frequency f _N / 2 pattern that is “1100” or “0011” or “0110” or “1001”. The equalization coefficient of the component of the frequency f _N / 2 to be performed may be adjusted. Here, the plurality of different patterns (frequency f _N pattern, frequency f _N / 2 pattern,...) Are patterns orthogonal to each other. If the bit length is longer than 4 in the above example, the orthogonal patterns may include the above two or more patterns. The adaptive equalization control circuit 13 may obtain a plurality of differences corresponding to a plurality of different patterns orthogonal to each other, and may adjust a plurality of equalization coefficients according to the obtained plurality of differences.

  Here, a first pattern and a second pattern orthogonal to each other are considered as a plurality of patterns orthogonal to each other. Since the first pattern and the second pattern are orthogonal to each other, the first equalization coefficient corresponding to the first pattern contributes to the first difference corresponding to the first pattern, but the second pattern Does not contribute at all to the second difference corresponding to. The second equalization coefficient corresponding to the second pattern contributes to the second difference corresponding to the second pattern, but does not contribute to the first difference corresponding to the first pattern at all. Therefore, it is only necessary to adjust the first equalization coefficient according to the first difference, and it is not necessary to adjust the second equalization coefficient according to the first difference. Further, the second equalization coefficient may be adjusted according to the second difference, and there is no need to adjust the first equalization coefficient according to the second difference. That is, the first and second equalization coefficients can be adjusted independently of each other based on the first and second differences.

  FIG. 2 is a diagram schematically showing an eye pattern of the signal after the equalization processing. FIG. 2A shows an eye pattern 35 in which the degree of emphasis of the high-frequency component by the equalization process is too strong, and the eye spread at the center of the eye pattern 35 is W1. FIG. 2B shows an eye pattern 36 in which the degree of emphasis of the high frequency component by the equalization processing is moderate, and the eye spread at the center of the eye pattern 36 is W2. The eye spread W2 in FIG. 2B is wider than the eye spread W1 in FIG. FIG. 2C shows an eye pattern 37 in which the degree of emphasis of the high frequency component by the equalization process is too weak, and the eye spread at the center of the eye pattern 37 is W3. The eye spread W3 in FIG. 2C is narrower than the eye spread W2 in FIG. 2, the position of the first threshold value (0 in FIG. 1) shown in FIG. Further, the position of the second threshold value (Vth in FIG. 1) shown in FIG.

  FIG. 3 is a diagram schematically showing the difference between the counter values of the pattern counter shown in FIG. Specifically, the difference obtained by subtracting the counter value of the pattern counter 26 from the counter value of the pattern counter 25 shown in FIG. That is, the difference obtained by subtracting the number of appearances of the same pattern appearing in the second signal determined by the second threshold from the number of appearances of the predetermined pattern appearing in the first signal determined by the first threshold is shown. The vertical axis indicates the difference between the counter values, and the count value increases as it goes upward in the drawing. The count value is 0 at the origin position. In the case of the condition shown in FIG. 2C, for example, when a pattern “1010” appears, the first threshold 31 is set to an appropriate position, and therefore the “1010” pattern is correctly determined by the first threshold 31. The However, since the second threshold value 32 is located near the upper limit of the eye spread W3, the “1010” pattern may not be correctly determined by the second threshold value 32. That is, the number of appearances of the pattern appearing in the first signal determined by the first threshold 31 is larger than the number of appearances of the pattern appearing in the second signal determined by the second threshold 32. Therefore, in this case, the counter value shown in FIG.

  In the case of the condition shown in FIG. 2B, for example, when a pattern “1010” appears, the first threshold 31 is set at an appropriate position, so that the “1010” pattern is correctly determined by the first threshold 31. The Further, since the second threshold 32 is located sufficiently below the upper limit of the eye spread W2, the “1010” pattern is correctly determined also by the second threshold 32. That is, the number of appearances of the pattern appearing in the first signal determined by the first threshold 31 is substantially equal to the number of appearances of the pattern appearing in the second signal determined by the second threshold 32. Therefore, in this case, the counter value shown in FIG.

  In the case of the condition shown in FIG. 2A, for example, when a pattern “1010” appears, the first threshold 31 is set to an appropriate position, so that the “1010” pattern is correctly determined by the first threshold 31. The Although it is not clear in the schematic diagram of FIG. 2A, the eye pattern 35 is a pattern in which the high frequency is excessively emphasized, and thus the eye is sufficiently opened for a high frequency received signal waveform such as “1010”. It becomes a waveform. However, the received signal waveform “01110” or the like that originally does not include such a high frequency is distorted so that the waveform after equalization becomes close to “01010” as a result of excessive harmonics being emphasized by the equalization processing. Therefore, when the “1010” pattern appears, the “1010” pattern is correctly determined by the second threshold 32. Furthermore, when the “1010” pattern does not appear, the second threshold 32 also sets “1010”. “Patterns may be detected incorrectly. That is, the number of appearances of the pattern appearing in the first signal determined by the first threshold 31 is smaller than the number of appearances of the pattern appearing in the second signal determined by the second threshold 32. Therefore, in this case, the counter value shown in FIG. 3 exists in the region III.

  Therefore, when the difference in the count value is larger than a predetermined threshold (for example, a value near the boundary between the regions I and II shown in FIG. 3), the adjustment coefficient is adjusted to be increased to emphasize the high frequency component. To do. As a result of this adjustment, the difference between the count values becomes smaller and changes so as to enter the region II, and the eye shown in FIG. 2C is in a narrow state (signal amplitude is small) to the state shown in FIG. 2B is wide. (A state in which the signal amplitude is large). Further, when the difference between the count values is smaller than a predetermined threshold (for example, a value in the vicinity of the boundary between the regions II and III shown in FIG. 3) and is in the region III, the equalization coefficient is decreased to adjust so as not to emphasize the high frequency component. . As a result of this adjustment, the difference in the count value increases and changes so as to enter the region II, and the eye shown in FIG. 2A changes from the narrow eye (the signal waveform is distorted) to the eye shown in FIG. A wide state (a state in which the signal amplitude is large and the waveform is arranged) can be obtained.

  In the adaptive equalization circuit 10 of FIG. 1, the second threshold value Vth can be adjusted by the adaptive equalization control circuit 13. With this configuration, when appropriate waveform shaping is achieved by equalization processing as shown in FIG. 2B with respect to a predetermined second threshold (for example, the second threshold 32 shown in FIG. 2) (that is, equality). The second threshold may be increased when the conversion factor converges and does not change. That is, the second threshold value 32 may be moved upward in the example of FIG. After the second threshold value is increased, the equalization coefficient is adjusted again according to the difference between the count values, so that it is possible to achieve an eye spread that allows appropriate signal determination using the increased second threshold value. That is, it is possible to obtain an appropriate signal waveform that can be appropriately determined by the increased second threshold value. When appropriate waveform shaping is achieved in this way (that is, when the equalization coefficient converges and does not change), the second threshold value may be further increased and the same processing may be repeated. Further, when appropriate waveform shaping by the equalization processing is achieved from the beginning with respect to the second threshold value at a certain position (when the state is as shown in FIG. 2B), the equalization coefficient is adjusted. Instead, the second threshold value may be increased. When the second threshold value is increased and the eye spread becomes insufficient as shown in FIG. 2C, the equalization coefficient is adjusted to achieve an appropriate waveform shaping, and then the second threshold value is further increased. Just go. By repeating such processing, that is, by changing the second threshold according to the change of the equalization coefficient by adjusting the equalization coefficient, it is possible to obtain an equalized signal with a sufficiently wide eye.

FIG. 4 is a diagram for explaining the adjustment of the equalization coefficient. In FIG. 4, the frequency characteristic of the channel 41 is indicated by a characteristic curve 45. The frequency characteristic of the equalization circuit 42 is indicated by a characteristic curve 46. The frequency characteristic 45 of the channel 41 is a low-pass characteristic in which the signal amplitude gently decreases as the signal frequency becomes higher. The frequency characteristic 46 of the equalizing circuit 42 is originally a high-pass characteristic that amplifies the signal amplitude at a high frequency. However, "1010" and "0101" because beyond the Nyquist limit for the maximum frequency f _N or more frequencies corresponding to, not specifically amplified for such high-frequency components. The signal waveform degraded by the frequency characteristic 45 of the channel 41 is equalized by the frequency characteristic 46 of the equalization circuit 42, so that the signal waveform after the equalization process is restored to a waveform close to the transmission signal waveform. In the adaptive equalization circuit 10 shown in FIG. 1, as described above, the frequency f corresponding to this pattern based on the difference calculated for the pattern of the frequency f _N that is “1010” or “0101”. The equalization coefficient of the _N component may be adjusted. Similarly, based on the difference calculated for the pattern of frequency f _N / 2, which is “1100” or “0011” or “0110” or “1001”, the component of frequency f _N / 2 corresponding to this pattern The equalization coefficient may be adjusted. As a result, the frequency characteristic 46 of the equalization circuit 42 is adjusted to an optimum value.

FIG. 5 is a diagram showing a data pattern and its power spectrum. Power spectrum of the data pattern "1010" or "0101" that in FIG. 5 shows a Type1 has a component only in the frequency _{f N,} no components in the frequency _f N / 2. Therefore, based on the difference of the count value obtained from the data pattern may be only adjusted equalizing coefficients corresponding to the component of the frequency f _N. The power spectrum of the data pattern “1100”, “0011”, “0110”, or “1001” shown as Type 2 has a component only at the frequency f _N / 2, and has no component at the frequency f _N. Therefore, only the equalization coefficient corresponding to the component of the frequency f _N / 2 needs to be adjusted based on the difference between the count values obtained from this data pattern. That is, since orthogonal to the Type1 data pattern and Type2 data pattern, based on the difference corresponding to each be adjusted independently of each other the equalization coefficients of the equalization coefficients and the frequency f _{N /} 2 frequency f _N Can do.

FIG. 6 is a diagram illustrating another example of the configuration of the adaptive equalization circuit. In the adaptive equalization circuit, based on the two difference calculated for the pattern and frequency f _{N /} 2 of the pattern of the frequency f _N, it is adjusted corresponding two equalization coefficients. The adaptive equalization circuit of FIG. 6 includes an equalization circuit 51, a determination circuit 52, a determination circuit 53, counters 54 to 57, subtraction circuits 58 and 59, an adaptive equalization control circuit 60, and an addition circuit 61. The function and operation of the equalization circuit 51 are the same as the function and operation of the equalization circuit 11 of FIG. The determination circuits 52 and 53, the counters 54 to 57, the subtraction circuits 58 and 59, and the addition circuit 61 constitute an error calculation circuit, and the functions and operations thereof are the same as those of the error calculation circuit 12 of FIG. The function and operation of the adaptive equalization control circuit 60 are the same as the function and operation of the adaptive equalization control circuit 13 of FIG.

The determination circuit 52 generates a first signal by performing threshold determination on the equalized signal based on a predetermined fixed first threshold (for example, a value at the center of the range in which the signal level changes). The adder circuit 61 adds a voltage corresponding to the signal ΔV (a 3-bit signal in this example) from the adaptive equalization control circuit 60 to the equalized signal. The determination circuit 53 determines the threshold value of the added signal based on a predetermined fixed threshold value, and generates a second signal. By adding a voltage corresponding to the variable signal ΔV to the equalized signal and then performing threshold determination, threshold determination based on the variable second threshold is realized. Judging circuit 52 and the determination circuit 53 may be a flip-flop to capture data in synchronism with the clock signal CK _R. The clock signal CK _R is a clock signal having a frequency and phase such that proper sampling of the data of the received signal. It clock signal CK _R may be supplied from the transmitting side or the system, or the receiving side may be a recovered clock signal from the received signal by the clock recovery technique.

  The counter 55 counts the number of “1010” and “0101” patterns in the first signal. The counter 54 counts the number of “1010” and “0101” patterns in the second signal. The subtraction circuit 58 subtracts the count value of the counter 54 from the count value of the counter 55 to generate a first difference. The counter 57 counts the number of patterns “1100”, “0011”, “0110”, and “1001” in the first signal. The counter 56 counts the number of patterns “1100”, “0011”, “0110”, and “1001” in the second signal. The subtraction circuit 59 subtracts the count value of the counter 56 from the count value of the counter 57 to generate a second difference.

Adaptive equalization control circuit 60 is configured to adjust the equalization coefficients C1 corresponding to the frequency f _N in response to the first difference, the equalization coefficient corresponding to the frequency f _{N /} 2 in response to the second differential Adjust C2. In addition, when a proper waveform shaping is achieved by the equalization coefficient C1, the value of the signal ΔV (that is, the amount of voltage to be added) is increased. As will be described below, in this example, when the change in the equalization coefficient C1 is small and converged, ΔV is increased. However, not only the equalization coefficient C1 but also the equalization coefficients C1 and C2 are both converged. If it is, ΔV may be increased.

  FIG. 7 is a diagram illustrating an example of the configuration of the counter and the adaptive equalization control circuit of FIG. The entire circuit shown in FIG. 7 operates in synchronization with the clock signal. The counters 55 and 57 that receive the first signal S1 from the determination circuit 52 in FIG. 6 are a demultiplexing circuit 70, a flip-flop 71, a counter group 72, maximum value selection circuits 73-1 and 73-2, and a selector circuit. 74-1 and 74-2. The counters 54 and 56 that receive the second signal S2 from the determination circuit 53 have the same configuration as the counters 55 and 57.

  The demultiplexing circuit 70 demultiplexes the first signal S1 and generates 16-bit parallel data data [15: 0] in which 16 data arranged in order on the time axis are arranged in parallel. This is performed in order to execute subsequent digital processing at a reasonable clock rate. The flip-flop 71 holds the lower 3 bits of the current parallel data data [15: 0], and adds the higher 3 bits data [18:16] to the next parallel data data [15: 0].

  The counter group 72 includes four sets, and each set includes a counter 72-1 and a counter 72-2. The counter 72-1 counts the data pattern of Type1 shown in FIG. That is, the counter 72-1 counts both “1010” and “0101” patterns. The counter 72-2 counts the data pattern of Type 2 shown in FIG. That is, the counter 72-2 counts all patterns “1100”, “0011”, “0110”, and “1001”. The first set of the above four sets performs pattern determination by dividing data [15: 0] every 4 bits from the top, and counts the patterns. That is, for example, if the collective data [7: 4] of the second 4 bits from the least significant bit is “1010”, the first set of counters 72-1 is incremented by one. The second set of the above four sets performs pattern determination by dividing data [16: 1] every 4 bits from the top, and counts the patterns. That is, for example, if the collective data [8: 5] of the second 4 bits from the least significant bit is “1010”, the second set of counters 72-1 is incremented by one. Similarly, the third set delimits data [17: 2] every 4 bits from the top and performs pattern determination and counts, and the fourth set delimits data [18: 3] every 4 bits from the top. Determine the pattern and count. In this way, an appropriate count value is generated without being influenced by the delimiter position of the 4-bit data in the parallel data.

  The maximum value selection circuit 73-1 selects the maximum value of the count values of the four counters 72-1 of the counter group 72, that is, the maximum value of the four count results of the Type 1 data pattern. This maximum value is selected by the selector circuit 74-1, and is output as the count value S1T1. Although the sum of the count values of the four counters 72-1 of the counter group 72 may be taken and outputted, the maximum value is selected and outputted in this embodiment. Similarly, the maximum value selection circuit 73-2 selects the maximum value of the count values of the four counters 72-2 of the counter group 72, that is, the maximum value of the four count results of the Type 2 data pattern. This maximum value is selected by the selector circuit 74-2 and output as the count value S1T2. Note that the selector circuits 74-1 and 74-2 allow other count values to be selected by a selection control signal for the purpose of testing, and are not essential to the operation of this embodiment.

  In this way, the counters 55 and 57 that receive the first signal S1 output the count value S1T1 of the Type 1 data pattern and the count value S1T2 of the Type 2 data pattern in the first signal S1. The counters 54 and 56 that receive the second signal S2 operate in the same manner, and output the count value S2T1 of the Type 1 data pattern and the count value S2T2 of the Type 2 data pattern in the second signal S2.

  7, the C1 control unit 65, the C2 control unit 66, and the threshold control unit 67 correspond to the subtraction circuits 58 and 59 and the adaptive equalization control circuit 60 in FIG. The C1 control unit 65 receives the count values S1T1 and S2T1 and generates an equalization coefficient C1. Similarly, the C2 control unit 66 receives the count values S1T2 and S2T2 and generates an equalization coefficient C2. The threshold control unit 67 updates the signal ΔV according to the change in the equalization coefficient C1. The C1 control unit 65 includes addition holding circuits 75-1 and 75-2, a subtraction circuit 76, a threshold determination circuit 77, a selector circuit 78, a selector circuit 79, an addition circuit 80, a flip-flop 81, a C1 convergence determination circuit 82, a flip-flop A group 83 and an AND circuit 84 are included. The C2 control unit 66 has the same configuration as the C1 control unit 65. The threshold control unit 67 includes selector circuits 85 to 88, an OR circuit 89, an adder circuit 90, a flip-flop 91, and condition determination circuits 92 to 94.

  The addition holding circuit 75-1 adds the count value S1T1 every predetermined period (every predetermined clock cycle), and holds the addition result. Each counter of the counter group 72 is set to be reset every predetermined period (every predetermined clock cycle) and to count from the initial value 0, and sequentially supplies count values for each predetermined period. The addition holding circuit 75-1 sequentially adds the sequentially supplied count value S1T1 for each predetermined period to the held value. As a result, the count value S1T1 counted over a long period is stored in the addition holding circuit 75-1. Similarly, the count value S2T1 counted over a long period is stored in the addition holding circuit 75-2. The subtraction circuit 76 subtracts the count value of the addition holding circuit 75-2 from the count value of the addition holding circuit 75-1 to obtain a difference between the count values. The threshold determination circuit 77 outputs 1 if the difference between the count values is larger than the predetermined threshold, and outputs 0 if the difference between the count values is less than or equal to the predetermined threshold.

  The selector circuit 78 selects and outputs +1 according to the output 1 of the threshold determination circuit 77, and selects and outputs −1 according to the output 0 of the threshold determination circuit 77. That is, the output of the selector circuit 78 becomes +1 when the difference in the count value is in the region I in FIG. 3, and becomes −1 when the difference in the count value is in the region III in FIG. The +1 or -1 output value of the selector circuit 78 is supplied to the adder circuit 80 via the selector circuit 79, and is added to the current equalization coefficient C1 held by the flip-flop 81. Thereby, the equalization coefficient C1 is controlled according to the difference of the count value. The clock CLK (input clock to the flip-flop 81) for updating the equalization coefficient C1 may be, for example, 1/4096 of the data rate clock of the first signal S1.

  The flip-flop group 83 holds, for example, the current equalization coefficient C1 and six recent equalization coefficients C1 that are sequentially updated. The C1 convergence determination circuit 82 determines whether or not the equalization coefficient C1 has converged based on the degree of change of the seven equalization coefficients C1 stored in the flip-flop group 83. If the output of the selector circuit 78 is a ternary value of +1, 0, −1, it can be determined that the equalization coefficient C1 has converged if there are no changes in the seven equalization coefficients C1 and the same value. In this embodiment, since the output of the selector circuit 78 is a binary value of +1 or -1, the seven equalization coefficients C1 have two values such as 3, 4, 3, 4, 3,. Can be determined that the equalization coefficient C1 has converged. When detecting the convergence, the C1 convergence determination circuit 82 asserts the convergence detection signal to 1. The convergence detection signal is supplied to the AND circuit 84 and also to the selector circuit 88 of the threshold control unit 67. When the convergence detection signal to the selector circuit 88 of the threshold control unit 67 becomes 1, ΔV is updated as will be described later.

  In this embodiment, the bit widths of ΔV and C1 are each 3 bits, and the maximum value is 7. The OR circuit 89 of the threshold control unit 67 outputs HIGH when any one of ΔV and C1 reaches the maximum value 7. At this time, if the convergence detection signal of the C1 convergence determination circuit 82 is 1, the output of the AND circuit 84 is 1, and the selector circuit 79 selects 0 and outputs it. Since the input to the adder circuit 80 is 0, the equalization coefficient C1 is not updated while this state continues.

  The threshold control unit 67 starts its operation from, for example, 1 as the initial value of the signal ΔV. The condition determination circuit 92 outputs 1 when ΔV is the maximum value 7, and outputs 0 otherwise. The condition determination circuit 93 outputs 1 when ΔV is the minimum value 0, and outputs 0 otherwise. The condition determination circuit 94 outputs 1 when C1 is the maximum value 7, and outputs 0 otherwise.

  When the initial value of the signal ΔV is 1, the outputs of the condition determination circuits 92 and 93 are both 0, and the selector circuits 85 and 86 output +1 and −1, respectively. The output of the condition determination circuit 94 is 0 when the equalization coefficient C1 does not reach the maximum value 7, and the selector circuit 87 selects and outputs +1. The selector circuit 88 selects and outputs 0 when the equalization coefficient C1 has not converged. This 0 is supplied to the adding circuit 90 and added to the current ΔV held by the flip-flop 91. Therefore, in a state where the equalization coefficient C1 has not converged, ΔV is maintained at a constant value, and the process waits for the equalization coefficient C1 to converge. When the equalization coefficient C1 converges, the selector circuit 88 selects and outputs the output of the selector circuit 87 (+1 in the above example). This +1 is supplied to the adder circuit 90 and added to the current ΔV held by the flip-flop 91. Therefore, every time the equalization coefficient C1 converges, ΔV is increased by +1.

  When the equalization coefficient C1 converges to reach the maximum value 7, the selector circuit 87 selects the output −1 from the selector circuit 86. In this case, −1 is added to ΔV, which decreases by 1. That is, it returns to the previous ΔV. As the equalization coefficient C1, it is preferable to use the previous convergence value instead of the maximum value 7 determined to be converged in a saturated state, so ΔV is also returned to the previous one.

  FIG. 8 is a diagram showing a configuration in which the previous convergence value is used instead of the maximum value 7 as the equalization coefficient. The circuit shown in FIG. 8 may be provided in the C1 output part (output part of the flip-flop 81) of the C1 control unit 65 and the C2 output part of the C2 control unit 66 shown in FIG. The circuit shown in FIG. 8 includes an AND circuit 100, holding circuits 101 and 102 such as D flip-flops, condition determination circuits 103 and 104, and selector circuits 105 and 106. The condition determination circuit 103 outputs 1 if C1 is the maximum value 7, and outputs 0 otherwise. Therefore, the selector circuit 105 outputs the stored value of the holding circuit 101 when C1 is the maximum value 7, and outputs the current equalization coefficient C1 otherwise. The condition determination circuit 104 outputs 1 if C2 is the maximum value 7, and outputs 0 otherwise. Therefore, the selector circuit 106 outputs the stored value of the holding circuit 102 when C2 is the maximum value 7, and outputs the current equalization coefficient C2 otherwise.

  C1_converged is a convergence detection signal that becomes 1 when C1 converges, and may be a signal output from the C1 convergence determination circuit 82. Similarly, C2_converged is a convergence detection signal that becomes 1 when C2 converges. When C1 and C2 converge, the output of the AND circuit 100 becomes 1, and the equalization coefficients C1 and C2 at that time are stored in the holding circuits 101 and 102. Thereafter, ΔV is increased as C1 converges, and the equalization coefficient C1 is adjusted with respect to ΔV after the increase, and C1 gradually increases. Also, the equalization coefficient C2 is adjusted, and C2 gradually increases. When C1 reaches the maximum value 7, the selector circuit 105 outputs C1 of the previous convergence value stored in the holding circuit 101 instead of C1 of the maximum value 7. Similarly, when C2 reaches the maximum value 7, the selector circuit 106 outputs C2 of the previous convergence value stored in the holding circuit 102 instead of C2 of the maximum value 7.

FIG. 9 is a diagram showing an example of the configuration of the equalization circuit 51 of FIG. The equalization circuit of FIG. 6 includes band-pass filters 110 and 111, variable gain amplifiers 112 and 113, a buffer 114, and an adder circuit 115. A reception signal is applied to the input terminal Vin. Bandpass filter 110 extracts the frequency component near frequency f _N. The band pass filter 111 extracts frequency components in the vicinity of the frequency f _N / 2. The variable gain amplifier 112, a frequency component near frequency f _N extracted by the bandpass filter 110, amplified at the amplification factor adaptive equalization control circuit 60 in accordance with the equalization coefficient C1 to output. The variable gain amplifier 113 amplifies the frequency component in the vicinity of the frequency f _N / 2 extracted by the bandpass filter 111 at an amplification factor according to the equalization coefficient C2 output from the adaptive equalization control circuit 60. The buffer 114 outputs the received signal directly supplied from the input terminal Vin without passing through the band pass filter with the gain as it is. The adder circuit 115 adds the output signals of the variable gain amplifiers 112 and 113 and the buffer 114 to obtain a sum, and outputs the obtained sum signal to the output terminal Vout.

FIG. 10 is a diagram illustrating an example of the configuration of the bandpass filter illustrated in FIG. 9. Each of the bandpass filters 110 and 111 shown in FIG. 9 may have the configuration shown in FIG. The band pass filter of FIG. 10 includes parallel circuits 121 and 122, NMOS transistors 123 to 126, and a capacitor 127. Each of the parallel circuits 121 and 122 includes an inductor element, a resistor element, a capacitor element, and a variable capacitor element connected in parallel, and adjusts the band pass band by controlling the capacitance value of the variable capacitor element. be able to. Differential input voltages V _{in +} and V _in− are input to the gate ends of the NMOS transistors 123 and 125. Differential output voltages V _{out +} and V _out− are output from the drain ends of the NMOS transistors 125 and 123.

FIG. 11 is a diagram illustrating an example of the configuration of the variable gain amplifier illustrated in FIG. 9. Each of variable gain amplifiers 112 and 113 shown in FIG. 9 may have the configuration shown in FIG. The variable gain amplifier shown in FIG. 11 includes resistance elements 131 and 132, NMOS transistors 133 to 136, NMOS transistors 137-1 to 137-8, resistance elements 138-1 to 138-8, and resistance elements 139-1 to 139-. 8 is included. Differential input voltages V _{in +} and V _in− are input to the gate terminals of the NMOS transistors 133 and 134. Differential output voltages V _{out +} and V _out− are output from the drain ends of the NMOS transistors 134 and 133. In this example, the amplifier amplifies with a gain according to the equalization coefficient C1, and the gates of the NMOS transistors 137-1 to 137-8 are connected to signals C1 <0> to C1 <according to the equalization coefficient C1. 7> is applied.

  The signals C1 <0> to C1 <7> are signals that become HIGH according to the value of the equalization coefficient C1 having a bit width of 3 bits. As a result, one of the NMOS transistors 137-1 to 137-8 becomes conductive, and the source ends of the NMOS transistors 133 and 134 are connected to each other. At this time, the resistance elements 139-1 to 139-8 connected in series to the NMOS transistors 137-1 to 137-8 respectively have eight different resistance values that decrease in this order, for example, 8R, 7R, 6R, 5R. 4R, 3R, 2R, 1R.

  For example, when the signal C1 <0> is HIGH, the left and right sides of the differential pair constituting the differential amplifier are connected via a resistance value of 8R (further, the resistance value of the resistance element 138-1). . In this case, since current does not flow so freely between the left and right sides of the differential pair, there is not much difference in the amount of current between the left and right sides of the differential pair, and the amplification factor of the differential amplifier is compared. Small. For example, when the signal C1 <7> is HIGH, the left side and the right side of the differential pair constituting the differential amplifier are connected via a resistance value of 1R (further, the resistance value of the resistance element 138-8). Become. In this case, since the current flows relatively freely between the left and right sides of the differential pair, there is a sufficient difference in the amount of current between the left and right sides of the differential pair, and the amplification factor of the differential amplifier is compared. Big.

  FIG. 12 is a diagram illustrating an example of a configuration of a circuit that generates the signals C1 <0> to C1 <7> illustrated in FIG. The circuit shown in FIG. 12 includes condition determination circuits 141-1 through 141-8 and selector circuits 142-1 through 142-8. When the equalization coefficient C1 having a bit width of 3 bits is 000, only the condition determination circuit 141-1 among the condition determination circuits 141-1 to 141-8 is 1, and the other outputs are 0. . In this case, only the output C1 <0> of the selector circuit 142-1 is 1 among the selector circuits 142-1 to 142-8. Similarly, for example, when the equalization coefficient C1 is 111, only the condition determination circuit 141-8 among the condition determination circuits 141-1 to 141-8 is 1, and the other outputs are 0. . In this case, only the output C1 <7> of the selector circuit 142-8 is 1 among the selector circuits 142-1 to 142-8.

FIG. 13 is a diagram illustrating another example of the configuration of the adaptive equalization circuit. In the adaptive equalization circuit, as in the case of FIG. 6, based on the two difference calculated for the pattern of the frequency f _N and the frequency f _{N /} 2 of the pattern, two corresponding equalization coefficient C1 And C2. However, only one determination circuit is provided, and this determination circuit is configured to be used separately for the first threshold and the second threshold in terms of time.

  The adaptive equalization circuit of FIG. 13 includes an equalization circuit 150, an addition circuit 151, a determination circuit 152, counters 153-1 and 153-2, memories 154-1 and 154-2, subtraction circuits 155-1 and 155-2, And an adaptive equalization control circuit 156. The function and operation of the equalization circuit 150 are the same as the function and operation of the equalization circuit 11 of FIG. The addition circuit 151, the determination circuit 152, the counters 153-1 and 153-2, the memories 154-1 and 154-2, and the subtraction circuits 155-1 and 155-2 constitute an error calculation circuit, and its functions and operations are shown in FIG. This is the same as the error calculation circuit 12. The functions and operations of the adaptive equalization control circuit 156 are the same as the functions and operations of the adaptive equalization control circuit 13 of FIG.

  In the configuration shown in FIG. 13, it is assumed that a predetermined data pattern is repeatedly transmitted in the initial sequence. First, ΔV is set to 0, for example, a predetermined data pattern is transmitted, and the determination circuit 152 obtains a first signal for the first threshold. The number of appearances of each pattern is counted by the counters 153-1 and 153-2 for the first signal thus obtained, and the count value is stored in the memories 154-1 and 154-2. Next, ΔV is set to 1, for example, the same data pattern as described above is transmitted, and the determination circuit 152 obtains a second signal for the second threshold. The number of appearances of each pattern is counted by the counters 153-1 and 153-2 for the second signal thus obtained. The subtraction circuits 155-1 and 155-2 calculate the difference between the count value thus obtained and the count values of the memories 154-1 and 154-2.

FIG. 14 is a diagram illustrating still another example of the configuration of the adaptive equalization circuit. In the adaptive equalization circuit, as in the case of FIG. 13, and the frequency f _N of the pattern and frequency f _{N /} 2 corresponding based on the two difference calculated for a pattern of two equalization coefficients C1 Only one determination circuit is used when adjusting C2. Further, in the configuration of FIG. 14, only one counter is provided, and this one counter is selectively used in time for counting different patterns.

  The adaptive equalization circuit of FIG. 14 includes an equalization circuit 160, an addition circuit 161, a determination circuit 162, a pattern counter 163, a memory 164, a subtraction circuit 165, a sequencer 166, a pattern setting circuit 167, selector circuits 168-1 and 168-2. And an adaptive equalization control circuit 169. The function and operation of the equalization circuit 160 are the same as the function and operation of the equalization circuit 11 of FIG. In the circuit shown in FIG. 13, portions other than the equalization circuit 160 and the adaptive equalization control circuit 169 constitute an error calculation circuit, and the functions and operations thereof are the same as those of the error calculation circuit 12 of FIG. The function and operation of the adaptive equalization control circuit 169 are the same as the function and operation of the adaptive equalization control circuit 13 of FIG.

In the configuration shown in FIG. 14, it is assumed that a predetermined data pattern is repeatedly transmitted in the initial sequence. First, ΔV is set to 0, for example, a predetermined data pattern is transmitted, and the determination circuit 162 obtains a first signal for the first threshold. At this time under the control of the sequencer 166, the pattern of the frequency f _N is set to the pattern counter 163 by the pattern setting circuit 167. By counting the number of occurrences of the pattern of the frequency f _N the pattern counter 163 with respect to the first signal, and stores the count value in the memory 164. Next, ΔV is set to 1, for example, the same data pattern as described above is transmitted, and the determination circuit 162 obtains a second signal for the second threshold. The pattern counter 163 against the second signal obtained in this manner to count the number of occurrences of the pattern of the frequency f _N. The subtraction circuit 165 calculates the difference between the count value thus obtained and the count value in the memory 164. At this time, based on the control of the sequencer 166, the selector circuit 168-1 selects the output of the subtraction circuit 165, and the selector circuit 168-2 selects 0. Accordingly, the first difference is supplied to the adaptive equalization control circuit 169 with respect to the pattern of the frequency f _N.

Next, ΔV is set again to 0, for example, a predetermined data pattern is transmitted, and the determination circuit 162 obtains a first signal for the first threshold. At this time, based on the control of the sequencer 166, the pattern setting circuit 167 sets the pattern of the frequency f _N / 2 in the pattern counter 163. The pattern counter 163 counts the number of appearances of the pattern with the frequency f _N / 2 with respect to the first signal, and the count value is stored in the memory 164. Next, ΔV is set to 1, for example, the same data pattern as described above is transmitted, and the determination circuit 162 obtains a second signal for the second threshold. The number of appearances of the pattern with the frequency f _N / 2 is counted by the pattern counter 163 with respect to the second signal thus obtained. The subtraction circuit 165 calculates the difference between the count value thus obtained and the count value in the memory 164. At this time, based on the control of the sequencer 166, the selector circuit 168-2 selects the output of the subtraction circuit 165, and the selector circuit 168-1 selects 0. As a result, the second difference with respect to the pattern of the frequency f _N / 2 is supplied to the adaptive equalization control circuit 169.

FIG. 15 is a diagram illustrating an example of a configuration of a signal transmission system. The signal transmission system illustrated in FIG. 15 includes a transmitter 170, a transmission line 171, and a receiver (receiver circuit) 172. When a transmission signal is output from the driver 173 of the transmitter 170, this signal propagates through the transmission line 171 and is received by the receiver (reception circuit) 172. The received signal is equalized by an adaptive equalization circuit 175 having the configuration shown in FIG. 1, FIG. 6, FIG. 13, or FIG. In this case, for example, as shown in FIG. 6, data values equalized signal is sampled by the clock signal CK _R, used for the adaptive equalization control. In fact, by performing sampling at twice the frequency of the clock signal CK _R, the data value (center value of the data eye) and boundary value data including the (value of the boundary between the detection target data) , And supplied to a clock data recovery circuit (CDR) 176. Clock data recovery circuit 176, based on a comparison of the data values and boundary values to detect a phase difference between the clock signal CK _R and the received data. Depending on the deviation of the detected phase, the clock data recovery circuit 176, so that the boundary between the center of the data eye and data are accurately sampled, it adjusts the timing of the clock signal CK _R.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

The present invention includes the following contents.
(Appendix 1)
An equalization circuit that performs an equalization process on the received signal according to the equalization coefficient and outputs an equalized signal; and
A first signal having signal values of 0 and 1 corresponding to the magnitude relationship between the equalized signal and the first threshold value is obtained, and 0 corresponding to the magnitude relationship between the equalized signal and the second threshold value. And a second signal having a signal value of 1, and the number of occurrences of the predetermined 0 and 1 patterns appearing in the first signal and the predetermined 0 and 1 patterns appearing in the second signal. An error calculation circuit for calculating a difference from the number of appearances;
And an adaptive equalization control circuit that adjusts the equalization coefficient according to the difference.
(Appendix 2)
The error calculation circuit uses a plurality of different patterns as the predetermined 0 and 1 patterns, calculates a plurality of differences corresponding to the plurality of different patterns, and the adaptive equalization control circuit calculates the plurality of differences. The receiving circuit according to appendix 1, wherein a plurality of equalization coefficients are adjusted accordingly.
(Appendix 3)
The receiving circuit according to claim 1 or 2, wherein the plurality of different patterns are orthogonal to each other.
(Appendix 4)
The receiving circuit according to claim 3, wherein the adaptive equalization control circuit adjusts the plurality of equalization coefficients independently of each other according to the plurality of differences.
(Appendix 5)
The receiving circuit according to any one of appendices 1 to 4, wherein the adaptive equalization control circuit changes the second threshold according to a change in the equalization coefficient by adjusting the equalization coefficient.
(Appendix 6)
An equalization process according to the equalization coefficient is performed on the received signal to generate an equalized signal,
Generating a first signal having signal values of 0 and 1 according to a magnitude relationship between the equalized signal and a first threshold;
Generating a second signal having signal values of 0 and 1 according to a magnitude relationship between the equalized signal and a second threshold value;
Obtaining a difference between the number of appearances of the predetermined 0 and 1 patterns appearing in the first signal and the number of appearances of the predetermined 0 and 1 patterns appearing in the second signal;
An equalization processing method comprising: adjusting each equalization coefficient according to the difference.
(Appendix 7)
The step of obtaining the difference includes using a plurality of different patterns as the predetermined 0 and 1 patterns, obtaining a plurality of differences corresponding to the plurality of different patterns, and adjusting the equalization coefficient The equalization processing method according to appendix 6, wherein a plurality of equalization coefficients are adjusted according to the difference between the two.
(Appendix 8)
The equalization processing method according to appendix 6 or 7, wherein the plurality of different patterns are patterns orthogonal to each other.
(Appendix 9)
9. The equalization processing method according to claim 8, wherein the step of adjusting the equalization coefficient adjusts the plurality of equalization coefficients independently of each other according to the plurality of differences.
(Appendix 10)
10. The method according to any one of appendices 6 to 9, wherein the step of adjusting the equalization coefficient includes changing the second threshold according to a change in the equalization coefficient due to the adjustment of the equalization coefficient. Processing method.

DESCRIPTION OF SYMBOLS 10 Adaptive equalization circuit 11 Equalization circuit 12 Error calculation circuit 13 Adaptive equalization control circuit 14 Pattern setting part 21 1st threshold value holding circuit 22 2nd threshold value holding circuit 23, 24 Judgment circuit 25, 26 Pattern counter 27 Subtraction circuit

Claims (5)

An equalization circuit that performs an equalization process on the received signal according to the equalization coefficient and outputs an equalized signal; and
A first signal having signal values of 0 and 1 corresponding to the magnitude relationship between the equalized signal and the first threshold value is obtained, and 0 corresponding to the magnitude relationship between the equalized signal and the second threshold value. And a second signal having a signal value of 1, and the number of occurrences of the predetermined 0 and 1 patterns appearing in the first signal and the predetermined 0 and 1 patterns appearing in the second signal. An error calculation circuit for calculating a difference from the number of appearances;
And an adaptive equalization control circuit that adjusts the equalization coefficient according to the difference.   The error calculation circuit uses a plurality of different patterns as the predetermined 0 and 1 patterns, calculates a plurality of differences corresponding to the plurality of different patterns, and the adaptive equalization control circuit calculates the plurality of differences. 2. The receiving circuit according to claim 1, wherein a plurality of equalization coefficients are adjusted accordingly.   The receiving circuit according to claim 1, wherein the plurality of different patterns are orthogonal to each other.   The receiving circuit according to claim 3, wherein the adaptive equalization control circuit adjusts the plurality of equalization coefficients independently of each other according to the plurality of differences.   5. The receiving circuit according to claim 1, wherein the adaptive equalization control circuit changes the second threshold according to a change in the equalization coefficient by adjusting the equalization coefficient. 6. .

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