JP5607118B2 - Memory system - Google Patents

Description

  The present invention relates to a buffering technique for access data in a memory system that performs external interface and non-volatile memory access control in response to an external access request, and relates to a technique that is effective when applied to, for example, a flash memory card.

  The flash memory card has a flash memory and a controller, and the flash memory operating speed, especially the writing or rewriting operating speed, is slower than the operating speed of the host device connected to the flash memory card, so as to absorb the difference in operating speed. The controller includes a buffer memory. In response to an external write request, the controller inputs external write data to the buffer memory and controls the input data to be written to the flash memory. In response to a read request from the outside, the controller temporarily accumulates data read from the flash memory in the buffer memory and outputs the accumulated data to the outside. Many conventional buffer memories employ a relatively small capacity SRAM (Static Random Access Memory) or a static latch.

  However, if a small-capacity SRAM is adopted, it is necessary to wait for data transfer from the host device to the memory card until data input from the outside to the buffer memory is completely written to the flash memory. Further, it is necessary to wait for a new read operation of the flash memory until the read data stored in the buffer memory from the flash memory is output to the outside. In particular, when writing to the flash memory fails, the next write data is received from the host device to the buffer memory, for example, when rewriting to the alternative sector has to be performed due to a defect in the sector in which the initial writing operation was performed. I can't. That is, due to a problem between the flash memory and the controller, it is necessary to wait for data transfer between the host device and the controller. This causes a problem that the burden on the host device and the processing time increase and the data processing efficiency decreases.

  In the course of studying the above problems, the present inventor has confirmed the existence of a patent application by the present applicant, although it is not publicly known. They are Japanese Patent Application 2001-174978, Japanese Patent Application 2001-177924, Japanese Patent Application 2001-213639, and Japanese Patent Application 2001-213640. These applications provide a technique that uses a flash memory as a non-volatile memory to back up information stored in an SDRAM as a volatile memory. SDRAM is not positioned as a buffer memory.

  An object of the present invention is to provide a memory system that contributes to an improvement in data processing immediate rate with memory access.

  Another object of the present invention is to reduce waiting time and processing of a host device related to data transfer with a host device in a memory system that performs access control of an external interface and a nonvolatile memory in response to an access request from the outside. An object of the present invention is to provide a memory system that can contribute to reducing the burden and the processing time.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] The memory system includes a rewritable nonvolatile memory, a buffer memory, and a controller. In response to an access request from an external device, the controller transmits a first data transfer between the controller and the external device, a second data transfer between the controller and the nonvolatile memory, and the controller. The third data transfer to and from the buffer memory is controlled, and the transfer from the controller to the buffer memory and the transfer from the buffer memory to the controller in the third data transfer are controlled in a time-sharing manner. The first data transfer or the second data transfer is made possible in parallel with the transfer by division.

  From the above, when responding to a write access request from the outside, the controller performs time-sharing of write data accumulation in the buffer memory and output of the write data accumulated in the buffer memory, and in parallel with the write data accumulation processing The write data can be transferred to the nonvolatile memory by the second data transfer, and the next write data can be input from the external device by the first data transfer in parallel with the write data output processing. it can. When responding to a read access request from the outside, the controller accumulates read data in the buffer memory and outputs the read data accumulated in the buffer memory in a time-sharing manner, and executes the first data in parallel with the read data accumulation processing. The read data can be transferred to the external device by the transfer, and the next read data from the nonvolatile memory can be input by the second data transfer in parallel with the read data output processing.

  Due to the buffering function of the buffer memory, a large waiting time is not required for the supply timing of a plurality of write data by an external device such as a host device, and a long waiting time is required for the acquisition timing of a plurality of read data by the host device. do not need. Therefore, it is possible to contribute to shortening the waiting time of the host device regarding the data transfer between the host device and the controller, reducing the processing load, and reducing the processing time. This contributes to an improvement in data processing immediate rate with memory access.

  As one desirable mode of the present invention, it is desirable that the operation speed of the third data transfer is higher than about twice the first data transfer speed in order to maximize the buffering function. Theoretically there is no waiting time for the host device.

  As a desirable mode of the present invention, it is preferable that the buffer memory is a single-port clock synchronous volatile memory and performs a FIFO operation. It is possible to increase the speed of the buffer memory and facilitate access control. The nonvolatile memory is, for example, a flash memory.

  As one aspect for realizing buffering between the first transfer and the third transfer and buffering between the second transfer and the third transfer, the controller is arranged between the external device and the buffer memory. Preferably, the dual-port data buffer and a dual-port data buffer disposed between the buffer memory and the nonvolatile memory are provided. Control for parallelization of the first data transfer and the third data transfer and parallelization of the second data transfer and the third data transfer are further facilitated.

  [2] A memory system according to another aspect of the present invention includes a rewritable nonvolatile memory, a buffer memory, and a controller. The controller includes a first data transfer control unit connected to an external device, a second data transfer control unit connected to the nonvolatile memory, and a transfer from the first data transfer control unit connected to the buffer memory. And a transfer arbitration unit that controls data transfer to and from the buffer memory in response to the request and a transfer request from the second data transfer control unit. The first data transfer control unit is connected to an external device and a transfer arbitration unit via a dual port data buffer, and outputs a transfer request to the transfer arbitration unit. The second data transfer control unit is connected to the nonvolatile memory and the transfer arbitration unit via a dual-port data buffer, and outputs a transfer request to the transfer arbitration unit. The transfer arbitration unit time-divides transfer in the write direction with respect to the buffer memory and transfer in the read direction with respect to the buffer memory in response to the transfer request from the first data transfer control unit and the transfer request from the second data transfer control unit. To control.

  As described above, data transfer between the external device and the controller is buffered by the data buffer in the first data transfer control unit, and data transfer between the nonvolatile memory and the controller is performed by the data buffer in the second data transfer control unit. Buffered, data transfer between both data buffers and buffer memory can be performed in a time-sharing manner. Therefore, when responding to a write access request from the outside, the controller performs time-sharing of the accumulation of write data to the buffer memory and the output of the write data accumulated in the buffer memory, and in parallel with the write data accumulation process. 2 Write data can be transferred from the data buffer of the transfer controller to the nonvolatile memory, and the next write data from the external device is transferred to the data buffer of the first transfer controller in parallel with the write data output processing. Can be imported. When responding to a read access request from an external device, the controller performs time-division for storing read data in the buffer memory and outputting read data stored in the buffer memory, and in parallel with the read data storage processing, The read data can be transferred from the data buffer of the transfer control unit to the external device, and in parallel with the read data output process, the second transfer control unit can store the next read data from the nonvolatile memory in the data buffer. Uptake can be performed.

  The above buffering function does not require a lot of waiting time for the supply timing of a plurality of write data by an external device such as a host device, and does not require a lot of waiting time for the acquisition timing of a plurality of read data by the host device. . Therefore, it is possible to contribute to shortening the waiting time, reducing the processing load, and reducing the processing time of the host device regarding data transfer between the host device and the controller. This contributes to an improvement in data processing immediate rate with memory access.

  As a specific aspect of the present invention, when responding to a write access request from the outside, the first data transfer control unit stores a predetermined amount of data in the data buffer from the external device, and transfers the buffer arbitration unit to the buffer memory. A transfer request for writing is output, and the second data transfer control unit outputs a transfer request for reading from the buffer memory to the data buffer when there is no predetermined amount of data in the data buffer. In response to an external read access request, the second data transfer control unit sends a transfer request for writing to the buffer memory to the transfer arbitration unit when a predetermined amount of data is stored in the data buffer from the buffer memory. The first data transfer control unit outputs a transfer request for reading to the buffer memory to the transfer arbitration unit when there is no predetermined amount of data in the data buffer.

  As a desirable aspect of the present invention, in order to maximize the buffering function, the operation speed of data transfer between the arbitration unit and the buffer memory is set to the outside by the first transfer control unit. It is desirable to make it faster than about twice the operation speed of data transfer. Theoretically there is no waiting time for the host device.

  As a desirable mode of the present invention, it is preferable that the buffer memory is composed of a single-port clock-synchronous volatile memory and performs a FIFO operation. Faster buffer memory and easier access control. The nonvolatile memory is, for example, a flash memory.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, when responding to a write access request from the outside, the controller can perform time-division of accumulation of write data in the buffer memory and output of the write data accumulated in the buffer memory. If the data buffer is dual ported, the write data can be transferred to the nonvolatile memory by the second data transfer in parallel with the write data accumulation process, and the second data transfer in parallel with the write data output process. The next write data can be input from the external device by one data transfer.

  When responding to a read access request from the outside, the controller performs time division of accumulation of read data in the buffer memory and output of the read data accumulated in the buffer memory. Due to the dual port of the data buffer, the read data can be transferred to the external device by the first data transfer in parallel with the read data accumulation process, and the second data in parallel with the read data output process. The next read data can be input from the nonvolatile memory by the transfer.

  Thus, a large waiting time is not required for the supply timing of a plurality of write data by an external device such as a host device, and a long waiting time is not required for the acquisition timing of a plurality of read data by the host device. Therefore, it is possible to contribute to shortening the waiting time, reducing the processing load, and reducing the processing time of the host device regarding data transfer between the host device and the controller. Data processing efficiency with memory access can be improved.

1 is a block diagram of a flash memory card which is an example of a memory system according to the present invention. It is a local memory address mapping figure of the flash memory functioning as a file memory. It is explanatory drawing which shows generally the address mapping of the host interface part of a controller. It is explanatory drawing which illustrates the FIFO format of SDRAM. It is a flowchart which illustrates the control operation by a transfer arbitration part. It is a flowchart which illustrates control operation of CPU at the time of a write transfer request. 6 is a flowchart illustrating a control operation of a CPU when a read access request is made. 6 is a timing chart correlating data transfer operations of the host device, SDRAM, and flash memory when a write access request is made. 5 is a timing chart showing the data transfer operations of the host device, SDRAM, and flash memory in correlation with each other when a read access request is made. 4 is a timing chart showing an example of a write cycle Tdw of the SDRAM. 4 is a timing chart showing an example of a read cycle Tdr of the SDRAM. 4 is a timing chart showing an example of a write cycle Tfw for a flash memory. It is a timing chart which shows an example of the read cycle Tfr with respect to flash memory. 10 is a flowchart showing a case where there is no write error to the flash memory as a data transfer processing flow in response to a write access request. 12 is a flowchart showing a case where there is a write error to the flash memory as another data transfer processing flow in response to a write access request. 6 is a flowchart illustrating a data transfer processing flow in response to a read access request.

  FIG. 1 illustrates a flash memory card which is an example of a memory system according to the present invention. The flash memory card 1 shown in FIG. 1 includes a flash memory (nonvolatile memory) 2 having a data storage area and a management area in a predetermined sector address (physical address) unit, and an external connected to the outside of the memory system. An information processing apparatus, for example, a controller 4 that controls access to the flash memory 2 in response to a request from the host apparatus 3, and a buffer memory 5 connected to the controller 4.

  Although not shown in particular, the flash memory 2 has a memory cell array in which flash memory cells that can be electrically erased and written are arranged in a matrix. Although the flash memory cell is not particularly limited, it has a floating gate and a control gate separated by an insulating film on the channel region. For example, the threshold voltage of the memory cell is increased by injecting electrons into the floating gate. The threshold voltage of the memory cell is lowered (referred to as erasing) by raising (for example, referred to as writing) and discharging electrons injected into the floating gate with a tunnel current through the gate insulating film. The flash memory cell has a drain connected to the bit line, a source connected to the source line, and a control gate connected to the word line. For example, an address assigned to a word line is the sector address. The word line selection by the sector address signal is performed by a word line selection circuit. Selection of a part of the plurality of flash memory cells designated by the sector address is performed based on a column address signal generated by a column address counter starting from the column address. For example, a configuration described in Japanese Patent Laid-Open No. 2001-23383 can be adopted as the flash memory.

  The flash memory 2 functions as, for example, a file memory, and local memory address mapping is performed by assigning a management area and a user data storage area to each address of the sector addresses 1 to n as illustrated in FIG. Stores information such as pass / fail (effectiveness) of each sector and the presence / absence of an alternative destination.

  The buffer memory 5 is composed of, for example, a single-port SDRAM (Synchronous Dynamic Random Access Memory) which is a clock synchronous volatile memory. Hereinafter, the buffer memory 5 is also simply referred to as SDRAM 5. The SDRAM 5 has, for example, a memory cell array in which dynamic memory cells are arranged in a matrix. A command and an address are input in synchronization with the clock, and write access or read access specified by the command is performed at high speed in synchronization with the clock signal. be able to. For example, if the speed of data transfer (first data transfer) between the host device 3 and the controller 4 is 100 MB (megabytes) / s (seconds), the bus between the SDRAM 5 and the controller 4 is transferred. The speed of data transfer (third data transfer) is 266 MB / s, which is more than twice that speed. The speed of data transfer (second data transfer) via the bus between the flash memory 2 and the controller 4 is about 20 MB / s in accordance with the low access speed of the flash memory 2 itself.

  The controller 4 includes a host data transfer control unit (first data transfer control unit) 11, a flash data transfer control unit (second data transfer control unit) 12, a transfer arbitration unit 13, a CPU 14, and a control register 15.

  The control register 15 includes a command register (15C), an address register (15A), and a status register (15S). When accessing the flash memory card 1, the host device 3 sets a command such as read or write in the command register 15C, and sets an access address in the address register 15A. The states of the host device 3 and the flash memory card 1 can be mutually recognized via the status register 15S.

  The CPU 14 controls the flash memory card 1 as a whole. When a command is set in the command register 15C, the CPU 14 interprets the command, controls the memory interface for the flash memory 2, the data interface control with the host device 3, and the buffer control for the interface-controlled data. Thus, the access to the sector of the flash memory 2 corresponding to the address set in the address register 15A is completed.

  The host data transfer control unit 11 connects the host device 3 and the transfer arbitration unit 13 via a dual port data buffer 20. The transfer request circuit 21 issues a transfer request to the transfer arbitration unit 13 with the signal HDRQ and receives an acknowledge with the signal HDACK, whereby the data buffer 20 is operated to input or output data with the transfer arbitration unit 13. For this input or output, the host data transfer control unit 11 instructs the transfer arbitration unit 13 using the signal HDIR. The HDIR signal is set in the host data transfer control unit 11 before the CPU 14 starts the transfer operation. The host data transfer control unit 11 asserts the signal HEND_IRQ to the CPU and terminates the transfer operation when the input or output operation amount to the transfer arbitration unit 13 of the data buffer 20 started in response to the acknowledge by the signal HDACK reaches a specified amount. To do. As a result, the CPU 14 enables the transfer arbitration unit 13 to accept a new transfer request. The host data transfer control unit 11 can output a wait signal HWAIT to the host apparatus 3 and instruct the host apparatus 3 to pause the operation by asserting it.

  Although not shown, whether or not the transfer operation between the data buffer 20 and the host apparatus 3 is possible is determined by exchanging the status via the status register 15S. When viewed from the host device 3, the data buffer 21 is mapped to the address space. FIG. 3 shows the address mapping of the host interface portion of the controller 4 as a whole.

  The flash data transfer control unit 12 connects the flash memory 2 and the transfer arbitration unit 13 via a dual port data buffer 22. The data buffer 22 is composed of a dual port FIFO buffer. The transfer request circuit 23 issues a transfer request with the signal FDRQ to the transfer arbitration unit 13 and receives an acknowledge with the signal FDACK, whereby the data buffer 22 is operated to input or output data with the transfer arbitration unit 13. For this input or output, the flash data transfer control unit 13 instructs the transfer arbitration unit 13 using the signal FDIR. This signal FDIR is set in the flash data transfer control unit 12 before the CPU 14 starts the transfer operation. The flash data transfer control unit 12 asserts the signal FEND_IRQ to the CPU when the input or output operation amount to the transfer arbitration unit 13 of the data buffer 22 started in response to the acknowledge by the signal FDACK reaches the CPU, and ends the transfer operation. To do. As a result, the CPU 14 enables the transfer arbitration unit 13 to accept a new transfer request. Although not shown, whether or not the transfer operation between the data buffer 22 and the flash memory 2 is possible is determined by the flash data transfer control unit 12 by exchanging the status via the status register of the flash memory 2.

  The transfer arbitration unit 13 includes a transfer permission circuit 30, a host transfer address counter 31, and a flash transfer address counter 32. The host transfer address counter 31 generates an access address of the SDRAM 5 in data transfer between the data buffer 20 and the buffer memory 5. The flash transfer address counter 32 generates an access address of the SDRAM 5 in data transfer between the data buffer 22 and the flash memory 2. Address presetting for the address counters 31 and 32 is performed by the CPU 14 for each access request from the host device 3. Here, the SDRAM 5 is access controlled in a FIFO format as illustrated in FIG. The host transfer address counter 31 functions as a write address pointer when writing from the data buffer 20 to the SDRAM 5, and functions as a read address pointer when reading from the SDRAM 5 to the data buffer 20. The flash transfer address counter 32 functions as a write address pointer when writing from the data buffer 22 to the SDRAM 5, and functions as a read address pointer when reading from the SDRAM 5 to the data buffer 22. The transfer permission circuit 30 arbitrates the conflict between the transfer request signals HDRQ and FDRQ, and returns the arbitration result to the transfer request circuits 21 and 23 by signals HDACK and FDACK.

  FIG. 5 illustrates a control operation by the transfer arbitration unit 13. The transfer arbitration unit 13 sequentially cyclically determines whether there is a host transfer request based on the signal HDRQ (S1), whether there is a flash transfer request based on the signal FDRQ (S2), or whether refresh is necessary (S3). When there is a host transfer request by the signal HDRQ, in the process of responding to the write access request from the host apparatus 3, writing to the address of the SDRAM 5 indicated by the address counter 31 is performed, and in the process of responding to the read access request from the host apparatus 3 The address of the SDRAM 5 indicated by the address counter 31 is read (S1A), and the address counter 31 is incremented (S1B). When there is a flash transfer request by the signal FDRQ, the process of responding to the write access request from the host apparatus 3 reads the address of the SDRAM 5 indicated by the address counter 32, and the process of responding to the read access request from the host apparatus 3 is the address counter 32. Is written to the address of the SDRAM 5, and the address counter 32 is incremented. If it is determined that refresh is required, the stored information in SDRAM 5 is refreshed. The refresh address is generated using a refresh address counter (not shown) held by the transfer arbitration unit 13.

  As is apparent from FIG. 5, in the process in response to the write access request from the host device 3, writing to the address of the SDRAM 5 indicated by the address counter 31 and reading to the address of the SDRAM 5 indicated by the address counter 32 are performed in units of 8 bytes. For example, time division, that is, alternately can be performed. In the process in response to the read access request from the host device 3, the read to the address of the SDRAM 5 indicated by the address counter 31 and the write to the address of the SDRAM indicated by the address counter 32 are time-divisionally divided, that is, alternately in units of 8 bytes. it can.

  FIG. 6 illustrates the control operation of the CPU when a write transfer request is made. When detecting a write access request from the host device 3 (S10), the CPU 14 sets the host transfer address counter 31, that is, initializes or presets an initial value (S11). Further, the CPU 14 instructs the host data transfer control unit 11 to transfer control data transferred from the host device 3 to the data buffer 20 to the transfer arbitration unit 13 (S12). Thereafter, the CPU 14 sets a transferable status in the status register 15S and notifies the host device 3 of the start of transfer of write data to the data buffer 20 (S13). As a result, the transfer arbitration unit 13 performs the processing when the host transfer request (S1) described with reference to FIG. 5 is received, so that each time 8-byte data is input from the host device 3 to the data buffer 20, the data is transferred. Can be stored in the SDRAM 5 specified by the address counter 31. Further, the CPU 14 calculates a physical address, that is, a sector address of the flash memory 2 from the access address input to the address register 15A (S14), and sends a write command to the calculated sector address via the flash data transfer control unit 4 to the flash memory. 2 is set (S15). Thereafter, the CPU 14 sets the flash transfer address counter 32, that is, initializes or presets an initial value (S16). Then, every time 8-byte data is input from the SDRAM 5 to the data buffer 22, the CPU 14 gives an instruction to transfer the data to the flash memory 2 to the flash data transfer control unit 12 (S 17). During this time, the transfer arbitration unit 13 performs processing when the flash transfer request (S2) described with reference to FIG. 5 is performed, so that the data stored in the SDRAM 5 is addressed so that the data held in the data buffer 22 becomes 8 bytes. The data buffer 22 is transferred according to the value of the counter 32.

  When the process corresponding to the host transfer request and the process corresponding to the flash transfer request in FIG. 5 are repeated in a time-sharing manner, the CPU 14 detects a state where both the signals HEND_IRQ and FEND_IRQ are active (S18), and a write access request. A wait state is entered (S10). That is, HEND_IRQ is activated when data corresponding to the number of write data to be executed in response to a write access request instructed from the host device 3 is stored in the SDRAM 5, and data corresponding to the number of write data to be executed is SDRAM 5. When read from, the signal FEND_IRQ is activated.

  FIG. 7 illustrates a CPU control operation at the time of a read access request. When the CPU 14 detects a read access request from the host device 3 (S20), the CPU 14 calculates the physical address, that is, the sector address of the flash memory 2 from the access address input to the address register 15A (S21), and transfers it to the calculated sector address. A read command is set in the flash memory 2 via the flash data transfer control unit 4 (S22). The CPU 14 sets the flash transfer address counter 32, that is, initializes or presets an initial value (S23). Further, the CPU 14 gives an instruction to the flash data transfer control unit 12 to control transfer of data input from the flash memory 2 to the data buffer 22 to the transfer arbitration unit 13 (S24). As a result, the transfer arbitration unit 13 performs the processing when the flash transfer request (S2) described with reference to FIG. 5 is performed, so that, for example, each time 8 bytes of data is input from the flash memory 2 to the data buffer 22, The data can be stored in the SDRAM 5 specified by the address counter 32. Thereafter, the CPU 14 sets the host transfer address counter 31, that is, initializes or presets an initial value (S25). Then, the CPU 14 instructs the host data transfer control unit 11 to read data from the SDRAM 5 and supply it to the data buffer 20 (S26). The CPU 14 sets a transferable status in the status register 15 and notifies the host device 3 that the read data can be taken in (S13), and the transfer arbitration unit 13 sends the host transfer request (S1) described in FIG. The data stored in the SDRAM 5 is transferred to the data buffer 20 in accordance with the value of the address counter 31 so that the data held in the data buffer 20 becomes 8 bytes.

  When the processing corresponding to the host transfer request and the processing corresponding to the flash transfer request in FIG. 5 are repeated in a time-sharing manner, the CPU 14 detects a state in which both the signals HEND_IRQ and FEND_IRQ are active (S28), and a read access request A waiting state is entered (S20). That is, when data corresponding to the number of read data to be executed in response to the read access request instructed from the host device 3 is stored in the SDRAM 5, FEND_IRQ is activated, and data corresponding to the number of read data to be executed is SDRAM 5 When read from, signal HEND_IRQ is activated.

  FIG. 8 correlates the data transfer operations of the host device 3, SDRAM 5 and flash memory 2 when there is a write access request. (A) shows the operating state of the host device 3, (B) shows the operating state of the SDRAM 5, and (C) shows the operating state of the flash memory 2. H_ADR is an address bus connected from the host device 3 to the controller 4, H_DAT is a data bus connecting the host device 3 and the controller 4, H_WE is a write enable signal output by the host device 3, and H_OE is an output output by the host device 3. This is an enable signal. D_CLK is a synchronous clock signal supplied to the SDRAM 5, D_WE is a write enable signal supplied from the controller 4 to the SDRAM 5, and D_DAT is a data bus connecting the controller 4 and the SDRAM 5. F_OE is an output enable signal output from the controller 4 to the flash memory 2, F_WE is a write enable signal supplied from the controller 4 to the flash memory 2, F_CS is a serial clock signal output from the controller 4 to the flash memory 2, and F_DAT is A data bus for connecting the controller 4 and the flash memory 2.

  The host device 3 outputs an address value to the address register 15A and a write transfer command to the command register 15C toward the controller 4, and reads the status register 15S of the controller 4. After reading the status indicating that transfer is possible, the data is transferred to the data register of the data buffer 20. Data transfer is in units of blocks, and each block is, for example, 8 bytes. The controller 4 gives a write sector address value and a write transfer command to the flash memory 2. When the controller 4 inputs the data of the data block 1, the controller 4 writes the data into the SDRAM 5. The write cycle at this time is indicated by Tdw. The data of the data block 1 thus written is read from the SDRAM 5 to the controller 4 this time. The read cycle at this time is indicated by Tdr. The data of the data block 1 read by the controller 4 is transferred to the flash memory 2. While the SDRAM 5 is performing the write cycle Tdw and the read cycle for the data of the data block 1, the host device 3 outputs the data of the next data block 2 toward the buffer 20 of the controller 4. When the data of the data block 1 is transferred to the flash memory 2, the SDRAM 5 performs a write cycle and a read cycle for the data of the data block 2 in a time division manner. The same processing as described above is performed on the data up to data block 4.

  According to this example, the controller 4 reads the data of the data block 3 from, for example, the transfer arbitration unit 13 side port of the data buffer 20, stores it in the SDRAM 5 (Ti to Tj), and subsequently stores the data stored in the SDRAM 5 as data. When data is stored in the buffer 22 from the transfer arbitration unit 13 side port (Tj to Tk), data of the next data block 4 is input to the data buffer 20 from the host device 3 side port of the data buffer 20 and data The data of the previous data block 2 is transferred to the flash memory 2 from the flash memory 2 side port of the buffer 22. In short, when responding to a write access request from the host device 3, the controller 4 accumulates the write data in the SDRAM 5 and outputs the write data accumulated in the SDRAM 5 in a time-sharing manner for the write data accumulation processing in the SDRAM 5. Write data can be transferred to the flash memory 2 in parallel, and next write data can be input from the host device 3 in parallel with the write data output processing from the SDRAM 5.

  In the example of FIG. 8, the write command sequence for the flash memory 2 is an address value (sector address value), a write transfer command, write data (data block 1 to data block 4), and a write start command. Under the condition that the write start command is input, the information input immediately before is interpreted as a set of command strings, and the write operation is started in the flash memory 2 according to the result. In FIG. 8, the command string supply cycle from address value input to write start command input is shown as Tfw.

  FIG. 9 correlates the data transfer operations of the host device, SDRAM, and flash memory when there is a read access request. (A) shows the operating state of the host device 3, (B) shows the operating state of the SDRAM 5, and (C) shows the operating state of the flash memory 2.

  The host device 3 outputs an address value to the address register 15A and a read transfer command to the command register 15C toward the controller 4. The controller 4 gives the address value and the flash read transfer command to the flash memory 2. As a result, the flash memory 2 sequentially reads data from the data block 1 to the data block 4 in synchronization with the clock signal F_CS. In FIG. 9, the read cycle is illustrated as Tfr. The data of the data block 1 read first is written into the SDRAM 5 via the data buffer 22. This write cycle is illustrated as Tdw. Further, the written data of the data block 1 is read from the SDRAM 5 and supplied to the data buffer 20. This read cycle is illustrated as Tdr. When the data of the data block 1 is ready in the data buffer 20, the status register 15S can be transferred. The host device 3 takes in the data of the data block 1 by recognizing the status. The same processing as described above is performed for data blocks 2 to 4.

  According to this example, the controller 4 reads the data of the data block 3 from the transfer arbitration unit 13 side port of the data buffer 22 and stores it in the SDRAM 5 (Tp to Tq), and subsequently stores the data stored in the SDRAM 5 as data. When the data is stored in the buffer 20 (Tq to Tr), the data of the next data block 4 is input to the data buffer 22 from the flash memory 2 side port of the data buffer 22 and the host device 3 side port of the data buffer 20 Data of the previous data block 2 is taken into the host device 3. In short, when responding to a read access request from the host device 3, the controller 4 accumulates read data in the SDRAM 5 and outputs read data accumulated in the SDRAM 5 in a time-sharing manner, and in parallel with the read data accumulation processing in the SDRAM 5. Thus, the host device 3 can fetch the read data from the buffer memory 20, and in parallel with the process of outputting the read data from the SDRAM 5, the process of inputting the next read data from the flash memory 2 to the buffer memory 22. Can be done.

  FIG. 10 shows an example of the write cycle Tdw of the SDRAM. CLK is a clock signal corresponding to the D_CLK, CKE is a clock enable signal, CS_N is a chip selection signal, RAS_N is a row address strobe signal, CAS_N is an address strobe signal, WE_N is a write enable signal corresponding to the D_WE, and A14 to A0 Is an address signal, and D15 to D0 are data.

  FIG. 11 shows an example of the read cycle Tdr of the SDRAM.

  FIG. 12 shows an example of a write cycle Tfw for the flash memory 2. 1FH is a write transfer command, SA8 (1) and SA (2) are address values, and 40H is a write start command. Write data (Din) is input in synchronization with the serial clock SC.

  FIG. 13 shows an example of a read cycle Tfr for the flash memory 2. 00H / F0H means a read transfer command, and SA8 (1) and SA (2) mean an address value. Read data (Dout) is output in synchronization with the serial clock SC.

  FIG. 14 illustrates a data transfer processing flow in response to a write access request. The processing flow in the figure assumes a case where there is no write error to the flash memory 2. When a write access request is issued from the host device 3, the controller 4 notifies the host device 3 that write transfer preparation is possible and issues a write transfer request to the flash memory 2. In response to this, the host device 3 performs write transfer of write data to the controller 4, and the controller 4 writes and transfers write data to the flash memory 2. The flash memory 2 performs a write operation, and returns a normal end to the controller 4 here. When there is no room to store the write data of the new block in the data buffer 20, the controller 4 asserts the signal HWAIT and issues a write transfer temporary suspension request to the host device 3. When the controller 4 can accumulate write data of a new block, the controller 4 negates the signal HWAIT and gives the host device 3 resumption of write transfer. As a result, the host apparatus 3 resumes write transfer to the controller 4, and the controller 4 resumes transfer of write data to the flash memory 2. When all processing in response to the write access request is completed, the controller 4 gives a write transfer end notification to the host device 3.

  FIG. 15 illustrates another data transfer processing flow in response to a write access request. The processing flow in the figure assumes a case where there is a write error to the flash memory 2. When a write access request is issued from the host device 3, the controller 4 notifies the host device 3 that write transfer preparation is possible and issues a write transfer request to the flash memory 2. In response to this, the host device 3 performs write transfer of write data to the controller 4, and the controller 4 writes and transfers write data to the flash memory 2. The flash memory 2 performs a write operation. Here, a write error occurs, and the controller 4 is notified of the end of the write failure. In response to this, the controller 4 asserts the signal HWAIT and issues a write transfer temporary interruption request to the host device 3. Thereafter, the controller 4 negates the signal bHWAIT to notify the host device 3 of resumption of write transfer, and issues a substitute block write transfer request to the flash memory 2. Then, the host device 3 writes and transfers the write data to the controller 4, and the controller 4 writes and transfers the write data to the flash memory 2. Here, the flash memory 2 further fails in writing, and notifies the controller 4 of the end of writing failure. Thereafter, the controller 4 requests the flash memory 2 to perform a writing process related to the failure. During this time, the host device 3 can transfer subsequent write data to the controller 4 in advance. Finally, when all the processes responding to the write access request are completed, the controller 4 gives a write transfer end notification to the host device 3.

  FIG. 16 illustrates a data transfer processing flow in response to a read access request. When a read access request is issued from the host device 3, the controller 4 notifies the host device 3 that read transfer preparation is possible and issues a read transfer request to the flash memory 2. In response to this, the flash memory 2 reads and transfers the read data to the controller 4, and the controller 4 reads and transfers the read data to the host device 3. Here, the flash memory 2 returns a normal end to the controller 4. When there is no room to store the read data of the new block in the data buffer 20, the controller 4 asserts the signal HWAIT and issues a read transfer temporary suspension request to the host device 3. When the controller 4 can store the read data of the new block, the controller 4 negates the signal HWAIT to request the host device 3 to resume the read transfer, and issues a read transfer request to the flash memory 2. As a result, as described above, the flash memory 2 performs read transfer of the read data to the controller 4, and the controller 4 performs read transfer of the read data to the host device 3. When all processing in response to the read access request is completed, the controller 4 gives a read transfer end notification to the host device 3.

  The buffering function using the SDRAM 5 by the controller 4 does not require much waiting time for the supply timing of the plurality of write data by the host device 3, and many timings for acquiring the plurality of read data by the host device 3. No waiting time is required. Therefore, it is possible to contribute to shortening the waiting time of the host device 3 regarding the data transfer between the host device 3 and the controller 4, reducing the processing load, and reducing the processing time. This can improve the data processing efficiency that accompanies access to the flash memory card 1.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the non-volatile memory is not limited to a flash memory, and may be a rewritable non-volatile memory that employs another storage format such as a high dielectric memory. Also, the number of information storage bits for one memory cell is not limited to 1 bit, and may be 2 bits or more. Further, the memory system is not limited to a flash memory card such as a PC card, but can be configured on a processor board on which a data processor is mounted. In the controller, the data buffer of the host interface part and the data buffer of the nonvolatile memory interface part are not limited to the dual port, but may be a single port memory, a register, or a latch circuit. In short, it suffices if data can be input / output at the host interface or the flash interface in parallel with the data transfer by the time division to the buffer memory.

  The embodiments of the present invention are listed below.

1. A rewritable nonvolatile memory, a buffer memory, and a controller;
The controller includes a first data transfer control unit connected to an external device, a second data transfer control unit connected to the nonvolatile memory, and a transfer from the first data transfer control unit connected to the buffer memory. A transfer arbitration unit that controls data transfer to and from the buffer memory in response to the request and a transfer request from the second data transfer control unit;
The first data transfer control unit is connected to an external device and a transfer arbitration unit via a data buffer, and outputs a transfer request to the transfer arbitration unit,
The second data transfer control unit is connected to the nonvolatile memory and the transfer arbitration unit via a data buffer, and outputs a transfer request to the transfer arbitration unit,
The transfer arbitration unit time-divides transfer in the write direction with respect to the buffer memory and transfer in the read direction with respect to the buffer memory in response to the transfer request from the first data transfer control unit and the transfer request from the second data transfer control unit. Control with
When responding to an external write access request, the first data transfer control unit outputs a transfer request for writing to the buffer memory to the transfer arbitration unit when a predetermined amount of data is accumulated in the data buffer from the external device. The second data transfer control unit outputs a transfer request for reading from the buffer memory to the data buffer to the transfer arbitration unit when there is no predetermined amount of data in the data buffer.

2. When responding to an external read access request, the second data transfer control unit outputs a transfer request for writing to the buffer memory to the transfer arbitration unit when a predetermined amount of data is accumulated in the data buffer from the buffer memory. 2. The memory system according to item 1, wherein the first data transfer control unit outputs a transfer request for reading to the buffer memory to the transfer arbitration unit when there is no predetermined amount of data in the data buffer.

DESCRIPTION OF SYMBOLS 1 ... Flash memory card 2 ... Flash memory 3 ... Host apparatus 4 ... Controller 5 ... Buffer memory (SDRAM)
11: Host data transfer control unit 12: Flash data transfer control unit 13: Transfer arbitration unit 14: CPU
15 ... Control register (command register, address register, status register)
20 ... Data buffer 21 ... Transfer request circuit 22 ... Data buffer 23 ... Transfer request circuit 31 ... Host transfer address counter 32 ... Flash transfer address counter 33 ... Transfer permission circuit

Claims (4)

A nonvolatile memory capable rewritten, a memory system comprising a buffer memory, and a controller,
The controller includes a first data transfer control unit having a first data buffer and a second data transfer control unit having a second data buffer,
The buffer memory is connected to an external device via the first data buffer, and is connected to the nonvolatile memory via the second data buffer;
In response to the write access request from the external device, the controller writes the data block from the first data buffer to the buffer memory, and then continues from the buffer memory to the second data buffer. A data block read process, and in parallel with the write process and the read process, a data block next to the data block on which the write process and the read process are executed is received from the external device. The data block immediately before the data block to be transferred to the first data buffer and subjected to the writing process and the reading process is transferred from the second data buffer to the nonvolatile memory. Control in a time-sharing manner to be transferred to the memory,
After the control by the time division method is repeated and a predetermined number of two or more series of data blocks are transferred from the second data buffer to the nonvolatile memory, the nonvolatile memory receives a command from the controller. In response to the write operation of the series of data blocks to the nonvolatile memory,
When the writing is normally terminated in the writing operation, the nonvolatile memory notifies the controller of the normal termination of the writing,
When a write error occurs in the write operation, the nonvolatile memory notifies the controller of a write failure,
When the controller is notified of the write failure, the controller requests the nonvolatile memory to perform a write process related to the failure and receives transfer of subsequent write data from the external device .   In response to the read access request from the external device, the controller writes the data block from the second data buffer to the buffer memory, and then continues the processing from the buffer memory to the first data buffer. A data block read process, and in parallel with the write process and the read process, a data block next to the data block on which the write process and the read process are performed is the nonvolatile memory From the first data buffer to the second data buffer, and the data block immediately before the data block on which the writing process and the reading process are performed is transferred from the first data buffer to the second data buffer. The method according to claim 1, wherein the control is performed in a time-sharing manner so as to be transferred to an external device. Placing the memory system.   3. The memory system according to claim 1, wherein the controller gives a write transfer end notification to the external device when all processing for the write access request from the external device is completed.   The memory system according to claim 2, wherein the controller gives a read transfer end notification to the external device when all processing for the read access request from the external device is completed.

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