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JP5684233B2 - Silicon wiring embedded glass substrate and manufacturing method thereof - Google Patents

Silicon wiring embedded glass substrate and manufacturing method thereof Download PDF

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JP5684233B2
JP5684233B2 JP2012507095A JP2012507095A JP5684233B2 JP 5684233 B2 JP5684233 B2 JP 5684233B2 JP 2012507095 A JP2012507095 A JP 2012507095A JP 2012507095 A JP2012507095 A JP 2012507095A JP 5684233 B2 JP5684233 B2 JP 5684233B2
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glass substrate
convex portion
main surface
silicon
substrate
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JPWO2011118785A1 (en
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真 奥村
真 奥村
巧 田浦
巧 田浦
友洋 中谷
友洋 中谷
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Panasonic Intellectual Property Management Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
    • G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
    • G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
    • G01P15/125—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values by capacitive pick-up
    • G—PHYSICS
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    • G01P1/00—Details of instruments
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • G01P2015/0825—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values being provided with a particular type of spring-mass-system for defining the displacement of a seismic mass due to an external acceleration for defining out-of-plane movement of the mass for one single degree of freedom of movement of the mass
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    • G01P2015/0862—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values being provided with particular means being integrated into a MEMS accelerometer structure for providing particular additional functionalities to those of a spring mass system
    • G01P2015/0877—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values being provided with particular means being integrated into a MEMS accelerometer structure for providing particular additional functionalities to those of a spring mass system using integrated interconnect structures
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Description

本発明は、ガラスベースの内部にシリコン配線が配置されたシリコン配線埋込ガラス基板及びその製造方法に関するものである。 The present invention relates to a silicon wiring embedded glass substrate in which silicon wiring is arranged inside a glass base and a method for manufacturing the same.

従来から、微細な構造を有するガラス基板を製造する目的で、例えば、特許文献１に記載された技術が知られている。   Conventionally, for example, a technique described in Patent Document 1 is known for the purpose of manufacturing a glass substrate having a fine structure.

特許文献１に記載されたガラス材料からなるフラット基板の製造方法では、先ず、平坦なシリコン基板の表面に窪みを形成し、平坦なガラス基板にシリコン基板の窪みが形成された面を重ね合わせる。そして、ガラス基板を加熱することによりガラス基板の一部をこの窪みの中に埋め込む。その後、ガラス基板を再固化させ、フラット基板の表裏面を研磨し、シリコンを除去する。   In the method of manufacturing a flat substrate made of a glass material described in Patent Document 1, first, a recess is formed on the surface of a flat silicon substrate, and a surface on which the recess of the silicon substrate is formed is superimposed on the flat glass substrate. And a part of glass substrate is embedded in this hollow by heating a glass substrate. Thereafter, the glass substrate is re-solidified, the front and back surfaces of the flat substrate are polished, and silicon is removed.

また、特許文献１には、このフラット基板を用いた応用例として、マイクロメカニカルスイッチが記載されている。フラット基板に埋め込まれたシリコンからなるチャンネルが、マイクロメカニカルスイッチの電極に接続され、このチャンネルはスイッチ動作に係わる入出力電圧を外部へ引き出す機能を果たしている。
特表２００４−５２３１２４号公報（特に、第１図及び第３図参照） Patent Document 1 describes a micromechanical switch as an application example using this flat substrate. A channel made of silicon embedded in a flat substrate is connected to an electrode of a micromechanical switch, and this channel has a function of extracting an input / output voltage related to the switch operation to the outside.
Japanese translation of PCT publication No. 2004-523124 (in particular, see FIGS. 1 and 3)

しかし、特許文献１に記載されたフラット基板の製造方法において、フラット基板の表裏面に露出するチャンネルの位置は、フラット基板の表裏面の法線方向から見て同じである。   However, in the flat substrate manufacturing method described in Patent Document 1, the positions of the channels exposed on the front and back surfaces of the flat substrate are the same as viewed from the normal direction of the front and back surfaces of the flat substrate.

したがって、特許文献１のチャンネルでは、入出力電圧を任意の箇所に引き出すことができず、入出力電圧の引き出し位置はマイクロメカニカルスイッチの電極の位置に応じて決まってしまう。よって、パッケージの設計自由度が下がり、デバイスの小型化を妨げてしまう。   Therefore, in the channel of Patent Document 1, the input / output voltage cannot be extracted to an arbitrary location, and the input / output voltage extraction position is determined according to the position of the electrode of the micromechanical switch. Therefore, the degree of freedom in designing the package is lowered, which hinders downsizing of the device.

本発明は、上記問題点に鑑みて成されたものであり、その目的は、シリコン配線の引き出し箇所を任意に設定できるシリコン配線埋込ガラス基板及びその製造方法を提供することである。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a silicon wiring embedded glass substrate and a method for manufacturing the same, in which a silicon wiring drawing position can be arbitrarily set.

以上の目的を達成するために、本発明に係るシリコン配線埋込ガラス基板は、対向する第１の主面及び第２の主面と側面とを有するシリコン配線埋込ガラス基板であって、
ガラスベース部と、該ガラスベース部の内部に埋設されたシリコン配線と、を備え、
前記シリコン配線は、
前記第１の主面に露出する第１の引出部と、
前記第１の主面、前記第２の主面或いは前記側面のいずれか１つの面に露出する第２の引出部と、
前記第１の引出部及び前記第２の引出部間を接続する接続部と、を備え、
前記第１の引出部及び前記第２の引出部は、前記第１の主面の法線方向からみて異なる位置に配置されていることを特徴とする。
ここで、第１の引出部及び前記第２の引出部は、前記第１の主面の法線方向からみて異なる位置に配置されているには、第１の引出部の面方向と第２の引出部の面方向が異なることの他、第１の引出部の中心軸と第２の引出部の中心軸とが一直線上にないことを含む。 In order to achieve the above object, a silicon wiring embedded glass substrate according to the present invention is a silicon wiring embedded glass substrate having a first main surface and a second main surface and side surfaces facing each other,
A glass base portion, and silicon wiring embedded in the glass base portion,
The silicon wiring is
A first lead portion exposed on the first main surface;
A second lead portion exposed on any one of the first main surface, the second main surface or the side surface;
A connecting portion connecting between the first drawer portion and the second drawer portion,
The first lead portion and the second lead portion are arranged at different positions as viewed from the normal direction of the first main surface.
Here, in order to arrange the first lead portion and the second lead portion at different positions as viewed from the normal direction of the first main surface, the first lead portion and the second lead portion are arranged in the second direction. In addition to the difference in the surface direction of the leading portion, the central axis of the first leading portion and the central axis of the second leading portion are not in a straight line.

本発明のある態様では、前記シリコン配線埋込ガラス基板において、
前記接続部は、前記第１の引出部を一端部として含む第１の貫通接続部と該第１の貫通接続部の他端に接続された内層接続部とを含む。 In one aspect of the present invention, in the silicon wiring embedded glass substrate,
The connection part includes a first through connection part including the first lead part as one end part and an inner layer connection part connected to the other end of the first through connection part.

本発明のある態様では、前記シリコン配線埋込ガラス基板において、
前記内層接続部の一端が前記ガラスベース部の側面に露出し、その露出した一端が前記第２の引出部である。 In one aspect of the present invention, in the silicon wiring embedded glass substrate,
One end of the inner layer connection portion is exposed on the side surface of the glass base portion, and the exposed one end is the second lead portion.

本発明のある態様では、前記シリコン配線埋込ガラス基板において、
前記接続部は、前記第２の引出部を一端として含み他端が前記内層接続部に接続された第２の貫通接続部をさらに含み、前記第２の貫通接続部の中心軸が前記第１の貫通接続部の中心軸とは異なる直線上に位置する。 In one aspect of the present invention, in the silicon wiring embedded glass substrate,
The connection portion further includes a second through connection portion having the second lead portion as one end and the other end connected to the inner layer connection portion, and a central axis of the second through connection portion is the first axis. It is located on a straight line different from the central axis of the through-connection portion.

本発明のある態様では、前記シリコン配線埋込ガラス基板は、
前記第１の貫通接続部の中心軸と前記第２の貫通接続部の中心軸とが平行である。 In an aspect of the present invention, the silicon wiring embedded glass substrate is
The central axis of the first through connection portion and the central axis of the second through connection portion are parallel to each other.

本発明のある態様では、前記シリコン配線埋込ガラス基板は、
前記第１の引出部及び前記第２の引出部の少なくとも一方の露出面を覆う金属電極を更に備える。 In an aspect of the present invention, the silicon wiring embedded glass substrate is
A metal electrode is further provided to cover at least one exposed surface of the first lead portion and the second lead portion.

本発明に係るシリコン配線埋込ガラス基板の製造方法は、
ガラスベース部にシリコン配線が埋め込まれてなるシリコン配線埋込ガラス基板の製造方法であって、
第１のシリコン基板の一方の面に第１の凸部を形成して、該第１の凸部の周囲にガラスを埋込むことと、前記第１の凸部を残して前記第１のシリコン基板を除くことにより前記第１の凸部の一端面が露出する第１の主面を形成することと、その第１の主面に対向しかつ前記第１の凸部の他端面が露出するように第２の主面を形成することとを含み、前記第１の主面から前記第１の凸部の一端面が露出し、前記第１の凸部の他端面が前記第２の主面から露出する第１のガラス基板を作製する第１の工程と、
第２のシリコン基板の一方の面に第２の凸部を峰状に形成して、該第２の凸部の周囲にガラスを埋込むことと、前記第２の凸部を残して前記第２のシリコン基板を除くことにより、前記第２の凸部の第１面が露出する第１の主面を形成することと、
その第１の主面に対向しかつ前記第２の凸部の第２面が露出する第２の主面を形成することとを含み、第１の主面から前記第２の凸部の前記第１面が露出し、前記第１面に対向する第２面が前記第２の主面から露出する第２のガラス基板を作製する第２の工程と、
前記第１の凸部の一端面と前記第２の凸部の第１面とが接続されるように前記第１のガラス基板の第１の主面と前記第２のガラス基板の第１の主面とを対向させ、前記第２のガラス基板の第２の主面に第３のガラス基板を対向させて前記第１〜第３のガラス基板を接合する接合工程と、
を含むことを特徴とする。 The method for producing a silicon wiring embedded glass substrate according to the present invention comprises:
A silicon wiring embedded glass substrate manufacturing method in which silicon wiring is embedded in a glass base portion,
Forming a first protrusion on one surface of the first silicon substrate, embedding glass around the first protrusion, and leaving the first protrusion to leave the first silicon; Forming a first main surface exposing one end surface of the first convex portion by removing the substrate, and exposing the other end surface of the first convex portion facing the first main surface. Forming the second main surface as described above, one end surface of the first convex portion is exposed from the first main surface, and the other end surface of the first convex portion is the second main surface. A first step of producing a first glass substrate exposed from the surface;
Forming a second convex portion in a ridge shape on one surface of the second silicon substrate, embedding glass around the second convex portion, and leaving the second convex portion, the second convex portion; Forming a first main surface exposing the first surface of the second convex portion by removing the silicon substrate of 2;
Forming a second main surface opposite to the first main surface and exposing a second surface of the second convex portion, and from the first main surface to the second convex portion, A second step of producing a second glass substrate in which a first surface is exposed and a second surface opposite to the first surface is exposed from the second main surface;
The first main surface of the first glass substrate and the first of the second glass substrate so that one end surface of the first convex portion and the first surface of the second convex portion are connected. A bonding step of facing the main surface and bonding the first to third glass substrates with the third glass substrate facing the second main surface of the second glass substrate;
It is characterized by including.

本発明のある態様では、前記シリコン配線埋込ガラス基板の製造方法において、
前記第１の工程は、
前記第１の凸部が形成された第１のシリコン基板の一方の面にガラス基板を重ね合わせることと、当該ガラス基板に熱を加えて軟化させて、当該ガラス基板の一部を前記第１のシリコン基板の凸部の周囲に埋め込むことを含み、
前記第２の工程は、
前記第２の凸部が形成された第２のシリコン基板の一方の面にガラス基板を重ね合わせることと、当該ガラス基板に熱を加えて軟化させて、当該ガラス基板の一部を前記第２のシリコン基板の凸部の周囲に埋め込むことを含む。 In one aspect of the present invention, in the method for producing a silicon wiring embedded glass substrate,
The first step includes
A glass substrate is overlaid on one surface of the first silicon substrate on which the first protrusion is formed, and heat is applied to the glass substrate to soften the glass substrate so that a part of the glass substrate is the first surface. Including embedding around the convex portion of the silicon substrate,
The second step includes
A glass substrate is overlaid on one surface of the second silicon substrate on which the second convex portions are formed, and heat is applied to the glass substrate to soften the glass substrate so that a part of the glass substrate is the second surface. Embedding around the convex part of the silicon substrate.

本発明のある態様では、前記シリコン配線埋込ガラス基板の製造方法は、
前記接合工程において、前記第１の凸部を、金属膜を介して前記第２の凸部に接触させる。 In one aspect of the present invention, the method for producing a silicon wiring embedded glass substrate comprises:
In the joining step, the first convex portion is brought into contact with the second convex portion via a metal film.

本発明のある態様では、前記シリコン配線埋込ガラス基板の製造方法において、
前記接合工程の前に、
第３のシリコン基板の一方の面に第３の凸部を形成して、該第３の凸部の周囲にガラスを埋込むことと、前記第３の凸部を残して前記第３のシリコン基板を除くことにより前記第３の凸部の一端面が露出する第１の主面を形成することと、その第１の主面に対向しかつ前記第３の凸部の他端面が露出するように第２の主面を形成することとを含み、前記第１の主面から前記第３の凸部の一端面が露出し、前記第３の凸部の他端面が前記第２の主面から露出するように前記第３のガラス基板を作製する第３の工程を更に有し、
前記接合工程において、前記第３の凸部の一端面と前記第２の凸部の第２面とが接続されるように前記第２のガラス基板の第２の主面と前記第３のガラス基板の第１の主面とを対向させて前記第２のガラス基板と第３のガラス基板とを接合する。 In one aspect of the present invention, in the method for producing a silicon wiring embedded glass substrate,
Before the joining process,
Forming a third convex portion on one surface of the third silicon substrate, embedding glass around the third convex portion, and leaving the third convex portion, the third silicon; By removing the substrate, a first main surface that exposes one end surface of the third convex portion is formed, and the other end surface of the third convex portion is exposed to face the first main surface. Forming the second main surface as described above, one end surface of the third convex portion is exposed from the first main surface, and the other end surface of the third convex portion is the second main surface. A third step of producing the third glass substrate so as to be exposed from the surface;
In the joining step, the second main surface of the second glass substrate and the third glass so that one end surface of the third convex portion and the second surface of the second convex portion are connected. The second glass substrate and the third glass substrate are bonded with the first main surface of the substrate facing each other.

本発明のある態様では、前記シリコン配線埋込ガラス基板の製造方法において、
前記第１の工程は、
前記第１の凸部が形成された第１のシリコン基板の一方の面にガラス基板を重ね合わせることと、当該ガラス基板に熱を加えて軟化させて、当該ガラス基板の一部を前記第１のシリコン基板の凸部の周囲に埋め込むことを含み、
前記第２の工程は、
前記第２の凸部が形成された第２のシリコン基板の一方の面にガラス基板を重ね合わせることと、当該ガラス基板に熱を加えて軟化させて、当該ガラス基板の一部を前記第２のシリコン基板の凸部の周囲に埋め込むことを含み、
前記第３の工程は、
前記第３の凸部が形成された第３のシリコン基板の一方の面にガラス基板を重ね合わせることと、当該ガラス基板に熱を加えて軟化させて、当該ガラス基板の一部を前記第３のシリコン基板の凸部の周囲に埋め込むことを含む。 In one aspect of the present invention, in the method for producing a silicon wiring embedded glass substrate,
The first step includes
A glass substrate is overlaid on one surface of the first silicon substrate on which the first protrusion is formed, and heat is applied to the glass substrate to soften the glass substrate so that a part of the glass substrate is the first surface. Including embedding around the convex portion of the silicon substrate,
The second step includes
A glass substrate is overlaid on one surface of the second silicon substrate on which the second convex portions are formed, and heat is applied to the glass substrate to soften the glass substrate so that a part of the glass substrate is the second Including embedding around the convex portion of the silicon substrate,
The third step includes
A glass substrate is overlaid on one surface of the third silicon substrate on which the third convex portion is formed, and heat is applied to the glass substrate to soften the glass substrate so that a part of the glass substrate is the third surface. Embedding around the convex part of the silicon substrate.

本発明のある態様では、前記シリコン配線埋込ガラス基板の製造方法は、
前記接合工程において、前記第１の凸部及び前記第３の凸部を、金属膜を介して前記第２の凸部にそれぞれ接触させる。 In one aspect of the present invention, the method for producing a silicon wiring embedded glass substrate comprises:
In the joining step, the first convex portion and the third convex portion are brought into contact with the second convex portion via a metal film, respectively.

本発明のある態様では、前記シリコン配線埋込ガラス基板の製造方法において、
前記第１の凸部の一端と他端は、前記第１のガラス基板の第１の主面の法線方向から見て同じ位置に配置され、
前記第２の凸部の第１面と第２面は、前記第２のガラス基板の第１の主面の法線方向から見て同じ位置に配置され、
前記第３の凸部の一端と他端は、前記第３のガラス基板の第１の主面の法線方向から見て同じ位置に配置されている。 In one aspect of the present invention, in the method for producing a silicon wiring embedded glass substrate,
One end and the other end of the first convex portion are arranged at the same position when viewed from the normal direction of the first main surface of the first glass substrate,
The first surface and the second surface of the second convex portion are arranged at the same position when viewed from the normal direction of the first main surface of the second glass substrate,
One end and the other end of the third convex portion are arranged at the same position when viewed from the normal direction of the first main surface of the third glass substrate.

本発明のシリコン配線埋込ガラス基板及びその製造方法によれば、シリコン配線の引き出し箇所を任意に設定することができる。   According to the silicon wiring embedded glass substrate and the method of manufacturing the same of the present invention, the drawing position of the silicon wiring can be arbitrarily set.

図１（ａ）は、本発明の第１の実施の形態に係わる半導体装置のうちパッケージ蓋の構成を示す斜視図であり、図１（ｂ）は、本発明の第１の実施の形態に係わる半導体装置のうちパッケージ蓋を除く構成を示す斜視図である。FIG. 1A is a perspective view showing a configuration of a package lid in the semiconductor device according to the first embodiment of the present invention, and FIG. 1B is a diagram illustrating the first embodiment of the present invention. It is a perspective view which shows the structure except a package lid | cover among the semiconductor devices concerning. 図１の加速度センサチップＡの概略構成を示す分解斜視図である。It is a disassembled perspective view which shows schematic structure of the acceleration sensor chip | tip A of FIG. 図２の加速度センサチップＡの概略構成を示す断面図である。FIG. 3 is a cross-sectional view illustrating a schematic configuration of an acceleration sensor chip A in FIG. 2. 図４（ａ）は、図２及び図３に示した第１の固定基板２の形成に用いられるガラス基板２０の一例としてのシリコン配線埋込ガラス基板の構成を示す断面図であり、図４（ｂ）は、図４（ａ）に示したシリコン配線埋込ガラス基板の製造方法を示す工程断面図である。4A is a cross-sectional view showing a configuration of a silicon wiring embedded glass substrate as an example of the glass substrate 20 used for forming the first fixed substrate 2 shown in FIG. 2 and FIG. (B) is process sectional drawing which shows the manufacturing method of the silicon wiring embedded glass substrate shown to Fig.4 (a). 図４に示したシリコン配線埋込ガラス基板の製造方法において金属電極６３ｃを形成することなくシリコン配線埋込ガラス基板を作製する製造方法の工程断面図である。FIG. 5 is a process cross-sectional view of a manufacturing method for manufacturing a silicon wiring embedded glass substrate without forming a metal electrode 63c in the method for manufacturing a silicon wiring embedded glass substrate shown in FIG. 図６（ａ）〜図６（ｅ）は、第１のシリコン配線埋込ガラス基板２０１及び第２のシリコン配線埋込ガラス基板２０２の製造方法を示す工程断面図である。FIG. 6A to FIG. 6E are process cross-sectional views illustrating a method for manufacturing the first silicon wiring embedded glass substrate 201 and the second silicon wiring embedded glass substrate 202. 図７（ａ）は、本発明の第２の実施の形態に係わる半導体装置のうちパッケージ蓋の構成を示す斜視図であり、図７（ｂ）は、本発明の第２の実施の形態に係わる半導体装置のうちパッケージ蓋を除く構成を示す斜視図である。FIG. 7A is a perspective view showing the configuration of the package lid of the semiconductor device according to the second embodiment of the present invention, and FIG. 7B shows the second embodiment of the present invention. It is a perspective view which shows the structure except a package lid | cover among the semiconductor devices concerning. 図７の加速度センサチップＡの概略構成を示す分解斜視図である。It is a disassembled perspective view which shows schematic structure of the acceleration sensor chip A of FIG. 図７の加速度センサチップＡの概略構成を示す断面図である。It is sectional drawing which shows schematic structure of the acceleration sensor chip A of FIG. 図１０（ａ）は、図８及び図９に示した第１の固定基板２の形成に用いられるガラス基板２０の一例としてのシリコン配線埋込ガラス基板の構成を示す断面図であり、図１０（ｂ）は、図１０（ａ）に示したシリコン配線埋込ガラス基板の製造方法を示す工程断面図である。FIG. 10A is a cross-sectional view showing a configuration of a silicon wiring embedded glass substrate as an example of the glass substrate 20 used for forming the first fixed substrate 2 shown in FIG. 8 and FIG. (B) is process sectional drawing which shows the manufacturing method of the silicon wiring embedded glass substrate shown to Fig.10 (a). 図１０に示したシリコン配線埋込ガラス基板の製造方法において金属電極６３ｃを形成することなくシリコン配線埋込ガラス基板を作製する製造方法の工程断面図である。FIG. 11 is a process cross-sectional view of a manufacturing method for manufacturing a silicon wiring embedded glass substrate without forming a metal electrode 63c in the method for manufacturing a silicon wiring embedded glass substrate shown in FIG. 10; ブラスト加工によりガラス基板２０に形成された穴８８から表出した電極パッド１８に対して直接、ボンディングワイヤＷを接続した従来例を示す断面図である。It is sectional drawing which shows the prior art example which connected the bonding wire W directly with respect to the electrode pad 18 exposed from the hole 88 formed in the glass substrate 20 by blasting.

５２ａ 第１の凸部
５２ｂ 第２の凸部
５４ａ 第１のガラス基板
５４ｂ 第２のガラス基板
５４ｃ 第３のガラス基板
６１ ガラス基板
６２ シリコン配線
６２ａ 第１の引出部
６２ｂ 第２の引出部
６２ｃ 接続部
６３ａ〜６３ｃ 金属電極
２０１ 第１のシリコン配線埋込ガラス基板
２０２ 第２のシリコン配線埋込ガラス基板
２０３ 第３のシリコン配線埋込ガラス基板
ＳＦ１ 第１の主面
ＳＦ２ 第２の主面
ＳＦ３ 側面 52a 1st convex part 52b 2nd convex part 54a 1st glass substrate 54b 2nd glass substrate 54c 3rd glass substrate 61 Glass substrate 62 Silicon wiring 62a 1st extraction part 62b 2nd extraction part 62c Connection Part 63a to 63c Metal electrode 201 First silicon wiring embedded glass substrate 202 Second silicon wiring embedded glass substrate 203 Third silicon wiring embedded glass substrate SF1 First main surface SF2 Second main surface SF3 Side surface

以下図面を参照して、本発明の実施の形態を説明する。図面の記載において同一部分には同一符号を付している。   Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, the same parts are denoted by the same reference numerals.

（第１の実施の形態）
図１（ａ）及び図１（ｂ）を参照して、本発明の第１の実施の形態に係わる半導体装置の概略構成を説明する。半導体装置は、ＭＥＭＳデバイスの一例としての加速度センサチップＡと、加速度センサチップＡから出力された信号を処理する信号処理回路が形成された制御ＩＣチップＢと、加速度センサチップＡ及び制御ＩＣチップＢが収納された表面実装型のパッケージ１０１とを備える。 (First embodiment)
With reference to FIGS. 1A and 1B, a schematic configuration of a semiconductor device according to the first embodiment of the present invention will be described. The semiconductor device includes an acceleration sensor chip A as an example of a MEMS device, a control IC chip B on which a signal processing circuit that processes a signal output from the acceleration sensor chip A is formed, and an acceleration sensor chip A and a control IC chip B. Are mounted on the surface mounting type package 101.

パッケージ１０１は、図１（ｂ）における上面に位置する一面が開放された箱形の形状を有するプラスチックパッケージ本体１０２と、パッケージ１０１の開放された一面を閉塞するパッケージ蓋（リッド）１０３とを備える。プラスチックパッケージ本体１０２は、加速度センサチップＡ及び制御ＩＣチップＢに電気的に接続される複数のリード１１２を備える。各リード１１２は、プラスチックパッケージ本体１０２の外側面から導出されたアウタリード１１２ｂと、プラスチックパッケージ本体１０２の内側面から導出されたインナリード１１２ａとを備える。各インナリード１１２ａは、ボンディングワイヤＷを通じて、制御ＩＣチップＢが備える各パッドに電気的に接続されている。   The package 101 includes a plastic package main body 102 having a box-like shape with one open surface located on the upper surface in FIG. 1B and a package lid (lid) 103 that closes one open surface of the package 101. . The plastic package body 102 includes a plurality of leads 112 that are electrically connected to the acceleration sensor chip A and the control IC chip B. Each lead 112 includes an outer lead 112 b led out from the outer side surface of the plastic package main body 102 and an inner lead 112 a led out from the inner side surface of the plastic package main body 102. Each inner lead 112a is electrically connected to each pad included in the control IC chip B through a bonding wire W.

加速度センサチップＡは、加速度センサチップＡの外周形状に基づいて規定した仮想三角形の３つの頂点に対応する３箇所に配置された接着部１０４により、プラスチックパッケージ本体１０２の底部に位置する搭載面１０２ａに固着されている。接着部１０４は、プラスチックパッケージ本体１０２に連続して一体に突設されている円錐台状の突起部と、この突起部を被覆する接着剤とからなる。接着剤は、例えば、弾性率が１ＭＰａ以下のシリコーン樹脂などのシリコーン系樹脂からなる。   The acceleration sensor chip A has a mounting surface 102a located at the bottom of the plastic package main body 102 by the adhesive portions 104 arranged at three locations corresponding to the three vertices of the virtual triangle defined based on the outer peripheral shape of the acceleration sensor chip A. It is fixed to. The adhesive portion 104 includes a frustoconical protrusion that is continuously and integrally provided on the plastic package body 102, and an adhesive that covers the protrusion. The adhesive is made of, for example, a silicone resin such as a silicone resin having an elastic modulus of 1 MPa or less.

ここで、加速度センサチップＡが備える総てのパッドは、プラスチックパッケージ本体１０２の開放された一面に垂直な加速度センサチップＡの側面のうち、制御ＩＣチップＢに対向する一側面において、この一側面の１辺に沿って配置されている。この１辺の両端の２箇所と、当該一側面に対向する加速度センサチップＡの側面の１箇所（例えば、中央部）との３箇所とに頂点を有する仮想三角形の各頂点に接着部１０４が位置している。   Here, all the pads included in the acceleration sensor chip A are arranged on one side surface of the acceleration sensor chip A that faces the control IC chip B out of the side surfaces of the acceleration sensor chip A that are perpendicular to the open surface of the plastic package body 102. It is arranged along one side. There are adhesive portions 104 at the vertices of the virtual triangle having vertices at two locations on both ends of the one side and one location (for example, the central portion) on the side surface of the acceleration sensor chip A facing the one side surface. positioned.

制御ＩＣチップＢは、単結晶シリコン等から成る半導体基板上に形成された複数の半導体素子、これらを接続する配線、及び半導体素子や配線を外部環境から保護するパッシベーション膜からなる半導体チップである。そして、制御ＩＣチップＢの裏面全体がシリコーン系樹脂によりプラスチックパッケージ本体１０２の底面に固着されている。制御ＩＣチップＢ上に形成される信号処理回路は、加速度センサチップＡの機能に応じて適宜設計すればよく、加速度センサチップＡと協働するものであればよい。例えば、制御ＩＣチップＢをＡＳＩＣ（Application Specific ＩＣ）として形成することができる。   The control IC chip B is a semiconductor chip formed of a plurality of semiconductor elements formed on a semiconductor substrate made of single crystal silicon or the like, wirings connecting them, and a passivation film that protects the semiconductor elements and wirings from the external environment. The entire back surface of the control IC chip B is fixed to the bottom surface of the plastic package body 102 with a silicone resin. The signal processing circuit formed on the control IC chip B may be appropriately designed according to the function of the acceleration sensor chip A, and may be any one that cooperates with the acceleration sensor chip A. For example, the control IC chip B can be formed as an ASIC (Application Specific IC).

図１の半導体装置を製造するには、先ず、加速度センサチップＡ及び制御ＩＣチップＢをプラスチックパッケージ本体１０２に固着するダイボンディング工程を行う。そして、加速度センサチップＡと制御ＩＣチップＢとの間、制御ＩＣチップＢとインナリード１１２ａとの間を、それぞれボンディングワイヤＷを介して電気的に接続するワイヤーボンディング工程を行う。その後、樹脂被覆部１１６を形成する樹脂被覆部形成工程を行い、続いて、パッケージ蓋（リッド）１０３の外周を、プラスチックパッケージ本体１０２に接合するシーリング工程を行う。これにより、プラスチックパッケージ本体１０２の内部は気密状態で封止される。なお、パッケージ蓋１０３の適宜部位には、レーザマーキング技術により、製品名称や製造日時などを示す表記１１３が形成されている。   In order to manufacture the semiconductor device of FIG. 1, first, a die bonding process for fixing the acceleration sensor chip A and the control IC chip B to the plastic package body 102 is performed. Then, a wire bonding step of electrically connecting the acceleration sensor chip A and the control IC chip B and the control IC chip B and the inner lead 112a via the bonding wires W is performed. Thereafter, a resin coating portion forming step for forming the resin coating portion 116 is performed, and subsequently, a sealing step for bonding the outer periphery of the package lid 103 to the plastic package body 102 is performed. Thereby, the inside of the plastic package main body 102 is sealed in an airtight state. Note that a notation 113 indicating a product name, a manufacturing date and the like is formed in an appropriate part of the package lid 103 by a laser marking technique.

なお、制御ＩＣチップＢが１枚のシリコン基板を用いて形成されているのに対して、加速度センサチップＡは、積層された複数の基板を用いて形成されている。よって、加速度センサチップＡの厚みが制御ＩＣチップＢの厚みに比べて厚くなっているので、プラスチックパッケージ本体１０２の底部において加速度センサチップＡを搭載する搭載面１０２ａを制御ＩＣチップＢの搭載部位よりも凹ませてある。したがって、プラスチックパッケージ本体１０２の底面について、加速度センサチップＡを搭載する部位の厚みは他の部位に比べて薄くなっている。   The control IC chip B is formed using a single silicon substrate, whereas the acceleration sensor chip A is formed using a plurality of stacked substrates. Therefore, since the thickness of the acceleration sensor chip A is thicker than the thickness of the control IC chip B, the mounting surface 102a on which the acceleration sensor chip A is mounted at the bottom of the plastic package body 102 is formed from the mounting portion of the control IC chip B. Is also recessed. Therefore, on the bottom surface of the plastic package main body 102, the thickness of the portion where the acceleration sensor chip A is mounted is thinner than other portions.

更に、本発明の第１の実施の形態では、プラスチックパッケージ本体１０２の外形を直方体としてあるが、これは一例であり、加速度センサチップＡや制御ＩＣチップＢの外形、リード１１２の本数やピッチなどに応じて適宜設定すればよい。   Furthermore, in the first embodiment of the present invention, the outer shape of the plastic package body 102 is a rectangular parallelepiped, but this is only an example, and the outer shape of the acceleration sensor chip A and the control IC chip B, the number of leads 112, the pitch, etc. What is necessary is just to set suitably according to.

プラスチックパッケージ本体１０２の材料としては、熱可塑性樹脂の一種であって、酸素および水蒸気の透過率が極めて低い液晶性ポリエステル（ＬＣＰ）を採用する。しかし、ＬＣＰに限らず、例えば、ポリフェニレンサルファイト（ＰＰＳ）、ポリビスアミドトリアゾール（ＰＢＴ）などを採用してもよい。   As a material of the plastic package body 102, a liquid crystalline polyester (LCP) which is a kind of thermoplastic resin and has extremely low oxygen and water vapor transmission rates is employed. However, not limited to LCP, for example, polyphenylene sulfite (PPS), polybisamide triazole (PBT), or the like may be employed.

また、各リード１１２の材料、つまり、各リード１１２の基礎となるリードフレームの材料としては、銅合金の中でもばね性の高いりん青銅を採用する。ここでは、リードフレームとして、材質がりん青銅で板厚が０．２ｍｍのリードフレームを用い、厚みが２μｍ〜４μｍのＮｉ膜と、厚みが０．２μｍ〜０．３μｍのＡｕ膜との積層膜からなるめっき膜を電解めっき法により形成してある。これにより、ワイヤーボンディングの接合信頼性と半田付け信頼性とを両立させることができる。また、熱可塑性樹脂成形品のプラスチックパッケージ本体１０２は、リード１１２が同時一体に成形されている。しかし、熱可塑性樹脂であるＬＣＰにより形成されるプラスチックパッケージ本体１０２とリード１１２のＡｕ膜とは密着性が低い。したがって、上述のリードフレームのうちプラスチックパッケージ本体１０２に埋設される部位にパンチ穴を設けることで各リード１１２が抜け落ちるのを防止する。 As the material of each lead 112, that is, the material of the lead frame that is the basis of each lead 112, phosphor bronze having high spring property among copper alloys is employed. Here, a lead frame made of phosphor bronze and having a thickness of 0.2 mm is used as the lead frame, and a laminated film of a Ni film having a thickness of 2 μm to 4 μm and an Au film having a thickness of 0.2 μm to 0.3 μm. A plating film made of is formed by an electrolytic plating method. Thereby, the joining reliability and soldering reliability of wire bonding can be made compatible. Also, plastic package body 102 of thermoplastic resin molded article, the lead 112 is molded simultaneously integrally. However, the adhesion between the plastic package body 102 formed by LCP, which is a thermoplastic resin, and the Au film of the lead 112 is low. Therefore, the lead 112 is prevented from falling off by providing a punch hole in a portion of the above-described lead frame embedded in the plastic package body 102.

また、図１の半導体装置は、インナリード１１２ａの露出部位およびその周囲を覆う樹脂被覆部１１６が設けられている。樹脂被覆部１１６は、例えば、アミン系エポキシ樹脂などのエポキシ系樹脂などの非透湿性の樹脂からなる。ワイヤーボンディング工程の後に、ディスペンサを用いてこの非透湿性の樹脂を塗布し、これを硬化させることで、気密性を向上させている。なお、この非透湿性の樹脂に代えてセラミックスを用いてもよく、セラミックスを用いる場合には、プラズマ溶射などの技術を用いて局所的に吹き付ければよい。   In addition, the semiconductor device of FIG. 1 is provided with a resin coating 116 that covers the exposed portion of the inner lead 112a and its periphery. The resin coating portion 116 is made of a moisture-impermeable resin such as an epoxy resin such as an amine epoxy resin. After the wire bonding process, this non-moisture permeable resin is applied using a dispenser and cured to improve airtightness. Note that ceramics may be used instead of the moisture-impermeable resin, and when ceramics are used, they may be sprayed locally using a technique such as plasma spraying.

また、ボンディングワイヤＷとしては、Ａｌワイヤに比べて耐腐食性の高いＡｕワイヤを用いる。また、直径が２５μｍのＡｕワイヤを採用するが、これに限らず、例えば、直径が２０μｍ〜５０μｍのＡｕワイヤから適宜選択すればよい。   Further, as the bonding wire W, an Au wire having higher corrosion resistance than the Al wire is used. In addition, although an Au wire having a diameter of 25 μm is adopted, the present invention is not limited thereto, and for example, an Au wire having a diameter of 20 μm to 50 μm may be appropriately selected.

図２を参照して、図１の加速度センサチップＡの概略構成を説明する。加速度センサチップＡは、静電容量型の加速度センサチップであって、ＳＯＩ（Silicon On Insulator）
基板１０を用いて形成されたセンサ本体１と、ガラス基板２０を用いて形成された第１の固定基板２と、ガラス基板３０を用いて形成された第２の固定基板３とを備えている。第１の固定基板２は、センサ本体１の一表面側（図２における上面側）に固着され、第２の固定基板３は、センサ本体１の他表面側（図２における下面側）に固着される。第１及び第２の固定基板２、３はセンサ本体１と同じ外形寸法に形成されている。 A schematic configuration of the acceleration sensor chip A of FIG. 1 will be described with reference to FIG. The acceleration sensor chip A is a capacitance type acceleration sensor chip, which is an SOI (Silicon On Insulator).
A sensor main body 1 formed using a substrate 10, a first fixed substrate 2 formed using a glass substrate 20, and a second fixed substrate 3 formed using a glass substrate 30 are provided. . The first fixed substrate 2 is fixed to one surface side (upper surface side in FIG. 2) of the sensor body 1, and the second fixed substrate 3 is fixed to the other surface side (lower surface side in FIG. 2) of the sensor body 1. Is done. The first and second fixed substrates 2 and 3 are formed to have the same outer dimensions as the sensor body 1.

なお、図２は、センサ本体１、第１の固定基板２及び第２の固定基板３のそれぞれの構成を示すべく、センサ本体１、第１の固定基板２及び第２の固定基板３が分離した状態を示している。また、センサ本体１は、ＳＯＩ基板１０に限らず、例えば、絶縁層を備えない通常のシリコン基板を用いて形成してもよい。また、第１及び第２の固定基板２、３は、それぞれ、シリコン基板及びガラス基板のどちらで形成してもかまわない。   2 shows that the sensor main body 1, the first fixed substrate 2 and the second fixed substrate 3 are separated to show the respective configurations of the sensor main body 1, the first fixed substrate 2 and the second fixed substrate 3. Shows the state. The sensor body 1 is not limited to the SOI substrate 10 and may be formed using, for example, a normal silicon substrate that does not include an insulating layer. Further, the first and second fixed substrates 2 and 3 may be formed of either a silicon substrate or a glass substrate, respectively.

センサ本体１は、２つの平面視矩形状の開口窓１２が上記一表面に沿って並設するフレーム部１１と、フレーム部１１の各開口窓１２の内側に配置された２つの平面視矩形状の重り部１３と、フレーム部１１と重り部１３との間を連結する各一対の支持ばね部１４とを備える。   The sensor main body 1 includes a frame portion 11 in which two rectangular windows 12 in a plan view are arranged side by side along the one surface, and two rectangular shapes in a plan view arranged inside each open window 12 of the frame portion 11. The weight part 13 and a pair of support spring parts 14 for connecting the frame part 11 and the weight part 13 to each other are provided.

２つの平面視矩形状の重り部１３は、第１及び第２の固定基板２、３からそれぞれ離間して配置されている。第１の固定基板２に対向する各重り部１３の主面上に可動電極１５Ａ、１５Ｂがそれぞれ配置されている。重り部１３の周囲を囲むフレーム部１１の外周全体が第１及び第２の固定基板２、３に接合されている。これにより、フレーム部１１と第１及び第２の固定基板２、３は、重り部１３及び後述する固定子１６を収納するチップサイズパッケージを構成している。   The two weight portions 13 having a rectangular shape in a plan view are arranged separately from the first and second fixed substrates 2 and 3, respectively. Movable electrodes 15A and 15B are arranged on the main surface of each weight portion 13 facing the first fixed substrate 2, respectively. The entire outer periphery of the frame portion 11 surrounding the weight portion 13 is joined to the first and second fixed substrates 2 and 3. Thus, the frame portion 11 and the first and second fixed substrates 2 and 3 constitute a chip size package that houses the weight portion 13 and a stator 16 described later.

一対の支持ばね部１４は、フレーム部１１の各開口窓１２の内側で重り部１３の重心を通る直線に沿って重り部１３を挟む形で配置されている。各支持ばね部１４は、ねじれ変形が可能なトーションばね（トーションバー）であって、フレーム部１１及び重り部１３に比べて薄肉に形成されており、重り部１３は、フレーム部１１に対して一対の支持ばね部１４の回りで変位可能となっている。   The pair of support spring portions 14 are arranged so as to sandwich the weight portion 13 along a straight line passing through the center of gravity of the weight portion 13 inside each opening window 12 of the frame portion 11. Each support spring portion 14 is a torsion spring (torsion bar) capable of torsional deformation, and is formed to be thinner than the frame portion 11 and the weight portion 13. It can be displaced around the pair of support spring portions 14.

センサ本体１のフレーム部１１には、各開口窓１２それぞれに連通する平面視矩形状の窓孔１７が２つの開口窓１２と同じ方向に並設されている。各窓孔１７の内側には、それぞれ２つの固定子１６が一対の支持ばね部１４の並設方向に沿って配置されている。   In the frame portion 11 of the sensor main body 1, a window hole 17 having a rectangular shape in plan view that communicates with each of the opening windows 12 is provided side by side in the same direction as the two opening windows 12. Inside each window hole 17, two stators 16 are arranged along the direction in which the pair of support spring portions 14 are arranged side by side.

各固定子１６と窓孔１７の内周面との間、各固定子１６と重り部１３の外周面との間、及び隣り合う固定子１６同士の間には、それぞれ隙間が形成され、互いに分離独立して電気的に絶縁されている。各固定子１６は、第１及び第２の固定基板２、３にそれぞれ接合されている。また、センサ本体１の一表面側において、各固定子１６には、例えば、Ａｌ−Ｓｉ膜などの金属薄膜からなる円形状の電極パッド１８が形成されている。また同様に、フレーム部１１において隣り合う窓孔１７の間の部位にも、例えば、Ａｌ−Ｓｉ膜などの金属薄膜からなる円形状の電極パッド１８が形成されている。   A gap is formed between each stator 16 and the inner peripheral surface of the window hole 17, between each stator 16 and the outer peripheral surface of the weight portion 13, and between adjacent stators 16. Separated and independently electrically insulated. Each stator 16 is joined to the first and second fixed substrates 2 and 3, respectively. In addition, on one surface side of the sensor body 1, each stator 16 is formed with a circular electrode pad 18 made of a metal thin film such as an Al—Si film. Similarly, a circular electrode pad 18 made of, for example, a metal thin film such as an Al—Si film is formed in a portion between adjacent window holes 17 in the frame portion 11.

各固定子１６に形成された各電極パッド１８は、後述の各固定電極２５に電気的にそれぞれ接続され、フレーム部１１に形成された電極パッド１８は、可動電極１５Ａ及び可動電極１５Ｂに電気的に接続されている。以上説明した複数の電極パッド１８は、加速度センサチップＡの矩形状の外周形状の１辺に沿って配置されている。   Each electrode pad 18 formed on each stator 16 is electrically connected to each fixed electrode 25 described later, and the electrode pad 18 formed on the frame portion 11 is electrically connected to the movable electrode 15A and the movable electrode 15B. It is connected to the. The plurality of electrode pads 18 described above are arranged along one side of the rectangular outer peripheral shape of the acceleration sensor chip A.

第１の固定基板２は、ガラス基板２０の一表面（センサ本体１に重なり合う面）とガラス基板２０の側面との間を貫通する複数の配線２８と、ガラス基板２０の一表面上に形成された複数の固定電極２５とを備える。   The first fixed substrate 2 is formed on one surface of the glass substrate 20 and a plurality of wirings 28 penetrating between one surface of the glass substrate 20 (the surface overlapping the sensor body 1) and the side surface of the glass substrate 20. A plurality of fixed electrodes 25.

固定電極２５Ａａ及び固定電極２５Ａｂは、対を成して可動電極１５Ａに対向して配置されている。同様に、固定電極２５Ｂａ及び固定電極２５Ｂｂは、対を成して可動電極１５Ｂに対向して配置されている。各固定電極２５は、例えば、Ａｌ−Ｓｉ膜などの金属薄膜からなる。   The fixed electrode 25Aa and the fixed electrode 25Ab are arranged in a pair so as to face the movable electrode 15A. Similarly, the fixed electrode 25Ba and the fixed electrode 25Bb are arranged in a pair so as to face the movable electrode 15B. Each fixed electrode 25 is made of a metal thin film such as an Al—Si film, for example.

各配線２８の一端は、ガラス基板２０の一表面において、センサ本体１の電極パッド１８にそれぞれ電気的に接続されている。各配線２８の他端は、ガラス基板２０の側面に表出している。これにより、電極パッド１８を介して、各固定電極２５の電位及び可動電極１５の電位をそれぞれ加速度センサチップＡの外部（側面）へ取り出すことができる。各配線２８の他端には金属電極２９がそれぞれ接続されている。図１のボンディングワイヤＷは、金属電極２９に接続されている。   One end of each wiring 28 is electrically connected to the electrode pad 18 of the sensor body 1 on one surface of the glass substrate 20. The other end of each wiring 28 is exposed on the side surface of the glass substrate 20. Thereby, the potential of each fixed electrode 25 and the potential of the movable electrode 15 can be taken out to the outside (side surface) of the acceleration sensor chip A via the electrode pad 18. A metal electrode 29 is connected to the other end of each wiring 28. The bonding wire W in FIG. 1 is connected to the metal electrode 29.

第２の固定基板３の一表面（センサ本体１に重なり合う面）であって、重り部１３と対応する位置に、例えば、Ａｌ−Ｓｉ膜などの金属薄膜からなる付着防止膜３５が配置されている。付着防止膜３５は、変位する重り部１３の付着を防止する。   An adhesion preventing film 35 made of a metal thin film such as an Al—Si film is disposed on one surface of the second fixed substrate 3 (a surface overlapping the sensor main body 1) at a position corresponding to the weight portion 13. Yes. The adhesion preventing film 35 prevents adhesion of the weight part 13 that is displaced.

図３を参照して、図２の加速度センサチップＡの断面構成を説明する。図３は、一対の支持ばね部１４を通る直線に垂直な切断面における加速度センサチップＡの構成を示す。センサ本体１はＳＯＩ基板１０を用いて形成されている。ＳＯＩ基板１０は、単結晶シリコンからなる支持基板１０ａと、支持基板１０ａの上に配置されたシリコン酸化膜からなる絶縁層１０ｂと、絶縁層１０ｂの上に配置されたｎ形のシリコン層（活性層）１０ｃとを有する。   With reference to FIG. 3, the cross-sectional structure of the acceleration sensor chip A of FIG. 2 will be described. FIG. 3 shows a configuration of the acceleration sensor chip A on a cut surface perpendicular to a straight line passing through the pair of support spring portions 14. The sensor body 1 is formed using an SOI substrate 10. The SOI substrate 10 includes a support substrate 10a made of single crystal silicon, an insulating layer 10b made of a silicon oxide film arranged on the support substrate 10a, and an n-type silicon layer (active) arranged on the insulating layer 10b. Layer) 10c.

センサ本体１のうち、フレーム１１及び固定子１６は、第１の固定基板２及び第２の固定基板３に接合されている。これに対して、重り部１３は、第１及び第２の固定基板２、３からそれぞれ離間して配置され、一対の支持ばね部１４によりフレーム１１に支持されている。   In the sensor body 1, the frame 11 and the stator 16 are joined to the first fixed substrate 2 and the second fixed substrate 3. On the other hand, the weight portion 13 is disposed separately from the first and second fixed substrates 2 and 3, and is supported by the frame 11 by a pair of support spring portions 14.

重り部１３の過度の変位を規制する複数の微小な突起部１３ｃが、重り部１３における第１及び第２の固定基板２、３のそれぞれとの対向面から突設されている。重り部１３には、矩形状に開口された凹部１３ａ、１３ｂが形成されている。凹部１３ａ、１３ｂは互いに大きさが異なるため、一対の支持ばね部１４を通る直線を境にして、重り部１３の左右の質量が異なっている。   A plurality of minute protrusions 13 c that restrict excessive displacement of the weight part 13 are provided so as to protrude from the surfaces of the weight part 13 facing the first and second fixed substrates 2 and 3. The weight portion 13 is formed with concave portions 13a and 13b opened in a rectangular shape. Since the sizes of the recesses 13a and 13b are different from each other, the masses on the left and right of the weight portion 13 are different from each other with a straight line passing through the pair of support spring portions 14 as a boundary.

第１の固定基板２の配線２８の一端は、電極パッド１８に電気的に接続されている。電極パッド１８は、固定子１６、連絡用導体部１６ｄ、金属配線２６を通じて、固定電極２５に接続されている。配線２８は、ガラス基板２０の一表面に平行な方向に延伸され、配線２８の他端は、ガラス基板２０の側面に表出する。ガラス基板２０の側面のうち配線２８の他端が位置する領域には金属電極２９が形成されている。   One end of the wiring 28 of the first fixed substrate 2 is electrically connected to the electrode pad 18. The electrode pad 18 is connected to the fixed electrode 25 through the stator 16, the connecting conductor portion 16 d, and the metal wiring 26. The wiring 28 extends in a direction parallel to one surface of the glass substrate 20, and the other end of the wiring 28 appears on the side surface of the glass substrate 20. A metal electrode 29 is formed in a region of the side surface of the glass substrate 20 where the other end of the wiring 28 is located.

上述の加速度センサチップＡは、センサ本体１に設けられた可動電極１５と第１の固定基板２に設けられた固定電極２５との対を４対有し、可動電極１５と固定電極２５との対ごとに可変容量コンデンサが構成されている。加速度センサチップＡ、すなわち重り部１３に加速度が加わると、支持ばね部１４がねじれて、重り部１３が変位する。これにより、対をなす固定電極２５と可動電極１５との対向面積及び間隔が変化し、可変容量コンデンサの静電容量が変化する。よって、加速度センサチップＡは、この静電容量の変化から加速度を検出することができる。   The acceleration sensor chip A described above has four pairs of the movable electrode 15 provided on the sensor body 1 and the fixed electrode 25 provided on the first fixed substrate 2. A variable capacitor is configured for each pair. When acceleration is applied to the acceleration sensor chip A, that is, the weight portion 13, the support spring portion 14 is twisted and the weight portion 13 is displaced. As a result, the facing area and interval between the paired fixed electrode 25 and movable electrode 15 change, and the capacitance of the variable capacitor changes. Therefore, the acceleration sensor chip A can detect acceleration from the change in capacitance.

次に、図４（ａ）を参照して、図２及び図３に示した第１の固定基板２の形成に用いられるガラス基板２０の一例としてのシリコン配線埋込ガラス基板の構成を説明する。シリコン配線埋込ガラス基板は、ガラス基板６１と、ガラス基板６１の内部に配置されたシリコン配線６２とを備える。ガラス基板６１は、対向する第１の主面ＳＦ１及び第２の主面ＳＦ２と、この第１の主面ＳＦ１及び第２の主面ＳＦ２の外周に接続された側面ＳＦ３とで規定される。   Next, with reference to FIG. 4A, a configuration of a silicon wiring embedded glass substrate as an example of the glass substrate 20 used for forming the first fixed substrate 2 shown in FIGS. 2 and 3 will be described. . The silicon wiring embedded glass substrate includes a glass substrate 61 and silicon wiring 62 arranged inside the glass substrate 61. The glass substrate 61 is defined by a first main surface SF1 and a second main surface SF2 facing each other, and a side surface SF3 connected to the outer periphery of the first main surface SF1 and the second main surface SF2.

シリコン配線６２は、ガラス基板６１の第１の主面ＳＦ１に露出する第１の引出部６２ａと、ガラス基板６１の第１の主面ＳＦ１、第２の主面ＳＦ２或いは側面ＳＦ３のいずれか１つの面に露出する第２の引出部６２ｂと、第１の引出部６２ａ及び第２の引出部６２ｂに接続された接続部６２ｃとを備える。第１の実施の形態では、第２の引出部６２ｂが、ガラス基板６１の側面ＳＦ３に露出している場合を示す。
尚、本明細書において、接続部６２ｃにおいて、第１のシリコン配線埋込ガラス基板２０１に形成された部分を貫通接続部といい、第２のシリコン配線埋込ガラス基板２０２に形成された部分を内層接続部ともいう。 The silicon wiring 62 includes a first lead portion 62a exposed on the first main surface SF1 of the glass substrate 61, and any one of the first main surface SF1, the second main surface SF2, or the side surface SF3 of the glass substrate 61. A second lead portion 62b exposed on one surface, and a connection portion 62c connected to the first lead portion 62a and the second lead portion 62b. In the first embodiment, a case where the second lead portion 62b is exposed on the side surface SF3 of the glass substrate 61 is shown.
In the present specification, in the connection portion 62c, a portion formed in the first silicon wiring embedded glass substrate 201 is referred to as a through connection portion, and a portion formed in the second silicon wiring embedded glass substrate 202 is referred to as a through connection portion. Also called inner layer connection.

第１の引出部６２ａ及び第２の引出部６２ｂは、第１の主面ＳＦ１の法線方向から見て異なる位置に配置されている。   The first lead portion 62a and the second lead portion 62b are arranged at different positions when viewed from the normal direction of the first main surface SF1.

シリコン配線埋込ガラス基板は、第１の引出部６２ａ及び第２の引出部６２ｂの露出面をそれぞれ覆う金属電極６３ａ、６３ｂと、接続部６２ｃの途中に配置された金属電極６３ｃとを更に備える。   The silicon wiring embedded glass substrate further includes metal electrodes 63a and 63b that respectively cover the exposed surfaces of the first lead portion 62a and the second lead portion 62b, and a metal electrode 63c disposed in the middle of the connection portion 62c. .

このように、シリコン配線埋込ガラス基板は、ガラス基板６１にシリコン配線６２が埋め込まれたものである。そして、シリコン配線６２の一端は、ガラス基板６１の第１の主面ＳＦ１に表出し、シリコン配線６２の他端は、ガラス基板６１の側面ＳＦ３に表出している。よって、図４（ａ）のシリコン配線６２を図２及び図３に示した配線２８に当てはめ、図４（ａ）のガラス基板６１を図２及び図３に示したガラス基板２０に当てはめる。そして、図４（ａ）の金属電極６３ｂを図２及び図３に示した金属電極２９に当てはめる。これにより、図２及び図３に示した第１の固定基板２の形成に用いられるガラス基板２０に、図４（ａ）に示したシリコン配線埋込ガラス基板を適用することができる。この場合、図４（ａ）のシリコン配線６２は、図２及び図３に示したセンサ本体１に入力される電気信号及びセンサ本体１から出力される電気信号を伝達する。   As described above, the silicon wiring embedded glass substrate is a glass substrate 61 in which the silicon wiring 62 is embedded. One end of the silicon wiring 62 is exposed on the first main surface SF <b> 1 of the glass substrate 61, and the other end of the silicon wiring 62 is exposed on the side surface SF <b> 3 of the glass substrate 61. Therefore, the silicon wiring 62 in FIG. 4A is applied to the wiring 28 shown in FIGS. 2 and 3, and the glass substrate 61 in FIG. 4A is applied to the glass substrate 20 shown in FIGS. Then, the metal electrode 63b in FIG. 4A is applied to the metal electrode 29 shown in FIGS. Accordingly, the silicon wiring embedded glass substrate shown in FIG. 4A can be applied to the glass substrate 20 used for forming the first fixed substrate 2 shown in FIGS. 2 and 3. In this case, the silicon wiring 62 in FIG. 4A transmits the electrical signal input to the sensor body 1 and the electrical signal output from the sensor body 1 shown in FIGS.

図４（ｂ）を参照して、図４（ａ）に示したシリコン配線埋込ガラス基板の製造方法を説明する。   With reference to FIG.4 (b), the manufacturing method of the silicon wiring embedded glass substrate shown to Fig.4 (a) is demonstrated.

（イ）先ず、単結晶シリコンから成る第１の凸部５２ａの周囲に第１のガラス基板５４ａを埋込み、第１のガラス基板５４ａの対向する表裏面に第１の凸部５２ａの両端部をそれぞれ露出させる。これにより、第１のシリコン配線埋込ガラス基板２０１を形成する（第１の工程）。その後、第１のガラス基板５４ａの表裏面のうち、第１の凸部５２ａの両端部が露出した部分に、フォトリソグラフィ方法、及びメッキ処理、スパッタリング、或いは化学的気相成長法（ＣＶＤ）等の成膜方法により、銅やアルミニウムからなる金属電極６３ａを形成する。なお、第１のシリコン配線埋込ガラス基板２０１及び後述する第２のシリコン配線埋込ガラス基板２０２を製造する詳細な工程は、図６を参照して、後述する。   (A) First, the first glass substrate 54a is embedded around the first convex portion 52a made of single crystal silicon, and both end portions of the first convex portion 52a are formed on the front and back surfaces of the first glass substrate 54a facing each other. Expose each one. Thereby, a first silicon wiring embedded glass substrate 201 is formed (first step). Thereafter, a portion of the front and back surfaces of the first glass substrate 54a where both ends of the first convex portion 52a are exposed is exposed to photolithography, plating, sputtering, chemical vapor deposition (CVD), or the like. The metal electrode 63a made of copper or aluminum is formed by the film forming method. A detailed process for manufacturing the first silicon wiring embedded glass substrate 201 and a second silicon wiring embedded glass substrate 202 described later will be described later with reference to FIG.

（ロ）そして、単結晶シリコンから成る第２の凸部５２ｂの周囲に第２のガラス基板５４ｂを埋込み、第２のガラス基板５４ｂの対向する表裏面の一方の面及び側面に第２の凸部５２ｂの両端部をそれぞれ露出させる。これにより、第２のシリコン配線埋込ガラス基板２０２を形成する（第２の工程）。その後、第２のガラス基板５４ｂの側面のうち、第２の凸部５２ｂの端部が露出した部分に、金属電極６３ｂを形成する。   (B) Then, the second glass substrate 54b is embedded around the second protrusion 52b made of single crystal silicon, and the second protrusion is formed on one surface and the side surface of the second glass substrate 54b facing each other. Both end portions of the portion 52b are exposed. Thereby, the second silicon wiring embedded glass substrate 202 is formed (second step). Then, the metal electrode 63b is formed in the part which the edge part of the 2nd convex part 52b exposed among the side surfaces of the 2nd glass substrate 54b.

（ハ）平板状の第３のガラス基板５４ｃをそのまま、第３のシリコン配線埋込ガラス基板２０３として、用意する（第３の工程）。第１の実施の形態において、第３のシリコン配線埋込ガラス基板２０３は、ガラス基板５４ｃのみから成り、シリコンからなる凸部を有していない。 (C) A plate-like third glass substrate 54c is prepared as it is as a third silicon wiring embedded glass substrate 203 (third step) . In the first embodiment, the third embedded silicon wiring glass substrate 203 is made only of the glass substrate 54c and does not have a convex portion made of silicon.

（ニ）図４（ｂ）に示すように、第２のシリコン配線埋込ガラス基板２０２の表裏面を、第１のシリコン配線埋込ガラス基板２０１及び第３のシリコン配線埋込ガラス基板２０３で挟む（第４の工程）。そして、金属電極６３ｃを介して第１の凸部５２ａを第２の凸部５２ｂに接触させる（第５の工程）。その後、第１乃至第３のシリコン配線埋込ガラス基板２０１〜２０３を、溶融接合、陽極接合、表面活性化結合、或いは樹脂接着などの方法により接合する（第６の工程）。第１〜第６の工程を実施することにより、図４（ａ）に示したシリコン配線埋込ガラス基板を製造することができる。   (D) As shown in FIG. 4B, the front and back surfaces of the second silicon wiring embedded glass substrate 202 are replaced with the first silicon wiring embedded glass substrate 201 and the third silicon wiring embedded glass substrate 203. (4th process). And the 1st convex part 52a is made to contact the 2nd convex part 52b via the metal electrode 63c (5th process). Thereafter, the first to third silicon wiring embedded glass substrates 201 to 203 are bonded by a method such as fusion bonding, anodic bonding, surface activation bonding, or resin bonding (sixth step). By performing the first to sixth steps, the silicon wiring embedded glass substrate shown in FIG. 4A can be manufactured.

以上の製造方法では、金属電極６３ｃを介して第１の凸部５２ａを第２の凸部５２ｂに接触させるようにした。このようにすると、第１の凸部５２ａと第２の凸部５２ｂとを接合する際に、第１の凸部５２ａと第２の凸部５２ｂ間の酸化膜の形成を容易に防止することができる。
しかしながら、本発明はこれに限定されるものではなく、図５に示すように、金属電極６３ｃを形成することなく、第１の凸部５２ａと第２の凸部５２ｂ間の酸化膜の形成を防止しながら、第１の凸部５２ａを第２の凸部５２ｂに接触させるようにしてもよい。 In the above manufacturing method, the first convex portion 52a is brought into contact with the second convex portion 52b through the metal electrode 63c. In this way, when the first convex portion 52a and the second convex portion 52b are joined, the formation of an oxide film between the first convex portion 52a and the second convex portion 52b is easily prevented. Can do.
However, the present invention is not limited to this, and as shown in FIG. 5, the formation of an oxide film between the first convex portion 52a and the second convex portion 52b can be performed without forming the metal electrode 63c. You may make it make the 1st convex part 52a contact the 2nd convex part 52b, preventing.

図６（ａ）〜図６（ｅ）を参照して、第１のシリコン配線埋込ガラス基板２０１及び第２のシリコン配線埋込ガラス基板２０２の製造方法の一例を説明する。   With reference to FIGS. 6A to 6E, an example of a method for manufacturing the first silicon wiring embedded glass substrate 201 and the second silicon wiring embedded glass substrate 202 will be described.

（い）先ず、図６（ｂ）に示すように、単結晶シリコンから成る平板状のシリコン基板５１を用意し、その主面（図６における上面）に凸部５２を形成する（第１段階）。なお、シリコン基板５１の全体には、ｐ型或いはｎ型の不純物が添加され、シリコン基板５１の電気抵抗は十分に小さい。ここでは、シリコン基板５１の全体に不純物を添加する場合を説明するが、シリコン基板５１全体に添加されていなくても構わない。少なくとも、シリコン配線６２として残す部分の深さまで不純物が添加されていればよい。   (Ii) First, as shown in FIG. 6B, a flat silicon substrate 51 made of single crystal silicon is prepared, and a convex portion 52 is formed on the main surface (upper surface in FIG. 6) (first step). ). Note that p-type or n-type impurities are added to the entire silicon substrate 51, and the electric resistance of the silicon substrate 51 is sufficiently small. Here, a case where an impurity is added to the entire silicon substrate 51 will be described. However, the impurity may not be added to the entire silicon substrate 51. It is sufficient that impurities are added at least to the depth of the portion to be left as the silicon wiring 62.

具体的には、先ず、図６（ａ）に示すように、フォトリソグラフィ技術を用いて、シリコン基板５１の主面のうち、凸部５２に対応する領域にレジスト膜５５を選択的に形成する。そして、レジスト膜５５をエッチングマスクとして用いて、ＴＭＡＨ（水酸化テトラメチルアンモニウム）水溶液をエッチャントとするウェットエッチングや反応性イオンエッチング（ＲＩＥ）などのドライエッチングを行う。これにより、シリコン基板５１の主面のうち、レジスト膜５５が形成されていない領域を選択的に除去して、シリコン基板５１の主面に凸部５２を形成することができる。   Specifically, first, as shown in FIG. 6A, a resist film 55 is selectively formed in a region corresponding to the convex portion 52 in the main surface of the silicon substrate 51 by using a photolithography technique. . Then, using the resist film 55 as an etching mask, dry etching such as wet etching or reactive ion etching (RIE) using a TMAH (tetramethylammonium hydroxide) aqueous solution as an etchant is performed. Thereby, a region where the resist film 55 is not formed in the main surface of the silicon substrate 51 can be selectively removed, and the convex portion 52 can be formed on the main surface of the silicon substrate 51.

（ろ）図６（ｃ）に示すように、対向する第１の主面（図６における下面）及び第２の主面（図６における上面）を有するガラス基板５４を用意する。そして、シリコン基板５１の主面にガラス基板５４の第１の主面を重ね合わせる（第２段階）。なお、重ね合わせたシリコン基板５１の凸部５２の頂上面とガラス基板５４の第１の主面とを、陽極接合、表面活性化結合、樹脂接着などの方法により接合してもよい。 (B) As shown in FIG. 6C, a glass substrate 54 having a first main surface (lower surface in FIG. 6) and a second main surface (upper surface in FIG. 6) facing each other is prepared. Then, the first main surface of the glass substrate 54 is overlaid on the main surface of the silicon substrate 51 (second stage). Note that the top surface of the convex portion 52 of the superimposed silicon substrate 51 and the first main surface of the glass substrate 54 may be bonded by a method such as anodic bonding, surface activation bonding, or resin bonding.

（は）図６（ｄ）に示すように、ガラス基板５４に熱を加えて軟化させて、ガラス基板５４の一部をシリコン基板５１の凸部５２の周囲に埋め込む（第３段階）。具体的には、平坦な板状の加熱・加圧治具でガラス基板５４とシリコン基板５１を挟み、ガラス基板５４をその屈伏点よりも高く且つシリコンの融点よりも低い温度まで加熱して軟化させる。そして、加熱・加圧治具を用いて、ガラス基板５４とシリコン基板５１をプレスする。プレス処理及びガラスの自重によって、軟化したガラス基板５４の一部は、シリコン基板５１の凸部５２の周囲に埋め込まれる。なお、ガラス基板５４とシリコン基板５１の配置を入れ替えた場合、ガラスの自重の代りに、シリコン基板５１の自重となる。   As shown in FIG. 6D, heat is applied to the glass substrate 54 to soften it, and a part of the glass substrate 54 is embedded around the convex portion 52 of the silicon substrate 51 (third stage). Specifically, the glass substrate 54 and the silicon substrate 51 are sandwiched by a flat plate-like heating / pressurizing jig, and the glass substrate 54 is heated to a temperature higher than its yield point and lower than the melting point of silicon to be softened. Let Then, the glass substrate 54 and the silicon substrate 51 are pressed using a heating / pressurizing jig. A portion of the glass substrate 54 that has been softened by the pressing process and the weight of the glass is embedded around the convex portion 52 of the silicon substrate 51. In addition, when arrangement | positioning of the glass substrate 54 and the silicon substrate 51 is replaced, it becomes the dead weight of the silicon substrate 51 instead of dead weight of glass.

（に）その後、ガラス基板５４を冷却する（第４段階）。そして、ガラス基板５４のうち、シリコン基板５１の凸部５２の周囲に埋め込まれた部分を残し、他の部分を除去する（第５段階）。具体的には、ダイヤモンド砥石を用いた研削、化学機械研磨（ＣＭＰ）等の研磨、或いはＲＩＥなどのドライエッチングやＨＦによるウェットエッチングなどの方法を用いて、ガラス基板５４の第２の主面を均一に削り取る。第２の主面を均一に削り取る処理を、図６（ｅ）に示すように、少なくともガラス基板５４の第２の主面に凸部５２の頂上面が表出するまで、実施する。これにより、ガラス基板５４の第２の主面に凸部５２の頂上面が露出する。   (Ii) Thereafter, the glass substrate 54 is cooled (fourth stage). Then, the portion of the glass substrate 54 embedded in the periphery of the convex portion 52 of the silicon substrate 51 is left, and the other portion is removed (fifth stage). Specifically, the second main surface of the glass substrate 54 is formed using a method such as grinding using a diamond grindstone, polishing such as chemical mechanical polishing (CMP), dry etching such as RIE, or wet etching using HF. Remove evenly. The process of evenly scraping the second main surface is performed until at least the top surface of the convex portion 52 appears on the second main surface of the glass substrate 54, as shown in FIG. Thereby, the top surface of the convex portion 52 is exposed on the second main surface of the glass substrate 54.

この第５段階で、例えば、化学機械研磨（ＣＭＰ）を採用する場合には、次のような工程も有効である。   In this fifth stage, for example, when chemical mechanical polishing (CMP) is employed, the following process is also effective.

先ず、単結晶シリコンからなる凸部５２を形成する際に、レジスト５５に代えて凸部５２の頂上部となる位置に金属膜を形成する。
つぎに、その金属膜よりもシリコン基板に対するエッチング速度が速い異方性のエッチング方法を用いて、シリコン基板５１の第１の主面ＳＦ１を選択的に除去することにより凸部５２を形成する。
その後、上述の第２段階〜第４段階を経てガラス基板５４を冷却した後、ガラス基板５４のうち、シリコン基板５１の凸部５２の周囲に埋め込まれた部分を残し、他の部分を以下のようにして除去する（第５段階）。 First, when the convex portion 52 made of single crystal silicon is formed, a metal film is formed at a position that becomes the top of the convex portion 52 instead of the resist 55.
Next, the convex portion 52 is formed by selectively removing the first main surface SF1 of the silicon substrate 51 by using an anisotropic etching method in which the etching rate with respect to the silicon substrate is faster than that of the metal film.
Then, after cooling the glass substrate 54 through the above-described second stage to fourth stage, the portion embedded in the periphery of the convex portion 52 of the silicon substrate 51 is left out of the glass substrate 54, and the other parts are replaced with (5th stage).

先ず、ガラス基板５４の第２の主面に対して、ダイヤモンド砥石を用いた研削を実施する。この研削は、ガラス基板５４の凸部５２上の金属膜（レジスト５５の代わりに形成したもの）が露出する前に終了する。その後、ガラス基板５４の第２の主面に対して、化学機械研磨（ＣＭＰ）を実施する。ＣＭＰは、ガラス基板５４の第２の主面に金属膜が露出するまで、実施する。これにより、凸部５２の頂上面（金属膜）が露出したガラス基板５４の第２の主面を、鏡面に仕上げることができる。なお、「ＣＭＰ」は、研磨剤或いは研磨液による化学的作用を伴う機械的研磨の一例である。
この凸部５２の上に残した金属膜が図４（ｂ）に示した金属電極６３ｃに相当する。 First, grinding using a diamond grindstone is performed on the second main surface of the glass substrate 54. This grinding is finished before the metal film (formed in place of the resist 55) on the convex portion 52 of the glass substrate 54 is exposed. Thereafter, chemical mechanical polishing (CMP) is performed on the second main surface of the glass substrate 54. CMP is performed until the metal film is exposed on the second main surface of the glass substrate 54. Thereby, the 2nd main surface of the glass substrate 54 from which the top surface (metal film) of the convex part 52 was exposed can be finished to a mirror surface. “CMP” is an example of mechanical polishing accompanied by chemical action by an abrasive or a polishing liquid.
The metal film left on the convex portion 52 corresponds to the metal electrode 63c shown in FIG.

（ほ）シリコン基板５１のうち、凸部５２を残し、他の部分を除去する（第６段階）。具体的には、研削、研磨、ドライエッチングやウェットエッチングなどの方法を用いて、シリコン基板５１の凸部５２を形成した主面に対向する裏面（図６における下面）を均一に削り取る。シリコン基板５１の裏面を均一に削り取る処理を、図６（ｅ）に示すように、少なくともシリコン基板５１の裏面にガラス基板５４が表出するまで、実施する。これにより、ガラス基板５４の第１の主面及び第２の主面に凸部５２の両端部が露出する。   (E) Of the silicon substrate 51, the convex part 52 is left and the other part is removed (sixth stage). Specifically, the back surface (the lower surface in FIG. 6) facing the main surface on which the convex portion 52 of the silicon substrate 51 is formed is uniformly cut using a method such as grinding, polishing, dry etching or wet etching. The process of uniformly scraping the back surface of the silicon substrate 51 is performed until the glass substrate 54 appears at least on the back surface of the silicon substrate 51 as shown in FIG. Thereby, both ends of the convex portion 52 are exposed on the first main surface and the second main surface of the glass substrate 54.

なお、軟化したガラス基板５４の一部をシリコン基板５１の凸部５２の周囲に埋め込むために、ガラスの自重による力で十分である場合、第３段階におけるプレス処理を行わなくてもよい。例えば、ガラス基板５４の温度を高くすることにより、ガラス基板５４の粘性が低下する。この場合、プレス処理を省略しても、ガラスの自重により凸部５２の周囲に軟化したガラス基板５４の一部を埋め込むことができる。   In addition, in order to embed a part of the softened glass substrate 54 around the convex portion 52 of the silicon substrate 51, when the force due to the weight of the glass is sufficient, the pressing process in the third stage may not be performed. For example, by increasing the temperature of the glass substrate 54, the viscosity of the glass substrate 54 decreases. In this case, even if the pressing process is omitted, a part of the glass substrate 54 softened around the convex portion 52 by the weight of the glass can be embedded.

以上説明したように、本発明の第１の実施の形態によれば、以下の作用効果が得られる。   As described above, according to the first embodiment of the present invention, the following operational effects can be obtained.

図４（ａ）に示したように、第１の引出部６２ａ及び第２の引出部６２ｂは、第１の主面ＳＦ１の法線方向から見て異なる位置に配置されている。このため、ガラス基板６１の内部に、ガラス基板６１の表面のうち任意の複数箇所の間の導通を取る、３次元方向に延伸されたシリコン配線６２を配置することができる。よって、シリコン配線６２の引き出し箇所（６２ａ、６２ｂ）を任意に設定することができる。   As shown in FIG. 4A, the first lead portion 62a and the second lead portion 62b are arranged at different positions when viewed from the normal direction of the first main surface SF1. For this reason, the silicon wiring 62 extended | stretched to the three-dimensional direction which can conduct | electrically_connect between arbitrary several places among the surfaces of the glass substrate 61 inside the glass substrate 61 can be arrange | positioned. Accordingly, the lead-out locations (62a, 62b) of the silicon wiring 62 can be arbitrarily set.

第２の引出部６２ｂがガラス基板６１の側面ＳＦ３に露出している。よって、図２及び図３に示した第１の固定基板２の形成に用いられるガラス基板２０に、図４（ａ）に示したシリコン配線埋込ガラス基板を適用した場合、加速度センサチップＡに入出力される電気信号を加速度センサチップＡの側面から引き出すことが出来る。したがって、図１の半導体装置における第１の主面の法線方向の小型化に貢献する。また、ボンディングワイヤＷの引回しが容易になり、パッケージ設計の自由度が向上する。   The second lead portion 62b is exposed on the side surface SF3 of the glass substrate 61. Therefore, when the silicon wiring embedded glass substrate shown in FIG. 4A is applied to the glass substrate 20 used for forming the first fixed substrate 2 shown in FIG. 2 and FIG. The input / output electric signal can be extracted from the side surface of the acceleration sensor chip A. Therefore, this contributes to downsizing in the normal direction of the first main surface in the semiconductor device of FIG. Further, the bonding wire W can be easily routed, and the degree of freedom in package design is improved.

金属電極６３ａ、６３ｂが、第１の引出部６２ａ及び第２の引出部６２ｂの露出面を覆っている。よって、図２及び図３に示したガラス基板２０に、図４（ａ）に示したシリコン配線埋込ガラス基板を適用した場合、第１の引出部６２ａ及び第２の引出部６２ｂへのワイヤーボンディングやはんだ付けが容易になる。   The metal electrodes 63a and 63b cover the exposed surfaces of the first lead portion 62a and the second lead portion 62b. Therefore, when the silicon wiring embedded glass substrate shown in FIG. 4A is applied to the glass substrate 20 shown in FIGS. 2 and 3, the wires to the first lead portion 62a and the second lead portion 62b are used. Bonding and soldering are easy.

図４（ｂ）の第５の工程において、第１の凸部５２ａを、金属膜６３ｃを介して第２の凸部５２ｂに接触させることにより、シリコン部材同士（５２ａ、５２ｂ）の電気的な接続抵抗を金属膜６３ｃが低減することができる。   In the fifth step of FIG. 4B, the first protrusions 52a are brought into contact with the second protrusions 52b through the metal film 63c, whereby the silicon members (52a, 52b) are electrically connected to each other. The connection resistance can be reduced by the metal film 63c.

図１２は、ブラスト加工によりガラス基板２０に形成された穴８８から表出した電極パッド１８に対して直接、ボンディングワイヤＷを接続した従来例を示す断面図である。第１の実施の形態によれば、図１２の従来例に比べて、容易にワイヤーボンディングやはんだ付けを行うことができる。また、図１の半導体装置を、第１の主面ＳＦ１の法線に垂直な方向に小型化することができる。   FIG. 12 is a cross-sectional view showing a conventional example in which bonding wires W are directly connected to the electrode pads 18 exposed from the holes 88 formed in the glass substrate 20 by blasting. According to the first embodiment, wire bonding and soldering can be easily performed as compared with the conventional example of FIG. In addition, the semiconductor device in FIG. 1 can be reduced in size in a direction perpendicular to the normal line of the first main surface SF1.

（第２の実施の形態）
図４（ａ）では、第１の引出部６２ａ及び第２の引出部６２ｂが、それぞれガラス基板６１の第１の主面ＳＦ１及び側面ＳＦ３に露出している場合を示したが、本発明はこれに限定されない。例えば、図１０（ａ）に示すように、第１の引出部７２ａ及び第２の引出部７２ｂが、それぞれガラス基板７１の第１の主面ＳＦ１及び第２の主面ＳＦ２に露出していてもよい。 (Second Embodiment)
FIG. 4A shows the case where the first lead portion 62a and the second lead portion 62b are exposed on the first main surface SF1 and the side surface SF3 of the glass substrate 61, respectively. It is not limited to this. For example, as shown to Fig.10 (a), the 1st drawer | drawing-out part 72a and the 2nd drawer | drawing-out part 72b are exposed to 1st main surface SF1 and 2nd main surface SF2 of the glass substrate 71, respectively. Also good.

図７（ａ）及び図７（ｂ）を参照して、本発明の第２の実施の形態に係わる半導体装置の概略構成を、図１（ａ）及び図１（ｂ）の半導体装置との対比において説明する。加速度センサチップＡが備える総てのパッドは、プラスチックパッケージ本体１０２の開放された一面に対向する加速度センサチップＡの主面において、この主面の１辺に沿って配置されている。   Referring to FIGS. 7A and 7B, the schematic configuration of the semiconductor device according to the second embodiment of the present invention is compared with the semiconductor device of FIGS. 1A and 1B. The comparison will be described. All the pads included in the acceleration sensor chip A are arranged along one side of the main surface of the acceleration sensor chip A facing the open surface of the plastic package main body 102.

図８を参照して、図７の加速度センサチップＡの概略構成を、図２の加速度センサチップＡとの対比において説明する。   With reference to FIG. 8, the schematic configuration of the acceleration sensor chip A of FIG. 7 will be described in comparison with the acceleration sensor chip A of FIG.

第１の固定基板２は、ガラス基板２０の第１の主面とこれに対向する第２の主面（センサ本体１に重なり合う面）との間を貫通する複数の配線３８を備える。   The first fixed substrate 2 includes a plurality of wirings 38 penetrating between a first main surface of the glass substrate 20 and a second main surface (a surface overlapping the sensor main body 1) facing the first main surface.

各配線３８の一端は、ガラス基板２０の第２の主面に表出し、ガラス基板２０の第２の主面において、センサ本体１の電極パッド１８にそれぞれ電気的に接続されている。各配線３８の他端は、ガラス基板２０の第１の主面に表出している。これにより、電極パッド１８を介して、各固定電極２５の電位及び可動電極１５の電位をそれぞれ加速度センサチップＡの外部へ取り出すことができる。各配線３８の他端には金属電極３９がそれぞれ接続されている。図１のボンディングワイヤＷは、金属電極３９に接続されている。各配線３８の一端と他端は、ガラス基板２０の第２の主面の法線方向から見て、異なる位置に配置されている。   One end of each wiring 38 is exposed on the second main surface of the glass substrate 20, and is electrically connected to the electrode pad 18 of the sensor body 1 on the second main surface of the glass substrate 20. The other end of each wiring 38 is exposed on the first main surface of the glass substrate 20. As a result, the potential of each fixed electrode 25 and the potential of the movable electrode 15 can be taken out from the acceleration sensor chip A via the electrode pad 18. A metal electrode 39 is connected to the other end of each wiring 38. The bonding wire W in FIG. 1 is connected to the metal electrode 39. One end and the other end of each wiring 38 are arranged at different positions when viewed from the normal direction of the second main surface of the glass substrate 20.

図９を参照して、図７の加速度センサチップＡの断面構成を、図３の加速度センサチップＡとの対比において説明する。図９は、一対の支持ばね部１４を通る直線に垂直な切断面における加速度センサチップＡの構成を示す。   With reference to FIG. 9, the cross-sectional configuration of the acceleration sensor chip A in FIG. 7 will be described in comparison with the acceleration sensor chip A in FIG. FIG. 9 shows a configuration of the acceleration sensor chip A on a cut surface perpendicular to a straight line passing through the pair of support spring portions 14.

第１の固定基板２の配線３８の一端は、電極パッド１８に電気的に接続されている。電極パッド１８は、固定子１６、連絡用導体部１６ｄ、金属配線２６を通じて、固定電極２５に接続されている。配線３８は、ガラス基板２０の第１の主面に平行な方向に延伸され、配線３８の他端は、ガラス基板２０の第１の主面に表出している。ガラス基板２０の第１の主面のうち配線３８の他端が位置する領域には金属電極３９が形成されている。   One end of the wiring 38 of the first fixed substrate 2 is electrically connected to the electrode pad 18. The electrode pad 18 is connected to the fixed electrode 25 through the stator 16, the connecting conductor portion 16 d, and the metal wiring 26. The wiring 38 extends in a direction parallel to the first main surface of the glass substrate 20, and the other end of the wiring 38 is exposed on the first main surface of the glass substrate 20. A metal electrode 39 is formed in a region of the first main surface of the glass substrate 20 where the other end of the wiring 38 is located.

以上の相違点を除き、図７（ａ）及び図７（ｂ）の半導体装置の構成、図８及び図９の加速度センサチップＡの構成は、図１（ａ）及び図１（ｂ）の半導体装置、図２及び図３の加速度センサチップＡと同じである。   Except for the above differences, the configuration of the semiconductor device of FIGS. 7A and 7B and the configuration of the acceleration sensor chip A of FIGS. 8 and 9 are the same as those of FIGS. 1A and 1B. The semiconductor device is the same as the acceleration sensor chip A in FIGS. 2 and 3.

次に、図１０（ａ）を参照して、図８及び図９に示した第１の固定基板２の形成に用いられるガラス基板２０の一例としてのシリコン配線埋込ガラス基板の構成を説明する。シリコン配線埋込ガラス基板は、対向する第１の主面ＳＦ１及び第２の主面ＳＦ２と、この第１の主面ＳＦ１及び第２の主面ＳＦ２の外周に接続された側面ＳＦ３とで規定されるガラス基板７１と、ガラス基板７１の内部に配置されたシリコン配線７２とを備える。   Next, with reference to FIG. 10A, a configuration of a silicon wiring embedded glass substrate as an example of the glass substrate 20 used for forming the first fixed substrate 2 shown in FIGS. 8 and 9 will be described. . The silicon wiring embedded glass substrate is defined by a first main surface SF1 and a second main surface SF2 facing each other, and a side surface SF3 connected to the outer circumferences of the first main surface SF1 and the second main surface SF2. And a silicon wiring 72 disposed inside the glass substrate 71.

シリコン配線７２は、ガラス基板７１の第１の主面ＳＦ１に露出する第１の引出部７２ａと、ガラス基板７１の第１の主面ＳＦ１、第２の主面ＳＦ２或いは側面ＳＦ３のいずれか１つの面に露出する第２の引出部７２ｂと、第１の引出部７２ａ及び第２の引出部７２ｂに接続された接続部７２ｃとを備える。第２の実施の形態では、第２の引出部７２ｂが、ガラス基板７１の第２の主面ＳＦ２に露出している場合を示す。
尚、本明細書において、接続部７２ｃにおいて、第１のシリコン配線埋込ガラス基板３０１及び第３のシリコン配線埋込ガラス基板３０３に形成された部分を貫通接続部といい、第２のシリコン配線埋込ガラス基板３０２に形成された部分を内層接続部ともいう。 The silicon wiring 72 is one of the first lead portion 72a exposed on the first main surface SF1 of the glass substrate 71, and the first main surface SF1, the second main surface SF2, or the side surface SF3 of the glass substrate 71. A second lead portion 72b exposed on one surface, and a connection portion 72c connected to the first lead portion 72a and the second lead portion 72b. In the second embodiment, a case where the second lead portion 72b is exposed on the second main surface SF2 of the glass substrate 71 is shown.
In the present specification, a portion formed in the first silicon wiring embedded glass substrate 301 and the third silicon wiring embedded glass substrate 303 in the connection portion 72c is referred to as a through connection portion, and the second silicon wiring. A portion formed in the embedded glass substrate 302 is also referred to as an inner layer connection portion.

第１の引出部７２ａ及び第２の引出部７２ｂは、第１の主面ＳＦ１の法線方向から見て異なる位置に配置されている。   The 1st drawer | drawing-out part 72a and the 2nd drawer | drawing-out part 72b are arrange | positioned in a different position seeing from the normal line direction of 1st main surface SF1.

シリコン配線埋込ガラス基板は、第１の引出部７２ａ及び第２の引出部７２ｂの露出面をそれぞれ覆う金属電極７３ａ、７３ｂと、接続部７２ｃの途中に配置された金属電極７３ｃ、７３ｄとを更に備える。   The silicon wiring embedded glass substrate includes metal electrodes 73a and 73b covering the exposed surfaces of the first lead portion 72a and the second lead portion 72b, respectively, and metal electrodes 73c and 73d disposed in the middle of the connection portion 72c. In addition.

このように、シリコン配線埋込ガラス基板は、ガラス基板７１にシリコン配線７２が埋め込まれたものである。そして、シリコン配線７２の一端は、ガラス基板７１の第１の主面ＳＦ１に表出し、シリコン配線７２の他端は、ガラス基板７１の第２の主面ＳＦ２に表出している。よって、図１０（ａ）のシリコン配線７２を図８及び図９に示した配線３８に当てはめ、図１０（ａ）のガラス基板７１を図８及び図９に示したガラス基板２０に当てはめる。そして、図１０（ａ）の金属電極７３ｂを図８及び図９に示した金属電極３９に当てはめる。これにより、図８及び図９に示した第１の固定基板２の形成に用いられるガラス基板２０に、図１０（ａ）に示したシリコン配線埋込ガラス基板を適用することができる。この場合、図１０（ａ）のシリコン配線７２は、図８及び図９に示したセンサ本体１に入力される電気信号及びセンサ本体１から出力される電気信号を伝達する。   As described above, the silicon wiring embedded glass substrate is a glass substrate 71 in which the silicon wiring 72 is embedded. One end of the silicon wiring 72 is exposed on the first main surface SF1 of the glass substrate 71, and the other end of the silicon wiring 72 is exposed on the second main surface SF2 of the glass substrate 71. Therefore, the silicon wiring 72 of FIG. 10A is applied to the wiring 38 shown in FIGS. 8 and 9, and the glass substrate 71 of FIG. 10A is applied to the glass substrate 20 shown in FIGS. Then, the metal electrode 73b of FIG. 10A is applied to the metal electrode 39 shown in FIGS. Accordingly, the silicon wiring embedded glass substrate shown in FIG. 10A can be applied to the glass substrate 20 used for forming the first fixed substrate 2 shown in FIGS. In this case, the silicon wiring 72 of FIG. 10A transmits the electrical signal input to the sensor body 1 and the electrical signal output from the sensor body 1 shown in FIGS.

図１０（ｂ）を参照して、図１０（ａ）に示したシリコン配線埋込ガラス基板の製造方法を説明する。   With reference to FIG.10 (b), the manufacturing method of the silicon wiring embedded glass substrate shown to Fig.10 (a) is demonstrated.

（イ）先ず、単結晶シリコンから成る第１の凸部５２ａの周囲に第１のガラス基板５４ａを埋込み、第１のガラス基板５４ａの対向する表裏面に第１の凸部５２ａの両端部をそれぞれ露出させる。これにより、第１のシリコン配線埋込ガラス基板３０１を形成する（第１の工程）。その後、第１のガラス基板５４ａの表裏面のうち、第１の凸部５２ａの両端部が露出した部分に、金属電極７３ａを形成する。なお、第１のシリコン配線埋込ガラス基板３０１及び後述する第２のシリコン配線埋込ガラス基板３０２及び第３のシリコン配線埋込ガラス基板３０３を製造する詳細な工程は、図６を参照して説明したとおりである。   (A) First, the first glass substrate 54a is embedded around the first convex portion 52a made of single crystal silicon, and both end portions of the first convex portion 52a are formed on the front and back surfaces of the first glass substrate 54a facing each other. Expose each one. Thereby, the first silicon wiring embedded glass substrate 301 is formed (first step). Then, the metal electrode 73a is formed in the part which the both ends of the 1st convex part 52a exposed among the front and back of the 1st glass substrate 54a. A detailed process for manufacturing the first silicon wiring embedded glass substrate 301 and the second silicon wiring embedded glass substrate 302 and the third silicon wiring embedded glass substrate 303 described later is described with reference to FIG. As explained.

（ロ）そして、単結晶シリコンから成る第２の凸部５２ｂの周囲に第２のガラス基板５４ｂを埋込み、第２のガラス基板５４ｂの対向する表裏面に第２の凸部５２ｂの両端部をそれぞれ露出させる。これにより、第２のシリコン配線埋込ガラス基板３０２を形成する（第２の工程）。   (B) Then, the second glass substrate 54b is embedded around the second convex portion 52b made of single crystal silicon, and both end portions of the second convex portion 52b are formed on the front and back surfaces of the second glass substrate 54b facing each other. Expose each one. Thereby, a second silicon wiring embedded glass substrate 302 is formed (second step).

（ハ）単結晶シリコンから成る第３の凸部５２ｃの周囲に第３のガラス基板５４ｃを埋込み、第３のガラス基板５４ｃの対向する表裏面に第３の凸部５２ｃの両端部をそれぞれ露出させる。これにより、第３のシリコン配線埋込ガラス基板３０３を形成する（第３の工程）。その後、第３のガラス基板５４ｃの表裏面のうち、第３の凸部５２ｃの両端部が露出した部分に、金属電極７３ｂを形成する。
ここで、金属電極７３ｃ，７３ｄについては、第１の実施の形態で説明した方法と同様にして、以下のようにして形成される。 (C) The third glass substrate 54c is embedded around the third convex portion 52c made of single crystal silicon, and both end portions of the third convex portion 52c are exposed on the front and back surfaces of the third glass substrate 54c facing each other. Let Thereby, a third silicon wiring embedded glass substrate 303 is formed (third step). Thereafter, the metal electrode 73b is formed on the front and back surfaces of the third glass substrate 54c on the exposed portions of both ends of the third convex portion 52c.
Here, the metal electrode 73c, for 73d, in the same manner as the method described in the first embodiment, is formed as follows.

先ず、単結晶シリコンからなるシリコン基板上に凸部５２ａ，５２ｃを形成する際、レジスト膜に代えて凸部５２ａ，５２ｃの頂上部となる位置に金属膜を形成する。
つぎに、金属膜が形成されていない部分にあるシリコン基板を選択的に除去することにより凸部５２ａ，５２ｃを形成する。
そして、ガラス基板を埋め込んで冷却した後、シリコン基板の凸部５２ａ，５２ｃの周囲に埋め込まれたガラスを残し、他の部分を金属膜が露出するまで除去する。この凸部５２ａ，５２ｃの上に残した金属膜がそれぞれ図１０（ｂ）に示した金属電極７３ｃ，７３ｄに相当する。 First, when the convex portions 52a and 52c are formed on the silicon substrate made of single crystal silicon, a metal film is formed at a position to be the top of the convex portions 52a and 52c instead of the resist film.
Next, the convex portions 52a and 52c are formed by selectively removing the silicon substrate in the portion where the metal film is not formed.
Then, after the glass substrate is embedded and cooled, the glass embedded around the convex portions 52a and 52c of the silicon substrate is left, and other portions are removed until the metal film is exposed. The metal films left on the convex portions 52a and 52c correspond to the metal electrodes 73c and 73d shown in FIG.

（ニ）図１０（ｂ）に示すように、第２のシリコン配線埋込ガラス基板３０２の表裏面を、第１のシリコン配線埋込ガラス基板３０１及び第３のシリコン配線埋込ガラス基板３０３で挟む（第４の工程）。そして、第１の凸部５２ａ及び第３の凸部５２ｃを、第１の主面ＳＦ１の法線方向から見て異なる位置において、第２の凸部５２ｂにそれぞれ接触させる（第５の工程）。詳細には、第１の凸部５２ａ及び第３の凸部５２ｃを金属電極７３ｃ、７３ｄを介して第２の凸部５２ｂに接触させる。   (D) As shown in FIG. 10B, the front and back surfaces of the second silicon wiring embedded glass substrate 302 are replaced with a first silicon wiring embedded glass substrate 301 and a third silicon wiring embedded glass substrate 303. (4th process). And the 1st convex part 52a and the 3rd convex part 52c are contacted with the 2nd convex part 52b, respectively in a different position seeing from the normal line direction of 1st main surface SF1 (5th process). . Specifically, the first convex portion 52a and the third convex portion 52c are brought into contact with the second convex portion 52b via the metal electrodes 73c and 73d.

（ホ）そして、第１乃至第３のシリコン配線埋込ガラス基板３０１〜３０３を、溶融接合、陽極接合、表面活性化結合、或いは樹脂接着などの方法により接合する（第６の工程）。第１〜第６の工程を実施することにより、図１０（ａ）に示したシリコン配線埋込ガラス基板を製造することができる。   (E) The first to third silicon wiring embedded glass substrates 301 to 303 are bonded by a method such as fusion bonding, anodic bonding, surface activation bonding, or resin bonding (sixth step). By carrying out the first to sixth steps, the silicon wiring embedded glass substrate shown in FIG. 10A can be manufactured.

以上説明したように、本発明の第２の実施の形態によれば、以下の作用効果が得られる。   As described above, according to the second embodiment of the present invention, the following operational effects can be obtained.

図１０（ａ）に示したように、第１の引出部７２ａ及び第２の引出部７２ｂは、第１の主面ＳＦ１及び第２の主面ＳＦ２にそれぞれ露出し、且つ第１の主面ＳＦ１の法線方向から見て異なる位置に配置されている。このため、ガラス基板７１の内部に、ガラス基板７１の対向する表裏面のうち任意の複数箇所の間の導通を取る、３次元方向に延伸されたシリコン配線７２を配置することができる。よって、シリコン配線７２の引き出し箇所（７２ａ、７２ｂ）を任意に設定することができる。   As shown in FIG. 10A, the first lead portion 72a and the second lead portion 72b are exposed to the first main surface SF1 and the second main surface SF2, respectively, and the first main surface. They are arranged at different positions when viewed from the normal direction of SF1. For this reason, the silicon wiring 72 extended | stretched in the three-dimensional direction which can conduct | electrically_connect between arbitrary several places among the front and back surfaces which the glass substrate 71 opposes inside the glass substrate 71 can be arrange | positioned. Accordingly, the lead-out locations (72a, 72b) of the silicon wiring 72 can be arbitrarily set.

第２の引出部７２ｂがガラス基板７１の第２の主面ＳＦ２に露出している。よって、図８及び図９に示した第１の固定基板２の形成に用いられるガラス基板２０に、図１０（ａ）に示したシリコン配線埋込ガラス基板を適用した場合、加速度センサチップＡに入出力される電気信号を加速度センサチップＡの表面の任意の箇所から引き出すことが出来る。したがって、ボンディングワイヤＷの引回しが容易になり、パッケージ設計の自由度が向上する。ひいては、図７の半導体装置の小型化に貢献する。 The second lead portion 72b is exposed on the second main surface SF2 of the glass substrate 71 . Therefore, when the silicon wiring embedded glass substrate shown in FIG. 10A is applied to the glass substrate 20 used for forming the first fixed substrate 2 shown in FIGS. The input / output electric signal can be extracted from any location on the surface of the acceleration sensor chip A. Accordingly, the bonding wire W can be easily routed, and the degree of freedom in package design is improved. Therefore, it contributes to miniaturization of the semiconductor device in FIG.

金属電極７３ａ、７３ｂが、第１の引出部７２ａ及び第２の引出部７２ｂの露出面を覆っている。よって、図８及び図９に示したガラス基板２０に、図１０（ａ）に示したシリコン配線埋込ガラス基板を適用した場合、第１の引出部７２ａ及び第２の引出部７２ｂへのワイヤーボンディングやはんだ付けが容易になる。   Metal electrodes 73a and 73b cover the exposed surfaces of the first lead portion 72a and the second lead portion 72b. Therefore, when the silicon wiring embedded glass substrate shown in FIG. 10A is applied to the glass substrate 20 shown in FIGS. 8 and 9, the wires to the first lead portion 72a and the second lead portion 72b are used. Bonding and soldering are easy.

図１０（ｂ）の第５の工程において、第１の凸部５２ａ及び第３の凸部５２ｃを、金属膜７３ｃ、７３ｄを介して第２の凸部５２ｂにそれぞれ接触させる。シリコン部材同士（５２ａ、５２ｂ、５２ｃ）の電気的な接続抵抗を低減することができる。   In the fifth step of FIG. 10B, the first convex portion 52a and the third convex portion 52c are brought into contact with the second convex portion 52b via the metal films 73c and 73d, respectively. The electrical connection resistance between the silicon members (52a, 52b, 52c) can be reduced.

以上の製造方法では、第１の凸部５２ａ及び第３の凸部５２ｃを、金属膜７３ｃ、７３ｄを介して第２の凸部５２ｂに接触させるようにした。
しかしながら、本発明はこれに限定されるものではなく、図１１に示すように、金属膜７３ｃ、７３ｄを形成することなく、第１の凸部５２ａ及び第３の凸部５２ｃを、酸化膜の形成を防止しながら、第２の凸部５２ｂに接触させるようにしてもよい。 In the above manufacturing method, the first convex portion 52a and the third convex portion 52c are brought into contact with the second convex portion 52b through the metal films 73c and 73d.
However, the present invention is not limited to this, and as shown in FIG. 11, the first protrusion 52a and the third protrusion 52c can be formed of an oxide film without forming the metal films 73c and 73d. You may make it contact the 2nd convex part 52b, preventing formation.

上記のように、本発明は、２つの実施の形態によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施の形態、実施例及び運用技術が明らかとなろう。   As described above, the present invention has been described by two embodiments. However, it should not be understood that the description and the drawings, which form a part of this disclosure, limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

例えば、第１及び第２の実施の形態では、第２の引出部６２ｂ、７２ｂがそれぞれガラス基板６１の側面及びガラス基板７１の第２の主面に露出している場合を示したが、本発明はこれに限定されない。第１の引出部及び第２の引出部は、第１の主面ＳＦ１の法線方向から見て異なる位置に配置されていればよく、両方ともガラス基板の第１の主面ＳＦ１に露出していてもよいし、両方ともガラス基板の側面ＳＦ３に露出していても構わない。   For example, in the first and second embodiments, the case where the second lead portions 62b and 72b are exposed on the side surface of the glass substrate 61 and the second main surface of the glass substrate 71, respectively, is shown. The invention is not limited to this. The first lead portion and the second lead portion only need to be arranged at different positions when viewed from the normal direction of the first main surface SF1, and both are exposed to the first main surface SF1 of the glass substrate. Both of them may be exposed on the side surface SF3 of the glass substrate.

また、シリコン基板５１の主面に凸部５２を形成する第１段階では、単結晶シリコンから成るシリコン基板５１の一部を加工して、単結晶シリコンから成る凸部５２を形成していた。しかし、これに限定されることない。例えば、単結晶シリコンから成るシリコン基板５１の主面に、多結晶シリコンから成るシリコン膜を堆積し、シリコン膜の一部を除去して多結晶シリコンから成る凸部５２を形成してもよい。   In the first step of forming the convex portion 52 on the main surface of the silicon substrate 51, a part of the silicon substrate 51 made of single crystal silicon is processed to form the convex portion 52 made of single crystal silicon. However, it is not limited to this. For example, a silicon film made of polycrystalline silicon may be deposited on the main surface of a silicon substrate 51 made of single crystal silicon, and a convex portion 52 made of polycrystalline silicon may be formed by removing a part of the silicon film.

また、３次元方向に延伸された凸部を有するシリコンの型を形成し、このシリコンの型に軟化したガラスを流し込むことにより、３次元方向に延伸されたシリコン配線を形成してもよい。複数のシリコン配線埋込ガラス基板を積層する必要がなくなり、製造工程を簡略化することができる。   Alternatively, a silicon mold having projections extending in the three-dimensional direction may be formed, and softened glass may be poured into the silicon mold to form a silicon wiring extending in the three-dimensional direction. It is not necessary to stack a plurality of silicon wiring embedded glass substrates, and the manufacturing process can be simplified.

本発明の実施の形態では、ＭＥＭＳデバイスの一例として静電容量型の加速度センサチップＡについて説明したが、本発明は、静電容量型の加速度センサチップＡ以外のＭＥＭＳデバイス、例えば、ピエゾ抵抗型の加速度センサチップ、ジャイロセンサ、マイクロアクチュエータ、マイクロリレー、赤外線センサ等や、ＩＣチップなどにも適用することができる。即ち、センサ本体１によるセンシング対象は、加速度に限らず、圧力、角度、角速度等であってもよい。   In the embodiment of the present invention, the capacitance type acceleration sensor chip A has been described as an example of the MEMS device. However, the present invention is not limited to the capacitance type acceleration sensor chip A, for example, a piezoresistive type. The present invention can also be applied to an acceleration sensor chip, a gyro sensor, a micro actuator, a micro relay, an infrared sensor, and an IC chip. That is, the sensing object by the sensor body 1 is not limited to acceleration, but may be pressure, angle, angular velocity, or the like.

このように、本発明はここでは記載していない様々な実施の形態等を包含するということを理解すべきである。したがって、本発明はこの開示から妥当な特許請求の範囲に係る発明特定事項によってのみ限定されるものである。   Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters according to the scope of claims reasonable from this disclosure.

Claims (12)

対向する第１の主面及び第２の主面と側面とを有するシリコン配線埋込ガラス基板であって、
ガラスベース部と、前記ガラスベース部の内部に埋設されたシリコン配線と、を備え、
前記シリコン配線は、
前記第１の主面に露出する第１の引出部と、
前記第１の主面、前記第２の主面或いは前記側面のいずれか１つの面に露出する第２の引出部と、
前記第１の引出部及び前記第２の引出部間を接続する接続部と、を備え、
前記接続部は、前記第１の引出部を一端部として含む第１の貫通接続部と前記第１の貫通接続部の他端に接続された内層接続部とを備え、
前記第１の引出部及び前記第２の引出部は、前記第１の主面の法線方向からみて異なる位置に配置され、
前記内層接続部は前記第１の主面に平行な方向に延伸されることを特徴とするシリコン配線埋込ガラス基板。 A silicon wiring embedded glass substrate having a first main surface and a second main surface and side surfaces facing each other,
Comprises a glass base, and a silicon wiring buried inside the glass base portion,
The silicon wiring is
A first lead portion exposed on the first main surface;
A second lead portion exposed on any one of the first main surface, the second main surface or the side surface;
A connecting portion connecting between the first drawer portion and the second drawer portion,
The connection portion includes a first through connection portion including the first lead portion as one end portion and an inner layer connection portion connected to the other end of the first through connection portion,
The first lead portion and the second lead portion are arranged at different positions when viewed from the normal direction of the first main surface,
The inner wiring connecting portion is stretched in a direction parallel to the first main surface, and is embedded in a silicon wiring glass substrate. 前記内層接続部の一端が前記側面に露出し、その露出した一端が前記第２の引出部であることを特徴とする請求項１に記載のシリコン配線埋込ガラス基板。 2. The silicon wiring embedded glass substrate according to claim 1 , wherein one end of the inner layer connection portion is exposed on the side surface, and the exposed one end is the second lead portion. 前記接続部は、前記第２の引出部を一端として含み他端が前記内層接続部に接続された第２の貫通接続部をさらに含み、前記第２の貫通接続部の中心軸が前記第１の貫通接続部の中心軸とは異なる直線上に位置する請求項１に記載のシリコン配線埋込ガラス基板。 The connection portion further includes a second through connection portion having the second lead portion as one end and the other end connected to the inner layer connection portion, and a central axis of the second through connection portion is the first axis. The silicon wiring embedded glass substrate according to claim 1 , which is located on a straight line different from the central axis of the through connection portion. 前記第１の貫通接続部の中心軸と前記第２の貫通接続部の中心軸とが平行である請求項３に記載のシリコン配線埋込ガラス基板。 The silicon wiring embedded glass substrate according to claim 3 , wherein a central axis of the first through-connection portion and a central axis of the second through-connection portion are parallel. 前記第１の引出部及び前記第２の引出部の少なくとも一方の露出面を覆う金属電極を更に備える請求項１〜４のうちのいずれか１つに記載のシリコン配線埋込ガラス基板。 Said first lead portion and said second silicon wiring buried glass substrate according to any one of claims 1-4, further comprising a metal electrode covering at least one of the exposed surface of the lead portion. 請求項１に記載のシリコン配線埋込ガラス基板の製造方法であって、
第１のシリコン基板の一方の面に第１の凸部を形成して、該第１の凸部の周囲にガラスを埋込むことと、前記第１の凸部を残して前記第１のシリコン基板を除くことにより前記第１の凸部の一端面が露出する第１の主面を形成することと、その第１の主面に対向しかつ前記第１の凸部の他端面が露出するように第２の主面を形成することとを含み、前記第１の主面から前記第１の凸部の一端面が露出し、前記第１の凸部の他端面が前記第２の主面から露出する第１のガラス基板を作製する第１の工程と、
第２のシリコン基板の一方の面に第２の凸部を峰状に形成して、該第２の凸部の周囲にガラスを埋込むことと、前記第２の凸部を残して前記第２のシリコン基板を除くことにより、前記第２の凸部の第１面が露出する第１の主面を形成することと、その第１の主面に対向しかつ前記第２の凸部の第２面が露出する第２の主面を形成することとを含み、第１の主面から前記第２の凸部の前記第１面が露出し、前記第１面に対向する第２面が前記第２の主面から露出する第２のガラス基板を作製する第２の工程と、
前記第１の凸部の一端面と前記第２の凸部の第１面とが接続されるように前記第１のガラス基板の第１の主面と前記第２のガラス基板の第１の主面とを対向させ、前記第２のガラス基板の第２の主面に第３のガラス基板を対向させて前記第１〜第３のガラス基板を接合する接合工程と、を含み、
前記第１の凸部が前記第１の貫通接続部となり、前記第２の凸部が前記内層接続部となることを特徴とするシリコン配線埋込ガラス基板の製造方法。 A method for producing a silicon wiring embedded glass substrate according to claim 1 ,
Forming a first protrusion on one surface of the first silicon substrate, embedding glass around the first protrusion, and leaving the first protrusion to leave the first silicon; Forming a first main surface exposing one end surface of the first convex portion by removing the substrate, and exposing the other end surface of the first convex portion facing the first main surface. Forming the second main surface as described above, one end surface of the first convex portion is exposed from the first main surface, and the other end surface of the first convex portion is the second main surface. A first step of producing a first glass substrate exposed from the surface;
Forming a second convex portion in a ridge shape on one surface of the second silicon substrate, embedding glass around the second convex portion, and leaving the second convex portion, the second convex portion; By removing the silicon substrate, the first main surface exposing the first surface of the second convex portion is formed, the first main surface is opposed to the second convex portion, and the second convex portion Forming a second main surface from which the second surface is exposed, wherein the first surface of the second convex portion is exposed from the first main surface and faces the first surface A second step of producing a second glass substrate exposed from the second main surface;
The first main surface of the first glass substrate and the first of the second glass substrate so that one end surface of the first convex portion and the first surface of the second convex portion are connected. a major surface is opposed, viewing including and a bonding step of bonding the first to third glass substrates to face the third glass substrate of the second main surface of said second glass substrate,
The method of manufacturing a silicon wiring embedded glass substrate , wherein the first convex portion serves as the first through connection portion, and the second convex portion serves as the inner layer connection portion . 前記第１の工程は、
前記第１の凸部が形成された第１のシリコン基板の一方の面にガラス基板を重ね合わせることと、当該ガラス基板に熱を加えて軟化させて、当該ガラス基板の一部を前記第１のシリコン基板の凸部の周囲に埋め込むことを含み、
前記第２の工程は、
前記第２の凸部が形成された第２のシリコン基板の一方の面にガラス基板を重ね合わせることと、当該ガラス基板に熱を加えて軟化させて、当該ガラス基板の一部を前記第２のシリコン基板の凸部の周囲に埋め込むことを含む、
請求項６記載のシリコン配線埋込ガラス基板の製造方法。 The first step includes
A glass substrate is overlaid on one surface of the first silicon substrate on which the first protrusion is formed, and heat is applied to the glass substrate to soften the glass substrate so that a part of the glass substrate is the first surface. Including embedding around the convex portion of the silicon substrate,
The second step includes
A glass substrate is overlaid on one surface of the second silicon substrate on which the second convex portions are formed, and heat is applied to the glass substrate to soften the glass substrate so that a part of the glass substrate is the second surface. Including embedding around the convex part of the silicon substrate,
The method for producing a silicon wiring embedded glass substrate according to claim 6 . 前記接合工程において、前記第１の凸部を、金属膜を介して前記第２の凸部に接触させることを特徴とする請求項６又は７に記載のシリコン配線埋込ガラス基板の製造方法。 In the joining step, the first convex portion, the silicon wiring buried glass substrate manufacturing method according to claim 6 or 7 via the metal film, characterized in that contacting with the second convex portion. 請求項３に記載のシリコン配線埋込ガラス基板の製造方法であって、
第１のシリコン基板の一方の面に第１の凸部を形成して、該第１の凸部の周囲にガラスを埋込むことと、前記第１の凸部を残して前記第１のシリコン基板を除くことにより前記第１の凸部の一端面が露出する第１の主面を形成することと、その第１の主面に対向しかつ前記第１の凸部の他端面が露出するように第２の主面を形成することとを含み、前記第１の主面から前記第１の凸部の一端面が露出し、前記第１の凸部の他端面が前記第２の主面から露出する第１のガラス基板を作製する第１の工程と、
第２のシリコン基板の一方の面に第２の凸部を峰状に形成して、該第２の凸部の周囲にガラスを埋込むことと、前記第２の凸部を残して前記第２のシリコン基板を除くことにより、前記第２の凸部の第１面が露出する第１の主面を形成することと、その第１の主面に対向しかつ前記第２の凸部の第２面が露出する第２の主面を形成することとを含み、第１の主面から前記第２の凸部の前記第１面が露出し、前記第１面に対向する第２面が前記第２の主面から露出する第２のガラス基板を作製する第２の工程と、
第３のシリコン基板の一方の面に第３の凸部を形成して、該第３の凸部の周囲にガラスを埋込むことと、前記第３の凸部を残して前記第３のシリコン基板を除くことにより前記第３の凸部の一端面が露出する第１の主面を形成することと、その第１の主面に対向しかつ前記第３の凸部の他端面が露出するように第２の主面を形成することとを含み、前記第１の主面から前記第３の凸部の一端面が露出し、前記第３の凸部の他端面が前記第２の主面から露出するように前記第３のガラス基板を作製する第３の工程と、
前記第１の凸部の一端面と前記第２の凸部の第１面とが接続されるように前記第１のガラス基板の第１の主面と前記第２のガラス基板の第１の主面とを対向させ、前記第３の凸部の一端面と前記第２の凸部の第２面とが接続されるように前記第２のガラス基板の第２の主面と前記第３のガラス基板の第１の主面とを対向させて前記第１〜第３のガラス基板を接合する接合工程と、を含み、
前記第１の凸部が前記第１の貫通接続部となり、前記第２の凸部が前記内層接続部となり、前記第３の凸部が前記第２の貫通接続部となることを特徴とするシリコン配線埋込ガラス基板の製造方法。 A method of manufacturing a silicon wiring embedded glass substrate according to claim 3,
Forming a first protrusion on one surface of the first silicon substrate, embedding glass around the first protrusion, and leaving the first protrusion to leave the first silicon; Forming a first main surface exposing one end surface of the first convex portion by removing the substrate, and exposing the other end surface of the first convex portion facing the first main surface. Forming the second main surface as described above, one end surface of the first convex portion is exposed from the first main surface, and the other end surface of the first convex portion is the second main surface. A first step of producing a first glass substrate exposed from the surface;
Forming a second convex portion in a ridge shape on one surface of the second silicon substrate, embedding glass around the second convex portion, and leaving the second convex portion, the second convex portion; By removing the silicon substrate, the first main surface exposing the first surface of the second convex portion is formed, the first main surface is opposed to the second convex portion, and the second convex portion Forming a second main surface from which the second surface is exposed, wherein the first surface of the second convex portion is exposed from the first main surface and faces the first surface A second step of producing a second glass substrate exposed from the second main surface;
Forming a third convex portion on one surface of the third silicon substrate, embedding glass around the third convex portion, and leaving the third convex portion, the third silicon; By removing the substrate, a first main surface that exposes one end surface of the third convex portion is formed, and the other end surface of the third convex portion is exposed to face the first main surface. Forming the second main surface as described above, one end surface of the third convex portion is exposed from the first main surface, and the other end surface of the third convex portion is the second main surface. A third step of producing the third glass substrate so as to be exposed from the surface;
The first main surface of the first glass substrate and the first of the second glass substrate so that one end surface of the first convex portion and the first surface of the second convex portion are connected. The second main surface of the second glass substrate and the third surface are arranged so that the main surface faces each other and the one end surface of the third convex portion and the second surface of the second convex portion are connected. Bonding the first to third glass substrates with the first main surface of the glass substrate facing each other,
The first convex portion serves as the first through-connecting portion, the second convex portion serves as the inner layer connecting portion, and the third convex portion serves as the second through-connecting portion. A method of manufacturing a silicon wiring embedded glass substrate. 前記第１の工程は、
前記第１の凸部が形成された第１のシリコン基板の一方の面にガラス基板を重ね合わせることと、当該ガラス基板に熱を加えて軟化させて、当該ガラス基板の一部を前記第１のシリコン基板の凸部の周囲に埋め込むことを含み、
前記第２の工程は、
前記第２の凸部が形成された第２のシリコン基板の一方の面にガラス基板を重ね合わせることと、当該ガラス基板に熱を加えて軟化させて、当該ガラス基板の一部を前記第２のシリコン基板の凸部の周囲に埋め込むことを含み、
前記第３の工程は、
前記第３の凸部が形成された第３のシリコン基板の一方の面にガラス基板を重ね合わせることと、当該ガラス基板に熱を加えて軟化させて、当該ガラス基板の一部を前記第３のシリコン基板の凸部の周囲に埋め込むことを含む、
請求項９記載のシリコン配線埋込ガラス基板の製造方法。 The first step includes
A glass substrate is overlaid on one surface of the first silicon substrate on which the first protrusion is formed, and heat is applied to the glass substrate to soften the glass substrate so that a part of the glass substrate is the first surface. Including embedding around the convex portion of the silicon substrate,
The second step includes
A glass substrate is overlaid on one surface of the second silicon substrate on which the second convex portions are formed, and heat is applied to the glass substrate to soften the glass substrate so that a part of the glass substrate is the second surface. Including embedding around the convex portion of the silicon substrate,
The third step includes
A glass substrate is overlaid on one surface of the third silicon substrate on which the third convex portion is formed, and heat is applied to the glass substrate to soften the glass substrate so that a part of the glass substrate is the third surface. Including embedding around the convex part of the silicon substrate,
The method for producing a silicon wiring embedded glass substrate according to claim 9 . 前記接合工程において、前記第１の凸部及び前記第３の凸部を、金属膜を介して前記第２の凸部にそれぞれ接触させることを特徴とする請求項９又は１０に記載のシリコン配線埋込ガラス基板の製造方法。 In the joining step, the first convex portion and the third convex portion, the silicon wiring according to claim 9 or 10, characterized in that via the metal film is contacted to each of the second protrusions Manufacturing method of embedded glass substrate. 前記第１の凸部の一端と他端は、前記第１のガラス基板の第１の主面の法線方向から見て同じ位置に配置され、
前記第２の凸部の第１面と第２面は、前記第２のガラス基板の第１の主面の法線方向から見て同じ位置に配置され、
前記第３の凸部の一端と他端は、前記第３のガラス基板の第１の主面の法線方向から見て同じ位置に配置されている
ことを特徴とする請求項９〜１１のいずれか一項に記載のシリコン配線埋込ガラス基板の製造方法。 One end and the other end of the first convex portion are arranged at the same position when viewed from the normal direction of the first main surface of the first glass substrate,
The first surface and the second surface of the second convex portion are arranged at the same position when viewed from the normal direction of the first main surface of the second glass substrate,
The third one and the other ends of the projections of the claims 9-11, characterized in that it is arranged at the same position when viewed from the normal direction of the first major surface of the third glass substrate The manufacturing method of the silicon wiring embedded glass substrate as described in any one of Claims.
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