JP5527806B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5527806B2 JP5527806B2 JP2010032048A JP2010032048A JP5527806B2 JP 5527806 B2 JP5527806 B2 JP 5527806B2 JP 2010032048 A JP2010032048 A JP 2010032048A JP 2010032048 A JP2010032048 A JP 2010032048A JP 5527806 B2 JP5527806 B2 JP 5527806B2
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5387—Flexible insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
ことを特徴とする付記5又は6に記載の半導体装置の製造方法。
10−1,20−1 半導体パッケージ
11,21 パッケージ本体
12,22 接続パッド
13,23 半田ボール
14,24 バンプ
40 フレキシブルプリント配線板
41 基板部
42 第1の接続パッド
43 第2の接続パッド
44 外部接続用接続パッド
45 表面側熱可塑性樹脂膜
46 裏面側熱可塑性樹脂膜
70,80 半導体パッケージ
70−1,80−1 半導体パッケージ
71,81 接続パッド
90 フレキシブルプリント配線板
91 基板部
92 第1の接続パッド
93 第2の接続パッド
94 外部接続用接続パッド
95 表面側異方性導電樹脂膜
96 熱可塑性樹脂膜
97 裏面側異方性導電樹脂膜
Claims (9)
- 表面側に形成された第1の接続パッドと、裏面側に形成された第2の接続パッドと、前記第1の接続パッド及び前記第2の接続パッドが形成された領域を覆う熱可塑性樹脂膜又は異方性導電膜と、を備えたフレキシブルプリント配線板と、裏面側に第3の接続パッドを備えた半導体パッケージとを用意し、
前記第3の接続パッドが前記第1の接続パッドに接続されるように、前記半導体パッケージを前記フレキシブルプリント配線板の前記表面側に実装し、
その後、前記第2の接続パッドが、前記半導体パッケージの表面の上方で、当該半導体パッケージの表面と同一方向を向くように、前記フレキシブルプリント配線板を折り曲げる、
ことを特徴とする半導体装置の製造方法。 - 前記半導体パッケージを前記フレキシブルプリント配線板に実装する前に、前記第3の接続パッド上に形成された半田ボールを除去することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第1の接続パッド及び前記第2の接続パッドが形成された領域が前記熱可塑性樹脂膜により覆われており、
前記半導体パッケージを前記フレキシブルプリント配線板に実装する前に、
前記第3の接続パッド上に、当該第3の接続パッドに比べて占有面積の小さいバンプを形成する、
ことを特徴とする請求項1又は2に記載の半導体装置の製造方法。 - 前記第1の接続パッド及び前記第2の接続パッドが形成された領域が前記異方性導電膜により覆われており、前記第3の接続パッドと前記第1の接続パッドとが熱圧着される、
ことを特徴とする請求項1又は2に記載の半導体装置の製造方法。 - 裏面側に第4の接続パッドが形成された別の半導体パッケージをさらに用意し、
前記フレキシブルプリント配線板を折り曲げた後、前記第4の接続パッドが前記第2の接続パッドに接続されるように、前記別の半導体パッケージを前記フレキシブルプリント配線板の前記裏面側に実装する、
ことを特徴とする請求項1乃至4のいずれか一項に記載の半導体装置の製造方法。 - 前記別の半導体パッケージを前記フレキシブルプリント配線板に実装する前に、前記第4の接続パッド上に形成された半田ボールを除去することを特徴とする請求項5に記載の半導体装置の製造方法。
- 前記別の半導体パッケージを前記フレキシブルプリント配線板に実装する前に、
前記第3の接続パッド上に、当該第3の接続パッドに比べて占有面積の小さいバンプを形成する、
ことを特徴とする請求項5又は6に記載の半導体装置の製造方法。 - 前記第4の接続パッドと前記第2の接続パッドとが熱圧着される、
ことを特徴とする請求項5又は6に記載の半導体装置の製造方法。 - 請求項1乃至8に記載の半導体装置の製造方法により製造された半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010032048A JP5527806B2 (ja) | 2010-02-17 | 2010-02-17 | 半導体装置の製造方法 |
US13/015,680 US20110197438A1 (en) | 2010-02-17 | 2011-01-28 | Method of manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010032048A JP5527806B2 (ja) | 2010-02-17 | 2010-02-17 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2011171411A JP2011171411A (ja) | 2011-09-01 |
JP5527806B2 true JP5527806B2 (ja) | 2014-06-25 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2010032048A Expired - Fee Related JP5527806B2 (ja) | 2010-02-17 | 2010-02-17 | 半導体装置の製造方法 |
Country Status (2)
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US (1) | US20110197438A1 (ja) |
JP (1) | JP5527806B2 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8363418B2 (en) * | 2011-04-18 | 2013-01-29 | Morgan/Weiss Technologies Inc. | Above motherboard interposer with peripheral circuits |
KR20130042210A (ko) * | 2011-10-18 | 2013-04-26 | 삼성전자주식회사 | 멀티-칩 패키지 및 그의 제조 방법 |
US9349709B2 (en) * | 2013-12-04 | 2016-05-24 | Infineon Technologies Ag | Electronic component with sheet-like redistribution structure |
US10064287B2 (en) | 2014-11-05 | 2018-08-28 | Infineon Technologies Austria Ag | System and method of providing a semiconductor carrier and redistribution structure |
US10192846B2 (en) | 2014-11-05 | 2019-01-29 | Infineon Technologies Austria Ag | Method of inserting an electronic component into a slot in a circuit board |
US10553557B2 (en) * | 2014-11-05 | 2020-02-04 | Infineon Technologies Austria Ag | Electronic component, system and method |
US11201096B2 (en) * | 2019-07-09 | 2021-12-14 | Texas Instruments Incorporated | Packaged device with die wrapped by a substrate |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
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JP3688755B2 (ja) * | 1995-06-12 | 2005-08-31 | 株式会社日立製作所 | 電子部品および電子部品モジュール |
US6300679B1 (en) * | 1998-06-01 | 2001-10-09 | Semiconductor Components Industries, Llc | Flexible substrate for packaging a semiconductor component |
JP3633559B2 (ja) * | 1999-10-01 | 2005-03-30 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
US20030234443A1 (en) * | 2001-10-26 | 2003-12-25 | Staktek Group, L.P. | Low profile stacking system and method |
US7071547B2 (en) * | 2002-09-11 | 2006-07-04 | Tessera, Inc. | Assemblies having stacked semiconductor chips and methods of making same |
JP4225036B2 (ja) * | 2002-11-20 | 2009-02-18 | 日本電気株式会社 | 半導体パッケージ及び積層型半導体パッケージ |
JP2009004454A (ja) * | 2007-06-19 | 2009-01-08 | Shinko Electric Ind Co Ltd | 電極構造体及びその形成方法と電子部品及び実装基板 |
JP2009016557A (ja) * | 2007-07-04 | 2009-01-22 | Fujikura Ltd | 半導体装置 |
WO2009038169A1 (ja) * | 2007-09-19 | 2009-03-26 | Nec Corporation | 半導体装置及びその製造方法 |
JP5012612B2 (ja) * | 2008-03-26 | 2012-08-29 | 日本電気株式会社 | 半導体デバイスの実装構造体及び実装構造体を用いた電子機器 |
-
2010
- 2010-02-17 JP JP2010032048A patent/JP5527806B2/ja not_active Expired - Fee Related
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2011
- 2011-01-28 US US13/015,680 patent/US20110197438A1/en not_active Abandoned
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Publication number | Publication date |
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US20110197438A1 (en) | 2011-08-18 |
JP2011171411A (ja) | 2011-09-01 |
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