JP5511299B2 - Data arithmetic device control circuit and data arithmetic device - Google Patents

Description

  The present invention relates to a control circuit that causes an arithmetic unit to repeatedly execute a series of arithmetic instructions, and a data arithmetic device in which the control circuit and the arithmetic unit are mounted.

In the case of a program that repeatedly executes a series of arithmetic instructions (loop execution), it is generally composed of a loop initialization part, a main part of arithmetic processing, and a post-processing part of the loop.
FIG. 7 is an explanatory diagram showing a program example for performing general loop control.
The program shown in FIG. 7 executes a series of “instructions C0 to C99”, which are a series of arithmetic instructions, in a loop execution 100 times.

That is, in the program of FIG. 7, in the loop initialization part, an initialization process is executed in which “100” is set in the loop counter as the number of repetitions of a series of operation instructions (the number of loops).
Next, “instructions C0 to C99” which are a series of arithmetic instructions are executed in the main part of the arithmetic processing.
In the post-processing portion of the loop, when “instruction C0 to C99”, which is a series of operation instructions, is executed, the count value of the loop counter is decremented and it is determined whether or not the count value after decrement is “0”. To do.
If the count value after decrement is not “0”, the process returns to the main part of the arithmetic processing again. If the count value after decrement is “0”, the loop is exited and execution of a series of operation instructions is terminated. .

At this time, the initialization part and the post-processing part of the loop are parts for executing the process for controlling the loop execution and not the part for actually executing the arithmetic instruction. Overhead.
In particular, the post-processing portion of the loop occurs every time the main body of the arithmetic processing is executed once. Therefore, if the number of loops increases, the overhead increases accordingly and the performance deteriorates.

Non-Patent Document 1 below discloses “loop unrolling” as a method of suppressing performance degradation due to loop control.
“Loop unrolling” is to reduce the number of iterations of a loop by creating a main part of a new operation process by combining a number of operations for one original loop.
As a result, the total overhead can be reduced and the speed of data operation can be increased. However, the number of instructions in the main part of the operation processing increases as the number of loop iterations is reduced.

For example, in order to reduce the overhead of loop execution that repeats a series of arithmetic processes 100 times, if “loop unrolling” is used to generate a main part of the arithmetic process by combining four arithmetic processes, the number of loop iterations Is reduced to 25 times, which is a quarter, so that the overhead due to loop control is reduced to a quarter.
However, if the arithmetic processing for four times is put together, the number of instructions in the main part of the arithmetic processing increases four times and the program amount increases.

  The following Patent Document 1 discloses a data arithmetic device provided with a dedicated loop control circuit that performs loop execution according to loop information.

JP-T-2006-508447

Masakazu Suwa, “Computer Architecture Principles”, Corona, published on August 20, 1993, first edition, first edition, pp. 110-112

  Since the control circuit of the conventional data operation device is configured as described above, if a dedicated loop control circuit for performing loop execution is provided, the program amount does not increase as in “loop unrolling”. The overhead due to loop control can be reduced. However, it is necessary to provide a dedicated loop control circuit in addition to a general control circuit that controls the execution of arithmetic instructions that do not involve loop execution, resulting in an increase in hardware scale. It was.

  The present invention has been made to solve the above-described problems, and is a data arithmetic apparatus capable of reducing the overhead due to loop control by providing only a slight increase in the program amount without providing a dedicated loop control circuit. It is an object to obtain a control circuit and a data operation device.

  The control circuit of the data arithmetic device according to the present invention sets the start address set by the initial setting means to the read address, outputs the read address, then increments the read address, and reads after the increment If the presence / absence of the repetition set by the initial setting means and the address output means for repeatedly performing the process of outputting the address is “Yes”, the read address output from the address output means is the end set by the initial setting means. If it matches the address, a one-loop end notification is output, and if no operation end instruction has been output so far, the read address set by the address output means is returned to the start address, and the continuation of the address output processing is addressed. Instruct the output means and make initial settings When the presence / absence of repetition set by the stage is “None”, when the read address output from the address output means matches the end address set by the initial setting means, the address output means is instructed to stop address output processing. Whether or not the calculation end determination means ends the repetition calculation by comparing the number of outputs of one loop end notification by the repetition processing control means with the number of repetitions set by the initial setting means. When the determination is made and the repetitive calculation is ended, a calculation end instruction is output to the repetitive processing control means.

  According to this invention, the start address set by the initial setting means is set as a read address, the read address is output, the read address is incremented, and the incremented read address is output. When the address output means to be repeatedly executed and the presence / absence of repetition set by the initial setting means are “present”, if the read address output from the address output means matches the end address set by the initial setting means, 1 A loop end notification is output, and if an operation end instruction has not been output by the present time, the read address set by the address output unit is returned to the start address, and the address output unit is instructed to continue the address output process. Repeat set by the initial setting means In the case where the presence / absence of the address is “None”, when the read address output from the address output unit coincides with the end address set by the initial setting unit, the repetitive process control unit instructs the address output unit to stop the address output process The calculation end determination means compares the number of outputs of one-loop end notification by the repetition processing control means with the number of repetitions set by the initial setting means, determines whether or not to end the repetition calculation, and repeats the calculation. Since the calculation end instruction is repeatedly output to the processing control means when ending the process, the overhead due to the loop control can be reduced with only a slight increase in the program amount without providing a dedicated loop control circuit. There is an effect that can be done.

It is a block diagram which shows the data arithmetic device by Embodiment 1 of this invention. 4 is an explanatory diagram showing a series of operation instructions stored in an operation instruction memory 32. FIG. It is explanatory drawing which shows the command in the program for sequence control stored by the command memory 12 for sequence control. It is explanatory drawing which shows the command in the program for sequence control stored by the command memory 12 for sequence control. It is a block diagram which shows the data arithmetic device by Embodiment 3 of this invention. It is explanatory drawing which shows the command in the program for sequence control stored by the command memory 12 for sequence control. It is explanatory drawing which shows the example of a program which performs general loop control.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a data operation apparatus according to Embodiment 1 of the present invention.
In FIG. 1, the control circuit 1 executes a sequence control program, thereby issuing a series of arithmetic instructions to the arithmetic unit 2 and executing a process of acquiring the arithmetic result of the arithmetic unit 2.
The arithmetic unit 2 executes a calculation instruction issued from the control circuit 1 and performs a process of returning the calculation result of the calculation instruction to the control circuit 1.

If the instruction in the sequence control program is an operation start instruction that causes the arithmetic unit 2 to execute a series of operation instructions stored in the operation instruction memory 32, the sequence control unit 11 A start address indicating an address in the operation instruction memory 32 in which the first operation instruction is stored is set in the start address register 22b of the register group 22, and the last operation instruction in the series of operation instructions is stored. An end address indicating an address in the operation instruction memory 32 is set in the end address register 22c of the register group 22, and a loop instruction (ON / OFF) indicating whether a series of operation instructions is repeated is set in the register group 22. Processing to set in the loop instruction register 22a is performed. Also, if the instruction in the program for sequence control is a setting instruction that sets the number of repetitions of a series of arithmetic instructions (hereinafter referred to as “loop number”), a process of setting the loop number in the general-purpose register 15 is performed. To do.
In addition, the sequence control unit 11 performs a process of determining whether or not to end the repetitive calculation (loop execution) as a post-process of the loop control in parallel with the calculation instruction issuance process in the arithmetic unit control unit 21. That is, the PC control unit 23 compares the number of outputs of “1 loop end notification” with the number of loops to determine whether or not to end the repetitive calculation. When the repetitive calculation is ended, the “control end instruction” is controlled by the PC. The process of outputting to the unit 23 is performed.

The sequence control instruction memory 12 is a recording medium storing a sequence control program.
The sequence control program includes a calculation start instruction (start address, end address, loop instruction (ON / OFF)) that causes the calculator 2 to execute a series of calculation instructions stored in the calculation instruction memory 32. In addition to an instruction), an instruction for setting the number of loops in the general-purpose register 15, an instruction for determining whether to repeat operation (loop execution) as post-processing of loop control, and an internal arithmetic unit 14 Single operation instructions executed by (single operation instructions are instructions that perform operations necessary for sequence control, such as instructions for binary addition, subtraction, multiplication, comparison, and register read / write) It is included.

The arithmetic unit control instruction generation circuit 13 causes the arithmetic unit 2 to execute a series of arithmetic instructions stored in the arithmetic instruction memory 32 according to instructions in the sequence control program stored in the sequence control instruction memory 12. If it is an operation start instruction, a write enable is output to the register group 22 to set a start address that is an operand of the operation start instruction in the start address register 22b of the register group 22, and is an operand of the operation start instruction. An end address is set in the end address register 22c of the register group 22, and a loop instruction (ON / OFF) that is an operand of the operation start instruction is set in the loop instruction register 22a of the register group 22.
Further, after completing the setting of the start address and the like, the arithmetic unit control instruction generation circuit 13 outputs “calculation start instruction” or “calculation end instruction” to the PC control unit 23 under the instruction of the internal arithmetic unit 14, A process of transferring the “1 loop end notification” output from the PC control unit 23 to the internal computing unit 14 is performed.
The calculator control instruction generation circuit 13 constitutes an initial setting means.

If the instruction in the sequence control program stored in the sequence control instruction memory 12 is a setting instruction for setting the number of loops, the internal arithmetic unit 14 sets the number of loops in the general-purpose register 15 and is used for sequence control. If the instruction in the program is a single operation instruction, a single operation is executed in accordance with the single operation instruction, and the result of storing the operation result in the general-purpose register 15 is executed.
Further, if the instruction in the sequence control program is a “do-while instruction” corresponding to a post-processing part of the loop control, the internal calculator 14 performs “1 loop end notification” by the calculator control instruction generation circuit 13. Is compared with the number of loops set in the general-purpose register 15 to determine whether or not to end the repetitive operation (loop execution). Then, a process of outputting an “arithmetic end instruction” to the PC control unit 23 is performed.
Further, the internal computing unit 14 executes a predetermined sequence control using the computation result returned from the computing unit 2.
The internal computing unit 14 constitutes a computation end judging means.
The general-purpose register 15 is a recording medium that stores the number of loops and the result of a single operation.

The computing unit control unit 21 includes a register group 22, a PC control unit 23, and an instruction issuing unit 31, and performs a process of issuing a series of computing instructions to the computing unit 2 under the instruction of the sequence control unit 11.
The register group 22 is a recording medium including a loop instruction register 22a for storing a loop instruction (ON / OFF), a start address register 22b for storing a start address, and an end address register 22c for storing an end address. The PC control unit 23 refers to the register group 22 and performs a process of generating a read address for reading the operation instruction stored in the operation instruction memory 32.

When the “calculation start instruction” is output from the arithmetic unit control instruction generation circuit 13, the flag generation circuit 24 sets “valid” (“1”) in the execution flag register 25 and also starts the start address from the start address register 22 b. , The end address is acquired from the end address register 22c, and the start address is subtracted from the end address to calculate a difference value (end address-start address).
When the register value of the current PC register 29 (the register value is “0” in the initial state) reaches the difference value, the flag generation circuit 24 sets the loop instruction stored in the loop instruction register 22a to “ON”. In some cases, if the operation end flag register 26 is “invalid” (“0”), “valid” (“1”) set in the execution flag register 25 is maintained, and the operation end flag register 26 is “valid”. If “” (“1”), a process of changing “valid” (“1”) set in the execution flag register 25 to “invalid” (“0”) is performed.
On the other hand, when the loop instruction stored in the loop instruction register 22a is “OFF”, “valid” (“1”) set in the execution flag register 25 is changed to “invalid” (“0”). Perform the process.
Further, the flag generation circuit 24 executes a process of setting “valid” (“1”) in the calculation end flag register 26 when the “calculation end instruction” is output from the arithmetic unit control instruction generation circuit 13.

The execution flag register 25 is set to “invalid” (“0”) in the initial state, and the setting state is appropriately changed by the flag generation circuit 24.
The operation end flag register 26 is set to “invalid” (“0”) in the initial state, and the setting state is appropriately changed by the flag generation circuit 24.

The PC generation circuit 27 obtains the start address from the start address register 22b, obtains the end address from the end address register 22c, and subtracts the start address from the end address to calculate a difference value (end address-start address). Perform the process.
The PC generation circuit 27 sets the register value of the next PC register 28 (the register value is “0” in the initial state) in the current PC register 29 when the execution flag register 25 is “valid” (“1”). If the register value of the current PC register 29 does not match the difference value, a process of incrementing the register value of the next PC register 28 by 1 is performed.
On the other hand, if the register value of the current PC register 29 matches the difference value, the register value of the next PC register 28 is cleared to “0” and “1 loop end notification” is output to the arithmetic unit control instruction generation circuit 13. Perform the process.

The count value of the next PC register 28 is set to “0” in the initial state, and the count value is incremented by 1 by the PC generation circuit 27 or cleared to “0”.
The count value of the current PC register 29 is set to “0” in the initial state, and the count value is set to the register value of the next PC register 28 by the PC generation circuit 27.
The address generation circuit 30 acquires the start address from the start address register 22b, acquires the register value of the current PC register 29, and uses the addition value of the start address and the register value of the current PC register 29 as a read address to issue an instruction. The process which outputs to 31 is implemented.

The PC output circuit 27, the next PC register 28, the current PC register 29, and the address generation circuit 30 constitute address output means.
The flag generation circuit 24, the execution flag register 25, the operation end flag register 26, the PC generation circuit 27, the next PC register 28, and the current PC register 29 constitute a repetitive processing control means.

When the execution flag register 25 is “valid” (“1”), the instruction issuing unit 31 corresponds to the read address output from the address generation circuit 30 among the arithmetic instructions stored in the arithmetic instruction memory 32. The operation instruction to be read is read and the operation instruction is issued to the computing unit 2. The instruction issuing unit 31 constitutes an instruction issuing unit.
The calculation instruction memory 32 is a recording medium that stores a series of calculation instructions issued to the calculator 2.

Here, FIG. 2 is an explanatory diagram showing a series of operation instructions stored in the operation instruction memory 32.
FIG. 3 is an explanatory diagram showing instructions in the sequence control program stored in the sequence control instruction memory 12.
FIG. 3 shows an example in which PROC_C (instructions C0 to C99) is repeatedly executed 100 times and PROC_D (instructions D0 to D44) is executed once.

Next, the operation will be described.
In the first embodiment, for convenience of explanation, it is assumed that the instructions in the program for sequence control are the instructions in FIG. 3, and the series of arithmetic instructions stored in the arithmetic instruction memory 32 are the instructions in FIG. explain.

The control circuit 1 is initialized before the processing starts, and “0” is set in the loop instruction register 22a, the start address register 22b, and the end address register 22c of the register group 22.
Further, “invalid” (“0”) is set in the execution flag register 25 and the operation end flag register 26, and “0” is set in the count values of the next PC register 28 and the current PC register 29.

The sequence control unit 11 reads a sequence control program stored in the sequence control instruction memory 12 and analyzes instructions in the program.
In the example of FIG. 3, first, a setting command for setting the number of loops in order to repeat PROC_C (commands C0 to C99) 100 times (in FIG. 3, “setting the loop counter to 100” is described). Is described in the program, the internal arithmetic unit 14 of the sequence control unit 11 sets the number of loops in the general-purpose register 15 in accordance with the setting instruction.
In the example of FIG. 3, “100” is set in the general-purpose register 15 as the number of loops.

Next, since the operation start instruction (description (1)) of PROC_C (instructions C0 to C99) is described in the program, the arithmetic unit control instruction generation circuit 13 of the sequence control unit 11 sets the write enable to the register group 22. By outputting, the operand (start address, end address, loop instruction (ON / OFF)) of the operation start instruction is set in the register group 22.
In the example of FIG. 3, the arithmetic unit control instruction generation circuit 13 outputs a write enable to the register group 22, thereby setting the start address = 0x0110 in the start address register 22b and the end address = 0x0173 in the end address register 22c. In addition, a loop instruction (LOOP = ON) is set in the loop instruction register 22a.

Here, the start address = 0x0110 indicates the address of the instruction C0 (the operation instruction at the head of the loop) stored in the operation instruction memory 32, and the end address = 0x0173 is the instruction stored in the operation instruction memory 32. The address of C99 (the last calculation instruction of the loop) is shown. The loop instruction (LOOP = ON) indicates that loop execution is performed.
Therefore, this operation start instruction means loop execution of the instructions C0 to C99.
After completing the setting of the start address and the like, the arithmetic unit control instruction generation circuit 13 outputs “calculation start instruction” to the flag generation circuit 24 of the PC control unit 23 under the instruction of the internal arithmetic unit 14.

The flag generation circuit 24 sets “valid” (“1”) in the execution flag register 25 when the “calculation start instruction” is output from the arithmetic unit control instruction generation circuit 13.
Further, the flag generation circuit 24 acquires the start address from the start address register 22b, acquires the end address from the end address register 22c, subtracts the start address from the end address, and calculates a difference value (end address−start address). ) Is calculated.
In this example, since the start address = 0x0110 and the end address = 0x0173, the difference value (end address−start address) is “99”.
The difference value is stored in an internal memory or the like because it is compared later with the register value of the current PC register 29 by the flag generation circuit 24.

When the flag generation circuit 24 sets “valid” (“1”) in the execution flag register 25, the PC generation circuit 27 starts a register value update process described below.
That is, when the flag generation circuit 24 sets “valid” (“1”) in the execution flag register 25, the PC generation circuit 27 acquires the start address from the start address register 22b, as in the flag generation circuit 24, and The end address is obtained from the end address register 22c, and the start address is subtracted from the end address to calculate a difference value (end address-start address). Here, the PC generation circuit 27 calculates the difference value, but the difference value calculated by the flag generation circuit 24 may be acquired. Alternatively, the difference value calculated by the PC generation circuit 27 may be given to the flag generation circuit 24.
The PC generation circuit 27 sets the register value of the next PC register 28 in the current PC register 29 when the execution flag register 25 is “valid” (“1”).
At this time, since the register value of the next PC register 28 is “0”, the register value of the current PC register 29 is set to “0”.

When the register value of the next PC register 28 is set in the current PC register 29, the PC generation circuit 27 compares the register value of the current PC register 29 with the difference value (end address-start address).
At this time, the register value of the current PC register 29 is “0”, and the difference value is “99”.
The PC generation circuit 27 increments the register value of the next PC register 28 by 1 because the register value of the current PC register 29 does not match the difference value.
At this time, the register value of the next PC register 28 is “1”.

The address generation circuit 30 acquires the start address from the start address register 22b, acquires the register value of the current PC register 29, and adds the start address and the register value of the current PC register 29.
At this time, since the register value of the current PC register 29 is “0” and the start address = 0x0110, the added value of the start address and the register value is “0x0110”.
The address generation circuit 30 outputs the addition value “0x0110” to the instruction issuing unit 31 as a read address.

When the execution flag register 25 is “valid” (“1”), the instruction issuing unit 31 sets the read address output from the address generation circuit 30 from among the operation instructions stored in the operation instruction memory 32. Read the corresponding operation instruction.
At this time, since the read address is “0x0110”, the instruction C0 corresponding to “0x0110” is read from the operation instruction memory 32.
The instruction issuing unit 31 issues the instruction C0 to the computing unit 2 when reading the instruction C0 that is an operation instruction.
When the instruction C0 is issued from the instruction issuing unit 31, the arithmetic unit 2 executes the instruction C0 and outputs the calculation result of the instruction C0 to the sequence control unit 11 of the control circuit 1.

When the address generation circuit 30 outputs the read address “0x0110” to the instruction issuing unit 31, the PC generation circuit 27 continues to confirm that the execution flag register 25 is “valid” (“1”), and the next PC register 28 register values are set in the current PC register 29.
At this time, since the register value of the next PC register 28 is “1”, the register value of the current PC register 29 is set to “1”.

When the register value of the next PC register 28 is set in the current PC register 29, the PC generation circuit 27 compares the register value of the current PC register 29 with the difference value (end address-start address).
At this time, the register value of the current PC register 29 is “1”, and the difference value is “99”.
The PC generation circuit 27 increments the register value of the next PC register 28 by 1 because the register value of the current PC register 29 does not match the difference value.
At this time, the register value of the next PC register 28 is “2”.

The address generation circuit 30 acquires the start address from the start address register 22b, acquires the register value of the current PC register 29, and adds the start address and the register value of the current PC register 29.
At this time, since the register value of the current PC register 29 is “1” and the start address = 0x0110, the added value of the start address and the register value is “0x0111”.
The address generation circuit 30 outputs the added value “0x0111” to the instruction issuing unit 31 as a read address.

When the execution flag register 25 is “valid” (“1”), the instruction issuing unit 31 sets the read address output from the address generation circuit 30 from among the operation instructions stored in the operation instruction memory 32. Read the corresponding operation instruction.
At this time, since the read address is “0x0111”, the instruction C1 corresponding to “0x0111” is read from the operation instruction memory 32.
The instruction issuing unit 31 issues the instruction C1 to the computing unit 2 when reading the instruction C1 that is an operation instruction.
When the instruction C1 is issued from the instruction issuing unit 31, the arithmetic unit 2 executes the instruction C1 and outputs the calculation result of the instruction C1 to the sequence control unit 11 of the control circuit 1.

Thereafter, until the register value of the current PC register 29 reaches “98”, the PC generation circuit 27, the address generation circuit 30, the instruction issuing unit 31, and the arithmetic unit 2 repeatedly perform the same processing.
As a result, the instructions C2 to C98 are executed by the computing unit 2, and the calculation results of the instructions C2 to C98 are output to the sequence control unit 11 of the control circuit 1.
At this time, the register value of the next PC register 28 is “99”, and the register value of the current PC register 29 is “98”.
The read address is “0x0172”.

When the address generation circuit 30 outputs the read address “0x0172” to the instruction issuing unit 31, the PC generation circuit 27 continues to confirm that the execution flag register 25 is “valid” (“1”), and the next PC register 28 register values are set in the current PC register 29.
At this time, since the register value of the next PC register 28 is “99”, the register value of the current PC register 29 is set to “99”.

When the register value of the next PC register 28 is set in the current PC register 29, the PC generation circuit 27 compares the register value of the current PC register 29 with the difference value (end address-start address).
At this time, the register value of the current PC register 29 is “99”, and the difference value is “99”.
When the register value of the current PC register 29 coincides with the difference value, the PC generation circuit 27 clears the register value of the next PC register 28 to “0” and outputs “1 loop end notification” to the arithmetic unit control instruction generation circuit 13. Output to.

The flag generation circuit 24 compares the register value of the current PC register 29 with the difference value held in the internal memory or the like, and if the register value of the current PC register 29 matches the difference value, it is stored in the loop instruction register 22a. It is confirmed whether the current loop instruction is “ON” or “OFF”.
At this time, the loop instruction stored in the loop instruction register 22a is “ON”.
When the flag generation circuit 24 confirms that the loop instruction is “ON”, it confirms whether the calculation end flag register 26 is “invalid” (“0”) or “valid” (“1”). To do.
At this time, since the “calculation end instruction” has not yet been output from the arithmetic unit control instruction generation circuit 13, the calculation end flag register 26 is “invalid” (“0”).

When the flag generation circuit 24 confirms that the operation end flag register 26 is “invalid” (“0”), the flag generation circuit 24 maintains “valid” (“1”) set in the execution flag register 25.
When the flag generation circuit 24 maintains “valid” (“1”) set in the execution flag register 25, the PC generation circuit 27, the address generation circuit 30, the instruction issuing unit 31, and the arithmetic unit 2 perform the above-described processing. The same process is repeated.
That is, the PC generation circuit 27 repeats the process of updating the register value of the current PC register 29 from “0” to “99”, and the address generation circuit 30 reads the read address from “0x0110”. The read addresses are sequentially output until “0x0173” is reached, and the instruction issuing unit 31 sequentially issues instructions C0 to C99.
As a result, the arithmetic unit 2 sequentially executes the instructions C0 to C99.

In this way, in the process in which the instructions C0 to C99 are sequentially issued from the instruction issuing unit 31, the “computation end instruction” is output from the computing unit control instruction generation circuit 13 and the operation end flag register 26 is set. Repeat until “valid” (“1”).
In the example of FIG. 3, since the loop count is set to “100”, the process of sequentially issuing the instructions C0 to C99 from the instruction issuing unit 31 is repeated 100 times.
It should be noted that in the above iterative process, the register value of the current PC register 29 can be returned to “0” in the cycle following the cycle in which the register value of the current PC register 29 is “99”, so that overhead is achieved. Without being able to return to the process of issuing the operation instruction at the head of the loop.

The sequence control unit 11 performs a process of determining whether or not to end the repetitive calculation (loop execution) as a post-process of the loop control in parallel with the calculation instruction issuance process in the calculator control unit 21.
That is, if the instruction in the sequence control program is a “do-while instruction” corresponding to a post-processing part of loop control, the internal arithmetic unit 14 of the sequence control unit 11 performs a do-while instruction (in FIG. 3). , Instruction of description (2)).
Specifically, it is as follows.

First, the internal arithmetic unit 14 of the sequence control unit 11 sets the loop count “100” set in the general-purpose register 15 in a loop counter (not shown).
Here, an example is shown in which the loop count is set in the loop counter. However, when the general-purpose register 15 is used as the loop counter, it is not necessary to set the loop count in another loop counter.
When the “1 loop end notification” is output from the PC generation circuit 27 of the PC control unit 23, the arithmetic unit control instruction generation circuit 13 transfers the “1 loop end notification” to the internal calculator 14.

The internal computing unit 14 decrements the count value of the loop counter by 1 each time “1 loop end notification” is transferred from the computing unit control instruction generation circuit 13.
When the count value of the loop counter is decremented, the internal computing unit 14 determines whether or not the count value after the decrement is “1” (calculation end determination).
As described above, the count value of the loop counter is set to “100”, and every time “1 loop end notification” is output from the PC generation circuit 27 of the PC control unit 23 (one loop execution is completed). Since the count value is decremented by 1 every time the operation unit control unit 21 completes 99 loop executions, the count value of the loop counter becomes “1”.

When the count value of the loop counter becomes “1”, the internal arithmetic unit 14 outputs “calculation end instruction” to the arithmetic unit control instruction generation circuit 13.
That is, when the remaining number of loops reaches one, the internal computing unit 14 outputs “calculation end instruction” to the computing unit control instruction generation circuit 13.
Upon receiving the “calculation end instruction” from the internal arithmetic unit 14, the arithmetic unit control instruction generation circuit 13 outputs the “calculation end instruction” to the flag generation circuit 24 of the PC control unit 23.

The PC generation circuit 27 of the PC control unit 23 has yet to execute the loop execution for 99 times (the remaining number of loops is 1) and outputs the 99th “1 loop end notification” yet, the sequence control unit 11 No “computation end instruction” is output from the arithmetic unit control instruction generation circuit 13 (the internal arithmetic unit 14 has received the 99th “1 loop end notification” from the PC generation circuit 27 and Since the calculation end determination is started, when the PC generation circuit 27 outputs the 99th “1 loop end notification”, the “calculation end instruction” is not output from the calculator control instruction generation circuit 13), the address generation circuit 30 When the read address is output to the instruction issuing unit 31, it is immediately confirmed that the execution flag register 25 is “valid” (“1”), and the register value of the next PC register 28 is displayed. Since set in the C register 29, 100th loop execution is started.
Therefore, the “computation end instruction” output from the arithmetic unit control instruction generation circuit 13 of the sequence control unit 11 is input to the flag generation circuit 24 of the PC control unit 23 when the 100th loop execution is performed. The

The flag generation circuit 24 sets “valid” (“1”) in the calculation end flag register 26 when receiving the “calculation end instruction” from the arithmetic unit control instruction generation circuit 13.
In the 100th loop execution, the flag generation circuit 24 sets the register value of the current PC register 29 to “99” (when the register value reaches “99”, the read address becomes “0x0173” and the instruction C99 is issued). When the register value of the current PC register 29 reaches the difference value (end address-start address), it is confirmed that the operation end flag register 26 is “valid” (“1”), and the execution flag register “Valid” (“1”) set to 25 is changed to “invalid” (“0”).

When the execution flag register 25 is set to “valid” (“1”), the PC generation circuit 27 starts the register value update process, and the execution flag register 25 is set to “invalid” (“0”). If it is set, the register value is not updated, so that the address generation circuit 30 does not output the read address related to the 101st loop execution.
The instruction issuing unit 31 also issues an operation instruction when “valid” (“1”) is set in the execution flag register 25 and “invalid” (“0”) is set in the execution flag register 25. If it is, the operation instruction is not issued, so the operation instruction related to the 101st loop execution is not issued.
Thus, 100 loop executions related to PROC_C (commands C0 to C99) are completed.

Next, since the operation start instruction (description (3)) of PROC_D (instructions D0 to D44) is described in the program, the arithmetic unit control instruction generation circuit 13 of the sequence control unit 11 sets the write enable to the register group 22. By outputting, the operand (start address, end address, loop instruction (ON / OFF)) of the operation start instruction is set in the register group 22.
In the example of FIG. 3, when the arithmetic unit control instruction generation circuit 13 outputs a write enable to the register group 22, the start address = 0x0174 is set in the start address register 22b, and the end address = 0x01A0 is set in the end address register 22c. In addition, a loop instruction (LOOP = OFF) is set in the loop instruction register 22a.

Here, the start address = 0x0174 indicates the address of the instruction D0 stored in the arithmetic instruction memory 32, and the end address = 0x01A0 indicates the address of the instruction D44 stored in the arithmetic instruction memory 32. . The loop instruction (LOOP = OFF) indicates that loop execution is not performed.
Therefore, this calculation start command means that the commands D0 to D44 are executed once.
After completing the setting of the start address and the like, the arithmetic unit control instruction generation circuit 13 outputs “calculation start instruction” to the flag generation circuit 24 of the PC control unit 23 under the instruction of the internal arithmetic unit 14.

The flag generation circuit 24 sets “valid” (“1”) in the execution flag register 25 when the “calculation start instruction” is output from the arithmetic unit control instruction generation circuit 13.
Further, the flag generation circuit 24 acquires the start address from the start address register 22b, acquires the end address from the end address register 22c, subtracts the start address from the end address, and calculates a difference value (end address−start address). ) Is calculated.
In this example, since the start address = 0x0174 and the end address = 0x01A0, the difference value (end address−start address) is “44”.
The difference value is stored in an internal memory or the like because it is compared later with the register value of the current PC register 29 by the flag generation circuit 24.

When the flag generation circuit 24 sets “valid” (“1”) in the execution flag register 25, the PC generation circuit 27 starts a register value update process described below.
That is, when the flag generation circuit 24 sets “valid” (“1”) in the execution flag register 25, the PC generation circuit 27 acquires the start address from the start address register 22b, as in the flag generation circuit 24, and The end address is obtained from the end address register 22c, and the start address is subtracted from the end address to calculate a difference value (end address-start address). Here, the PC generation circuit 27 calculates the difference value, but the difference value calculated by the flag generation circuit 24 may be acquired. Alternatively, the difference value calculated by the PC generation circuit 27 may be given to the flag generation circuit 24.
The PC generation circuit 27 sets the register value of the next PC register 28 in the current PC register 29 when the execution flag register 25 is “valid” (“1”).
At this time, since the register value of the next PC register 28 is “0”, the register value of the current PC register 29 is set to “0”.

When the register value of the next PC register 28 is set in the current PC register 29, the PC generation circuit 27 compares the register value of the current PC register 29 with the difference value (end address-start address).
At this time, the register value of the current PC register 29 is “0”, and the difference value is “44”.
The PC generation circuit 27 increments the register value of the next PC register 28 by 1 because the register value of the current PC register 29 does not match the difference value.
At this time, the register value of the next PC register 28 is “1”.

The address generation circuit 30 acquires the start address from the start address register 22b, acquires the register value of the current PC register 29, and adds the start address and the register value of the current PC register 29.
At this time, since the register value of the current PC register 29 is “0” and the start address = 0x0174, the added value of the start address and the register value is “0x0174”.
The address generation circuit 30 outputs the addition value “0x0174” to the instruction issuing unit 31 as a read address.

When the execution flag register 25 is “valid” (“1”), the instruction issuing unit 31 sets the read address output from the address generation circuit 30 from among the operation instructions stored in the operation instruction memory 32. Read the corresponding operation instruction.
At this time, since the read address is “0x0174”, the instruction D0 corresponding to “0x0174” is read from the operation instruction memory 32.
The instruction issuing unit 31 issues the instruction D0 to the computing unit 2 when reading the instruction D0 that is an operation instruction.
When the instruction D0 is issued from the instruction issuing unit 31, the arithmetic unit 2 executes the instruction D0 and outputs the calculation result of the instruction D0 to the sequence control unit 11 of the control circuit 1.

When the address generation circuit 30 outputs the read address “0x0174” to the instruction issuing unit 31, the PC generation circuit 27 continues to confirm that the execution flag register 25 is “valid” (“1”), and the next PC register 28 register values are set in the current PC register 29.
At this time, since the register value of the next PC register 28 is “1”, the register value of the current PC register 29 is set to “1”.

When the register value of the next PC register 28 is set in the current PC register 29, the PC generation circuit 27 compares the register value of the current PC register 29 with the difference value (end address-start address).
At this time, the register value of the current PC register 29 is “1”, and the difference value is “44”.
The PC generation circuit 27 increments the register value of the next PC register 28 by 1 because the register value of the current PC register 29 does not match the difference value.
At this time, the register value of the next PC register 28 is “2”.

The address generation circuit 30 acquires the start address from the start address register 22b, acquires the register value of the current PC register 29, and adds the start address and the register value of the current PC register 29.
At this time, since the register value of the current PC register 29 is “1” and the start address = 0x0174, the added value of the start address and the register value is “0x0175”.
The address generation circuit 30 outputs the added value “0x0175” to the instruction issuing unit 31 as a read address.

When the execution flag register 25 is “valid” (“1”), the instruction issuing unit 31 sets the read address output from the address generation circuit 30 from among the operation instructions stored in the operation instruction memory 32. Read the corresponding operation instruction.
At this time, since the read address is “0x0175”, the instruction D1 corresponding to “0x0175” is read from the operation instruction memory 32.
The instruction issuing unit 31 issues the instruction D1 to the computing unit 2 when reading the instruction D1, which is an operation instruction.
When the instruction D1 is issued from the instruction issuing unit 31, the arithmetic unit 2 executes the instruction D1 and outputs the calculation result of the instruction D1 to the sequence control unit 11 of the control circuit 1.

Thereafter, until the register value of the current PC register 29 becomes “43”, the PC generation circuit 27, the address generation circuit 30, the instruction issuing unit 31, and the arithmetic unit 2 repeatedly perform the same processing.
Thereby, the instructions D2 to D43 are executed by the computing unit 2, and the calculation results of the instructions D2 to D43 are output to the sequence control unit 11 of the control circuit 1.
At this time, the register value of the next PC register 28 is “44”, and the register value of the current PC register 29 is “43”.
The read address is “0x019F”.

When the address generation circuit 30 outputs the read address “0x019F” to the instruction issuing unit 31, the PC generation circuit 27 continues to confirm that the execution flag register 25 is “valid” (“1”), and the next PC register 28 register values are set in the current PC register 29.
At this time, since the register value of the next PC register 28 is “44”, the register value of the current PC register 29 is set to “44”.

When the register value of the next PC register 28 is set in the current PC register 29, the PC generation circuit 27 compares the register value of the current PC register 29 with the difference value (end address-start address).
At this time, the register value of the current PC register 29 is “44”, and the difference value is “44”.
When the register value of the current PC register 29 coincides with the difference value, the PC generation circuit 27 clears the register value of the next PC register 28 to “0” and outputs “1 loop end notification” to the arithmetic unit control instruction generation circuit 13. Output to.

The flag generation circuit 24 compares the register value of the current PC register 29 with the difference value held in the internal memory or the like, and if the register value of the current PC register 29 matches the difference value, it is stored in the loop instruction register 22a. It is confirmed whether the current loop instruction is “ON” or “OFF”.
At this time, the loop instruction stored in the loop instruction register 22a is “OFF”.
Upon confirming that the loop instruction is “OFF”, the flag generation circuit 24 changes “valid” (“1”) set in the execution flag register 25 to “invalid” (“0”).

  When “invalid” (“0”) is set in the execution flag register 25, the PC generation circuit 27 does not perform the register value update process, and the instruction issuing unit 31 sets “invalid” in the execution flag register 25. When "" ("0") is set, the operation instruction is not issued, so that the execution of PROC_D (instructions D0 to D45) ends.

  As apparent from the above, according to the first embodiment, the start address set in the start address register 22b is set as the read address, the read address is output, and then the read address is incremented. If the loop instruction set in the loop instruction register 22a is “LOOP = ON”, the address output means that repeatedly executes the process of outputting the incremented read address and the read address output from the address output means If the end address matches the end address set in the end address register 22c, “1 loop end notification” is output, and if no “computation end instruction” has been output from the sequence control unit 11 up to the present time, the address output means The read address set by Is returned to the start address, the address output means is instructed to continue the address output process, and if the loop instruction is “LOOP = OFF”, if the read address output from the address output means matches the end address, It is provided with repetition processing control means for instructing the address output means to stop the output processing, and the internal computing unit 14 compares the number of outputs of “1 loop end notification” with the number of loops to determine whether or not to repeat the calculation Since it is configured to output a “computation end instruction” to the repetitive processing control means when the repetitive calculation is finished, the dedicated control circuit 21 is not accompanied by a loop execution without providing a dedicated loop control circuit. (Combined operation instruction issuance control and operation instruction issuance control without loop execution), only a slight increase in program amount , An effect which can reduce the overhead of loop control.

That is, since the “do-while instruction” corresponding to the post-processing part of the loop control is executed by the internal arithmetic unit 14 in parallel with the operation instruction issuance process in the arithmetic unit control unit 21, loop execution (final round) It is possible to conceal the number of cycles related to post-processing) (excluding loop execution), and it is possible to reduce overhead related to post-processing of loop control.
The only program added to reduce the overhead associated with the post-processing of the loop control is the “do-while instruction” executed by the internal computing unit 14, so the overhead due to the loop control can be reduced by a slight increase in the program amount. Can be reduced.
As described above, since the overhead can be reduced by the loop control, the processing speed can be increased and the power consumption can be reduced.

  In the first embodiment, the sequence control program is stored in the sequence control instruction memory 12 and the operation instruction is stored in the operation instruction memory 32. However, the sequence control program or Arithmetic instructions may be downloaded from the outside.

Embodiment 2. FIG.
In the first embodiment, the operation start instruction that is an instruction in the sequence control program has a start address, an end address, and a loop instruction (ON / OFF) as operands, and the start address, Although the end address and loop instruction (ON / OFF) are shown, the start address, end address and loop instruction (ON / OFF) are set by a parameter setting instruction different from the operation start instruction having no operand. You may be made to do.

FIG. 4 is an explanatory diagram showing instructions in the sequence control program stored in the sequence control instruction memory 12.
4 also shows an example in which PROC_C (instructions C0 to C99) is repeatedly executed 100 times and PROC_D (instructions D0 to D44) is executed once, similarly to FIG.

Next, the operation will be described.
However, since the processing other than the setting processing of the start address and the like by the arithmetic unit control instruction generation circuit 13 is the same as that of the first embodiment, the setting processing of the arithmetic unit control instruction generation circuit 13 will be mainly described.

As in the first embodiment, the control circuit 1 is initialized before the start of processing, and “0” is set in the loop instruction register 22a, the start address register 22b, and the end address register 22c of the register group 22.
Further, “invalid” (“0”) is set in the execution flag register 25 and the operation end flag register 26, and “0” is set in the count values of the next PC register 28 and the current PC register 29.

The sequence control unit 11 reads a sequence control program stored in the sequence control instruction memory 12 and analyzes instructions in the program.
In the example of FIG. 4, in order to first repeat PROC_C (commands C0 to C99) 100 times, a setting command for setting the number of loops (in FIG. 4, “setting the loop counter to 100” is described). Is described in the program, the internal arithmetic unit 14 of the sequence control unit 11 sets the number of loops in the general-purpose register 15 in accordance with the setting instruction.
In the example of FIG. 4, “100” is set in the general-purpose register 15 as the number of loops.

Next, since the parameter setting instruction (description (1-1)) whose operand is the start address is described in the program, the arithmetic unit control instruction generation circuit 13 of the sequence control unit 11 sets the write enable to the register group 22. By outputting, the start address = 0x0110, which is the operand of the parameter setting instruction, is set in the start address register 22b.
Next, since the parameter setting instruction (description (1-2)) whose operand is the end address is described in the program, the arithmetic unit control instruction generation circuit 13 of the sequence control unit 11 sets the write enable to the register group 22. By outputting, the end address = 0x0173 which is the operand of the parameter setting instruction is set in the end address register 22c.

Next, since the parameter setting instruction (description (1-3)) whose operand is a loop instruction is described in the program, the arithmetic unit control instruction generation circuit 13 of the sequence control unit 11 sets the write enable to the register group 22. By outputting, the loop instruction (LOOP = ON) which is the operand of the parameter setting instruction is set in the loop instruction register 22a.
Next, since an operation start instruction (description (1-4)) having no operand is described in the program, the operation unit control instruction generation circuit 13 of the sequence control unit 11 performs the following operation under the instruction of the internal operation unit 14: “Calculation start instruction” is output to the flag generation circuit 24 of the PC control unit 23.
Thereafter, PROC_C (instructions C0 to C99) is looped 100 times in the same manner as in the first embodiment.

When the loop execution of PROC_C (instructions C0 to C99) is completed, a parameter setting instruction (description (3-1)) whose operand is the start address is described in the program in order to execute PROC_D (instructions D0 to D44) once. Therefore, the arithmetic unit control instruction generation circuit 13 of the sequence control unit 11 outputs the write enable to the register group 22 to set the start address = 0x0174 as the operand of the parameter setting instruction in the start address register 22b. To do.
Next, since the parameter setting instruction (description (3-2)) whose operand is the end address is described in the program, the arithmetic unit control instruction generation circuit 13 of the sequence control unit 11 sets the write enable to the register group 22. By outputting, the end address = 0x01A0 which is the operand of the parameter setting instruction is set in the end address register 22c.

Next, since the parameter setting instruction (description (3-3)) whose operand is a loop instruction is described in the program, the arithmetic unit control instruction generation circuit 13 of the sequence control unit 11 sets the write enable to the register group 22. By outputting, the loop instruction (LOOP = OFF) which is the operand of the parameter setting instruction is set in the loop instruction register 22a.
Next, since the operation start instruction (description (3-4)) having no operand is described in the program, the arithmetic unit control instruction generation circuit 13 of the sequence control unit 11 performs the following operation under the instruction of the internal arithmetic unit 14: “Calculation start instruction” is output to the flag generation circuit 24 of the PC control unit 23.
Thereafter, PROC_D (commands D0 to D44) is executed once as in the first embodiment.

  As is apparent from the above, according to the second embodiment, the start address, the end address, and the loop instruction (ON / OFF) are set by the parameter setting instruction which is a separate instruction from the calculation start instruction. The operation start instruction operand is eliminated, and the operation start instruction can be prevented from becoming too long.

  In the second embodiment, the parameter setting instruction and the calculation start instruction are used. However, if a compound instruction that simultaneously instructs parameter setting and calculation start is provided, the calculation is performed simultaneously with the last parameter setting. Since the start can be instructed, the cycle up to the calculation start instruction can be reduced by one cycle, and the control speed can be increased.

Embodiment 3 FIG.
FIG. 5 is a block diagram showing a data operation apparatus according to Embodiment 3 of the present invention. In the figure, the same reference numerals as those in FIG.
Therefore, the sequence control unit 11 includes a sequence control instruction memory 12, an arithmetic unit control instruction generation circuit 13, an internal arithmetic unit 14, and a general-purpose register 15 as in the data arithmetic unit of FIG.
The PC control unit 23 includes a flag generation circuit 24, an execution flag register 25, an operation end flag register 26, a PC generation circuit 27, a next PC register 28, a current PC register 29, and an address generation circuit 30.
The instruction issuing unit 31 includes a calculation instruction memory 32.

The register storage unit 40 is a recording medium such as a memory in which two register groups 41 a and 41 b and selectors 42 and 43 are mounted.
In the example of FIG. 5, the register storage unit 40 is provided with two register groups 41a and 41b. However, the present invention is not limited to this, and three or more register groups are installed. It may be.
The register groups 41a and 41b correspond to the register group 22 in FIG. 1, and are composed of a loop instruction register 22a, a start address register 22b, and an end address register 22c.

The selector 42 is a register that indicates the register group 41a or the register group 41b that is the setting destination from the arithmetic unit control instruction generation circuit 13 when the arithmetic unit control instruction generation circuit 13 of the sequence control unit 11 sets the start address, end address, and loop instruction. When the selection signal is output, a process of selecting the register group 41a or the register group 41b indicated by the register selection signal is performed.
When the PC control unit 23 acquires a start address, an end address, and a loop instruction, the selector 43 outputs a register selection signal indicating the register group 41a or the register group 41b as an acquisition destination from the arithmetic unit control instruction generation circuit 13. Processing for selecting the register group 41a or the register group 41b indicated by the register selection signal is performed.

In the first embodiment, the computing unit control unit 21 is mounted with one register group 22. However, the computing unit control unit 21 is mounted with two register groups 41a and 41b. A start address, an end address, and a loop instruction related to two calculation start instructions may be set for each of the register groups 41a and 41b.
The processing contents will be specifically described below.

FIG. 6 is an explanatory diagram showing instructions in the sequence control program stored in the sequence control instruction memory 12.
In FIG. 6, PROC_C (instructions C0 to C99) is repeatedly executed 100 times using the register group 41a, and PROC_D (instructions D0 to D44) is executed once using the register group 41b. In this example, PROC_A (instructions A0 to A7) is executed once using the register group 41a after rewriting the start address and the like.
However, in FIG. 6, description regarding setting of the start address and the like related to PROC_C (commands C0 to C99) and PROC_D (commands D0 to D44) is omitted.

First, the arithmetic unit control instruction generation circuit 13 of the sequence control unit 11 sets the start address and the like related to PROC_C (commands C0 to C99) in the register group 41a before starting the control process. The write enable is output to the register storage unit 40, and a register selection signal ("0") indicating that the setting destination is the register group 41a is output to the selector 42.
When the selector 42 receives a register selection signal (“0”) indicating that the setting destination is the register group 41 a from the arithmetic unit control instruction generation circuit 13, the selector 42 selects the register group 41 a and the arithmetic unit control instruction generation circuit 13. Is set in the start address register 22b of the register group 41a.
The end address output from the arithmetic unit control instruction generation circuit 13 is set in the end address register 22c of the register group 41a, and the loop instruction output from the arithmetic unit control instruction generation circuit 13 is set as the loop instruction register 22a of the register group 41a. Set to.
In this example, the start address = 0x0110 is set in the start address register 22b, the end address = 0x0173 is set in the end address register 22c, and the loop instruction (LOOP = ON) is set in the loop instruction register 22a.

Next, the arithmetic unit control instruction generation circuit 13 of the sequence control unit 11 sets the start address and the like related to PROC_D (instructions D0 to D44) in the register group 41b before the start of the control processing. Under the instruction, a write enable is output to the register storage unit 40, and a register selection signal ("1") indicating that the setting destination is the register group 41b is output to the selector 42.
When the selector 42 receives a register selection signal (“1”) indicating that the setting destination is the register group 41 b from the arithmetic unit control instruction generation circuit 13, the selector 42 selects the register group 41 b and selects the arithmetic unit control instruction generation circuit 13. Is set in the start address register 22b of the register group 41b.
The end address output from the arithmetic unit control instruction generation circuit 13 is set in the end address register 22c of the register group 41b, and the loop instruction output from the arithmetic unit control instruction generation circuit 13 is set as the loop instruction register 22a of the register group 41b. Set to.
In this example, the start address = 0x0174 is set in the start address register 22b, the end address = 0x01A0 is set in the end address register 22c, and the loop instruction (LOOP = OFF) is set in the loop instruction register 22a.

As described above, when the start address and the like related to PROC_C (commands C0 to C99) and PROC_D (commands D0 to D44) are set, execution of PROC_C (commands C0 to C99) and PROC_D (commands D0 to D44) is started. .
First, in order to repeat PROC_C (instructions C0 to C99) 100 times, a setting instruction for setting the number of loops (described as “setting the loop counter to 100” in FIG. 6) is described in the program. Therefore, the internal arithmetic unit 14 of the sequence control unit 11 sets the number of loops in the general-purpose register 15 in accordance with the setting instruction.
In the example of FIG. 6, “100” is set in the general-purpose register 15 as the number of loops.

Next, the operation start instruction (description (1)) of PROC_C (instructions C0 to C99) is described in the program, and the operand of the operation start instruction indicates that the acquisition destination register group is the register group 41a. (Register selection = 0), the arithmetic unit control instruction generation circuit 13 of the sequence control unit 11 generates a register selection signal (“0”) instructing selection of the register group 41a under the instruction of the internal arithmetic unit 14. Output to the selector 43.
When the selector 43 receives a register selection signal (“0”) instructing selection of the register group 41a from the arithmetic unit control instruction generation circuit 13, the selector 43 selects the register group 41a and sets it to the start address register 22b of the register group 41a. The start address = 0x0110 is output to the PC control unit 23, and the end address = 0x0173 set in the end address register 22c of the register group 41a is output to the PC control unit 23.
Further, the loop instruction (LOOP = ON) set in the loop instruction register 22 a of the register group 41 a is output to the PC control unit 23.
The arithmetic unit control instruction generation circuit 13 outputs an “arithmetic start instruction” to the PC control unit 23 under the instruction of the internal arithmetic unit 14.

When receiving the “calculation start instruction” from the arithmetic unit control instruction generation circuit 13, the PC control unit 23 reads the read addresses “0x0110” to “0x0173” related to PROC_C (commands C0 to C99) in the same manner as in the first embodiment. The process of sequentially outputting “to the instruction issuing unit 31 is repeated 100 times.
The instruction issuing unit 31 repeatedly issues the instructions C0 to C99 corresponding to the read addresses “0x0110” to “0x0173” output from the PC control unit 100 to the arithmetic unit 2 100 times as in the first embodiment.
The loop execution of PROC_C (instructions C0 to C99) is terminated when the PC control unit 23 receives an “operation end instruction” from the sequence control unit 11 in the same manner as in the first embodiment.

When the loop execution of PROC_C (instructions C0 to C99) is completed, the operation start instruction (description (3)) of PROC_D (instructions D0 to D44) is described in the program, and the operand of the operation start instruction is the acquisition destination. Since the register group indicates that it is the register group 41b (register selection = 1), the arithmetic unit control instruction generation circuit 13 of the sequence control unit 11 selects the register group 41b under the instruction of the internal arithmetic unit 14. A register selection signal (“1”) to be instructed is output to the selector 43.
When the selector 43 receives a register selection signal (“1”) instructing selection of the register group 41b from the arithmetic unit control instruction generation circuit 13, the selector 43 selects the register group 41b and sets it to the start address register 22b of the register group 41b. The generated start address = 0x0174 is output to the PC control unit 23, and the end address = 0x01A0 set in the end address register 22c of the register group 41b is output to the PC control unit 23.
Further, the loop instruction (LOOP = OFF) set in the loop instruction register 22 a of the register group 41 b is output to the PC control unit 23.
The arithmetic unit control instruction generation circuit 13 outputs an “arithmetic start instruction” to the PC control unit 23 under the instruction of the internal arithmetic unit 14.

When receiving the “calculation start instruction” from the arithmetic unit control instruction generation circuit 13, the PC control unit 23 reads the read addresses “0x0174” to “0x01A0” related to PROC_D (commands D0 to D44) in the same manner as in the first embodiment. The process of sequentially outputting “to the instruction issuing unit 31 is executed once.
The instruction issuing unit 31 issues the instructions D0 to D44 corresponding to the read addresses “0x0174” to “0x01A0” output from the PC control unit 23 once to the computing unit 2 as in the first embodiment.
Execution of PROC_D (instructions D0 to D44) is terminated when instructions D0 to D44 are issued from the instruction issuing unit 31, as in the first embodiment.

Next, in the sequence control program, a parameter setting instruction for rewriting the start address and the like of the register group 41a during execution of PROC_D (instructions D0 to D44) is described.
That is, a parameter setting instruction (description (4-1)) having an operand indicating that the register group to be set is the register group 41a (register selection = 0) and an operand indicating that the start address is “0x0000”. ) Is described in the program, and in parallel with the issuance processing of PROC_D (commands D0 to D44) in the computing unit control unit 21, the computing unit control instruction generation circuit 13 in the sequence control unit 11 Under the instruction, a write enable is output to the register storage unit 40, and a register selection signal (“0”) indicating that the setting destination is the register group 41a and a start address = “0x0000” are output to the selector 42. .
When the selector 42 receives a register selection signal (“0”) indicating that the setting destination is the register group 41 a from the arithmetic unit control instruction generation circuit 13, the selector 42 selects the register group 41 a and the arithmetic unit control instruction generation circuit 13. Is set to the start address register 22b of the register group 41a.

Next, a parameter setting instruction (description (4-2) having an operand indicating that the register group to be set is the register group 41a (register selection = 0) and an operand indicating that the end address is “0x0007”. )) Is described in the program, and in parallel with the issuance processing of PROC_D (commands D0 to D44) in the computing unit control unit 21, the computing unit control instruction generation circuit 13 in the sequence control unit 11 Under the instruction, a write enable is output to the register storage unit 40, and a register selection signal (“0”) indicating that the setting destination is the register group 41a and an end address = “0x0007” are output to the selector 42. To do.
When the selector 42 receives a register selection signal (“0”) indicating that the setting destination is the register group 41 a from the arithmetic unit control instruction generation circuit 13, the selector 42 selects the register group 41 a and the arithmetic unit control instruction generation circuit 13. Is set to the end address register 22c of the register group 41a.

Next, a parameter setting instruction (description (4-3) having an operand indicating that the register group to be set is the register group 41a (register selection = 0) and an operand indicating that the loop instruction is “OFF”. )) Is described in the program, and in parallel with the issuance processing of PROC_D (commands D0 to D44) in the computing unit control unit 21, the computing unit control instruction generation circuit 13 in the sequence control unit 11 Under the instruction, the write enable is output to the register storage unit 40, and a register selection signal (“0”) indicating that the setting destination is the register group 41a and a loop instruction (LOOP = OFF) are sent to the selector 42. Output.
When the selector 42 receives a register selection signal (“0”) indicating that the setting destination is the register group 41 a from the arithmetic unit control instruction generation circuit 13, the selector 42 selects the register group 41 a and the arithmetic unit control instruction generation circuit 13. The loop instruction (LOOP = OFF) output from is set in the loop instruction register 22a of the register group 41a.

When the setting of the start address and the like related to PROC_A (commands A0 to A7) is completed, the sequence control unit 11 waits until the execution of PROC_D (commands D0 to D44) is completed. Alternatively, another single operation is executed.
The arithmetic unit control instruction generation circuit 13 of the sequence control unit 11 has the operation start instruction (description (5)) of PROC_A (instructions A0 to A7) described in the program, and the operand of the operation start instruction is the acquisition destination. Since the register group indicates that it is the register group 41a (register selection = 0), when “1 loop end notification” is output from the PC generation circuit 27 of the PC control unit 23, the instruction of the internal arithmetic unit 14 is instructed. Below, a register selection signal (“0”) instructing selection of the register group 41 a is output to the selector 43.

When the selector 43 receives a register selection signal (“0”) instructing selection of the register group 41a from the arithmetic unit control instruction generation circuit 13, the selector 43 selects the register group 41a and sets it to the start address register 22b of the register group 41a. The start address = 0x0000 is output to the PC control unit 23, and the end address = 0x0007 set in the end address register 22c of the register group 41a is output to the PC control unit 23.
Further, the loop instruction (LOOP = OFF) set in the loop instruction register 22 a of the register group 41 a is output to the PC control unit 23.
The arithmetic unit control instruction generation circuit 13 outputs an “arithmetic start instruction” to the PC control unit 23 under the instruction of the internal arithmetic unit 14.

When receiving the “calculation start instruction” from the arithmetic unit control instruction generation circuit 13, the PC control unit 23 performs PROC_A (instructions A0 to A7) in the same manner as when the read address related to PROC_D (instructions D0 to D44) is output. The process of sequentially outputting the read addresses “0x0000” to “0x0007” to the instruction issuing unit 31 is executed once.
The instruction issuing unit 31 issues instructions A0 to A7 corresponding to the read addresses “0x0000” to “0x0007” output from the PC control unit 23 to the computing unit 2 once.
The execution of PROC_A (instructions A0 to A7) ends when instructions A0 to A7 are issued from the instruction issuing unit 31.

  As apparent from the above, according to the third embodiment, the arithmetic unit control unit 21 mounts two register groups 41a and 41b, and two register groups 41a and 41b are provided with two registers. Since the start address, the end address, and the loop instruction related to the calculation start instruction are set, the start address, the end address, and the loop instruction related to the two calculation start instructions are previously registered before starting the control process. , 41b, it becomes unnecessary to set a start address or the like related to the second calculation start instruction before executing the second calculation start instruction, thereby further speeding up the calculation process. The effect which can aim at is produced. This effect increases as the number of mounted register groups increases.

  In the third embodiment, the sequence controller 11 sets the start address and the like related to the calculation start instruction in the two register groups 41a and 41b. However, before the control process is started, the calculation is performed from the outside. The start address or the like related to the start command may be downloaded to the two register groups 41a and 41b.

  DESCRIPTION OF SYMBOLS 1 Control circuit, 2 arithmetic unit, 11 Sequence control part, 12 Sequence control command memory, 13 Operation unit control instruction generation circuit (initial setting means), 14 Internal arithmetic unit (calculation end determination means), 15 General-purpose register, 21 arithmetic Control unit, 22 register group, 22a loop instruction register, 22b start address register, 22c end address register, 23 PC control unit, 24 flag generation circuit (repetition process control means), 25 execution flag register (repetition process control means), 26 calculation end flag register (repetition processing control means), 27 PC generation circuit (address output means, repetition processing control means), 28th PC register (address output means, repetition processing control means), 29 current PC register (address output means) , Repetitive processing control means), 0 address generation circuit (address output means), 31 instruction issue unit (instruction issuing means) 32 arithmetic instruction memory, 40 a register storing portion, 41a, 41b registers, 42 and 43 selector.

Claims (6)

If the instruction in the sequence control program is an operation start instruction that causes an external arithmetic unit to execute a series of operation instructions stored in the operation instruction memory, the first operation instruction in the series of operation instructions is A process of setting a start address indicating an address in the stored instruction memory, a process of setting an end address indicating an address in the instruction instruction memory storing the last operation instruction, and a series of When there is a repetition of a series of operation instructions , either when the operation start instruction is executed or before the execution of the operation start instruction. , the processing for setting the number of repetitions of a sequence of arithmetic instructions, the initial setting unit that performs prior to performing an operation start command, set by the initial setting means An address output means for setting the read start address as a read address, outputting the read address, then incrementing the read address, and outputting the read address after the increment; Instruction issuing means for reading out an operation instruction corresponding to the read address output from the address output means from among the operation instructions stored in the instruction memory, and issuing the operation instruction to the calculator; and the initial setting means When the presence / absence of the repetition set by “Yes” is “Yes”, if the read address output from the address output unit matches the end address set by the initial setting unit, a one-loop end notification is output and If the calculation end instruction has not been output before, When the read address set by the address output means is returned to the start address, the address output means is instructed to continue the address output processing, and the repetition set by the initial setting means is “None” When the read address output from the address output means coincides with the end address set by the initial setting means, a repetition processing control means for instructing the address output means to stop the address output processing, and the repetition processing control means The number of outputs of one-loop end notification by means of the above and the number of repetitions set by the initial setting means are compared to determine whether or not to end the repetition calculation, and when the repetition calculation ends, the calculation end instruction is sent to the repetition process. Control of a data operation device having operation end determination means for outputting to the control means circuit.   The calculation end determination means sets the number of repetitions set by the initial setting means in advance in the loop counter, and decrements the count value of the loop counter every time one loop end notification is output from the repetition processing control means. 2. A control circuit for a data arithmetic device according to claim 1, wherein when the count value after decrement becomes "1", an arithmetic end instruction is output to said repetitive processing control means.   When the instruction in the program for sequence control is an operation start instruction including a start address, an end address, and whether or not a series of operation instructions are repeated, a start address included in the operation start instruction, 3. The control circuit for a data arithmetic device according to claim 1, wherein an end address and whether or not a series of arithmetic instructions are repeated are set.   When the operation start instruction does not include the start address, the end address, and whether a series of operation instructions are repeated, the initial setting means sets the start address, the end address, or a series of operation instructions to be repeated. 3. The control circuit for a data arithmetic device according to claim 1, wherein a start address, an end address, or whether or not a series of arithmetic instructions are repeated is set. In the control circuit of the data operation device, a plurality of memories for storing the start address, end address and presence / absence of repetition of a series of operation instructions are mounted .
The initial setting means sets the start address, end address, and presence / absence of a series of operation instructions related to a plurality of operation start instructions in the memory,
The address output means reads the start address from the memory indicated by the selection signal,
5. The data operation device according to claim 1, wherein the repetitive processing control unit reads an end address and presence / absence of repetition of a series of operation instructions from a memory indicated by the selection signal. Control circuit. An arithmetic unit that executes the issued arithmetic instruction and returns the operation result of the arithmetic instruction, and a series of arithmetic instructions stored in the arithmetic instruction memory are stored in the arithmetic unit. If it is an operation start instruction to be executed, a process for setting a start address indicating an address in the operation instruction memory in which the first operation instruction in the series of operation instructions is stored, and the last operation instruction are stored. Each of the processing for setting the end address indicating the address in the arithmetic instruction memory and the processing for setting the presence / absence of repetition of a series of arithmetic instructions when the arithmetic start instruction is executed, or be performed prior to performing the operation start instruction, when the repetition of a sequence of operation instruction is present, the process of setting the number of repetitions of a sequence of operation instruction, the operation start instruction An initial setting unit that carried out prior to the line, and set the read address start address set by the initial setting means, and outputs the read address, then increment the read address, the incremented Read out the operation instruction corresponding to the read address output from the address output means from among the address output means for repeatedly executing the process of outputting the read address and the operation instructions stored in the operation instruction memory. When the presence / absence of the repetition set by the instruction issuing means and the initial setting means is “Yes”, the read address output from the address output means is set by the initial setting means. If it matches the specified end address, a one-loop end notification is sent. If no calculation end instruction has been output by the present time, the read address set by the address output unit is returned to the start address, and the address output unit is instructed to continue the address output process. When the presence / absence of repetition set by the initial setting means is “none”, when the read address output from the address output means matches the end address set by the initial setting means, the address output processing is stopped. It is determined whether or not to end the repetitive calculation by comparing the repetitive processing control means instructing the address output means, the number of outputs of one loop end notification by the repetitive processing control means and the repetitive number set by the initial setting means When the repetitive calculation ends, the calculation end instruction is A data computation device comprising computation end determination means for outputting to the physical control means.

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