JP5574021B2 - Waveform control device - Google Patents

Description

  This case relates to a waveform control device.

In an element applied to an optical signal processing system or an optical communication system, an optical pulse having a rectangular wave shape is ideal for an optical waveform to be handled.
For example, an optical element such as a semiconductor optical amplifier (SOA) is applied as a gate switch that is driven by an electrical signal (driving signal) that is switched on and off on the time axis to switch conduction / shut-off of input light. The The output light from the SOA becomes an optical pulse whose on / off is switched on the time axis by switching between conduction / cutoff of the drive signal. An optical pulse output from the SOA is often required to be close to a true (ideal) rectangular wave shape.

Some electronic devices that handle binary digital electrical signals include internal elements, wiring, and the like that ideally make a conducting signal a binary rectangular wave signal. For example, there are transmission line devices such as a memory, a buffer, a modulator, and a high-speed input / output interface device. Even in such an electronic device, it is often required that the signal waveform can be easily shaped so as to have an optimal rectangular shape.
JP 9-36471 A JP 2000-341728 A

In view of this, one of the purposes of this case is to generate a pulse having a target rectangularity by simple waveform shaping.
Note that the present invention is not limited to the above-mentioned object, and is an effect derived from each configuration or operation according to the best mode for carrying out the invention to be described later. It can be positioned as a purpose.

For example, the following means are used.
A monitor unit that monitors a waveform of an output pulse obtained by a response element responding to a supplied drive signal; a drive waveform shaping unit that shapes the waveform of the drive signal based on a monitoring result in the monitor unit; The monitor unit detects a rising edge and a falling edge in the waveform of the output pulse, and detects the rising edge in the edge detection unit based on the detection of the rising edge in the waveform of the output pulse. A peak hold unit that holds a value of a rising peak level in response to a rising edge of the drive signal, and a flat area before the falling edge of the drive signal based on the detection of the rising edge by the edge detection unit A sample hold unit that samples and holds the value of the response waveform level, and the drive waveform shaping unit includes the peak hold The value sample-hold with in the held values and the sample-hold section receives as the result of monitoring, it is possible to use the waveform controller.

  According to the disclosed technology, a pulse having a target rectangularity can be generated with a simple configuration.

Hereinafter, embodiments will be described with reference to the drawings. However, the embodiment described below is merely an example, and there is no intention of excluding various modifications and application of technology that are not explicitly described below. In other words, the present embodiment can be implemented with various modifications without departing from the spirit of the present embodiment.
[A] First Embodiment At present, wavelength division multiplexing (WDM) transmission systems are the mainstream of trunk optical communication network systems. However, in the future, from the viewpoint of improving the network utilization efficiency, it is expected to progress to an optical packet / burst switching network system that switches a route with an optical signal.

In an optical packet / burst switching network system, in order to improve line utilization efficiency, it is necessary to have a function to divide an optical signal into packets and perform switching / route switching processing with the optical signal as the packet unit. Is expected.
In an apparatus having such a function, when performing the above-described exchange in units of packets and switching routes, it is possible to perform switching processing in a time dimension smaller than at least a millisecond dimension, for example, a microsecond to nanosecond dimension. It is expected to be able to do that.

As an example, there is a distribution / merging type optical packet switch system in which an element such as an optical semiconductor amplifier (SOA) is used as a gate switch and a plurality of elements are arranged in a matrix. In the distribution / merging type optical packet switch system, N × N or more switching elements are required for N ports.
FIG. 1 shows a distribution / merging gate switch type optical packet switch (optical switch device, interconnect system) 100 having eight input ports (# 1 to # 8) and eight output ports (# 1 to # 8). An example of Optical packet signals input from the 8 ports are each divided into 8 by the 1: 8 coupler 101 provided for each input port. An 8: 8 optical gate switch unit 102 is provided for each output port of the output destination.

  One optical gate switch unit 102 connects one distribution path from the 1: 8 coupler 101 corresponding to eight input ports # 1 to # 8 one by one, and the optical gate switch 102a for each distribution path. Is provided. The optical gate switch 102a controls the passage / blocking of an input optical packet signal based on a drive signal from the drive circuit 105. For example, an SOA can be used as the optical gate switch 102a. Other optical elements such as can also be used. The optical packet switch (interconnect system) 100 may be housed in a casing.

The drive circuit 105 is provided for each optical gate switch 102a and supplies a drive signal corresponding to the trigger signal input from the trigger signal output unit 106 to the optical gate switch 102a. In FIG. 1, attention is paid to the drive circuit 105 corresponding to the optical gate switch 102a in the optical gate switch unit 102 corresponding to the output port # 8.
The trigger signal output unit 106 supplies a trigger signal corresponding to the conduction / cutoff control timing for each optical gate switch 102 a to the corresponding drive circuit 105. The output timing of the trigger signal to each drive circuit 105 output from the trigger signal output unit 106 can be controlled by the synchronization means 107.

  The synchronization unit 107 synchronizes the timing at which the optical packet signal is input to and passed through the optical gate switch 102a to be controlled to conduct the optical packet signal, and the conduction / cutoff control of the optical gate switch 102a. Let For example, the trigger signal output unit 106 is controlled so that the trigger signal for conduction / cutoff control of the optical gate switch 102a output from the trigger signal output unit 106 is substantially synchronized with the input and passage timing of the optical packet signal. To do.

Note that the synchronization unit 107 can control the trigger signal output unit 106 in a manner corresponding to a location where the optical packet switch 100 is mounted, for example.
For example, when applied to a network relay point, an optical transmission line is connected to each of the input / output ports # 1 to # 8. Then, the input of the optical packet signal to each of the input ports # 1 to # 8 is detected at a location upstream of the 1: 8 coupler 101. Then, the optical gate switch 102a determined according to the output ports # 1 to # 8 to which the optical packet signal whose input is detected is to be guided is brought into a conductive state before the optical packet signal reaches the corresponding optical gate switch 102a. The output of the trigger signal is controlled so that Also, the trigger signal output is controlled so that the optical packet signal is blocked after passing.

  Alternatively, when applied to a transmitter portion that transmits an optical packet signal, an optical packet signal source that generates an optical packet signal is connected to each of the input ports # 1 to # 8. In this case, information relating to the supply timing of the data signal for generating the optical packet signal at the corresponding optical packet signal source is received, and the trigger signal for the optical gate switch 102a to be derived is the input timing of the packet signal. Control to be almost synchronized.

  Note that in any case where the optical packet switch 100 is mounted, the 1: 8 light is transmitted from the position where the input of the optical packet signal is detected or the optical packet signal source where the optical packet signal is generated. A delay means can be appropriately provided on the optical path to the coupler 101. Thereby, the control of the optical gate switch 102a can be completed before the input of the optical packet signal to the optical gate switch 102a.

  As a result, the optical gate switch 102a is turned on only during a period during which the optical packet signal passes, and is turned off during the other periods to prevent crosstalk and noise light leakage. The path switching can be performed, for example, by turning off (shut-off control) the optical gate switch 102a corresponding to the path before switching and turning on the optical gate switch 102a corresponding to the path after switching.

  Thus, when the optical gate switch 102a between the desired input / output ports and the corresponding downstream SOA 104 are turned on (pass control), the path of the optical packet signal can be set between the input / output ports. For example, when an optical packet signal is set between the input port #i and the output port #j, the SOA 102a having the gate output i-j in the figure passes through the SOA 104 on the downstream side of the SOA 102a (ON). Control to do.

That is, the optical packet signal that has passed through the turned-on optical gate switch 102a is multiplexed by the 8: 1 coupler 103 for each output port and output. The SOA 104 is provided for the output of the 8: 1 coupler 103, for example, in order to compensate for the optical loss in the 8: 1 coupler 103, but may be omitted as appropriate.
In FIG. 1, the loss compensation SOA 104 is provided for each output port, so that the two SOAs 102a, 104 provided on the same path are turned on or off almost simultaneously or simultaneously. At this time, it is possible to process an optical packet signal with finer granularity (short packet length) as the time required for on / off switching is shorter. Furthermore, the faster the switching from on to off or from off to on, the shorter the idle time (guard time) between optical packet signals.

Thus, in the optical packet switch 100 shown in FIG. 1, 8 × 8 + 8 = 72 SOAs 102a and 104 are used. That is, SOAs 102a and 104, which are more switching elements than N × N when the number of ports is N (= 8), are applied.
When switching in the order of nanoseconds is required as in the distribution / merging type optical packet switch 100, the wiring length for supplying drive signals to the plurality of SOAs 102a and 104 responsible for optical gate switching is in millimeters. If they are different, the response characteristics are affected, for example, the switching time is delayed.

  That is, the switching response of the SOAs 102a and 104 is slow due to the influence of time constants determined by the capacitance component (parasitic capacitance) and resistance component of the SOAs 102a and 104 themselves, the inductance L component of the wiring between the drive circuit and the SOA, and the like. May be. Specifically, even when the drive waveform for conducting / blocking light with respect to the SOA is input as an ideal rectangular wave, the waveform of the output light that is a response signal may become dull and the switching response may be delayed.

  A drive circuit that outputs a drive signal to each of the SOAs 102a and 104 is arranged in the immediate vicinity of the corresponding SOA 102a and 104, and the wiring lengths are arranged so as to be equidistant from each other, thereby defining the response characteristics of each SOA 102a and 104. One improvement can be expected. However, when there are many SOAs 102a and 104 and their drive circuits as in the case illustrated in FIG. 1, it is not easy to keep the wiring lengths at a uniform distance. For this reason, it can be said that the response characteristics of each of the SOAs 102a and 104 are substantially different because each wiring length is different and each parasitic capacitance has an individual difference.

  Technology such as pre-emphasis is known as a technique for sharpening the rise of the square wave of the response signal by raising the rise of the drive signal (speeding up the rise response) using a circuit unit, CR circuit, etc. It has been. It can be assumed that the response characteristics of the SOAs 102a and 104 are accelerated by using such a pre-emphasis technique. However, in order to improve the characteristics of the SOAs 102a and 104, the amount of pre-emphasis to be given is individually adjusted. Is required. In the illustrated optical packet switch 100, individual adjustments are required for the SOAs 102a and 104, which are 72 switch elements.

  In order to adjust the amount of pre-emphasis, it is necessary to adjust the element characteristics of the circuit having the function of raising the rectangular wave edge of the drive waveform. Even if the drive waveform is individually adjusted, it is assumed that the characteristics of the SOA that is the switch element may change over time, or that the characteristics may change due to moisture absorption of the drive circuit board. Becomes indispensable. It is desirable to reduce the burden of such individual adjustment as much as possible in order to maintain maintenance and increase the efficiency of the manufacturing process.

Therefore, in the first embodiment, the waveform control device 1 and the response element module 10 shown in FIG. 2 are proposed. The waveform control device 1 monitors the rectangularity of the optical pulse that makes a response output to the driving signal of the SOA 2 that is the response element, controls the driving waveform of the driving signal according to the rectangularity of the monitoring result, and Control rectangularity freely.
That is, by applying the waveform control device 1 shown in FIG. 2 to drive the respective SOAs 102a and 104 shown in FIG. 1 described above, the rectangularity of the optical pulses that form the response outputs of the respective SOAs 102a and 104 is set to the target shape. Can be shaped to have

  When the SOA 2 is applied as an element (reference numerals 102a and 104) of the optical packet switch 100 shown in FIG. 1, the period of the optical pulse output from the SOA 2 is set in the waveform control device 1 for controlling the rectangularity. It needs to be known. For this reason, before the operation of the optical packet switch 100 is started (that is, the input light to the SOA 2 is not input), the waveform control device 1 can shape the rectangularity of the optical pulse.

  The response element module 10 includes the above-described waveform control device 1 and at least one SOA 2 as a response element. A waveform control device 1 shown in FIG. 2 includes a rectangularity identification circuit 3, an arithmetic control circuit 4, and a drive voltage control circuit 5 as an example of the embodiment (hereinafter referred to as an example). The arithmetic control circuit 4 is an example of the trigger signal output unit 106 shown in FIG. That is, in synchronization with the timing when an optical packet that is input light is input to the SOA 2 in operation (see 102a and 104 in FIG. 1), the trigger signal for conducting the input light to the SOA 2 is set to the following rectangularity. Can be supplied through the drive voltage control circuit 5 that has been shaped.

  In the waveform control apparatus 1, when shaping the rectangularity of the output light pulse, spontaneous emission light (ASE light) obtained by driving the SOA 2 with a trigger signal having a fixed period is used for the SOA 2 during non-operation. That is, when a drive signal having a constant on / off cycle generated by the arithmetic control circuit 4 is supplied to the SOA 2 to which no input light is input via the drive voltage control circuit 5, the spontaneous emission light is output from the SOA 2 as a response output. (ASE light) is output.

At this time, the ASE light has an optical pulse intensity fluctuation according to the on / off of the drive signal. That is, when the drive signal is turned on, the ASE light is output, which corresponds to turning on the optical pulse. On the other hand, when the drive signal is turned off, the output light level of the ASE light becomes 0, which corresponds to turning off the optical pulse.
The rectangularity identification circuit 3 is an example of a monitor unit that monitors the waveform of an output pulse obtained by the SOA 2 as a response element in response to a drive signal supplied from a drive voltage control circuit 5 described later. The rectangularity identification circuit 3 identifies the rectangularity of the waveform of the output optical pulse from the SOA 2 by, for example, quantifying the degree to which the waveform of the output optical pulse has a true (ideal) rectangular shape. . As an example, the rectangularity identification circuit 3 includes a harmonic component extraction unit 3a, an average power detection circuit 3b, and an analog / digital (A / D) converter 3c.

  The harmonic component extraction unit 3a extracts even-order or odd-order harmonic components with respect to the frequency (known) of the trigger pulse forming the drive signal included in the output pulse (output optical pulse) from the SOA2. When the high-frequency component extraction unit 3a extracts even-order harmonic components of the trigger pulse, as shown in FIG. 3A, for example, the branching unit 11, the delay unit 12, and the light receiving units 13 and 14 are used. And a combining unit 15.

For example, a 3 dB coupler or the like is applied to the branching unit 11. A part of the output optical pulse output from the SOA 2 is received through the optical branching unit 7 including the optical coupler and the received output optical pulse is branched into two. One branched by the branching unit 11 is connected to the light receiving unit 13, while the other is connected to the light receiving unit 14 via the delay unit 12.
For example, a delay line (optical fiber) interposed between the branching unit 11 and the light receiving unit 14 is applied to the delay unit 12, and light input to the light receiving unit 14 is input from the branching unit 11 to the light receiving unit 13. It is delayed by a predetermined time from the light to be emitted. The delay time is, for example, a time corresponding to a half period of a pulse period of an output pulse from the SOA 2 (or a period of a pulse signal forming a drive signal output from the drive voltage control circuit 5 to the SOA 2).

  The light receiving units 13 and 14 both convert input light into electrical signals (photoelectric conversion), and for example, a photodiode (PD) is applied. That is, the electric signal output from the light receiving units 13 and 14 is an electric pulse signal having an amplitude change corresponding to the output light pulse output from the SOA 2. However, the electrical pulse signal from the light receiving unit 14 that receives the light delayed by the delay unit 12 is delayed by a half cycle time of the pulse period with respect to the electrical pulse signal from the light receiving unit 13.

  The synthesizer 15 synthesizes, ie superimposes, the electric pulse signals output from the light receiving units 13 and 14 described above. In the synthesizer 15, by overlapping electrical pulse signals having a relative delay time difference corresponding to a half cycle time of the pulse period, odd-order harmonic components that are shifted by a half wavelength in the pulse period are canceled with each other. As a result, only the even-order harmonic component remains in the signal after synthesis by the synthesis unit 15. As a result, even harmonic components can be output as the harmonic component extraction unit 3a.

  By the way, Expression (1) is an example of a Fourier class expression of the instantaneous value v (t) at time t of non-sinusoidal alternating current. The ideal rectangular wave v (t) can be derived as an example from the Fourier series expansion expression of Expression (2) from Expression (1). In equations (1) and (2), V is the amplitude, ω is the angular velocity, and ω = 2π / T, where T is the period. The rectangular wave v (t) shown in the equation (2) is v (t) = V when −T / 4 <t <T / 4, and −T / 2 <t <−T / 4, T / When 4 <t <T / 2, v (t) = − V.

  An ideal rectangular wave includes a superposition of odd harmonic components of a pulse period forming a pulse signal. That is, the component of ωt shown in the equation (2) is the first-order wave, and the components of 3ωt, 5ωt, and 7ωt are the third, fifth, and seventh-order harmonics, respectively. As shown in Equation (2), in an ideal rectangular wave, the even-order harmonic components (components of n = 2, 4,...) In Equation (1) are zero.

Therefore, even-order harmonic components (for example, 2ωt and 4ωt components in the Fourier series expansion equation in the equation (1)) extracted by the above-described harmonic component extraction unit 3a have an ideal pulse signal waveform. It can be said that the element is substantially deformed from the rectangular wave shape.
FIG. 4 shows an example of the transmission characteristic (B) as the above-described harmonic component extraction unit 3 a together with an example of the spectrum characteristic (A) included in the pulse signal input from the optical branching unit 7 to the rectangularity identification circuit 3. FIG. As illustrated in FIG. 4, the pulse signal input to the rectangularity identification circuit 3 includes ideal harmonic components A1, A3, A5,. .., Which are components that deform a typical rectangular wave shape, are included. In FIG. 4, the number attached to “A” indicates the order of the harmonic component. In FIG. 4, the horizontal axis represents frequency, and the vertical axis represents amplitude (instantaneous value voltage).

  For example, the harmonic component extraction unit 3a has a transmission frequency band as indicated by a hatched portion B in FIG. In other words, it can have characteristics as a comb filter in which the transmission frequency band (B) and the cut-off frequency band are alternately arranged. As a result, the even-order harmonic components A2, A4, A6,... Can be transmitted while the odd-order harmonic components A1, A3, A5,.

5 (a) to 5 (e), for example, by changing the coefficient of the even-order harmonic component in Equation (1), the even-order harmonic component is included with respect to the odd-order harmonic component of the pulse period. It is an example of the simulation result of the pulse signal waveform at the time of changing a ratio.
Here, FIG.5 (c) is an example of the simulation result at the time of superimposing the odd-order harmonic component except the even-order harmonic component among the harmonic components from 1st to 199th order. FIG. 5A shows the case where the superposition of the odd-order harmonic components of the first to 199th-order harmonic components and the even-order harmonic components of the first ratio are superposed in the same phase. It is an example of the simulation result. FIG. 5B shows an example of a simulation result in the case where the even-order harmonic components of the second ratio smaller than the first ratio are superimposed in the same phase on the superposition of the odd-order harmonic components.

  On the other hand, FIG. 5 (d) shows an example of the simulation result when the above-mentioned first-order even-order harmonic component is superimposed with the odd-order harmonic component in the opposite phase to the odd-order harmonic component. It is. FIG. 5E shows an example of a simulation result when the above-mentioned second-order even-order harmonic component is superimposed with the odd-order harmonic component in the opposite phase to the odd-order harmonic component.

  That is, in the case of superimposing odd-order harmonic components of the pulse period forming the pulse signal, as shown in the simulation result of FIG. On the other hand, as shown in FIGS. 5 (a), 5 (b), 5 (d), and 5 (e), the pulse signal waveform becomes ideal as the proportion of even-order harmonic components increases. The degree of deformation from a rectangular wave shape increases.

  The average power detection circuit 3b, which is an element of the rectangularity identification circuit 3, is an example of a power monitoring unit that monitors the power of even-order or odd-order harmonic components extracted by the harmonic component extraction unit 3a. In the average power detection circuit 3b in the first embodiment, the power (average power) of the even-order harmonic component extracted by the harmonic component extraction unit 3a is detected. In the A / D converter 3 c, the average power value detected by the average power detection circuit 3 b is converted from an analog signal to a digital signal and output to the arithmetic control circuit 4.

  Thereby, the rectangularity identifying circuit 3 outputs the magnitude of the even-order harmonic component, which is an element deformed from the ideal rectangular wave shape in the output light pulse, as the monitoring result. In this case, when the power of the even-order harmonic component included in the output light pulse is minimum, a substantially ideal rectangular wave shape can be obtained as the waveform of the output light pulse.

  In FIG. 3A described above, the light receiving units 13 and 14 for photoelectrically converting the branched light are provided in the subsequent stage of the light branching in the branching unit 11. As another example, for example, as shown in FIG. 3B, the light receiving unit 19 may be provided in the preceding stage of the function as the branching unit 11. In this case, the branching unit 11 'branches the electric pulse signal from the light receiving unit 19 into two branches, and the delay unit 12' has a delay time difference equivalent to that described above for the electric pulse signal from the branching unit 11 '. give. Thereby, in the synthesis | combining part 15, the harmonic component of the even order similar to the case of Fig.3 (a) can be output.

Further, in the case where pulse signals having a delay time difference as shown in FIG. 3A and FIG. 3B are overlapped by the combining unit 15, on the input side of the combining unit 15 to match the level of each input pulse signal. You may make it interpose an amplifier etc. suitably.
Further, the harmonic component extraction unit 3a may extract odd-order harmonic components, and the rectangularity identification circuit 3 may output the power information (digital signal) as a monitoring result. In this case, the harmonic component extraction unit 3a passes the odd-order harmonic components A1, A3, A5,... Shown in FIG. 4 and blocks the even-order harmonic components A2, A4,. As a comb filter. The odd harmonic component is an element that forms an ideal rectangularity shape in the output pulse. Therefore, if the power of the odd-order harmonic component detected by the average power detection circuit 3b is maximized, an almost ideal rectangular wave shape can be obtained as the waveform of the output light pulse.

FIG. 3C is an example of a harmonic component extraction unit 3a that extracts odd-order harmonic components of the trigger pulse. The harmonic component extraction unit 3a shown in FIG. 3C includes a branching unit 11, a delay unit 12, light receiving units 13, 14, a combining unit 15, a light receiving unit 16, a phase adjusting circuit 17, and a subtracting unit 18.
Unlike the one shown in FIG. 3A described above, the branching unit 11 equally divides the power of the output optical pulse received through the optical branching unit 7 into three parts. Lead. The delay unit 12, the light receiving units 13 and 14, and the combining unit 15 are basically the same as those shown in FIG. That is, the synthesis unit 15 can output even-order harmonic components of the output light pulse.

  In addition, the light receiving unit 16 converts the input light, that is, one of the output light pulses divided into three by the branching unit 11 into an electric signal (photoelectric conversion), and outputs the electric signal to the subtracting unit 18. The phase adjustment circuit 17 adjusts the phase of the even-order harmonic component signal from the synthesizing unit 15, and the even-order harmonic component included in the electrical pulse signal from the light receiving unit 16 input to the subtracting unit 18. Match the phase.

Further, the subtracting unit 18 subtracts the even-order harmonic component from the synthesizing unit 15 from the electric pulse signal from the light receiving unit 16 and extracts the odd-order harmonic component that is the remaining component after the subtraction. Thereby, the harmonic component extraction part 3a shown in FIG.3 (c) can extract the odd-order harmonic component of a trigger pulse.
In addition, in what is branched into 3 in the branch part 11 shown in the above-mentioned FIG.3 (c), it is good also as applying 3 branch paths in the branch element branched into 4 branches. Moreover, the amplitude of each electric signal output from the light receiving units 13, 14, and 16 is matched by appropriately using an amplifier or an attenuator that adjusts the amplitude of the electric signal output from the light receiving units 13, 14, and 16. You can also.

The arithmetic control circuit 4 and the drive voltage control circuit 5 correspond to an example of a drive waveform shaping unit that cooperates with each other to shape the waveform of the drive signal based on the monitoring result of the monitor unit 3. That is, the drive waveform shaping sections 4 and 5 shape the waveform of the drive pulse signal so that the power monitored by the rectangularity identification circuit 3 is at a predetermined level or a predetermined range.
For example, when the average power detection circuit 3b outputs the power of even harmonic components as a monitoring result, the waveform of the drive pulse signal is shaped with the control target being the minimum monitored power. To do. When the power of odd harmonic components is output as a monitoring result by the average power detection circuit 3b, the waveform of the drive pulse signal is shaped with the control target being the maximum monitored power. To do.

  Here, the arithmetic control circuit 4 is composed of, for example, a digital arithmetic element, and supplies a trigger signal for turning on / off the gate to the gate switch driving circuit 5c which is an element of the driving voltage control circuit 5. The arithmetic control circuit 4 outputs a control signal for controlling the waveform of the optical pulse in the SOA 2 as a digital signal based on the monitor result input as a digital signal from the rectangularity identification circuit 3.

  The drive voltage control circuit 5 generates a drive pulse signal based on the pulse signal for gate on / off from the arithmetic control circuit 4 and supplies it to the SOA 2. At this time, the drive voltage control circuit 5 shapes the waveform of the drive pulse signal to be output based on the control signal for controlling the optical pulse waveform output by the SOA 2. As an example, the drive voltage control circuit 5 includes a D / A converter 5a, a rectangularity shaping circuit 5b, and a gate switch drive circuit 5c shown in FIG.

The D / A converter 5a converts a control signal input as a digital signal from the arithmetic control circuit 4 into an analog signal. Based on the control signal from the D / A converter 5a, the rectangularity shaping circuit 5b generates a control signal to the variable capacitor 16a (see FIG. 6) that is an element of the gate switch drive circuit 5c.
The gate switch drive circuit 5c generates a drive pulse signal (drive signal) based on a trigger signal for gate on / off from the arithmetic control circuit 4, and the waveform of the drive pulse signal generated here is a rectangularity shaping circuit. It is shaped based on the control signal from 5b. In other words, the gate switch drive circuit 5c is an example of a drive circuit unit that shapes the waveform of the drive signal to the SOA 2 that is a response element based on the control signal, and the arithmetic control circuit 4 is provided in the monitor unit 3. It is an example of the control part which outputs a control signal to the drive circuit part 5c based on the monitoring result (via the rectangularity shaping circuit 5b).

  FIG. 6 shows an example of the gate switch drive circuit 5c. The switch drive circuit 5c shown in FIG. 6 includes a circuit unit 16 including a variable capacitance element 16a and resistors 16b and 16c, and a driver amplifier (Driver AMP) 17. Here, the trigger signal from the arithmetic control circuit 4 is amplified by the driver amplifier 17 via the circuit unit 16, and is output to the SOA 2 as a drive pulse signal.

  The variable capacitance element 16a forming the circuit unit 16 is an element whose capacitance is varied according to the value of the control signal from the rectangularity shaping circuit 5b. The varicap is an example of the variable capacitor 16a. In this case, the varicap voltage control circuit that varies the voltage (varicap voltage) to be applied as the control signal to the varicap 16a in accordance with the control signal from the arithmetic control circuit 4 is an example of the rectangularity shaping circuit 5b. is there.

When the capacitance of the variable capacitive element 16a is varied through the control signal from the rectangularity shaping circuit 5b, the response time constant of the circuit unit 16 is varied, so that the drive pulse signal from the gate switch drive circuit 5c rises and falls. The waveform is shaped. Assuming that the capacitance C ₁₂ of the variable capacitance element 16a and the resistance values of the resistors 16b and 16c are fixed values R ₂₁ and R ₂₃ , respectively, the response time constant τ ₁ of the circuit unit 16 is expressed by Expression (3). Therefore, when the capacitance C ₁₂ is increased, the response time constant τ ₁ is increased, and when the capacitance C ₁₂ is decreased, the response time constant τ ₁ is decreased.

In the variable capacitance element 16a as a varicap, for example, the control voltage signal from the rectangularity shaping circuit 5b decreases as the capacitance C ₁₂ is increased, the capacitance C ₁₂ when the control voltage signal from the rectangularity shaping circuit 5b becomes larger The relationship can be reduced. Thereby, the response time constant of the circuit unit 16 constituting the gate switch drive circuit 5c can be varied through the control voltage signal generated by the control signal from the arithmetic control circuit 4. In other words, the arithmetic control circuit 4 controls the response time constant of the circuit unit 16 by controlling the capacitance of the variable capacitance element 16a, and thereby the waveform of the drive pulse signal output from the gate switch drive circuit 5c. Can be controlled.

FIG. 7A to FIG. 7C show examples of rising waveforms of the drive pulse signal and the optical pulse in accordance with the capacity of the variable capacitor 16a (or the control voltage signal (applied voltage)). FIG. FIG. 7A shows a case where the value of the control voltage signal is made relatively small and the capacity C ₁₂ is made relatively large. FIG. 7C shows that the control voltage signal is made relatively large and the capacity C ₁₂ is made relatively large. a case where a relatively small _12, (b) in FIG. 7 is a case where a value between when the control voltage signal and the capacitance C ₁₂ of FIG. 7 described above (b) and 7 (c) .

That is, as shown in FIG. 7 (a), the response time constant and increasing the capacity C ₁₂ increases. For this reason, the drive pulse signal A1 from the gate switch drive circuit 5c rises sharply, its transient rise width W1 becomes large, and the time until it settles to a constant value becomes relatively long. Further, since the SOA 2 is driven by the drive pulse signal A1 whose rise width is thus increased, the rise width of the output optical pulse A2 is also increased.

In contrast, as shown in FIG. 7 (c), the response time constant and to reduce the capacity C ₁₂ is reduced. For this reason, the drive pulse signal C1 from the gate switch drive circuit 5c rises dull, its transient rise width W3 becomes small, and the time until it settles to a constant value becomes relatively short. Further, since the SOA 2 is driven by the drive pulse signal C1 whose rise is slow as described above, the rise of the output optical pulse C2 is also slow.

7 (b) is a control voltage signal and the capacitor C ₁₂ is set to a value between the time of the above-described FIGS. 7 (a) and 7 (c). In this case, the rising characteristic of the drive pulse signal B1 has a sharpness between the rising characteristics of A1 and C1 described above, and its transient rising width W2 is a value between W1 and W3, which is a constant value. The time to settle is also a value between the time of FIG. 7 (a) and FIG. 7 (c). Note that the optical pulse from the SOA 2 driven by the drive pulse signal B1 has a rise close to a true (ideal) rectangular wave shape.

In the arithmetic control circuit 4, based on the monitoring result of the optical pulse waveform from the rectangularity identification circuit 3, the optical pulse waveform output from the SOA 2 is subjected to feedback control through the rectangularity shaping circuit 5b and the gate switch drive circuit 5c. I have control. FIG. 8A to FIG. 8C are the even numbers extracted by the harmonic component extraction unit 3a according to the value of the control voltage signal (or the capacitance C _{12 at} that time) to the variable capacitance element 16a described above. It is an example of the signal waveform of a second harmonic component, and the waveform of the optical pulse output from SOA2.

  As illustrated in FIG. 8A, when the optical pulse a1 rises steeply, the even-order harmonic component signal b1 extracted by the harmonic component extraction unit 3a includes a portion having a relatively large amplitude. . Further, as illustrated in FIG. 8C, even when the rise of the optical pulse a3 is dull, the even-order harmonic component signal b3 extracted by the harmonic component extraction unit 3a also has a relatively large amplitude. Including For this reason, in both the cases of FIGS. 8A and 8C, the even-order harmonic component power detected by the power detection circuit 3b is relatively large.

On the other hand, as illustrated in FIG. 8B, when the optical pulse a2 has a waveform close to a true (ideal) rectangular wave shape, the harmonic component extraction unit 3a extracts the pulse. The even-order harmonic component b2 has a relatively small amplitude. In this case, the power of the even-order harmonic component detected by the power detection circuit 3b is smaller than in the case of FIGS. 8 (a) and 8 (c).
Therefore, in the arithmetic control circuit 4, as an example, the control signal is subjected to the rectangularity shaping so that the power of the even-order harmonic component, which is the monitoring result from the rectangularity identifying circuit 3, falls within the minimum range including the minimum or constant error. Output to the circuit 5b. As a result, the waveform of the output light pulse can be maintained, for example, the waveform B2 of FIG. 7B. As described above, when the even-order harmonic components included in the output light pulse are minimized, the waveform of the light pulse has an ideal rectangular wave shape that is a superposition of odd-order harmonic components. Because it comes to have almost.

  As described above, the light output from the SOA 2 by controlling the capacitance of the variable capacitance element 16a via the rectangularity shaping circuit 5b based on the even-order harmonic component power from the rectangularity identification circuit 3 in the arithmetic control circuit 4. The pulse waveform keeps a predetermined waveform. The arithmetic control circuit 4 can store a control amount of a control signal (for example, a control signal to the rectangularity shaping circuit 5b) when a predetermined waveform is maintained. As a result, when the SOA 2 is actually operated as a gate switch, the output optical waveform can be set to an intended waveform without performing feedback control.

Further, the waveform of the optical pulse that is the control target may be a true rectangular wave shape as illustrated, or may be a rectangular waveform with a large rising width such as A2 in FIG. It can also be a rectangular waveform with a slow rise like C2 in (c).
FIG. 9 is a diagram showing a gate switch drive circuit 5c ′ which is a modification of the gate switch drive circuit 5c shown in FIG. The gate switch drive circuit 5c ′ is another example of the drive circuit unit that shapes the waveform of the drive signal to the SOA 2 that is the response element based on the control signal, and is the driver amplifier similar to the case of FIG. 17 is provided. The circuit unit 18 includes resistors 18a and 18b and an inductor element 18c whose inductance can be changed by a control signal from the rectangularity shaping circuit 5b.

When the inductance of the variable inductor element 18c is varied through the control signal from the rectangularity shaping circuit 5b, the response time constant of the circuit unit 18 is varied. For this reason, the rising and falling waveforms of the drive pulse signal output from the gate switch drive circuit 5c are shaped. Assuming that the inductance of the variable inductor element 18c is L ₁ and the resistance values of the resistors 18a and 18b are fixed values R ₁₁ and R ₁₃ , respectively, the response time constant τ ₂ of the circuit unit 18 is expressed by Expression (4). Therefore, when the inductance L ₁ is increased, the response time constant τ ₂ is increased, and when the inductance L ₁ is decreased, the response time constant τ ₂ is decreased.

In other words, the arithmetic control circuit 4 controls the response time constant of the circuit unit 18 by controlling the inductance of the variable inductor element 18c via the rectangularity shaping circuit 5b, and is output from the gate switch drive circuit 5c. The waveform of the driving pulse signal can be controlled.
Next, an operation example of the waveform control device 1 or the response element module 10 as described above will be described.

  For example, the waveform control apparatus 1 is used when adjusting the SOAs 102a and 104 as response elements applied as elements of the optical packet switch 100 in the previous stage of starting the operation of the optical packet switch 100 shown in FIG. Alternatively, in the response element module 10 having the SOA 2 applied as the SOAs 102a and 104, the drive pulse waveform to the SOA 2 is shaped.

  The drive voltage control circuit 5 supplies an output pulse from the SOA 2 by supplying a drive signal to the SOA 2. At this time, the input light to the SOA 2 is non-input, and the ASE light that is repeatedly output / non-output by turning on / off the drive signal supplied from the drive voltage control circuit 5 is an output pulse output from the SOA 2. Note that the on / off cycle of the drive signal, that is, the pulse cycle as the drive pulse signal is derived from the cycle of the trigger signal from the calculation control circuit 4 and is known in the calculation control circuit 5.

  The rectangularity identifying circuit 3 monitors the waveform of the output pulse output from the SOA 2 and identifies the rectangularity or the sharpness of the rising edge. For example, the harmonic component extraction unit 3a extracts even-order harmonic components in the pulse period of the output optical pulse output from the SOA 2, and the power detection circuit 3b detects the power of the extracted even-order harmonic components. To do.

  The arithmetic control circuit 4 receives the detected power of the even harmonic component as a digital signal via the A / D converter 3c. Then, the arithmetic control circuit 4 and the drive voltage control circuit 5 cooperate with each other based on the received power of the even harmonic component, and the power is a target value (for example, a minimum or a minimum range including a predetermined error). ) To control the waveform of the drive pulse signal to the SOA 2 so as to match or approach.

  Specifically, in the arithmetic control circuit 4, the capacitance of the variable capacitance element 16a of the circuit unit 16 (see FIG. 6) constituting the gate switch drive circuit 5c is varied by passing through the rectangularity shaping circuit 5b, so that the SOA2 To shape the waveform of the drive pulse signal. Alternatively, the sharpness of the rising edge of the drive pulse signal to the SOA 2 is shaped by changing the capacitance of the variable inductor element 18 c of the circuit unit 18 (see FIG. 9) forming the gate switch drive circuit 5 c ′.

The SOA 2 is driven by the drive pulse signal described above and outputs an output pulse. For this reason, the arithmetic control circuit 4 controls the waveform of the drive pulse signal output from the gate switch drive circuit 5c via the rectangularity shaping circuit 5b, whereby the rectangularity of the waveform of the output pulse output from the SOA 2 is controlled. Will be able to control.
When the drive pulse signal as the control target can be obtained as described above, the calculation control circuit 4 stores the control amount of the control signal for the rectangularity shaping circuit 5b at that time. Also good. In this way, when the operation is shifted to actual operation, the gate switch drive circuit 5c can be controlled through the rectangularity shaping circuit 5b with the fixed control amount stored in the arithmetic control circuit 4.

  In actual operation, a trigger signal is input from the arithmetic control circuit 4 to the gate switch drive circuit 5c in accordance with the timing at which the input light should be conducted / blocked, so that the frequency of the trigger signal is constant. Not exclusively. However, in the arithmetic control circuit 4, the rising waveform of the output light from the SOA 2 can be set to the initial shape by controlling the rectangularity shaping circuit 5b with the stored control amount. Even after actual operation, in the state where the input light to be turned on / off is not input, the above-described feedback can be appropriately used as necessary.

Thus, according to the first embodiment, there is an advantage that a pulse having a target rectangularity can be generated by simple waveform shaping.
In the first embodiment described above, the rectangularity of the optical pulse is shaped by monitoring the optical pulse including the ASE light output from the SOA 2. In addition, it is good also as shaping using the input signal from the outside, for example, the input light used as the object of conduction | electrical_connection when SOA2 is applied as an optical gate switch. In this case, by setting the frequency of the trigger signal output from the arithmetic control circuit 4 to a known constant frequency, the frequency extraction characteristic of the harmonic component extraction unit 3a forming the rectangularity identification circuit 3 is set to the constant frequency. It becomes possible to decide based on.

[B] Second Embodiment FIG. 10 is a diagram showing a waveform control device 1A or a response element module 10A according to a second embodiment. In the second embodiment, as compared with the first embodiment, a rectangularity identifying circuit 3A having different elements is provided, and an arithmetic control circuit 4A having a different control mode is provided. In addition, the above-mentioned code | symbol shows a substantially similar part. That is, the waveform control device 1A includes a rectangularity identification circuit 3A and an arithmetic control circuit 4A, and also includes a drive voltage control circuit 5 similar to that in the first embodiment, and the response element module 10A includes the above-described waveform control device. SOA2 is provided with the element as 1A.

  The rectangularity identification circuit 3A is an example of a monitor unit that monitors the waveform of an output pulse obtained by the SOA 2 in response to a drive signal supplied to the SOA 2 that is a response element. In the second embodiment, the light receiving unit 3d and a high-speed A / D converter 3e. The light receiving unit 3d receives the light output from the SOA 2 via the optical coupler 7, and converts the light into an electrical signal such as a voltage signal having an amplitude change corresponding to the amplitude change as an optical pulse. The photodiode (PD) and the transimpedance amplifier cooperate to correspond to an example of the light receiving unit 3d.

The high-speed A / D converter 3e is an example of a sampling unit that samples the waveform of the output pulse, and samples an electrical signal from the light receiving unit 3d at high speed. In the high-speed A / D converter 3e, in order to sample the amplitude change according to the light pulse, it is necessary to sample a plurality of response waveforms when the SOA 2 is switched on and off.
For this reason, as the high-speed A / D converter 3e, for example, a high-speed A / D converter 3e having a sampling period of about 5 to 10 times the on / off switching speed of the SOA 2 is used. For example, when an optical gate switch having a performance of performing switching in 10 nanoseconds is used, one having a sampling period of 1 to 2 nanoseconds which is 5 to 10 times faster than that is used. That is, a high-speed A / D converter 3e having a sampling period of 500 Msps to 1 Gsps or more is used.

  The arithmetic control circuit 4A corresponds to an example of a drive waveform shaping unit that cooperates with the drive voltage control circuit 5 to shape the waveform of the drive signal to the SOA 2 based on the sampling result in the sampling unit 3e. Specifically, the arithmetic control circuit 4A outputs a trigger signal having a constant frequency to the gate switch driving circuit 5c, while performing an operation using the output from the high-speed A / D converter 3e, and based on the calculation result, A control signal is output to the rectangularity shaping circuit 5b. As described above, the control signal to the rectangularity shaping circuit 5b changes the circuit time constant of the circuit unit 16 or the circuit unit 18 (see FIG. 6 or 9) forming the gate switch drive circuit 5c (5c ′). Control signal.

  As an example, in the arithmetic control circuit 4A, in the high-speed A / D converter 3e, a variation index of a value sampled in the rising region of the output pulse is derived by, for example, computation such as dispersion, and a control signal corresponding to the derived result is obtained. Output to the rectangularity shaping circuit 5b. For example, in the arithmetic control circuit 4A, when the control amount of the control signal to the rectangularity shaping circuit 5b is controlled so that the calculated variance is minimized, the waveform of the output pulse output from the SOA 2 is different from that of the control signal. Compared to the case of the control amount, it is closest to a true (ideal) rectangular wave shape.

  FIG. 11 is a flowchart for explaining an operation example of the waveform control device 1A focusing on the processing of the arithmetic control circuit 4A. First, a control signal for initially setting a control amount in the rectangularity shaping circuit 5b is output from the arithmetic control circuit 4A to the rectangularity shaping circuit 5b. When the circuit unit 16 having the variable capacitance element 16a as the varicap shown in FIG. 6 is applied as an element of the gate switch drive circuit 5c, the control voltage signal to the varicap 16a is set to the initial value Vk = Vb. The control signal to be output is output to the rectangularity shaping circuit 5b (step A1).

Next, the arithmetic control circuit 4A generates a trigger signal for on / off control of the ASE light output from the SOA 2, and supplies it to the gate switch drive circuit 5c. Thereby, the SOA 2 can output an output light pulse (for example, ASE light) having a rising waveform corresponding to the initial value of the varicap voltage (step A2).
Then, the sampling result for a certain time of the output light pulse output from the SOA 2 is received from the high-speed A / D converter 3e. As an example, the arithmetic control circuit 4A receives a sampling result for a time of an integer multiple of 1 or more of a known trigger signal from the high-speed A / D converter 3e, and provides a storage area in a memory or the like, for example. (Step A3).

Further, an average value X (= sampling total value / sampling number) is calculated for the sampling result of the predetermined time held in the storage area (step A4).
Next, sample points exceeding the calculated average value X are extracted from the sampling results of the predetermined time held in the storage area, and the leading N sample standard deviation σ in the time series of the extracted sample points is extracted. Is calculated (step A5). As the first N samples, as shown in FIG. 12, the number of sample points in the time range R1 in which the rising waveform of the output optical pulse appears varies according to the capacitance value of the variable capacitance element 16a. it can.

  The standard deviation σ calculated as described above is stored in a storage area (not shown) in association with the set voltage signal Vk (step A6). Thereafter, the voltage signal from the rectangularity shaping circuit 5b is changed with the unit step width ΔV over the control range (Vb to Vend) (Vk = Vk + ΔV). Then, the standard deviation is calculated as described above based on the respective sampling results (step A8, step A3 to step A6 from the No route of step A7).

  When the calculation of the value of the standard deviation over the control range is completed, that is, when Vk ≧ Vend in Step A7 (Yes route of Step A7), the value of the voltage signal having the standard deviation serving as the target point is A search is made with reference to the storage area described above (step A9). That is, the voltage signal value at which the standard deviation σ becomes the target value (for example, the minimum standard deviation) is searched from the relationship of the standard deviation value according to the voltage signal value in the rectangularity shaping circuit 5b held in the storage area. To do.

The voltage signal value searched in this way is set as the optimum voltage signal value Vopt. In other words, in the arithmetic control circuit 4A, by outputting a control signal, the voltage signal supplied from the rectangularity shaping circuit 5b to the varicap 16a of the gate switch driving circuit 5c is set to Vopt (step A10).
When the rising edge is closest to the true square wave shape, the standard deviation σ has the smallest variation, and thus takes the minimum value. Therefore, as illustrated, the rectangularity of the pulse is controlled through the control signal to the rectangularity shaping circuit 5b so that the calculated standard deviation σ is minimized. In this way, the waveform of the output light pulse can be brought closer to a rectangular wave shape as compared with the output light pulse having another standard deviation.

Thus, also in the second embodiment, there is an advantage that a pulse having a target rectangularity can be generated by simple waveform shaping.
In the above case, the standard deviation is calculated for the sample point for the range where the fluctuation in the rising waveform of the output light pulse appears, but the standard deviation is calculated for the sample point for the range where the fluctuation in the falling waveform appears. May be. In this case, the standard deviation σ may be calculated for the first N samples of sample points below the average value X after calculating the average value X in the same manner as in step A4 described above.

[C] Third Embodiment FIG. 13 is a diagram showing a waveform control device 1B or a response element module 10B according to a second embodiment. In the third embodiment, compared to the first and second embodiments described above, a rectangularity identification circuit 3B having different elements is provided, and an arithmetic control circuit 4B having a different control mode is provided. In addition, the above-mentioned code | symbol shows a substantially similar part. That is, the waveform control device 1B includes a rectangularity identification circuit 3B and an arithmetic control circuit 4B, and also includes a drive voltage control circuit 5 similar to that of the first and second embodiments, and the response element module 10B includes the above-described response element module 10B. The SOA 2 is provided together with the elements as the waveform control device 1B.

  The rectangularity identification circuit 3B is an example of a monitor unit that monitors the waveform of an output pulse obtained by the SOA 2 responding to a drive signal supplied to the SOA 2 that is a response element. In the rectangularity identification circuit 3B of the third embodiment, the light receiving unit 3d, the AC coupling unit 3f, the level adjustment unit 3g, the edge detection circuit 3h, the peak hold circuit 3i, the sample hold circuit 3j, and the two A / D converters 3m, 3n is provided. The light receiving unit 3d is the same as that in the second embodiment.

The AC (Alternating Current) coupling unit 3f cuts a DC component of the electrical signal from the light receiving unit 3d by AC coupling and outputs the cut signal component to the edge detection circuit 3h. Further, the level adjusting unit 3g includes an amplifier for adjusting the level of the electrical output from the light receiving unit 3d, and outputs it to the peak hold circuit 3i and the sample hold circuit 3j, respectively.
The edge detection circuit (edge detection unit) 3h receives an output pulse from which a DC component has been removed as an electric signal from the AC coupling unit 3f, and detects a rising edge and a falling edge in the waveform of the output pulse.

  The peak hold circuit (peak hold unit) 3i holds the value of the rising peak level in response to the rising edge of the drive signal in the waveform of the output pulse based on the detection of the rising edge by the edge detection circuit 3h. Specifically, with the detection of the rising edge detected by the edge detection circuit 3h as a trigger, the peak of the output pulse from the level adjustment unit 3g with respect to the time required to detect the rising peak level from the switching time of the SOA 2 Holds the value (maximum value).

  The time required to detect the rising peak level can be determined as shown in FIG. 14, for example. That is, it can be set to the time T1 from the start of receiving the trigger signal by the detection of the rising edge in the edge detection circuit 3h (time T11) to the predetermined time T12 when the rising starts to converge. Thereby, in the peak hold circuit 3i, as shown in FIG. 14, the rising peak levels P1, P2 according to the rising waveforms W1, W2, W3 that differ depending on the capacitance of the variable capacitor 16a (see FIG. 6). , P3 can be obtained.

Note that because of the above-described peak hold operation in the peak hold circuit 3i, the peak hold circuit 3i or the edge detection circuit 3h can have a time management function for the above-described T1.
Alternatively, the peak hold circuit 3i starts the peak hold upon receiving the trigger signal from the edge detection circuit 3h by the rising edge detection, and continues the peak hold until the trigger signal by the falling edge detection from the edge detection circuit 3h is received. It is good to do.

Further, the sample hold circuit (sample hold unit) 3j detects the rising edge by the edge detection circuit 3h, and outputs the level of the output pulse that is the response waveform level corresponding to the flat area before the drive signal falls. Sample and hold the value.
Specifically, the level value S is sampled and held at a time when the level of the output pulse is stabilized before the falling after a predetermined time has elapsed from the detection of the rising edge detected by the edge detection circuit 3h.

  For example, as shown in FIG. 14, the sample-and-hold circuit 3j receives the trigger signal from the detection of the rising edge (T11), and after the time T2 has elapsed, the level is stabilized (time immediately before the falling) T3. Sample and hold the level value of the output pulse. Because of the above sample and hold operation in the sample and hold circuit 3j, the sample and hold circuit 3j or the edge detection circuit 3h can have a time management function for the above T2 and T3.

  The output pulse input to the rectangularity identification circuit 3B has an on / off cycle corresponding to the trigger signal output from the arithmetic control circuit 4B. Therefore, also in the sample hold circuit 3j, the ON time from the rising edge to the falling edge of the output pulse is fixed. Therefore, in the sample hold circuit 3j or the edge detection circuit 3h, the above-described times T2 and T3 can be set according to the value of the on-time.

  The A / D converter 3m converts the analog signal indicating the value of the rising peak level from the peak hold circuit 3i into a digital signal and outputs the digital signal to the arithmetic control circuit 4B. The A / D converter 3n converts an analog signal indicating the value sampled and held in the sample and hold circuit 3j into a digital signal and outputs the digital signal to the arithmetic control circuit 4B.

The arithmetic control circuit 4B cooperates with the drive voltage control circuit 5 to receive the value held by the peak hold circuit 3i and the value sampled and held by the sample hold circuit 3j as a monitor result, and based on the monitor result, the drive signal This corresponds to an example of a drive waveform variable unit that shapes the waveform.
Specifically, the arithmetic control circuit 4B outputs a trigger signal having a constant frequency to the gate switch driving circuit 5c, and performs an arithmetic operation using each output from the A / D converters 3m and 3n, and based on the arithmetic result. And outputs a control signal to the rectangularity shaping circuit 5b. As described above, the control signal to the rectangularity shaping circuit 5b is a response of the circuit 16 (or 18) through the control of the capacitance of the variable capacitance element 16a shown in FIG. 6 (or the inductance of the variable inductor element 18c shown in FIG. 9). This is a control signal for changing the time constant.

  As an example, the peak hold value from the A / D converter 3m is used as the rising amplitude value, and the difference between the two is calculated using the sample hold value from the A / D converter 3n as the falling amplitude value. The control amount by the control signal to the above-described rectangularity shaping circuit 5b is controlled according to the difference value thus calculated. For example, when the control amount by the control signal to the rectangularity shaping circuit 5b is controlled so that the calculated difference value is minimized, the waveform of the output pulse output from the SOA 2 is that the control signal is another control amount. Compared to the case, it is closest to a true (ideal) rectangular wave shape.

  FIG. 15 is a flowchart for explaining an operation example of the waveform control device 1B focusing on the processing of the arithmetic control circuit 4B. In this operation example, the waveform control device 1B is applied to the optical packet switch 100 shown in FIG. 1 so that the drive signals (or output optical pulse waveforms) for the plurality of SOAs 102a and 104 have an ideal rectangular wave shape. It is shaping sequentially. Further, a circuit section 16 shown in FIG. 6 is applied as the gate switch driving circuit 5c, and a varicap is applied as the variable capacitance element 16a.

  First, a control signal for initially setting a control amount in the rectangularity shaping circuit 5b is output from the arithmetic control circuit 4B to the rectangularity shaping circuit 5b. When the circuit unit 16 having the variable capacitance element 16a as the varicap shown in FIG. 6 is applied to the element of the gate switch drive circuit 5c, the control voltage signal to the varicap 16a is set to the initial value α. A signal is output (step B1).

Next, the arithmetic control circuit 4B generates a trigger signal for on / off control of the ASE light output from the SOA 2, and supplies it to the gate switch drive circuit 5c. Thereby, the SOA 2 can output an output light pulse (for example, ASE light) having a rising waveform corresponding to the initial value of the varicap voltage (step B2).
Then, the edge detection circuit 3h detects the rising and falling edges of the output pulse from the output pulse input from the light receiving unit 3d via the AC coupling unit 3f (step B3). In this case, the edge detection circuit 3h outputs a trigger signal to that effect to the peak hold circuit 3i and the sample hold circuit 3j when an edge is detected.

  Further, the peak hold circuit 3i is activated for a certain time at the rising timing of the output pulse by the trigger signal corresponding to the rising edge from the edge detection circuit 3h. The peak hold circuit 3i holds the peak value (maximum value) of the rising waveform (step B4). Further, the A / D converter 3m reads the peak value held by the peak hold circuit 3i, and outputs this to the arithmetic control circuit 4B as the rising amplitude Vr (step B5).

  In the sample hold circuit 3j, the level value S is sampled and held at a time when the level of the output pulse is stabilized before the falling after a predetermined time has elapsed from the detection of the rising edge detected by the edge detecting circuit 3h (step S3). B6). Further, the A / D converter 3n reads the peak value held by the sample hold circuit 3j, and outputs this to the arithmetic control circuit 4B as the fall amplitude Vf (step B7).

  The arithmetic control circuit 4B compares the rising amplitude value Vr and the falling amplitude value Vf from the A / D converters 3m and 3n. When the difference between the two is equal to or greater than a certain value D, the waveform of the output pulse output from the SOA 2 has collapsed from the ideal rectangular wave shape, so that the rectangularity is close to the ideal rectangular wave shape. The control amount of the control signal to the shaping circuit 5b is changed (Yes route in step B8).

  Specifically, when the rising amplitude Vr is larger than the falling amplitude Vf (Yes route of step B9), the edge is too sharp, that is, the rising is steep from the ideal rectangularity. For this reason, the rising waveform is blunted by raising the varicap voltage from the rectangularity shaping circuit 5b by ΔV through the control signal from the arithmetic control circuit 4B to the rectangularity shaping circuit 5b (step B10).

  Further, when the rising amplitude Vr is equal to or lower than the falling amplitude Vf (No route of Step B9), the edge is excessively rounded, that is, the rising is dull from an ideal rectangularity. Therefore, the rising waveform is sharpened by lowering the varicap voltage from the rectangularity shaping circuit 5b by ΔV through the control signal from the arithmetic control circuit 4B to the rectangularity shaping circuit 5b (step B11).

The arithmetic control circuit 4B repeats the control for changing the varicap voltage as described above until the difference between the rising amplitude value Vr and the falling amplitude value Vf becomes smaller than D (from step B10, B11 to step B3).
When the difference between Vr and Vf becomes smaller than the constant value D through the control of the varicap voltage from the rectangularity shaping circuit 5b, the SOA 2 (SOA 102a, 104) for which the drive signal is adjusted is adjusted. The adjustment of the drive signal ends. In this way, the drive signals are sequentially adjusted for all the SOAs 102a and 104 to be measured (step B12).

  When the adjustment of the drive signals for all the SOAs is completed, the actual operation as an apparatus can be started. For example, when the adjustment of the drive signals for all the SOAs 102a and 104 constituting the optical packet switch 100 of FIG. 1 is completed, the optical packet switch 100 can be actually operated. That is, the SOA 102a can be used as an optical gate switch for controlling conduction / shut-off of input light, or the SOA 104 can be used for amplification in addition to conduction / shut-off of input light.

Note that the reference value D for the difference between Vr and Vf described above can correspond to an allowable value for obtaining the target rectangularity, for example, in the waveform of the output pulse output from the SOA 2.
In the above-described operation example, the output pulse from the SOA 2 is controlled so as to be close to an ideal rectangular wave shape. However, the control target may be a specific rectangular wave shape that is not ideal. . As an example, in the arithmetic control circuit 4B, the rectangular wave shaping circuit 5b is controlled so that the difference between the rising amplitude value and the falling amplitude value becomes a specific (not minimum) value including an error range. Also good.

Thus, the third embodiment also has an advantage that a pulse having a target rectangularity can be generated by simple waveform shaping.
[D] Examples The waveform control devices 1, 1 </ b> A, 1 </ b> B and response element modules 10, 10 </ b> A, 10 </ b> B illustrated in the first to third embodiments are applied to, for example, an optical packet switch that performs optical packet switching. Can do. An example is shown in FIG. In the optical packet switch 200 shown in FIG. 16, as in the optical packet switch 100 shown in FIG. 1, eight 1: 8 couplers 101, eight 8: 8 optical gate switch units 102, and eight 8: 1. A coupler 103 and eight SOAs 104 are provided. The same reference numerals as those in FIG. 1 indicate almost the same parts.

  The optical packet switch 200 is an example of an optical switch device having a plurality of SOAs 102a and 104 as optical gate switches that switch conduction / blocking of input light in response to a drive signal. The optical packet switch 200 includes optical couplers 207a-1 to 207a-8, 207b, a rectangularity identification circuit 203, an arithmetic control circuit 204, and a number of drive voltage control circuits 205 corresponding to each SOA 102a, 104.

  The drive voltage control circuit 205 includes 72 SOAs corresponding to the 8 SOAs 104 as well as the 64 SOAs 102a forming the 8: 8 optical gate switch unit 102, and sends drive signals to the individual SOAs 102a and 104, respectively. To supply. As each drive voltage control circuit 205, the drive voltage control circuit 5 which is an element of the waveform control devices 1, 1A, 1B in the above-described embodiments can be applied.

That is, the gate switch drive circuit 5c (see FIGS. 2, 10, and 13) constituting each drive voltage control circuit 205 is provided corresponding to a plurality of optical gate switches 102a and 104 connected in cascade, It is an example of the several drive circuit part which shapes the waveform of the drive signal to corresponding optical gate switch 102a, 104 based on a control signal.
The arithmetic control circuit 204 outputs a trigger signal for driving the corresponding SOAs 102a and 104 to the gate switch drive circuit 5c constituting each drive voltage control circuit 205, and the rectangularity constituting each drive voltage control circuit 205. A control signal is given to the shaping circuit 5b. As the arithmetic control circuit 204, one mode of the arithmetic control circuits 4, 4A, 4B which are elements of the waveform control devices 1, 1A, 1B in the above-described embodiments is controlled, and the 72 drive voltage control circuits 205 described above are controlled. Can be applied to

Therefore, the rectangularity shaping circuit 5b (see FIGS. 2, 10, and 13) and the operation control circuits 4, 4A, and 4B that form each drive voltage control circuit 205 cooperate to monitor results in the monitor unit 203. This corresponds to an example of a control unit that outputs a control signal to the drive circuit unit 5c.
The optical couplers 207a-1 and 207a-8 branch light propagating through the output ports # 1 to # 8, respectively. The optical coupler 207 b joins the branched light paths from the optical couplers 207 a-1 to 207 a-8 and inputs it to the rectangularity identification circuit 203.

  The rectangularity identifying circuit 203 is an example of a monitoring unit that monitors the waveforms of output light pulses (output pulses) output from the 72 SOAs 102a and 104, and identifies the rectangularity of the output light pulses. Here, the light output from the SOA 102a that forms the 8: 8 optical gate switch unit 102 corresponding to the output port #j (j = 1 to 8) and the corresponding downstream SOA 104 are optical couplers 207a-j, This is input to the rectangularity identification circuit 203 via 207b.

  At this time, it becomes possible to sequentially identify the rectangularity of the optical pulses output from one SOA 102a, 104 by the supply mode of the drive signal from the drive voltage control circuit 205 to each SOA 102a, 104. Further, as the rectangularity identification circuit 203, one aspect of the rectangularity identification circuits 3, 3A, and 3B that are elements of the waveform control devices 1, 1A, and 1B in the above-described embodiments can be applied.

  As described above, in the drive voltage control circuit 205, 72 are provided corresponding to the respective SOAs 102a and 104. However, the arithmetic control circuit 204 and the rectangularity identification circuit 203 can be shared by the respective SOAs 102a and 104. it can. That is, the drive voltage control circuit 205 and the arithmetic control circuit 204 cooperate to drive the optical gate switches 102a and 104 that monitor the output optical waveform based on the monitoring result of the monitor unit 203. This corresponds to a drive waveform shaping unit that shapes the waveform of the signal.

Next, an example of the adjustment operation of the drive signal for driving each SOA 102a, 104 before the operation start of the optical packet switch 200 will be described. In adjusting the drive signal of each SOA 102a, 104, the drive signal for the downstream SOA 104 constituting the optical packet switch 200 is preferentially adjusted.
Corresponding to the output ports # 1 to # 8, one SOA 104 is provided on the most downstream side and eight SOAs 102a are provided on the upstream side. The optical couplers 207a-1 to 207a-8 and 207b provide output ports # 1 to # 1. The outputs to # 8 are collected and connected to the rectangularity identifying circuit 203. Therefore, in order to adjust the drive signal for the upstream side SOA 102a, the output light pulse through the downstream side SOA 104 is monitored.

  Therefore, in order to adjust the drive signal for the upstream SOA 102a associated with one output port, it is desirable that the adjustment of the drive signal to the downstream SOA 104 is completed. Thereby, when the drive signal to the downstream SOA 104 is not adjusted, it is possible to prevent the influence on the adjustment of the drive signal to the upstream SOA 102a.

  For example, corresponding to one output port #j, the drive signal from the drive voltage control circuit 205 for the most downstream SOA 104 is adjusted first, and second, the drive voltage for the eight upstream SOAs 102a. The drive signal from the control circuit 205 is adjusted. Thereafter, the drive signals for the SOAs 104 and 102a for the other output ports are similarly adjusted.

  That is, the operation control circuit 204 turns off the drive signal to the upstream side SOA 102 a, while supplying a trigger signal to the drive voltage control circuit 205 corresponding to one SOA 104, an output including ASE light. A light pulse is generated. The output light pulse is input to the rectangularity identification circuit 203 via the optical couplers 207a-j and 207b. The operation control circuit 204 and the corresponding drive voltage control circuit 205 cooperate to shape the waveform of the drive signal based on the monitoring result from the rectangularity identification circuit 203.

  Note that when shaping the drive signals for the eight SOAs 102a on the upstream side, the SOA 104 on the downstream side of the SOA 102a to be adjusted is fixed in the ON state. As a result, the optical pulse generated by the ASE light generated in the upstream side SOA 102a is input to the rectangularity identification circuit 203 via the downstream side SOA 104 and the optical couplers 207a-j and 207b, and can be monitored.

Alternatively, the drive signals for the downstream SOAs 104 corresponding to the output ports # 1 to # 8 are sequentially adjusted with priority, and then the drive signals for the upstream SOA 102a corresponding to the output ports # 1 to # 8 are adjusted. May be.
When the drive signal adjustment operation for all the SOAs 102a and 104 is completed in this way, the actual operation as the optical packet switch 200 can be started.

  Thus, by applying the illustrated waveform control devices 1, 1 </ b> A, and 1 </ b> B as elements of the optical packet switch 200, a multiport-to-multiport optical packet switch system can be easily constructed. That is, it is not necessary to individually adjust the drive circuit for each of the optical gate switches 102a and 104, and the number of man-hours required for assembly adjustment can be greatly reduced. In addition, since the adjustment work for the optical gate switches 102a and 104 is made efficient even after the operation of the apparatus is started, maintenance and system reliability are also improved. That is, by periodically optimizing the drive waveforms for the optical gate switches 102a and 104, it is possible to maintain the device performance over a long period of time.

  FIG. 17 shows an application example of the waveform control devices 1, 1 </ b> A, 1 </ b> B and response element modules 10, 10 </ b> A, 10 </ b> B exemplified in the first to third embodiments described above to other optical packet switches 300. In the optical packet switch 300 shown in FIG. 17, 256 distribution units 310-k provided corresponding to 256 input ports, 256 junction units 320- provided corresponding to the output ports of 256. k is provided (k is an integer of 1 to 256).

Note that, in FIG. 17, attention is paid to a path in which a pair of input / output ports # 1 are connected together with elements constituting one distribution unit 310-1, 320-1. In addition, since each distribution unit 310-k has the same configuration as each other and each merging unit 320-k also has the same configuration as each other, one distribution unit 310-1 and one merging unit 320-1 will be described below. This will be explained with a focus on.
Distribution unit 310-1 distributes 256 light from input port # 1 and connects each distribution path to one junction unit 320-k. Therefore, as an example, the distribution unit 310-1 includes, from the upstream side, an erbium-doped fiber amplifier (EDFA) 311, 1:16 coupler 312, 16 EDFAs 313, 16 1:16 couplers 314, and 16 × 16. Of EDFA315.

  Light from the input port # 1 is optically amplified by the EDFA 311 and branched into 16 by the 1:16 coupler 312. Each light of 16 paths branched by the 1:16 coupler 312 is optically amplified by the corresponding EDFA 313. Each of the 16 paths of light amplified by the EDFA 313 is further branched into 16 by a corresponding 1:16 coupler 314. Each light of a total of 16 × 16 (= 256) paths branched by the 1:16 coupler 314 is optically amplified by the corresponding EDFA 315 and output to the corresponding junction unit 320-k.

  The merge unit 320-1 connects the paths from the respective distribution units 310-k one by one, joins a total of 256 optical paths, and guides them to the output port # 1. Then, light from any one of 256 paths is selectively conducted, and light from other paths is blocked. For this reason, the merging unit 320-1 includes, for example, 256 SOAs 321, 32 8: 1 couplers 322, 32 SOAs 323, 32 4: 1 couplers 324, 8 SOAs 325, from the upstream side. One 8: 1 coupler 326 and one SOA 327 are provided.

  The SOA 321 switches between conduction / blocking of light from each distribution unit 310-k. Each 8: 1 coupler 322 joins the optical paths from the eight SOAs 321. Each SOA 323 switches between conduction / blocking for light from one 8: 1 coupler 322. Each 4: 1 coupler 324 joins the optical paths from the four SOAs 323. Each SOA 325 switches on / off for light from one 4: 1 coupler 324. The 8: 1 coupler 326 joins the optical paths from the eight SOAs 325. The SOA 327 switches between conduction / blocking for the light from the 8: 1 coupler 326.

As a result, in the merging unit 320-1, a total of four SOAs 321, 323, 325, and 327, one for each cascaded stage, are simultaneously controlled to be connected from any of the distributing units 310-k. Light can be guided to the output port # 1.
Also in the optical packet switch 300 having such a configuration, a rectangularity identification circuit (see reference numeral 203), an arithmetic control circuit (see reference numeral 204), and a drive voltage control circuit, following the case of the optical packet switch 200 shown in FIG. (See reference numeral 205) can be applied. As a result, the drive signal can be easily adjusted for (256 + 32 + 8 + 1) × 256 SOAs.

Even in this case, one rectangularity identifying circuit can be shared. In addition, by sequentially adjusting the drive signal from the downstream SOA to the upstream SOA in a path unit forming a pair of input / output ports, the optical packet switch 300 as a whole is efficiently and highly accurately driven. Can be adjusted.
Further, when adjusting the drive signal for the upstream SOA in the path forming the pair of input / output ports, all the SOAs downstream from the SOA to be adjusted are fixed to the ON state. As a result, the optical pulse generated by the ASE light generated in the upstream SOA is input to the rectangularity identification circuit via the downstream SOA, and can be monitored.

Thus, by applying the illustrated waveform control devices 1, 1 </ b> A, and 1 </ b> B as elements of the optical packet switch 300, a multiport-to-multiport optical packet switch system can be easily constructed. In particular, the number of elements of the optical gate switch increases as compared with the case of FIG.
[E] Others In addition, in the response element modules 10, 10A, and 10B in the first to third embodiments, the control amount of the control signal to the rectangularity adjustment circuit 5b is stored in the manufacturing process. May be. For example, after assembling each element of the response element module 10, 10A, 10B, the above-mentioned drive signal adjustment control using the optical pulse by the ASE light is performed, and the monitor result becomes a value that becomes a control target. In such a case, the control amount of the control signal to the rectangularity adjustment circuit 5b is stored. In this way, when the response element modules 10, 10A, 10B are started up, the SOA 2 can be driven using the control amount stored in the arithmetic control circuit 4, so that the same advantages as those in the above embodiments are provided. In addition, pulse waveform adjustment control at startup can be omitted, the startup time can be increased, and the processing load can be reduced.

  In the above-described embodiment, the waveform of the output optical pulse output from the optical gate switch element is shaped by adjusting the drive signal for the optical gate switch element such as the SOA. However, it is of course possible to use it, for example, when shaping the waveform of an output pulse for an electric element. That is, since the waveform control devices 1, 1A, 1B illustrated in FIG. 1 shape the waveform of the drive signal through the electrical signal, the waveform control devices 1, 1A, 1B serve as response elements that output output pulses to be monitored. Of course, an electrical element can be used.

  In this case, the response element 2 constituting the illustrated response element module 10, 10A, 10B is replaced with an electric element, and the function of receiving light in the rectangularity identification circuits 3, 3A, 3B can be omitted as appropriate. Such a response element module can be applied to various electronic devices that handle binary digital signals, and can achieve the effects described in the embodiments.

  FIG. 18 shows an example of the waveform control device 1C and the response element module 10C when an electric element is applied as the response element. The response element module 10C includes a switch 21, an amplifier 22, a switch 27, and a waveform control device 1C. The waveform control device 1C monitors the waveform of the electric signal output from the amplifier 22, and supplies the amplifier 22 based on the monitoring result. The drive signal waveform is shaped. Thereby, the rectangularity of the electric signal output from the amplifier 22 is freely controlled.

  The switch 21 switches conduction or interruption of the input electric signal to the amplifier 22. The amplifier 22 is an example of a response element, and amplifies the electrical signal input from the switch 21 based on a gain control signal that is an example of a drive signal that is waveform-controlled by the waveform control device 1C. The switch 27 selectively switches either the output route of the response element module 10C or the route input to the waveform control device 1C for the output electrical signal output from the amplifier 22.

  As illustrated in FIG. 18, the waveform control device 1 </ b> C includes a rectangularity identification circuit 23, an arithmetic control circuit 24, and a drive voltage control circuit 25. The arithmetic control circuit 24 can control the switching setting of the switches 21 and 27. For example, by controlling the switches 21 and 27, the input electrical signal is supplied to the amplifier 22, and the output of the amplifier 22 is guided to the output of the response element module 10C. Thereby, the electrical signal which passed through amplifier 22 of response element module 10C can be used.

  Further, by controlling the switch 21, the supply of the input electric signal to the amplifier 22 can be cut off. Further, by controlling the switch 27, the output of the amplifier 22 can be guided to the comb filter 3 a ′ of the rectangularity identification circuit 23. In this case, for example, an electrical signal (a pseudo signal as an example) generated by the arithmetic control circuit 24 may be output to the amplifier 22 through the switch 21.

  The rectangularity identification circuit 23 is an example of a monitor unit that monitors the waveform of an output pulse obtained by a response element responding to a supplied drive signal, and together with the comb filter 3a ′, the case of the first embodiment described above. A similar average power detection circuit 3b and A / D converter 3c are provided. In this case, the electric signal generated by the arithmetic control circuit 24 is amplified by the amplifier 22, and the output electric signal output from the amplifier 22 is input to the rectangularity identification circuit 23 via the switch 27.

The comb filter 3a ′ is an example of a harmonic component extraction unit. The output electrical signal from the amplifier 22 is input through the switch 27, and even-order or odd-order harmonic components included in the output electrical signal are extracted. . Thereby, the rectangularity identification circuit 23 outputs the average power value of the even-order or odd-order harmonic components included in the output electrical signal to the arithmetic control circuit 24.
The arithmetic control circuit 24 and the drive waveform control circuit 25 correspond to an example of a drive waveform shaping unit that shapes the drive signal waveform based on the monitoring result of the monitor unit 23 by cooperating with each other. The arithmetic control circuit 24 controls the gain of the amplifier 22 via the drive waveform control circuit 25 based on the monitor result from the rectangularity identification circuit 23.

  For example, when the average power value of the even-order harmonic component is received from the rectangularity identification circuit 23, the arithmetic control circuit 24 uses the amplifier 22 via the drive waveform control circuit 25 so that the average power value is minimized. The signal which controls the gain of is output. On the other hand, when receiving the average power value of the odd-order harmonic component, the calculation control circuit 24 controls the gain of the amplifier 22 via the drive waveform control circuit 25 so that the average power value becomes maximum. Output a signal.

  Further, as an example, the drive waveform control circuit 25 includes a drive circuit 5c equivalent to that illustrated in FIG. 6 together with the D / A converter 5a and the rectangularity shaping circuit 5b similar to those in the first embodiment described above. . As a result, as in the case of the first embodiment, the arithmetic control circuit 24 and the drive waveform control circuit 25 cooperate to shape the rising waveform of the drive signal supplied to the amplifier 22 as a gain control signal. . As a result, the rectangularity of the output electric signal can be set to the target rectangularity.

As described above, also in the example shown in FIG. 18, an output electric signal having a target rectangularity can be obtained by simple waveform shaping.
[F] Appendix (Appendix 1)
A monitor for monitoring the waveform of the output pulse obtained by the response element responding to the supplied drive signal;
A waveform control apparatus comprising: a drive waveform shaping unit that shapes a waveform of the drive signal based on a monitoring result in the monitor unit.

(Appendix 2)
The drive waveform shaping unit
A drive circuit unit that shapes the waveform of the drive signal to the response element based on a control signal;
The waveform control device according to appendix 1, further comprising: a control unit that outputs the control signal to the drive circuit unit based on a monitoring result of the monitoring unit.

(Appendix 3)
The waveform control apparatus according to appendix 2, wherein the control unit outputs the control signal so that a waveform of the output pulse as the monitoring result maintains a predetermined waveform.
(Appendix 4)
3. The waveform control device according to appendix 2, wherein the drive circuit unit has a response time constant that is varied according to the control signal.

(Appendix 5)
The waveform control device according to appendix 4, wherein the drive circuit unit includes a variable capacitance element whose capacitance is varied by the control signal.
(Appendix 6)
The waveform control device according to appendix 4, wherein the drive circuit unit includes an inductor element whose inductance is variable by the control signal.

(Appendix 7)
The monitor unit
A harmonic component extraction unit that extracts even-order or odd-order harmonic components of the frequency of the drive signal from the output pulse;
The waveform control apparatus according to appendix 1, further comprising: a power monitoring unit that monitors power including the even-order or odd-order harmonic components extracted by the harmonic component extraction unit.

(Appendix 8)
The waveform control device according to appendix 7, wherein the drive waveform shaping unit shapes the waveform of the drive signal so that the power monitored by the power monitor unit is at a predetermined level or a predetermined range.
(Appendix 9)
The monitor unit includes a sampling unit that samples the waveform of the output pulse,
The waveform control apparatus according to appendix 1, wherein the drive waveform shaping unit shapes the waveform of the drive signal based on a sampling result in the sampling unit.

(Appendix 10)
The monitor unit
An edge detector for detecting a rising edge and a falling edge in the waveform of the output pulse;
Based on the detection of the rising edge in the edge detection unit, in the waveform of the output pulse, a peak hold unit that holds the value of the rising peak level in response to the rising of the drive signal;
Based on the detection of the rising edge in the edge detection unit, a sample hold unit that samples and holds the value of the response waveform level corresponding to the flat region before the drive signal falls,
The waveform control apparatus according to claim 1, wherein the drive waveform shaping unit receives the value held by the peak hold unit and the value sampled and held by the sample hold unit as the monitoring result.

(Appendix 11)
The drive waveform shaping unit shapes the waveform of the drive signal so that a difference between a value held by the peak hold unit and a value sampled and held by the sample hold unit becomes a predetermined value or a predetermined range. The waveform control device according to appendix 10, wherein:
(Appendix 12)
A response element that obtains an output pulse in response to a supplied drive signal;
A monitor for monitoring the waveform of the output pulse from the response element;
A response element module comprising: a drive waveform shaping unit that shapes a waveform of the drive signal based on a monitoring result in the monitor unit.

(Appendix 13)
13. The response element module according to appendix 12, wherein the response element is a semiconductor optical amplifier that outputs an optical pulse output in response to the drive signal as the output pulse.
(Appendix 14)
14. The response element module according to appendix 13, wherein the light pulse is spontaneous emission light.

(Appendix 15)
An optical switch device having a plurality of optical gate switches that switch conduction / shut-off of input light in response to a drive signal,
A monitor unit for monitoring an optical waveform output from one of the optical gate switches;
An optical switch comprising: a drive waveform shaping unit that shapes a waveform of the drive signal to the optical gate switch that monitors the output optical waveform based on a monitoring result in the monitor unit apparatus.

(Appendix 16)
The optical switch device according to appendix 15, wherein a plurality of the optical gate switches are connected in cascade.
(Appendix 17)
The monitor unit includes a light receiving element installed at the output end of the most downstream optical gate switch among the plurality of optical gate switches connected in cascade, and outputs the light from the output of the light receiving element. The optical switch device according to appendix 16, wherein the waveform is monitored.

(Appendix 18)
The drive waveform shaping unit
A plurality of drive circuit units provided corresponding to the plurality of optical gate switches connected in cascade, and shaping a waveform of the drive signal to the corresponding optical gate switch based on a control signal;
A control unit that outputs the control signal to a drive circuit unit corresponding to the one gate switch among the plurality of drive circuit units based on a monitoring result in the monitor unit; The waveform control device according to appendix 16.

(Appendix 19)
The response element according to claim 1, wherein the response element is driven by a drive signal having the shaped waveform.
(Appendix 20)
A method of controlling an optical switch device in which a plurality of optical gate switches that switch conduction / shut-off of input light in response to a drive signal are connected in cascade,
Supplying the drive signal to one optical gate switch of the plurality of optical gate switches connected in cascade;
Using the light receiving element installed at the output end of the most downstream optical gate switch among the plurality of optical gate switches, monitoring the optical waveform output from one of the one optical gate switches,
Based on the monitoring result in the monitor unit, while shaping the waveform of the drive signal to the most downstream optical gate switch,
The optical gate switch to be used for shaping the waveform of the drive signal is sequentially changed from the most downstream optical gate switch among the plurality of cascaded optical gate switches to the upstream optical gate switch. A method for controlling an optical switch device.

It is a figure which shows an example of an optical packet switch. It is a figure which shows 1st Embodiment. (A)-(c) is a figure which shows the harmonic component extraction part of 1st Embodiment. It is a figure for demonstrating the effect | action function of the harmonic component extraction part of 1st Embodiment. It is a figure for demonstrating the effect | action function of the harmonic component extraction part of 1st Embodiment. It is a figure which shows an example of a gate switch drive circuit. (A)-(c) is a figure which shows an example of the rising waveform of a drive pulse signal and an optical pulse according to the magnitude | size of the capacity | capacitance of a variable capacitance element. (A)-(c) is an example of the signal waveform of the even-order harmonic component according to the value of the control voltage signal to a variable capacitance element, and the waveform of an optical pulse. It is a figure which shows an example of a gate switch drive circuit. It is a figure which shows 2nd Embodiment. It is a flowchart for demonstrating the operation example of 2nd Embodiment. It is a figure for demonstrating the effect | action function of the arithmetic control circuit of 2nd Embodiment. It is a figure which shows 3rd Embodiment. It is a figure for demonstrating the effect | action function of 3rd Embodiment. It is a flowchart for demonstrating the operation example of 3rd Embodiment. It is a figure for demonstrating the example of application of 1st-3rd embodiment. It is a figure for demonstrating the example of application of 1st-3rd embodiment. It is a figure which shows other embodiment.

1, 1A, 1B Waveform control device 2 SOA (response element)
3, 3A, 3B, 203 Rectangularity identification circuit (monitor unit)
3a, 3a ′ Harmonic component extraction unit 3b Average power detection circuit 3c A / D converter 3d Light receiving unit 3e High-speed A / D converter 3f AC coupling unit 3g Level adjustment unit 3h Edge detection circuit 3i Peak hold circuit 3j Sample hold circuit 3m, 3n A / D converter 4, 4A, 4B, 204 Arithmetic control circuit (drive waveform shaping unit)
5,205 Drive voltage control circuit (drive waveform shaping unit)
5a D / A converter 5b Rectangularity shaping circuit 5c, 5c 'Gate switch drive circuit 7 Optical coupler 10, 10A, 10B Response element module 11, 11' Branching unit 12, 12 'Delay unit 13, 14 Light receiving unit 15 Synthesis unit 16 , 18 Circuit section 16a Variable capacitance element 16b, 16c, 18a, 18b Resistance 17 Driver amplifier 18c Inductor element 100, 200, 300 Optical packet switch 101 1: 8 coupler 102 8: 8 optical gate switch section 102a, 104 SOA
103 8: 1 coupler 207a-1 to 207a-8, 207b optical coupler 310-1 distribution unit 311 313 EDFA
312 and 314 1:16 coupler 320-1 merging section 321,323,325,327 SOA
322, 326 8: 1 coupler 324 4: 1 coupler

Claims (1)

A monitor for monitoring the waveform of the output pulse obtained by the response element responding to the supplied drive signal;
A drive waveform shaping unit for shaping the waveform of the drive signal based on the monitoring result in the monitor unit;
The monitor unit
An edge detector for detecting a rising edge and a falling edge in the waveform of the output pulse;
Based on the detection of the rising edge in the edge detection unit, in the waveform of the output pulse, a peak hold unit that holds the value of the rising peak level in response to the rising of the drive signal;
Based on the detection of the rising edge in the edge detection unit, a sample hold unit that samples and holds the value of the response waveform level corresponding to the flat region before the drive signal falls,
The drive waveform shaping unit receives the value held by the peak hold unit and the value sampled and held by the sample hold unit as the monitoring result.

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