JP5558222B2 - Method for manufacturing thin film transistor substrate - Google Patents

Description

  The present invention relates to a method for manufacturing a thin film transistor substrate, and more particularly to a method for manufacturing a thin film transistor substrate using a semiconductor layer of an oxide semiconductor.

  In the active matrix substrate, for example, a thin film transistor (hereinafter also referred to as “TFT”) is provided as a switching element for each pixel which is the minimum unit of an image.

  A typical bottom-gate TFT includes, for example, a gate electrode provided on an insulating substrate, a gate insulating layer provided so as to cover the gate electrode, and an island shape so as to overlap the gate electrode on the gate insulating layer. And a source electrode and a drain electrode provided to face each other on the semiconductor layer.

  Further, in a general peripheral circuit integrated display device, for example, a thin film transistor with a low leakage current used for a switching element of a pixel and a thin film transistor that has a low threshold voltage and can be driven at a high speed are used. The

  Further, when a peripheral circuit is manufactured using a plurality of thin film transistors, the threshold voltage of the CMOS inverter that requires both the n-type channel and the p-type channel or the two thin film transistors that constitute the inverter from the viewpoint of high-speed driving. Enhancement-depletion (E / D) inverters with large differences are widely used.

  In recent years, in an active matrix substrate, an IGZO (In—Ga—Zn—) that can move at high speed is used instead of a conventional thin film transistor using an amorphous silicon semiconductor layer as a switching element of each pixel that is the minimum unit of an image. A TFT using an oxide semiconductor layer (hereinafter also referred to as “oxide semiconductor layer”) formed of an O) -based oxide semiconductor film has been proposed.

  Here, most of high-speed moving oxide semiconductors such as amorphous IGZO have n-type (electron) conduction, and do not become p-type (hole) conduction even by doping, so that a CMOS circuit configuration cannot be used. Accordingly, there is a problem that a CMOS inverter circuit cannot be used in a circuit using a high-speed moving oxide semiconductor, and an E / D inverter circuit capable of independently controlling the threshold voltage of each thin film transistor and capable of high-speed operation. The production of is needed.

  Therefore, an E / D inverter composed of a thin film transistor using an oxide semiconductor as a channel layer is disclosed. More specifically, an E / D inverter is disclosed that includes a first thin film transistor and a second thin film transistor having different channel layer thicknesses, and at least one of the channel layers of the first and second thin film transistors is heat-treated. Has been.

  With such a configuration, a difference occurs in the threshold voltage due to a difference in film thickness of the channel layers of the first and second thin film transistors constituting the E / D inverter or due to a difference in heat treatment conditions of the channel layers. It is described that the difference between the threshold voltages of the two thin film transistors constituting the E / D inverter can be sufficiently increased (see, for example, Patent Document 1).

JP 2009-4733 A

  However, in the E / D inverter described in Patent Document 1, after an amorphous IGZO film serving as a channel layer is formed on a substrate, etching (dry etching or wet etching) is performed on the amorphous IGZO film. Since the first and second thin film transistors having different channel layer thicknesses are formed, if the substrate size is increased, it becomes difficult to control the channel layer thickness and the uniformity of the film thickness decreases. there were.

  More specifically, in the E / D inverter described in Patent Document 1, an amorphous IGZO film having a film thickness of 60 nm is formed in a portion corresponding to each channel layer of the first and second thin film transistors, and then a dry film is formed. Etching is performed so that the film thickness of the amorphous IGZO film serving as the channel layer of the second thin film transistor becomes half the thickness (ie, 30 nm) at the time of film formation. Etching uniformly to half the thickness at the time of film formation requires both establishment of a highly advanced technique and introduction of an expensive apparatus. Therefore, it is difficult to manufacture the thin film transistor, and as a result, there is a problem that the yield is lowered.

  In the E / D inverter described in Patent Document 1, after an amorphous IGZO film serving as a channel layer is formed on a substrate, for example, the channel layer is heated by contact heating or electromagnetic wave irradiation (high frequency irradiation). Or the ultraviolet light irradiation), the threshold voltage of the first and second thin film transistors is changed. However, the selective heat treatment in such a local region complicates the process and has high definition and fineness. It can be said that application to a thin film transistor is difficult. As a result, there is a problem that the yield decreases.

  Therefore, the present invention has been made in view of the above-described problems, and can manufacture a plurality of thin film transistors having different threshold voltages by a simple method, and manufacture of a thin film transistor substrate capable of suppressing a decrease in yield. It aims to provide a method.

  In order to achieve the above object, an invention according to claim 1 is directed to an insulating substrate, a first gate electrode provided on the insulating substrate, a first channel electrode provided on the first gate electrode, and having a first channel region. A second thin film transistor including a first thin film transistor including an oxide semiconductor layer; a second gate electrode provided over an insulating substrate; and a second oxide semiconductor layer provided over the second gate electrode and including a second channel region. A method of manufacturing a thin film transistor substrate including a thin film transistor, comprising: forming a first metal film on an insulating substrate; and forming a second metal film on the first metal film; and a first metal film, The second metal film is patterned by etching to form a second gate electrode composed of a first conductive layer made of the first metal film and a second conductive layer made of the second metal film, and on the first metal film. Product with two metal films stacked A second gate electrode forming step of forming a film; and a first gate having a thickness smaller than the thickness of the second gate electrode, the second metal film in the stacked film being removed by etching to form a first metal film A first gate electrode forming step of forming an electrode; an insulating layer forming step of forming an insulating layer on the insulating substrate so as to cover the first gate electrode and the second gate electrode; and a liquid oxide semiconductor on the insulating layer An oxide semiconductor layer forming step of forming an oxide semiconductor layer by applying a material and sintering an oxide semiconductor material; patterning the oxide semiconductor layer by etching; and a first oxide semiconductor layer; And at least a first oxide semiconductor layer forming step for forming a second oxide semiconductor layer having a second channel region having a thickness smaller than that of the first channel region. And butterflies.

  According to the configuration, after the first gate electrode and the second gate electrode having different thicknesses are formed, the first oxide semiconductor layer and the second oxide semiconductor layer are formed using the liquid oxide semiconductor material. Thus, the first thin film transistor and the second thin film transistor in which the first channel region and the second channel region have different thicknesses can be formed. Therefore, the threshold voltages of the first thin film transistor and the second thin film transistor can be made different, and the difference between the threshold voltages of the first thin film transistor and the second thin film transistor can be made sufficiently large. As a result, a thin film transistor (that is, an E / D inverter) including a first thin film transistor and a second thin film transistor having different threshold voltages can be manufactured by a simple method, and a reduction in yield can be suppressed.

According to a second aspect of the invention, a method of manufacturing a thin film transistor substrate according to claim 1, E ₁ the etching rate of the first metal _film, the etching rate of the second metal layer when the E _2, The relationship of E ₁ <E ₂ is established.

  According to this configuration, since the laminated film can be configured by the first metal film and the second metal film having different etching rates, the first gate electrode and the second gate electrode having different thicknesses can be easily formed. It becomes possible.

  Invention of Claim 3 is a manufacturing method of the thin-film transistor substrate of Claim 1 or Claim 2, Comprising: An oxide semiconductor material is indium (In), gallium (Ga), aluminum (Al), copper It is characterized by comprising a metal oxide material containing at least one selected from the group consisting of (Cu) and zinc (Zn).

  According to the structure, the oxide semiconductor layer made of any of these materials has high mobility even if it is amorphous, so that the on-resistance of the switching element can be increased.

  A fourth aspect of the present invention is the method of manufacturing a thin film transistor substrate according to the third aspect, wherein the oxide semiconductor material is made of an In—Ga—Zn—O-based metal oxide material. .

  According to this configuration, good characteristics such as high mobility and low off-state current can be obtained in the first and second thin film transistors.

  In addition, as in the fifth aspect of the present invention, the first channel region and the second channel region are protected by the first channel region and the second channel region after the first and second oxide semiconductor layer forming steps. It is good also as a structure further provided with the channel protective layer formation process which forms a channel protective layer.

  According to a sixth aspect of the invention, there is provided an insulating substrate, a first gate electrode provided on the insulating substrate, and a first oxide semiconductor layer provided on the first gate electrode and having a first channel region. A thin film transistor substrate comprising: a thin film transistor; a second gate electrode provided on an insulating substrate; and a second thin film transistor provided on the second gate electrode and having a second oxide semiconductor layer having a second channel region. In the manufacturing method, the first metal film forming step of forming the first metal film on the insulating substrate, the first metal film is patterned by etching, the first gate electrode made of the first metal film, and the second A first gate electrode forming step for forming a first conductive layer constituting the gate electrode; and a second metal for forming a second metal film on the insulating substrate so as to cover the first gate electrode and the first conductive layer. Film formation And patterning the second metal film by etching to form a second conductive layer constituting the second gate electrode, which is constituted by the first conductive layer and the second conductive layer, the thickness of the first gate electrode being A second gate electrode forming step of forming a second gate electrode having a large thickness, an insulating layer forming step of forming an insulating layer on the insulating substrate so as to cover the first gate electrode and the second gate electrode, and an insulating layer A liquid oxide semiconductor material is applied onto the oxide semiconductor material, and the oxide semiconductor material is sintered. Thus, an oxide semiconductor layer forming step for forming an oxide semiconductor layer is formed, and the oxide semiconductor layer is patterned by etching. The first and second oxide semiconductor layer forming steps for forming the first oxide semiconductor layer and the second oxide semiconductor layer having the second channel region having a thickness smaller than the thickness of the first channel region are reduced. Characterized in that it comprises also.

  According to the configuration, after the first gate electrode and the second gate electrode having different thicknesses are formed, the first oxide semiconductor layer and the second oxide semiconductor layer are formed using the liquid oxide semiconductor material. Thus, the first thin film transistor and the second thin film transistor in which the first channel region and the second channel region have different thicknesses can be formed. Therefore, the threshold voltages of the first thin film transistor and the second thin film transistor can be made different, and the difference between the threshold voltages of the first thin film transistor and the second thin film transistor can be made sufficiently large. As a result, a thin film transistor (that is, an E / D inverter) including a first thin film transistor and a second thin film transistor having different threshold voltages can be manufactured by a simple method, and a reduction in yield can be suppressed.

  In addition, after the first gate electrode is formed by patterning by etching the first metal film and the second metal film, the second gate electrode is formed, and the first gate electrode and the second gate electrode having different thicknesses are formed. It becomes possible to do.

  The invention according to claim 7 is the method of manufacturing a thin film transistor substrate according to claim 6, wherein the oxide semiconductor material is indium (In), gallium (Ga), aluminum (Al), copper (Cu) and It is characterized by comprising a metal oxide material containing at least one selected from the group consisting of zinc (Zn).

  According to the structure, the oxide semiconductor layer made of any of these materials has high mobility even if it is amorphous, so that the on-resistance of the switching element can be increased.

  The invention according to claim 8 is the method for manufacturing the thin film transistor substrate according to claim 7, wherein the oxide semiconductor material is made of an In—Ga—Zn—O-based metal oxide material. .

  According to this configuration, good characteristics such as high mobility and low off-state current can be obtained in the first and second thin film transistors.

  The channel protection layer for protecting the first channel region and the second channel region in the first channel region and the second channel region after the second oxide semiconductor layer forming step as in the invention according to claim 9. It is good also as a structure further provided with the channel protective layer formation process of forming.

  According to the present invention, a plurality of thin film transistors having different threshold voltages can be formed by a simple method, and a reduction in yield of the thin film transistor substrate can be suppressed.

1 is a cross-sectional view of a thin film transistor according to a first embodiment of the present invention. It is explanatory drawing which shows the manufacturing process of the thin-film transistor substrate which concerns on the 1st Embodiment of this invention in a cross section. It is explanatory drawing which shows the manufacturing process of the thin-film transistor substrate which concerns on the 1st Embodiment of this invention in a cross section. It is explanatory drawing which shows the manufacturing process of the thin-film transistor substrate which concerns on the 1st Embodiment of this invention in a cross section. It is explanatory drawing which shows the manufacturing process of the thin-film transistor substrate which concerns on the 1st Embodiment of this invention in a cross section. It is explanatory drawing which shows the manufacturing process of the thin-film transistor substrate which concerns on the 1st Embodiment of this invention in a cross section. It is explanatory drawing which shows the manufacturing process of the thin-film transistor substrate which concerns on the 1st Embodiment of this invention in a cross section. It is explanatory drawing which shows the manufacturing process of the thin-film transistor substrate which concerns on the 1st Embodiment of this invention in a cross section. It is explanatory drawing which shows the manufacturing process of the thin-film transistor substrate which concerns on the 1st Embodiment of this invention in a cross section. It is explanatory drawing which shows the manufacturing process of the thin-film transistor substrate which concerns on the 1st Embodiment of this invention in a cross section. It is explanatory drawing which shows the manufacturing process of the thin-film transistor substrate which concerns on the 1st Embodiment of this invention in a cross section. It is explanatory drawing which shows the manufacturing process of the thin-film transistor substrate which concerns on the 1st Embodiment of this invention in a cross section. It is explanatory drawing which shows the manufacturing process of the thin-film transistor substrate which concerns on the 2nd Embodiment of this invention in a cross section. It is explanatory drawing which shows the manufacturing process of the thin-film transistor substrate which concerns on the 2nd Embodiment of this invention in a cross section. It is explanatory drawing which shows the manufacturing process of the thin-film transistor substrate which concerns on the 2nd Embodiment of this invention in a cross section. It is explanatory drawing which shows the manufacturing process of the thin-film transistor substrate which concerns on the 2nd Embodiment of this invention in a cross section. It is explanatory drawing which shows the manufacturing process of the thin-film transistor substrate which concerns on the 2nd Embodiment of this invention in a cross section. It is explanatory drawing which shows the manufacturing process of the thin-film transistor substrate which concerns on the 2nd Embodiment of this invention in a cross section. It is explanatory drawing which shows the manufacturing process of the thin-film transistor substrate which concerns on the 2nd Embodiment of this invention in a cross section.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiment.

(First embodiment)
FIG. 1 is a cross-sectional view of a thin film transistor according to a first embodiment of the present invention.

  As shown in FIG. 1, the thin film transistor substrate 1 includes a thin film transistor 5, and the thin film transistor 5 includes a first thin film transistor 5 a and a second thin film transistor 5 b formed on an insulating substrate 20.

  The thin film transistor 5 functions as an active element of a driving circuit such as a gate driver or a source driver provided in the liquid crystal display device, for example.

  As shown in FIG. 1, the thin film transistor substrate 1 is provided so as to cover the first thin film transistor 5a and the second thin film transistor 5b, and covers the interlayer insulating layer 17 that functions as a channel protective layer and the interlayer insulating layer 17. And a planarizing film 18 provided as described above.

  The first thin film transistor 5a has a bottom gate structure, and as shown in FIG. 1, a first gate electrode 11 provided on the insulating substrate 20 and a gate provided so as to cover the first gate electrode 11. An insulating layer 12, a first oxide semiconductor layer 13a having a first channel region Ca provided in an island shape so as to overlap the first gate electrode 11 on the gate insulating layer 12, and the first oxide semiconductor layer 13a The source electrode 15 and the drain electrode 16 are provided so as to overlap the first gate electrode 11 and to face each other across the first channel region Ca.

  Similarly, the second thin film transistor 5b has a bottom gate structure, and covers the second gate electrode 10 provided on the insulating substrate 20 and the second gate electrode 10 as shown in FIG. A second oxide semiconductor layer 13b having a second channel region Cb provided in an island shape so as to overlap the second gate electrode 10 on the gate insulating layer 12, and a second oxide semiconductor layer 13b. A source electrode 15 and a drain electrode 16 are provided on the physical semiconductor layer 13b so as to overlap the second gate electrode 10 and to face each other across the second channel region Cb.

  The first and second oxide semiconductor layers 13a and 13b are formed of, for example, an IGZO (In—Ga—Zn—O) -based oxide semiconductor film.

  As shown in FIG. 1, the second gate electrode 10 is composed of a laminated film of a first conductive layer 10a and a second conductive layer 10b.

  Next, an example of a method for manufacturing the thin film transistor substrate 1 of the present embodiment will be described with reference to the drawings. 2 to 12 are explanatory views showing in cross section the manufacturing process of the thin film transistor substrate according to the first embodiment of the present invention.

<Metal film formation process>
First, as shown in FIG. 2, for example, an aluminum film 21 that is a first metal film having a thickness of 300 nm is formed on the entire substrate of the insulating substrate 20 such as a glass substrate, a silicon substrate, or a heat-resistant plastic substrate by a sputtering method. Next, a titanium film 22 as a second metal film having a thickness of 100 nm is sequentially formed and laminated on the aluminum film 21.

<Photosensitive resin formation process>
Next, as shown in FIG. 2, for example, a positive type (exposed portion is dissolved and removed by development processing by spin coating so as to cover the aluminum film 21 and the titanium film 22 on the insulating substrate 20. A photosensitive resin (for example, acrylic photosensitive resin) 23 is applied to a thickness of about 1.5 μm.

<Exposure / resist formation process>
Next, an exposure process is performed on the photosensitive resin 23 using a photomask (not shown), and a development process is performed on the photosensitive resin 23 on which the exposure process has been performed. A resist 24 is formed.

<Second gate electrode formation step>
Next, the aluminum film 21 and the titanium film 22 are patterned by performing dry etching using a predetermined etching gas (for example, a mixed gas in which CL ₂ is added to BCl ₃ gas) using the resist 24 as a mask. As shown in FIG. 4, on the second gate electrode 10 constituted by the first conductive layer 10a made of the aluminum film 21 and the second conductive layer 10b made of the titanium film 22, and on the aluminum film 21 which is the first metal film. A laminated film 25 in which a titanium film 22 as a second metal film is laminated is formed.

<Photosensitive resin formation process>
Next, after removing the resist 24 with a stripping solution or the like, as shown in FIG. 5, for example, a positive type is formed by spin coating so as to cover the second gate electrode 10 and the laminated film 25 on the insulating substrate 20. A photosensitive resin (for example, acrylic photosensitive resin) 26 is applied to a thickness of about 1.5 μm.

<Exposure / resist formation process>
Next, an exposure process is performed on the photosensitive resin 26 using a photomask (not shown), and a development process is performed on the photosensitive resin 26 on which the exposure process has been performed, as shown in FIG. A resist 27 is formed. At this time, the resist 27 is formed on the insulating substrate 20 so as to cover the second gate electrode 10.

<First gate electrode formation step>
Next, by performing dry etching using a predetermined etching gas (for example, CF ₄ gas) using the resist 27 as a mask, the titanium film 22 in the laminated film 25 is removed, and as shown in FIG. The first gate electrode 11 having a thickness smaller than that of the second gate electrode 10 is formed.

Here, when CF ₄ gas is used as the etching gas, fluorine in the CF ₄ gas reacts with aluminum to form aluminum fluoride (AlF ₃ ) on the surface of the aluminum film 21. The aluminum film 21 is not etched, and only the titanium film 25 is etched.

That is, when the etching rate of the aluminum film 21 is E ₁ and the etching rate of the titanium film is E ₂ , the relationship of E ₁ <E ₂ is established.

Thus, in the present embodiment, the laminated film 25 is composed of the aluminum film 21 and the titanium film 22 having different etching rates, so that the thicknesses are different (that is, as shown in FIG. 7, the first gate electrode 11 _{T 1} the thickness of the case where the thickness of the second gate electrode 10 and _{T 2,} T 2> _{T 1} relationship is established) can be produced with the first gate electrode 11 and the second gate electrode 10 become.

In view of the difference between the thickness T ₂ of the thickness T ₁ and the second gate electrode 10 of the first gate electrode 11 is sufficiently formed, the etching selectivity ratio of the titanium film 22 to aluminum layer 21 (etching of a titanium film 22 The etching rate E ₁ ) of the rate E ₂ / aluminum film 21 is preferably 50 or more.

<Gate insulation layer formation process>
Next, after removing the second resist 27 with a stripping solution or the like, for example, a silicon nitride film (thickness of about 200 nm to 500 nm) is formed on the entire substrate on which the first gate electrode 11 and the second gate electrode 10 are formed by CVD. As shown in FIG. 8, a gate insulating layer 12 is formed on the insulating substrate 20 so as to cover the first gate electrode 11 and the second gate electrode 10.

  Note that the gate insulating layer 12 may have a two-layer structure. In this case, for example, a silicon oxide film (SiOx), a silicon oxynitride film (SiOxNy, x> y), a silicon nitride oxide film (SiNxOy, x> y), or the like is used in addition to the above-described silicon nitride film (SiNx). be able to.

  Further, from the viewpoint of preventing diffusion of impurities and the like from the insulating substrate 20, a silicon nitride film or a silicon nitride oxide film is used as a lower gate insulating layer, and a silicon oxide film as an upper gate insulating layer, Alternatively, a structure using a silicon oxynitride film is preferable.

For example, a silicon nitride film having a thickness of 100 to 200 nm is formed as a lower gate insulating layer using SiH ₄ and NH ₃ as reaction gases, and N ₂ O and SiH ₄ are reacted as an upper gate insulating layer. A silicon oxide film with a thickness of 50 nm to 100 nm can be formed as a gas.

  Further, from the viewpoint of forming a dense gate insulating layer 12 with a small gate leakage current at a low film formation temperature, it is preferable that a rare gas such as argon gas is included in the reaction gas and mixed into the insulating layer.

<Oxide semiconductor layer formation process>
Next, the liquid oxide semiconductor material 28 is applied to the gate insulating layer 12 with a thickness of, for example, 2 μm by, for example, spin coating or slit coating.

  Here, as the liquid oxide semiconductor material 28, for example, a liquid In— composed of an organic metal compound (for example, zinc oxide, indium oxide, gallium oxide) and an organic solvent (for example, 2-methoxyethanol) is used. A Ga—Zn—O-based metal oxide material can be used.

Further, since the oxide semiconductor material 28 is in a liquid state, the surface 28a of the oxide semiconductor material 28 becomes flat as shown in FIG. 9, and the thickness of the oxide semiconductor material 28 on the first gate electrode 11 is T _3. becomes the thickness of the oxide semiconductor material 28 in the second gate electrode on 10 when the T _4, that the relationship of T _3> T ₄ is satisfied. Further, the difference in thickness (T ₃ −T ₄ ) of the oxide semiconductor material 28 is substantially the same as the difference in thickness (T ₂ −T ₁ ) between the first gate electrode 11 and the second gate electrode.

Next, the oxide semiconductor material 28 is baked under predetermined conditions (for example, at 350 ° C. for 40 minutes), and the liquid oxide semiconductor material 28 is sintered, whereby the thickness of the oxide semiconductor material 28 is increased. (That is, the thicknesses T ₃ and T ₄ ) are reduced to form the oxide semiconductor layer 29 as shown in FIG.

The thickness of _{T 5} of the oxide semiconductor layer 29 on the first gate electrode 11, when the thickness of the oxide semiconductor layer 29 in the second gate electrode on the 10 was _{T 6,} the relationship of T 5> _{T 6} established (for example, the thickness _{T 5} is 80 nm, the thickness _{T 6} is 50 nm).

<First and second oxide semiconductor layer forming step>
Next, after, for example, a titanium film (thickness: 30 nm to 150 nm) and an aluminum film (thickness: about 50 nm to 400 nm) are sequentially formed on the entire substrate on which the oxide semiconductor layer 29 has been formed by sputtering, By performing photolithography and wet etching on the aluminum film, and performing dry etching (for example, plasma etching) on the titanium film and removing and cleaning the resist, as shown in FIG. And the drain electrode 16 is formed.

  At this time, as shown in FIG. 11, the oxide semiconductor layer 29 shown in FIG. 10 is also etched, and the oxide semiconductor layer 29 is patterned by etching, so that the first gate electrode 11 is covered with the first The oxide semiconductor layer 13 a is formed, and the second oxide semiconductor layer 13 b is formed on the second gate electrode 10.

  As shown in FIG. 11, the first channel region Ca of the first oxide semiconductor layer 13a is exposed by the above-described etching, and in the first thin film transistor 5a, the source electrode 15 and the drain electrode 16 are formed in the first channel region. It is provided so that it may mutually oppose on both sides of Ca.

  Similarly, as shown in FIG. 11, the above-described etching exposes the second channel region Cb of the second oxide semiconductor layer 13b. In the second thin film transistor 5b, the source electrode 15 and the drain electrode 16 are 1 channel region Cb is provided so as to face each other.

As described above, the first having a first oxide semiconductor layer 13a having a first channel region Ca of thickness T _5, the second channel region Cb with a thickness T ₅ less than the thickness T ₆ of the first channel region Ca The second oxide semiconductor layer 13b is formed, and the first thin film transistor 5a including the first oxide semiconductor layer 13a and the second thin film transistor 5b including the second oxide semiconductor layer 13b are manufactured.

  Thus, in this embodiment, after forming the first gate electrode 11 and the second gate electrode 10 having different thicknesses, the first oxide semiconductor layer 13a and the first gate electrode 10 are formed using the liquid oxide semiconductor material 28. By forming the two oxide semiconductor layer 13b, the first thin film transistor 5a and the second thin film transistor having different thicknesses of the first channel region Ca and the second channel region Cb are manufactured.

  In the prior art, for example, when dry etching is performed by plasma etching in which gas is ionized and radicalized by plasma, the resistance of the amorphous IGZO film is reduced due to plasma damage. There is a problem that the channel layer becomes a conductor and the yield decreases.

  On the other hand, in this embodiment, when the oxide semiconductor layer 29 is patterned by etching by performing an etching process on the oxide semiconductor layer 29 illustrated in FIG. By performing plasma etching in a state of being covered with a resist, unlike the conventional technique, plasma damage to the oxide semiconductor layer 29 constituting the first oxide semiconductor layer 13a and the second oxide semiconductor layer 13b is prevented. be able to.

  In the present embodiment, as the metal film constituting the source electrode 15 and the drain electrode 16, a titanium film and an aluminum film having a laminated structure are exemplified. However, for example, a metal such as a copper film, a tungsten film, a tantalum film, or a chromium film is used. The source electrode 15 and the drain electrode 16 may be formed by a film or a film made of an alloy film or a metal nitride thereof.

  As the etching process, either dry etching or wet etching described above may be used. However, when processing a large area substrate, it is preferable to use dry etching.

As an etching gas, a fluorine-based gas such as CF ₄ , NF ₃ , SF ₆ , or CHF ₃ , a chlorine-based gas such as Cl ₂ , BCl ₃ , SiCl ₄ , or CCl ₄ , an oxygen gas, or the like can be used. Alternatively, an inert gas such as argon may be added.

<Channel protective layer formation process>
Next, for example, a silicon nitride film or a silicon oxide film is formed on the entire substrate on which the source electrode 15 and the drain electrode 16 are formed (that is, the first thin film transistor 5a and the second thin film transistor 5b are formed) by a plasma CVD method. Then, a silicon nitride oxide film or the like is formed, and as shown in FIG. 12, an interlayer insulating layer 17 covering the first thin film transistor 5a and the second thin film transistor 5b is formed to a thickness of about 200 to 300 nm.

  At this time, the interlayer insulating layer 17 is formed in the first channel region Ca and the second channel region Cb so as to protect the first channel region Ca and the second channel region Cb.

  In the present embodiment, as the interlayer insulating layer 17, a silicon oxide film having a thickness of 200 nm to 300 nm is formed by, for example, plasma CVD using TEOS (Tetra Ethyl Ortho Silicate) as a source gas. be able to.

<Planarization film formation process>
Next, an organic insulating film made of a photosensitive acrylic resin or the like is applied to a thickness of about 1.0 μm to 3.0 μm by spin coating or slit coating on the entire substrate on which the interlayer insulating layer 17 is formed. Thus, the planarizing film 18 is formed on the surface of the interlayer insulating layer 17, and the thin film transistor substrate 1 shown in FIG. 1 is manufactured.

  According to the present embodiment described above, the following effects can be obtained.

  (1) In the present embodiment, after the first gate electrode 11 and the second gate electrode 10 having different thicknesses are formed, the first oxide semiconductor layer 13 a and the second gate electrode 10 are formed using the liquid oxide semiconductor material 28. By forming the oxide semiconductor layer 13b, the first thin film transistor 5a and the second thin film transistor in which the first channel region Ca and the second channel region Cb have different thicknesses are manufactured. Accordingly, the threshold voltages of the first thin film transistor 5a and the second thin film transistor 5b can be made different, and the difference between the threshold voltages of the first and second thin film transistors 5a and 5b can be made sufficiently large. As a result, a thin film transistor (that is, an E / D inverter) including the first thin film transistor 5a and the second thin film transistor 5b having different threshold voltages can be manufactured by a simple method, and a reduction in yield can be suppressed. .

(2) In this embodiment, the etching rate _{E 1} of the aluminum film 21, during the etching rate _{E 2} of the titanium film 22 _has a configuration in which E 1 _{<E 2} the relationship is established. Therefore, since the laminated film 25 can be composed of the aluminum film 21 and the titanium film 22 having different etching rates, the first gate electrode 11 and the second gate electrode 10 having different thicknesses can be easily formed. Become.

  (3) In this embodiment, an In—Ga—Zn—O-based metal oxide material is used as the oxide semiconductor material. Therefore, good characteristics such as high mobility and low off-state current can be obtained in the first and second thin film transistors 5a and 5b.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted. The overall configuration of the thin film transistor substrate is the same as that described in the first embodiment, and a detailed description thereof is omitted here.

  This embodiment is characterized in the manufacturing process of the first gate electrode 11 and the second gate electrode 10. Hereinafter, an example of a method for manufacturing the thin film transistor substrate of the present embodiment will be described with reference to the drawings. 13 to 19 are explanatory views showing, in cross section, the manufacturing process of the thin film transistor substrate according to the second embodiment of the present invention.

<First metal film forming step>
First, as shown in FIG. 13, an aluminum film 21 which is a first metal film having a thickness of, for example, 300 nm is formed on a substrate of an insulating substrate 20 such as a glass substrate, a silicon substrate, or a heat-resistant plastic substrate by a sputtering method. Form.

<Photosensitive resin formation process>
Next, as shown in FIG. 13, for example, a positive photosensitive resin (for example, an acrylic photosensitive resin) 30 is formed on the insulating substrate 20 by spin coating so as to cover the aluminum film 21. It is applied to a thickness of about 1.5 μm.

<Exposure / resist formation process>
Next, an exposure process is performed on the photosensitive resin 30 using a photomask (not shown), and a development process is performed on the photosensitive resin 30 that has been subjected to the exposure process, as shown in FIG. A resist 31 is formed.

<First gate electrode formation step>
Next, the aluminum film 21 is patterned by performing dry etching using a predetermined etching gas (for example, Cl ₂ ) using the resist 31 as a mask, and as shown in FIG. 15, the first film made of an aluminum film is formed. The gate electrode 11 is formed, and the first conductive layer 10a constituting the second gate electrode is formed.

<Second metal film forming step>
Next, after removing the resist 31 with a stripping solution or the like, as shown in FIG. 16, for example, by a sputtering method so as to cover the first gate electrode 11 and the first conductive layer 10 a on the insulating substrate 20, the thickness is increased. A 100 nm thick titanium film 22 is formed.

<Photosensitive resin formation process>
Next, as shown in FIG. 17, for example, a positive photosensitive resin (for example, acrylic photosensitive resin) 32 is formed on the insulating substrate 20 by spin coating so as to cover the titanium film 22. It is applied to a thickness of about 1.5 μm.

<Exposure / resist formation process>
Next, an exposure process is performed on the photosensitive resin 32 using a photomask (not shown), and a development process is performed on the photosensitive resin 32 that has been subjected to the exposure process, as shown in FIG. A resist 33 is formed. At this time, the resist 33 is formed on the titanium film 22 so as to cover the first conductive layer 10a.

<Second gate electrode formation step>
Next, the titanium film 22 is patterned by performing dry etching using a predetermined etching gas (for example, CF ₄ ) using the resist 33 as a mask, and the second gate electrode 10 is configured as shown in FIG. to the second conductive layer 10b is formed, is constituted by a first conductive layer 10a and the second conductive layer 10b, a second gate electrode 10 having a larger thickness T ₂ than the thickness T ₁ of the first gate electrode 11 To do.

  Thus, in the present embodiment, unlike the first embodiment described above, the second gate electrode 10 is formed after the first gate electrode 11 is formed by patterning the aluminum film 21 and the titanium film 22 by etching. As in the case of the first embodiment described above, the first gate electrode 11 and the second gate electrode 10 having different thicknesses are formed.

  After the second gate electrode 10 is formed, the thin film transistor substrate 1 is manufactured by performing the steps described in FIGS. 8 to 12 of the first embodiment.

That is, a gate insulating layer 12 is formed on the insulating substrate 20 so as to cover the first gate electrode 11 and the second gate electrode 10, and a liquid oxide semiconductor material 28 is applied on the gate insulating layer 12. The oxide semiconductor layer 29 is formed by sintering the semiconductor material 28. Then, the oxide semiconductor layer 29 is patterned by etching, the second oxide having a first oxide semiconductor layer 13a, a second channel region Cb with a thickness T ₅ less than the thickness T ₆ of the first channel region Ca A semiconductor layer 13b is formed.

  In the present embodiment described above, the following effects can be obtained in addition to the effects (1) and (3) described above.

  (4) In the present embodiment, after the first gate electrode 11 is formed by patterning by etching the aluminum film 21 and the titanium film 22, the second gate electrode 10 is formed, and the first gate electrodes 11 having different thicknesses are formed. And the second gate electrode 10 can be formed.

  In addition, you may change the said embodiment as follows.

  In the above embodiment, an oxide semiconductor layer made of an In—Ga—Zn—O-based metal oxide is used as the oxide semiconductor layer; however, the oxide semiconductor layer is not limited to this. For example, a metal containing at least one of indium (In), gallium (Ga), aluminum (Al), copper (Cu), zinc (Zn), magnesium (Mg), and cadmium (Cd) as an oxide semiconductor material An oxide material may be used.

  Since the first and second oxide semiconductor layers 13a and 13b made of these oxide semiconductor materials have high mobility even if they are amorphous, the on-resistance of the switching element can be increased. Therefore, the difference in output voltage at the time of data reading becomes large, and the S / N ratio can be improved.

For example, in addition to IGZO (In—Ga—Zn—O), oxide semiconductor films such as InGaO ₃ (ZnO) ₅ , Mg _x Zn _1-x O, Cd _x Zn _1-x O, and CdO can be given. it can.

  In the above embodiment, an oxide semiconductor layer is used as the semiconductor layer. However, the semiconductor layer is not limited to this, and instead of the oxide semiconductor layer, for example, a silicon-based semiconductor layer made of amorphous silicon or polysilicon. May be used as a semiconductor layer of a thin film transistor.

  As an application example of the present invention, there is a method for manufacturing a thin film transistor substrate using a semiconductor layer of an oxide semiconductor.

DESCRIPTION OF SYMBOLS 1 Thin-film transistor substrate 5 Thin-film transistor 5a 1st thin-film transistor 5b 2nd thin-film transistor 10 2nd gate electrode 10a 1st conductive layer 10b 2nd conductive layer 11 1st gate electrode 12 Gate insulating layer (insulating layer)
13a First oxide semiconductor layer 13b Second oxide semiconductor layer 15 Source electrode 16 Drain electrode 17 Interlayer insulating layer (channel protective layer)
18 Planarizing film 20 Insulating substrate 21 Aluminum film (first metal film)
22 Titanium film (second metal film)
25 Stacked film 28 Liquid oxide semiconductor material 29 Oxide semiconductor layer Ca First channel region Cb Second channel region T ₁ First gate electrode thickness T ₂ Second gate electrode thickness T ₃ Oxidation on first gate electrode Thickness of oxide semiconductor material T ₄ Thickness of oxide semiconductor material on second gate electrode T ₅ Thickness of oxide semiconductor layer on first gate electrode (thickness of first channel region)
T ₆ the thickness of the oxide semiconductor layer on the second gate electrode (thickness of the second channel region)

Claims (9)

A first thin film transistor including an insulating substrate, a first gate electrode provided on the insulating substrate, and a first oxide semiconductor layer provided on the first gate electrode and having a first channel region; and the insulating substrate. A method of manufacturing a thin film transistor substrate, comprising: a second gate electrode provided on the second gate electrode; and a second thin film transistor provided on the second gate electrode and having a second oxide semiconductor layer having a second channel region. ,
Forming a first metal film on the insulating substrate and forming a second metal film on the first metal film; and
The second gate configured by patterning the first metal film and the second metal film by etching to include a first conductive layer made of the first metal film and a second conductive layer made of the second metal film. A second gate electrode forming step of forming an electrode and a laminated film in which a second metal film is laminated on the first metal film;
A first gate electrode is formed by removing the second metal film in the stacked film by etching to form the first gate electrode that is formed of the first metal film and has a thickness smaller than the thickness of the second gate electrode. Forming process;
Forming an insulating layer on the insulating substrate so as to cover the first gate electrode and the second gate electrode;
An oxide semiconductor layer forming step of forming an oxide semiconductor layer by applying a liquid oxide semiconductor material on the insulating layer and sintering the oxide semiconductor material;
The oxide semiconductor layer is patterned by etching to form the second oxide semiconductor layer having the first oxide semiconductor layer and the second channel region having a thickness smaller than that of the first channel region. A method for producing a thin film transistor substrate, comprising at least a first oxide semiconductor layer formation step and a second oxide semiconductor layer formation step. Wherein E ₁ to the etching rate of the first metal _layer, wherein in the case where the etching rate of the second metal film and E _2, the thin film transistor of claim 1 in which E 1 _{<E 2} the relationship, characterized in that the established A method for manufacturing a substrate.   The oxide semiconductor material is made of a metal oxide material containing at least one selected from the group consisting of indium (In), gallium (Ga), aluminum (Al), copper (Cu), and zinc (Zn). 3. The method for manufacturing a thin film transistor substrate according to claim 1, wherein the thin film transistor substrate is a thin film transistor substrate.   4. The method of manufacturing a thin film transistor substrate according to claim 3, wherein the oxide semiconductor material is made of an In—Ga—Zn—O-based metal oxide material.   After the first and second oxide semiconductor layer forming steps, channel protection for forming a channel protection layer for protecting the first channel region and the second channel region in the first channel region and the second channel region. The method for manufacturing a thin film transistor substrate according to claim 1, further comprising a layer forming step. A first thin film transistor including an insulating substrate, a first gate electrode provided on the insulating substrate, and a first oxide semiconductor layer provided on the first gate electrode and having a first channel region; and the insulating substrate. A method of manufacturing a thin film transistor substrate, comprising: a second gate electrode provided on the second gate electrode; and a second thin film transistor provided on the second gate electrode and having a second oxide semiconductor layer having a second channel region. ,
A first metal film forming step of forming a first metal film on the insulating substrate;
Patterning the first metal film by etching to form a first gate electrode formed of the first metal film and a first gate electrode forming step of forming a first conductive layer constituting the second gate electrode;
A second metal film forming step of forming a second metal film on the insulating substrate so as to cover the first gate electrode and the first conductive layer;
The second metal film is patterned by etching to form a second conductive layer that constitutes the second gate electrode, the first conductive layer and the second conductive layer, and the first metal layer. A second gate electrode forming step of forming the second gate electrode having a thickness larger than a thickness;
Forming an insulating layer on the insulating substrate so as to cover the first gate electrode and the second gate electrode;
An oxide semiconductor layer forming step of forming an oxide semiconductor layer by applying a liquid oxide semiconductor material on the insulating layer and sintering the oxide semiconductor material;
The oxide semiconductor layer is patterned by etching to form the second oxide semiconductor layer having the first oxide semiconductor layer and the second channel region having a thickness smaller than that of the first channel region. A method for producing a thin film transistor substrate, comprising at least a first oxide semiconductor layer formation step and a second oxide semiconductor layer formation step.   The oxide semiconductor material is made of a metal oxide material containing at least one selected from the group consisting of indium (In), gallium (Ga), aluminum (Al), copper (Cu), and zinc (Zn). The method of manufacturing a thin film transistor substrate according to claim 6.   The method for manufacturing a thin film transistor substrate according to claim 7, wherein the oxide semiconductor material is made of an In—Ga—Zn—O-based metal oxide material.   After the first and second oxide semiconductor layer forming steps, channel protection for forming a channel protection layer for protecting the first channel region and the second channel region in the first channel region and the second channel region. The method of manufacturing a thin film transistor substrate according to claim 6, further comprising a layer forming step.

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