JP5438037B2 - Active filter device - Google Patents

Description

  The present invention relates to an active filter device for suppressing power supply harmonics generated by a load.

The conventional active filter device is connected in parallel to the harmonic generation load connected to the system power supply, detects the load input of the harmonic generation load, extracts the harmonic component contained in the load input, and cancels the harmonic component Compensation output is generated by on / off control of the switching element. In the control of the active filter device, a phase detection unit that detects the power supply voltage phase, an error amount calculation unit that calculates an error amount between the compensation output command and the actual compensation output output by the main circuit for each phase, An error amount integrating means for integrating and storing the error amount for each phase, and a control amount calculating means for calculating the control amount of the compensation output from the integrated value of the stored error amount. Is generated. The error amount integration means has N error integrators corresponding to the control phase, and the error amount is integrated by the error integrator selected by the switching means according to the control phase, and according to the control phase. An error integrated value obtained from the error integrator selected by the switching means is output.
As described above, the conventional active filter device provides an integrated value of the error amount for each phase divided by the control cycle in one power cycle, and enables compensation output synchronized with the power cycle (for example, Patent Document 1). reference).

JP 2001-186752 A

In the conventional active filter device, the number of control cycles in the power cycle is fixed to N, and it is a premise of control that the power cycle and the control cycle are synchronized, and the power cycle and the control cycle are not completely synchronized. If there is an error in the detection of the power supply voltage phase, the error integrator that should be selected according to the actual phase of the power supply cannot be selected correctly, and the control accuracy deteriorates and the harmonic suppression performance cannot be maintained. There was a point.
Further, since it is necessary to synchronize the control cycle with the power supply cycle, when used for power supplies with different power supply frequencies, the control cycle needs to be changed, and the design of the control system becomes complicated.

The present invention has been made to solve the above-described problems, and provides high control even when the power supply cycle and the control cycle are not synchronized or when there is an error in detection of the power supply voltage phase. An object of the present invention is to provide an active filter device capable of obtaining accuracy and harmonic suppression performance.
It is another object of the present invention to make it easy to design a control system without changing the control cycle in accordance with the power supply frequency in the active filter device.

  The active filter device according to the present invention includes a power converter connected in parallel with the load between the AC power source and the load, and generates a compensation output that cancels a harmonic component included in the load input. The active filter device includes a zero-cross detection unit that detects a zero-cross point of the AC power supply voltage, and a compensation output command calculation unit that calculates the compensation output command value that extracts the harmonic component from the load input and cancels the harmonic component. And error amount calculation means for calculating an error amount between the compensation output command value and the detected value of the compensation output, which is the output of the power converter, for each predetermined control period, each having an address and being input N error integrators for integrating the error amounts and storing the error amount integral values and input / output switching means are provided, and the error amounts are input and the error amount integral values are output at each control period. The number of control cycles in each cycle of the AC power supply voltage is counted up based on the error amount integrating means and the zero cross point, and the input / output is performed on the basis of the count value at that time for each control cycle. Address determining means for determining an address of the error integrator selected by the switching means, control amount calculating means for calculating a control amount for each control period based on the error amount integrated value, and power conversion from the control amount Control signal generating means for generating a control signal to the device. In the error amount integrating means, the number N of error integrators in the error amount integrating means is 1 / (fs · dt), which is the reciprocal of the product of the control period dt and the frequency fs of the AC power supply. For each control cycle, the input / output switching means selects an error integrator corresponding to the address determined by the address determination means from among the N error integrators, and the selected error The error amount is input to an integrator, and the error amount integration value stored in the selected error integrator is output from the error amount integration means.

  According to the present invention, the number of error integrators larger than 1 / (fs · dt), which is the reciprocal of the product of the control period dt and the power supply frequency fs, is provided in the error amount integrating means, and each AC power supply voltage is set. Since the number of control cycles in the cycle is counted up and an error integrator is selected for each control cycle based on the count value at that time, the power cycle and the control cycle do not need to be synchronized. For this reason, even when the power supply cycle and the control cycle are not synchronized, or when there is an error in the detection of the power supply voltage phase, the active filter device can maintain high control accuracy and harmonic suppression performance. In addition, a constant control cycle can be used regardless of the power supply frequency, and the control system can be easily designed.

It is a block diagram of the active filter apparatus by Embodiment 1 of this invention. It is a control block diagram which shows the address determination means by Embodiment 1 of this invention. It is a figure which shows the waveform of each part in the active filter apparatus by Embodiment 1 of this invention. It is explanatory drawing of the address determination means by Embodiment 1 of this invention. It is a control block diagram which shows the error amount integration means and control amount calculation means by Embodiment 1 of this invention. It is a figure which shows the waveform of each part in the active filter apparatus by Embodiment 1 of this invention. It is a control block diagram which shows the address determination means by Embodiment 2 of this invention. It is a flowchart explaining the address determination means by Embodiment 2 of this invention. It is a control block diagram which shows the error amount integration means and control amount calculation means by Embodiment 3 of this invention. It is a control block diagram which shows the error amount integration means and control amount calculation means by another example of Embodiment 3 of this invention. It is a control block diagram which shows the error amount integration means and control amount calculation means by another example of Embodiment 3 of this invention. It is a control block diagram which shows the error amount integration means and control amount calculation means by another example of Embodiment 3 of this invention.

Embodiment 1 FIG.
Hereinafter, an active filter device according to Embodiment 1 of the present invention will be described.
1 is a block diagram showing an active filter device for suppressing harmonics generated from a power supply harmonic generation load according to Embodiment 1 of the present invention.
As shown in FIG. 1, a load 2 that is a power harmonic generation load is connected to a system power source 1 as an AC power source, and an active filter device 3 is connected in parallel with the load 2 between the system power source 1 and the load 2. The load current If input to the load 2 is detected by the current detector 4, and a harmonic compensation current Ia (hereinafter simply referred to as a compensation current Ia) as a compensation output for canceling out the harmonic component included in the load current If. ).

  The active filter device 3 detects a power supply voltage zero-cross point and generates a zero-cross signal Szc as a detection signal, a noise filter 6, an AC reactor 7, and a compensation current for detecting a compensation current Ia. A power converter 9 that is a main circuit of the active filter device 3 that includes a detector 8 and an inverter circuit having a plurality of switching elements and outputs a compensation current Ia, and an electrolytic capacitor connected to a DC portion of the power converter 9 10, a gate drive circuit 11 for driving the switching element in the power converter 9, and control signal generation means 12 for generating a control signal from the given control amount Icn to the gate drive circuit 11.

Furthermore, the active filter device 3 extracts an harmonic component from the detected load current If and an address determination unit 13 for determining an input address and an output address used in an error amount integration unit 16 to be described later based on the zero-cross signal Szc. Compensation output command calculation means 14 for calculating a compensation current command value Ia ^* for canceling out the harmonic component, and an error amount ΔIa between the compensation current command value Ia ^* and the compensation current Ia detected by the compensation current detector 8. An error amount calculating means 15 for calculating the error amount, an error amount integrating means 16 for inputting the error amount ΔIa and outputting an error amount integrated value ΔIai, and calculating a control amount Icn based on the error amount integrated value ΔIai and the error amount ΔIa And a control amount calculating means 20 for outputting to the control signal generating means 12.

The error amount integrating means 16 includes N error integrators 17 each having addresses m _{0 to} m _N−1 , an input switching means 18 as an input / output switching means, and an output switching means 19. Then, the input switching unit 18 selects the error integrator 17 that inputs the error amount ΔIa from the error amount calculation unit 15 in accordance with the input address from the address determination unit 13. Each error integrator 17 integrates the error amount ΔIa input to itself to store the error amount integrated value ΔIai, and the output switching means 19 corresponds to the stored error in accordance with the output address from the address determining means 13. The error integrator 17 that outputs the quantity integration value ΔIai is selected.
Reference numeral 21 denotes a power receiving point for connecting the load 2 and the active filter device 3 to the system power supply 1.

  The operation of the active filter device 3 configured as described above will be described with reference to FIG. The active filter device includes a current compensation type that compensates the harmonic current included in the load input and a voltage compensation type that compensates the harmonic voltage. Here, the former current compensation type will be described as an example. However, it can be similarly applied to the voltage compensation type. Further, in this case, the system power supply 1 is a three-phase AC power supply, but can be similarly applied to a single-phase AC power supply.

First, in the power converter 9 which is the main circuit of the active filter device 3, the switching element is ON / OFF controlled by the drive signal from the gate drive circuit 11, and the output current (compensation current Ia) of the power converter 9 is changed to the AC reactor. 7 and the noise filter 6 are supplied to the power receiving point 21.
When the harmonic generation load 2 connected to the system power supply 1 is operated, the load current If including the power supply harmonic is input from the system power supply 1 to the load 2. The harmonic component generated by the load 2 is canceled by the compensation current Ia output from the active filter device 3 and compensated so that the harmonic current does not flow into the system power supply 1.

Next, the operation of the control system of the active filter device 3 will be described.
The address determination means 13, the compensation output command calculation means 14, the error amount calculation means 15, the error amount integration means 16 and the control amount calculation means 20 of the active filter device 3 perform processing in discrete time in the control cycle dt.
Here, the control cycle dt is set to the same cycle as the carrier cycle for controlling on / off of the switching element of the power converter 9. The carrier period may be 1/2 times the control period dt or an integer multiple of 2 or more.

If the control cycle dt [1 / Hz] and the frequency fs [Hz] of the system power supply 1 are determined, an ideal control number Ni generated within one cycle of the power supply voltage can be obtained by Ni = 1 / (fs · dt). Since the error integrator 17 in the error amount integrating means 16 is selected and used for each control cycle within one cycle of the power supply voltage, the number N of error integrators 17 is considered in consideration of errors in the system power supply 1 and voltage zero cross detection. Is larger than Ni, for example, about 1.1 times.
For example, the power supply frequency is 50.1 Hz and the carrier frequency is 15 kHz. At this time, if the control cycle dt is equal to the carrier cycle, the ideal number of times of control Ni generated within one cycle of the power supply voltage is about 299.4, for example, N = 330.

2 is a control block diagram of the address determining means 13, FIG. 3 is a waveform diagram of each part, and FIG. 4 is a diagram for explaining the operation of the address determining means 13.
The zero cross detection means 5 detects a zero cross where the power supply voltage input to the active filter device 3 is switched from negative to positive, and generates a zero cross signal Szc.

The address determining means 13 determines the input address A1 and the output address A2 for selecting the error integrator 17 in the error amount integrating means 16 as follows.
The count-up means 22 receives the control cycle dt and the zero cross signal Szc, and counts up the number of control cycles dt that are clock signals using the zero cross signal Szc as a reset signal. That is, the count value n is generated by executing the count-up at the rising edge of the signal in the control cycle dt. When the zero cross signal Szc is input, the count value n is reset to n = 0 in the next control cycle dt, and the total value Nmax of the control cycle dt is generated for each power cycle. That is, Nmax becomes the count value +1 immediately before the reset of the immediately preceding power cycle. The count value n is output as the input address A1.
The count value n and the total value Nmax of the control period dt, which are outputs from the count-up means 22, are input to the dead time compensation unit 23. The dead time compensator 23 outputs n + 2 obtained by adding 2 counts of the control cycle dt, which is a dead time reflected in the control, to compensate for a control delay caused by a calculation delay in the microcomputer. Output as. At this time, the output address A2 is corrected and output using the total value Nmax of the control cycle dt as an upper limit value as a reset value. That is, when n + 2 becomes equal to or greater than Nmax, Nmax is subtracted and the output address A2 is reset to zero.

  As shown in FIGS. 3 and 4, the input address A <b> 1 is a value counted from 0 every control cycle until the next zero cross point is reached, for example, up to 299. At this time, Nmax of the cycle is 300. In the next cycle, when the input address A1 is generated in the same manner, it becomes 0 to 298. At this time, after the output address A2 increases from 2 to 299, the value obtained by adding 2 when the input address A1 is 298 is the previous cycle. Since it becomes equal to Nmax, it is reset to 0. Note that the total value Nmax of the control cycle dt is determined at the stage when the power cycle ends, and Nmax used as the upper limit value of the output address A2 of the current cycle is Nmax of the immediately preceding cycle. In FIG. Show.

The load current If including harmonics is detected by the current detector 4 every control cycle. The compensation output command calculation means 14 extracts a harmonic component from the detected load current If and calculates a command value Ia ^* of the compensation current Ia that cancels the harmonic component. The error amount calculation means 15 calculates an error amount ΔIa between the compensation current command value Ia ^* and the actual compensation current Ia detected by the compensation current detector 8.

The error amount integrating means 16 receives the error amount integrated value ΔIai from the error amount calculating means 15 and the input address A1 and the output address A2 from the address determining means 13 for each control cycle as follows: Output as follows.
As described above, the error amount integrating unit 16 includes N error integrators 17 each having an address, in this case, 330 error integrators 17, an input switching unit 18, and an output switching unit 19. The input switching means 18 selects the error integrator 17 (hereinafter referred to as A1 error integrator) corresponding to the input address A1, and inputs the error amount ΔIa from the error amount calculation means 15 to the A1 error integrator. The A1 error integrator stores the integrated value of the error amount ΔIa that has already been input, and stores the error amount integrated value ΔIai obtained by integrating the error amount ΔIa in addition to the newly input error amount ΔIa. At the same time, the output switching means 19 selects the error integrator 17 (hereinafter referred to as A2 error integrator) corresponding to the output address A2, and uses the error amount integration value ΔIai stored in the A2 error integrator as the error amount integration. Connect to the output of means 16.

FIG. 5 is a control block diagram showing the flow of the process (error amount calculation means 15, error amount integration means 16 and control amount calculation means 20) until the control amount Icn is derived from the compensation current command value Ia ^* . This control block is a control means using repetitive control and is processed in a microcomputer incorporated in a control circuit in the active filter device 3. In the control block, 24 is a repetitive control unit, 25 is a delay element that delays the output in digital control by one control cycle dt, and 26 is a control gain in the repetitive control unit 24. Further, the control amount calculation means 20 includes the control gain 26 in the repetitive control unit 24 and a proportional gain 27 that multiplies the error amount ΔIa.

As shown in FIG. 5, the error amount calculation means 15 calculates the error amount ΔIa from the difference between the compensation current command value Ia ^* generated by the compensation output command calculation means 14 and the actual compensation current Ia. In the error integrator 17, the error amount ΔIa is summed with the error amount ΔIa before Nmax control cycles dt, and enters the loop of Nmax delay elements 25 again. Each time the zero cross signal Szc is generated, Nmax is updated, and the number Nmax of the delay elements 25 changes.
For example, if the input address A1 at that time is 2, the input address A1 before Nmax control cycles dt is also the same at 2, and the error amount ΔIa is integrated and stored in the error integrator 17 specified by the address. The At that time, the output address A2 is 4, and the error amount integrated value ΔIai stored in the error integrator 17 designated by the address is multiplied by the control gain 26 to obtain the output of the controller 24 repeatedly. Then, the control amount calculation means 20 multiplies the error amount ΔIa from the error amount calculation means 15 by the proportional gain 27 and adds it to the value obtained by multiplying the error amount integral value ΔIai by the control gain 26, so that the error amount ΔIa is zero. The control amount Icn is calculated as follows.

  Then, the control signal generation means 12 generates a control signal for PWM control of the power converter 9 according to the control amount Icn, and the gate drive circuit 11 turns on / off each switching element in the power converter 9 by this control signal. Control off.

The active filter device 3 operates as described above. For example, the waveforms of the respective parts when the load 2 is an air conditioner equipped with an inverter are shown in FIG. The load current If has a periodic waveform synchronized with the power supply cycle. Therefore, the compensation current command value Ia ^* for compensating the power supply harmonics also has a periodic waveform synchronized with the power supply period. That is, the compensation current Ia at the same power supply voltage phase for each power supply cycle has substantially the same output every cycle. Therefore, by detecting the zero cross point of the power supply voltage in one cycle of the power supply and outputting the compensation current Ia corresponding to the address determined by the address determination means 13 every cycle, the compensation current Ia follows the compensation current command value Ia ^* . To be controlled with high accuracy. Thereby, the harmonic component of the load current If is canceled by the compensation current Ia, and the power source current Is of the system power source 1 becomes a sine wave current.

In this embodiment, if there is no disturbance in the detection of the zero cross point of the power supply voltage and the detection can be performed correctly, the total value Nmax of the control periods dt generated for each power supply period is 299, 300, 299, 300,. And operate so that the average value becomes 299.4. Nmax vibrates in this way, and the control cycle dt and the power supply cycle are not synchronized, and the addresses A1 and A2 determined by the address determining means 13 are slightly shifted from the original power supply phase angle. The control response of the integrating means 16 is slow and causes no problem. Further, in the same phase of the power supply voltage, the addresses A1 and A2 determined by the address determining means 13 operate in a oscillating manner, and each error integrator 17 in the error amount integrating means 16 is averaged to the original power supply. The operation is the same as when the phase angle error amount ΔIa is accumulated.
Further, even if a disturbance occurs in the detection of the zero cross point of the power supply voltage and a deviation occurs from the position where it is originally detected, the control cycle dt and the power supply cycle do not need to be synchronized. Each error integrator 17 in 16 operates in the same manner as an error amount ΔIa of the original power supply phase angle is accumulated on average.

Thus, even when the power supply cycle and the control cycle dt are not synchronized or when there is an error in detection of the power supply voltage phase, the active filter device 3 can maintain high control accuracy and harmonic suppression performance. Further, since it is not necessary to synchronize the control cycle dt and the power supply cycle, a constant control cycle dt can be used regardless of the power supply frequency, the carrier cycle used for controlling the switching element can be fixed, and the control system can be designed. Becomes easier.
Further, by setting the number N of error integrators 17 to be about 1.1 times larger than Ni, an error in detecting the power supply system and the zero cross point occurs, and even if the number of Nmax slightly changes, The integrator 17 is not insufficient, and the control can be continued stably.
Further, the control amount calculation means 20 can use the above repeat control and the proportional control of the error amount ΔIa together to follow the change in the instantaneous load current If with a period different from the power supply period, and the power supply harmonics. The suppression ability can be improved.

Embodiment 2. FIG.
Next, an active filter device according to Embodiment 2 of the present invention will be described.
In the first embodiment, the count value n that is the input address A1 and the total value Nmax of the control cycle dt are generated by the count-up means 22, and Nmax of the immediately preceding cycle is used as the upper limit value of the count value n of the current cycle. However, in the second embodiment, the address determination means 13 is configured as follows. The rest of the configuration is the same as in the first embodiment, the overall configuration shown in FIG. 1 is the same, and the operations other than the address determination means 13 are the same as in the first embodiment.

FIG. 7 is a control block diagram of the address determining unit 13 according to the second embodiment, and FIG. 8 is a flowchart for explaining the Nmax determining operation in the address determining unit 13.
The address determination unit 13 includes a control cycle counter 22a, an address total number determination unit 22b, a count-up unit 22c, and a dead time compensation unit 23, and an input address A1 for selecting the error integrator 17 in the error amount integration unit 16 The output address A2 is determined as follows.
The control cycle counter 22a and the count-up unit 22c operate every control cycle, and the address total number determination unit 22b operates when the output of the control cycle counter 22a is updated every zero cross signal. That is, the operation is performed once in one cycle of the power source.

  The control cycle counter 22a receives the control cycle dt and the zero cross signal Szc, and counts up the number of control cycles dt that are clock signals using the zero cross signal Szc as a reset signal. That is, the count-up is executed at the rising edge of the signal in the control cycle dt. When the zero-cross signal Szc is input, the count value is reset to 0 in the next control cycle dt, and the total number of control cycles dt for each power cycle. Nx is generated. That is, Nx becomes the count value +1 immediately before the reset of the immediately preceding power cycle. Further, an average value Nxave of Nx in the past several cycles is also output. This average value Nxave indicates the average number of control cycles dt between the zero-cross point and the zero-cross point in the past several cycles. If Nx vibrates, the calculation is performed up to the decimal part.

The address total number determining means 22b receives the total value Nx of the control cycle dt of the immediately preceding cycle and the average value Nxave of Nx of the past several cycles, and determines the total number Nmax of addresses. This address total number Nmax is determined according to the flow shown in FIG.
First, Nxave is subtracted from Nx to calculate the error Ne, and the total Net of the errors Ne is calculated. Then, a reference address total number NNmax is set, an error adjustment address Ad is provided, and after adjusting the total Net of errors Ne and the reference address total number NNmax, Ad is added to NNmax to determine the address total number Nmax.

Adjustment of the total Net of errors Ne and the total number of reference addresses NNmax is performed by separating the following five conditions (i) to (v) according to the value of Net.
Condition (i) is that the total Net of errors Ne is Net ≧ 2, the reference address total number NNmax is excessive, and cannot be adjusted only by the error adjustment address Ad. Therefore, NNmax is decreased by 1, and the error adjustment address Ad is 0. To do. At that time, the total Net of errors Ne is reset to zero.
Condition (ii) is 2> Net ≧ 1, the reference address total number NNmax is excessive, and the error adjustment address Ad = −1. The total Net of the errors Ne needs to be changed by the adjustment amount, and is reduced by one.
The condition (iii) is 1> Net ≧ −1, the reference address total number NNmax is appropriate, and the error adjustment address Ad = 0.
The condition (iv) is -1> Net ≧ -2, the reference address total number NNmax is insufficient, and the error adjustment address Ad = 1. The total Net of the errors Ne needs to be changed by the adjustment amount, and is increased by 1.
Condition (v) is −2> Net, the total number of reference addresses NNmax is insufficient, and adjustment cannot be made only by the error adjustment address Ad. Therefore, NNmax is increased by 1, and the error adjustment address Ad is set to 0. At that time, the total Net of errors Ne is reset to zero.

  As described above, when the total Net of the errors Ne increases to the positive side, a deviation occurs between the address and the power supply phase by the address determination unit 13 and the total number Nmax of the address is excessive, so that the control is performed to decrease Nmax. On the contrary, when the total Net of the errors Ne becomes larger on the negative side, the total number of addresses Nmax is insufficient, so that control is performed to increase Nmax.

The generated total number of addresses Nmax is input to the count-up unit 22c to which the control cycle dt is input. The count-up unit 22c uses the total number of addresses Nmax as an upper limit value as a reset value, and the number of control cycles dt that are clock signals is used. Count up to generate a count value n. That is, the count-up is executed at the rising edge of the signal in the control cycle dt, and is reset to 0 when the count value n becomes equal to the total number of addresses Nmax. The count value n is output as the input address A1.
The count value n output from the count-up means 22c and the address total number Nmax from the address total number determination means 22b are input to the dead time compensation unit 23. As in the first embodiment, the dead time compensation unit 23 compensates for a control delay caused by a calculation delay or the like in the microcomputer by 2 counts of a control cycle dt that is a dead time reflected in the control. N + 2 obtained by adding is output as the output address A2. At this time, the total address Nmax is used as the reset value as the upper limit value, and the output address A2 is corrected and output. That is, when n + 2 becomes equal to or greater than Nmax, Nmax is subtracted and the output address A2 is reset to zero.

In this embodiment, when generating the count value n to be the input address A1 by counting up the number of control cycles dt, the upper limit value of the number of control cycles used for the reset value is set to the total number of control cycles in the past several cycles. The total number Nmax of addresses determined based on the average value Nxave of Nx and the total control period value Nx of the immediately preceding cycle is used. Also in this case, as in the first embodiment, when the control cycle dt and the power supply cycle are not synchronized, Nmax vibrates, and the addresses A1 and A2 determined by the address determining means 13 vibrate in the same phase of the power supply voltage. Thus, each error integrator 17 in the error amount integrating means 16 is on average the same operation as when the error amount ΔIa of the original power supply phase angle is accumulated. The same effect can be obtained.
Thus, even when the power supply cycle and the control cycle dt are not synchronized or when there is an error in detection of the power supply voltage phase, the active filter device 3 can maintain high control accuracy and harmonic suppression performance. Further, since it is not necessary to synchronize the control cycle dt and the power supply cycle, a constant control cycle dt can be used regardless of the power supply frequency, the carrier cycle used for controlling the switching element can be fixed, and the control system can be designed. Becomes easier.

  In addition, the zero-cross signal Szc is not directly used as a reset signal when generating the count value n serving as the input address A1 by counting up the number of control periods dt, and is generated based on the total number Nx of control periods in the past period. Since the total number Nmax of addresses is used, the pulsation of the zero cross signal Szc due to the voltage detection error becomes strong, and the harmonic suppression performance of the active filter device 3 is improved.

In the first and second embodiments, in order to compensate for the control delay, the output address A2 is advanced by an amount corresponding to two control cycles dt than the input address A1, but the control cycle dt It is also possible to use one piece or a plurality of pieces other than two.
In addition, the input address A1 and the output address A2 may be the same number without considering the control delay.

Embodiment 3 FIG.
Next, an active filter device according to Embodiment 3 of the present invention will be described.
In the first embodiment, the control amount calculation unit 20 calculates the control amount Icn based on the error amount ΔIa and the error amount integration value ΔIai from the error amount integration unit 16. Then, the control amount calculation means 20a different from the first embodiment is provided. The other configurations are the same as those in the first embodiment, the overall configuration shown in FIG. 1 is also the same, and the operations other than the control amount calculation means 20a are the same as those in the first embodiment.

FIG. 9 shows the flow of the process (error amount calculation means 15, error amount integration means 16 and control amount calculation means 20a) until the control amount Icn is derived from the compensation current command value Ia ^{* according} to the third embodiment. It is a control block diagram. Since the operation other than the control amount calculation means 20a is the same as that of the first embodiment, the description thereof is omitted.
The control amount calculation means 20a includes a control gain 26 that multiplies the error amount integration value ΔIai that is the output of the error amount integration means 16, a proportional gain 27 that multiplies the error amount ΔIa, an integration means 28 that integrates the error amount ΔIa, and an integration gain. 29. In the control amount calculation means 20a, the error amount ΔIa from the error amount calculation means 15 and the error amount integration value ΔIai from the error amount integration means 16 are input, and a value obtained by multiplying the error amount integration value ΔIai by the control gain 26 Then, the value obtained by multiplying the error amount ΔIa by the proportional gain 27 and the value obtained by integrating the error amount ΔIa by the integrating means 28 and multiplying by the integral gain 29 are added, and the control amount Icn is set so that the error amount ΔIa becomes zero. Is calculated.
As described above, in the control amount calculation means 20a, the control accuracy is further improved and the power supply harmonic suppression capability can be improved by using the repetitive control and the proportional control and integral control of the error amount ΔIa in combination.

  As shown in FIG. 10, instead of the integration means 28 and the integration gain 29, a control amount calculation means 20b having a differentiation means 30 and a differentiation gain 31 for calculating the amount of change may be used. By using the proportional control and differential control of the amount ΔIa together, the control accuracy can be improved and the power supply harmonic suppression capability can be improved.

Furthermore, as shown in FIG. 11, a control amount calculating means 20c having both an integrating means 28 and a differentiating means 30 may be used, and the above-described repetitive control and error amount ΔIa proportional control, differential control and integral control. By using together, it is possible to further improve the control accuracy and improve the power supply harmonic suppression capability.
Also, as shown in FIG. 12, only the error amount integral value ΔIai may be input to the control amount calculation means 20d, and the control amount Icn may be calculated using the control gain 26 only by repeated control.

1 System power supply as AC power supply 2 Load 3 Active filter device
5 zero cross detection means, 9 power converter, 12 control signal generation means,
13 address determining means, 14 compensation output command calculating means, 15 error amount calculating means,
16 error amount integration means, 17 error integrator, 18 input switching means,
19 Output switching means, 20, 20a to 20d Control amount calculating means,
22 count-up means, 22a control cycle counter,
22b Address total number determining means, 22c counting up means,
23 dead time compensation unit, 28 integrating means, 30 differentiating means, A1 input address,
A2 output address, dt control cycle, Ia compensation current as compensation output,
Ia ^* Compensation current command value as compensation output command value, ΔIa error amount,
ΔIai error amount integral value, Icn control amount, Is power supply current,
If load current as load input, n count value,
Nmax upper limit value (total number of control cycles / total number of addresses), total number of Nx control cycles,
Nxave Average total number of control cycles, Szc zero cross signal.

Claims (12)

In an active filter device that includes a power converter connected in parallel with an AC power supply and a load, and generates a compensation output that cancels a harmonic component included in the load input.
Zero-cross detection means for detecting the zero-cross point of the AC power supply voltage;
Compensation output command calculating means for extracting the harmonic component from the load input and calculating a compensation output command value for canceling the harmonic component;
An error amount calculation means for calculating an error amount between the compensation output command value and the detected value of the compensation output, which is an output of the power converter, for each constant control cycle;
N error integrators each integrating an error amount inputted and storing an error amount integral value and an input / output switching means are provided, and the error amount is inputted every control period. An error amount integrating means for outputting the error amount integrated value;
The number of the control cycles in each cycle of the AC power supply voltage is counted up based on the zero cross point, and the error integrator selected by the input / output switching unit based on the count value at that time for each control cycle. An address determining means for determining an address;
Control amount calculation means for calculating a control amount for each control period based on the error amount integral value;
Control signal generating means for generating a control signal from the control amount to the power converter,
In the error amount integrating means, the number N of error integrators in the error amount integrating means is set to be larger than 1 / (fs · dt) which is the reciprocal of the product of the control period dt and the frequency fs of the AC power supply. In each control cycle, the input / output switching means selects an error integrator corresponding to the address determined by the address determination means from the N error integrators, and the selected error integrator An active filter device, wherein the error amount is input to the selected error integrator, and the error amount integration value stored in the selected error integrator is output from the error amount integration means. The address determining means determines an input address corresponding to the count value at that time and an output address advanced by a predetermined count from the input address for each control cycle as the address,
The error amount integrating means stores the error integrated value obtained by integrating the error amount into the error integrator selected at the input address, and stores the error integrated value in the error integrator selected at the output address. 2. The active filter device according to claim 1, wherein the stored error amount integral value is output.   3. The address determination unit according to claim 1, wherein the address determination unit counts up the number of the control periods using the zero cross point detection signal as a reset signal, and determines the address based on the count value. 4. Active filter device.   The address determining means includes means for generating a total value of the control periods for each period of the AC power supply voltage based on the zero cross point, and the current period based on the total value of the control periods in the past period. The upper limit value of the number of control cycles is determined, the number of control cycles is counted up using the upper limit value as a reset value, and the address is determined based on the count value. Active filter device.   The address determining means counts up the number of the control periods by using the zero cross point detection signal as a reset signal, generates the total number of the control periods for each period of the AC power supply voltage, and in the current period, The input address is determined based on the count value of the number of control cycles, the address advanced by a predetermined count from the input address is corrected with the total number of control cycles in the immediately preceding cycle as an upper limit value, and the output address is The active filter device according to claim 2, wherein the active filter device is determined.   The address determining means includes means for generating a total value of the control periods for each period of the AC power supply voltage based on the zero cross point, and the current period based on the total value of the control periods in the past period. An upper limit value for the number of control cycles is determined, the number of control cycles is counted up using the upper limit value as a reset value, the input address is determined based on the count value, and a predetermined count is advanced from the input address. 3. The active filter device according to claim 2, wherein the output address is determined by correcting the address by the upper limit value.   The upper limit value of the number of control cycles is determined based on an average value of the total number of the control cycles in a plurality of past cycles and a total value of the control cycles of the immediately preceding cycle. 6. The active filter device according to 6.   The active filter device according to claim 1, wherein the load input and the compensation output are currents.   9. The active filter device according to claim 1, wherein the control amount calculation unit further calculates the control amount based on the error amount from the error amount calculation unit.   10. The control amount calculation unit according to claim 9, wherein the control amount calculation unit calculates an integral value by integrating the error amount from the error amount calculation unit, and further calculates the control amount based on the integration value. Active filter device.   11. The control amount calculation unit according to claim 9, wherein the control amount calculation unit calculates a change amount of the error amount from the error amount calculation unit, and further calculates the control amount based on the change amount. Active filter device.   The power converter includes a plurality of switching elements, and outputs the compensation output by on / off control of the plurality of switching elements using a predetermined carrier period, and the carrier period is 1/2 of the control period. The active filter device according to claim 1, wherein the active filter device is a multiple or an integral multiple.

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