JP5427959B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device that stores information using a substance whose electrical characteristics change by passing a current through an element.

In recent years, a resistance change type memory has been studied as a memory to replace a flash memory that is approaching the limit of miniaturization. As an example, a phase change memory using chalcogenide (phase change material) such as Ge ₂ Sb ₂ Te ₅ for a resistance change type storage element has been actively studied.

  The resistance value of the phase change material is controlled between an amorphous state and a crystalline state by Joule heat generated by the applied current. The resistance is high in the amorphous state and low in the crystalline state. These resistance values are associated with stored information.

  In the rewrite operation of the phase change memory, the applied current is controlled according to the stored information. In the reset operation, that is, the information “0” writing operation, a large current is passed for a short time to dissolve the phase change material, and then the current is rapidly decreased. By such control, the phase change material is rapidly cooled to change the phase change material into a high-resistance amorphous state. On the other hand, in the set operation, that is, the writing operation of information ‘1’, the phase change material changes to a low-resistance crystalline state by passing a current sufficient to maintain the crystallization temperature of the phase change material for a long time. In the read operation of the phase change memory, the resistance value of the element is determined by giving a constant potential difference to both ends of the memory element and measuring the current flowing through the element. In this phase change memory, when the shape of the memory element is reduced, the current required to change the state of the phase change material is reduced. For this reason, it is suitable for miniaturization in principle.

  The following two methods are known as methods for highly integrating the phase change memory.

  As a first method, Patent Document 1 discloses a phase change memory device in which memory cells having a configuration in which a selection element made of a Schottky diode and a variable resistance element made of a phase change film are connected in series are stacked.

In FIGS. 15 to 19 of Patent Document 1, polycrystalline n-type silicon is laminated on a word line to form a Schottky diode SD, a chalcogenide material is laminated thereon, and a bit line is further formed thereon. A technique for laminating is disclosed. With this technique, as shown in FIG. 14, memory cells each having a resistance element VR at the intersection of the word line and the bit line are formed. The unit cell area of the memory cell in such a structure becomes 4F ² by processing the word line and the bit line so that the width and interval of the memory cell become the minimum processing dimension F. Further, FIGS. 20 to 25 and FIGS. 27 to 28 of Patent Document 1 describe a technique for halving the effective cell area by stacking the memory cells described above. Specifically, one of the word lines or the bit lines is shared by the upper and lower memory cells, and the other is formed symmetrically in the vertical direction, thereby suppressing the wiring processing step and reducing the execution cell area to 2F ² . To do.

  As a second method, a plurality of through-holes that penetrate all layers are formed in a laminated structure in which gate electrode materials and insulating films are alternately stacked, and a gate insulating film, a channel layer, and a phase change film are formed inside each through-hole. A deposited phase change memory is disclosed in Patent Document 2.

  In FIGS. 3 to 4 of Patent Document 2, through holes are formed after a plurality of layers of a gate electrode and a gate insulating film are stacked, and a gate insulating film, a silicon layer serving as a channel, and a chalcogenide layer are formed in the through holes. A technique for forming a plurality of memory cells in the height direction by forming toward the center is described. Patent Document 2 does not particularly mention the minimum processing dimension.

JP 2005-522045 gazette JP 2008-160004 A

  Prior to this application, the inventors of the present application examined the structure of the memory cell described in the prior art document. Here, a region obtained by projecting a memory cell onto a silicon substrate is referred to as a unit cell area, and a value obtained by dividing the unit cell area by the number of memory cells that can be projected onto the same region is referred to as an effective cell area. Moreover, the expense required when manufacturing one chip | tip is called manufacturing cost. In large-capacity memories that are demanding cost reduction, it is required to reduce both the effective cell area and the manufacturing cost. Below, the problem of a prior art is demonstrated from these two viewpoints.

In the memory cell structure shown in FIGS. 14 to 19 of Patent Document 1, only one resistance element can be arranged at each intersection of a word line and a bit line. Therefore, it is difficult to reduce the effective cell area. The effective cell area can be reduced only to 4F ^{2 in} the structure of FIGS. 14 to 19, and even if memory cells are stacked as shown in FIG. 26, the effective cell area can be reduced only to 2F ² which is half of 4F ² . In addition, wiring and memory cell patterning are required each time the memory cells are stacked, resulting in increased manufacturing costs. Therefore, another approach is necessary.

Next, the memory cell described in Patent Document 2 will be examined. In the memory cell described in Patent Document 2, if the through hole can be processed with the minimum processing size F, the effective cell area when n layers (n = 4 in Patent Document 2) are stacked is 4F ² . The value divided by n. Further, n memory cells can be formed at a time by forming through holes and forming a gate insulating film, a silicon film serving as a channel, and a chalcogenide film. Therefore, the memory cell described in Patent Document 2 is effective in reducing both the effective cell area and the manufacturing cost.

  However, with the technique described in Patent Document 2, it is difficult to process the through hole with the minimum processing dimension F when the miniaturization progresses. In the memory cell described in Patent Document 2, after a through hole is formed, a gate insulating film, a silicon film serving as a channel, and a chalcogenide film are formed toward the center of the through hole. This silicon film cannot be thin unconditionally because the on-resistance of the transistor needs to be sufficiently low. Similarly, the chalcogenide film needs to have a thickness of several atomic layers in order to easily cause a phase transition, and thus cannot be unconditionally thinned. On the other hand, when the miniaturization progresses and the minimum processing dimension F becomes smaller, the thickness required for the silicon film or the chalcogenide film becomes relatively thicker than the minimum processing dimension F. As a result, even if the through hole itself can be formed with the minimum processing dimension F, the thickness of the silicon film or the chalcogenide film inside the through hole cannot be secured, so that the through hole is made larger than the minimum processing dimension F. Need to spread. Therefore, even if a microfabrication technique is established, the memory cell cannot be made small, so that improvement in the degree of integration is hindered.

  In view of the above problems, an object of the present invention is to provide a structure and a circuit of a memory cell and a memory array that are suitable for miniaturization and reduce both effective cell area and manufacturing cost in a phase change memory. It is in. The above object and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  First, in the semiconductor memory device, a plurality of first wirings extending in a first direction, a plurality of second wirings extending in a second direction different from the first direction, and the plurality of the plurality of wirings A plurality of first diodes connected to the first wiring, a plurality of first memory cells connected in series to the plurality of first diodes, and between the plurality of first memory cells and the plurality of second wirings A plurality of first transistors provided with source-drain paths, a plurality of second memory cells connected in series to the plurality of first diodes, the plurality of second memory cells, and the plurality of second wirings A plurality of second transistors provided with a source-drain path therebetween, an x th gate of the plurality of second transistors, and an (x + 1) th gate of the plurality of first transistors. Multiple connected A plurality of first drive circuits for supplying a drive voltage to the plurality of first wires, and a plurality of second drive circuits for supplying a drive voltage to the plurality of third wires. Each of the plurality of first memory cells has a third transistor in which a source-drain path is provided between the plurality of first diodes and the plurality of second wirings; and A first storage element connected in parallel to the source-drain path and having stored information written by current, wherein each of the plurality of second memory cells has a source-drain path of the plurality of first diodes And a fourth transistor provided between the plurality of second wirings and a second transistor in which stored information is written by a current connected in parallel to the source-drain path of the fourth transistor Each of the plurality of first wirings, and different driving circuits among the plurality of first driving circuits are connected to each of the plurality of first wirings, and the plurality of second wirings are connected to each of the plurality of third wirings. Among the drive circuits, different drive circuits are connected.

  Second, the semiconductor memory device includes a plurality of first wirings extending in a first direction, a plurality of second wirings extending in a second direction different from the first direction, and the plurality of the plurality of second wirings. A plurality of first diodes connected to the first wiring, a plurality of first memory cells connected in series to the plurality of first diodes, and between the plurality of first memory cells and the plurality of second wirings A plurality of first transistors provided with source-drain paths, a plurality of second memory cells connected in series to the plurality of first diodes, the plurality of second memory cells, and the plurality of second wirings A plurality of second transistors provided with a source-drain path therebetween, an x th gate of the plurality of second transistors, and an (x + 1) th gate of the plurality of first transistors. Multiple connected A plurality of first driving circuits for supplying a driving voltage to each of the plurality of first wirings, and a plurality of first driving circuits for supplying a driving voltage to each of the plurality of third wirings. Each of the plurality of first memory cells includes a third transistor whose source-drain path is provided between the plurality of first diodes and the plurality of second wirings; A first memory element connected in parallel to the source-drain path of a third transistor and into which stored information is written by current, and each of the plurality of second memory cells has a plurality of source-drain paths A fourth transistor provided between the first diode of the first transistor and the plurality of second wirings; and a current connected to the source-drain path of the fourth transistor and connected to the memory information by current. A second memory element into which the odd-numbered ones of the plurality of first wirings are short-circuited to each other, and the even-numbered ones of the plurality of first wirings are short-circuited to each other, Different driving circuits among the plurality of first driving circuits are connected to the odd-numbered and even-numbered wirings, respectively, and the third wirings are different from each other among the plurality of second driving circuits. A drive circuit is connected.

Third, the semiconductor memory device includes a plurality of first wirings extending in a first direction, a plurality of second wirings extending in a second direction different from the first direction, and the plurality of the plurality of second wirings. A plurality of first diodes connected to the first wiring, a plurality of first memory cells connected in series to the plurality of first diodes, and between the plurality of first diodes and the plurality of second wirings A plurality of first transistors provided with the source-drain paths, a plurality of second memory cells connected in series to the plurality of first diodes, and between the plurality of first diodes and the plurality of second wirings Are connected to a plurality of second transistors provided with source-drain paths, an mth gate of the plurality of second transistors, and an (m + 1) th gate of the plurality of first transistors. Double The third wiring (m is a natural number), a plurality of first drive circuits for supplying a driving voltage to each of the plurality of first wirings, and a plurality of first driving circuits for supplying a driving voltage to each of the plurality of third wirings. Each of the plurality of first memory cells includes a third transistor having a source-drain path provided in series between the plurality of first diodes and the plurality of second wirings. A first storage element provided in parallel with the source-drain path of the third transistor and into which stored information is written by a current. Each of the plurality of second memory cells has a source-drain path A fourth transistor provided in series between the plurality of first diodes and the plurality of second wires; and a current provided in parallel with the source-drain path of the fourth transistor. A plurality of third wirings, wherein each of the plurality of first wirings is connected to a different driving circuit among the plurality of first driving circuits. Of the plurality of third wirings, the even number of the plurality of third wirings are short-circuited to each other, and the odd numbered and even numbered of the plurality of third wirings are connected to the second driving circuit. Different drive circuits are connected to each other.

  According to the present invention, it is possible to reduce the bit cost of a semiconductor memory device.

It is a figure which shows the example of a circuit structure of the memory array of Example 1 of this invention. FIG. 2 is a diagram illustrating an example of a circuit configuration of a memory block illustrated in FIG. 1. FIG. 2 is a three-dimensional schematic diagram of the memory array illustrated in FIG. 1. FIG. 4 is a cross-sectional view of a part of the memory array shown in FIG. 3. It is a figure which shows the example of the layout pattern of the anode line of the memory array described in FIG. FIG. 2 is a diagram showing an example of a layout pattern of cell selection gate lines of the memory array shown in FIG. 1. It is a figure which shows the example of the layout pattern of the cell chain selection line of the memory array shown in FIG. It is a figure which shows the example of the detailed circuit structure in a part of memory array as described in FIG. FIG. 2 is a diagram illustrating an example of operating voltages of an anode line and a bit line in the memory array illustrated in FIG. 1. FIG. 2 is a diagram illustrating an example of an operating voltage of a cell chain selection line in the memory array illustrated in FIG. 1. FIG. 2 is a diagram illustrating an example of an operating voltage of a first-layer cell selection gate line in the memory array illustrated in FIG. 1. FIG. 2 is a diagram illustrating an example of an operating voltage of a second layer cell selection gate line in the memory array illustrated in FIG. 1. FIG. 2 is a diagram illustrating an example of operating voltages of a third-layer cell selection gate line in the memory array illustrated in FIG. 1. FIG. 2 is a diagram showing an example of operating voltages of a cell select gate line in a fourth layer in the memory array shown in FIG. FIG. 5 is a cross-sectional view of a part of the memory array shown in FIG. 4 and a diagram showing operating voltages in each of a reset operation, a set operation, and a read operation of the memory cell array. 10 is a diagram illustrating an example of a layout pattern of comb-shaped wiring in Example 2. FIG. 10 is a diagram illustrating an example of a layout pattern of common wiring in Example 2. FIG. It is a figure which shows the wiring format in the memory array of FIG. FIG. 3 is a main block diagram of a memory block illustrated in FIG. 2. FIG. 20 is a diagram illustrating a state of a cell chain in the memory block illustrated in FIG. 19. It is a figure which shows the example of selection operation | movement of the memory array in Example 2 of this invention. It is a figure which shows the state of the cell chain in the memory array of FIG. It is a figure which shows another example of selection operation | movement of the memory array in Example 2 of this invention. It is a figure which shows another example of selection operation of the memory array in Example 2 of this invention. It is a figure which shows the example of the layout pattern of the cell selection gate line of the memory array in Example 2 of this invention. It is a figure which shows the example of a circuit structure of the memory array in Example 2 of this invention. FIG. 27 is a diagram showing an example of a detailed circuit configuration in a part of the memory array shown in FIG. 26. It is a figure which shows another example of the layout pattern of the cell selection gate line of the memory array in Example 2 of this invention. It is a figure which shows another example of the circuit structure of the memory array in Example 2 of this invention. FIG. 30 is a diagram showing an example of a detailed circuit configuration in a part of the memory array shown in FIG. 29. It is a figure which shows the example of the layout pattern of the anode line of the memory array in Example 3 of this invention. It is a figure which shows another example of the layout pattern of the anode line of the memory array in Example 3 of this invention. It is a figure which shows the example of a circuit structure of the memory array in Example 3 of this invention. FIG. 34 is a diagram showing an example of a detailed circuit configuration in a part of the memory array shown in FIG. 33. It is a figure which shows another example of the circuit structure of the memory array in Example 3 of this invention. FIG. 36 is a diagram showing an example of a detailed circuit configuration in a part of the memory array shown in FIG. 35. It is a figure which shows another example of the circuit structure of the memory array in Example 3 of this invention. FIG. 38 is a diagram showing an example of a detailed circuit configuration in a part of the memory array shown in FIG. 37. It is a figure which shows the example of the layout pattern of the cell chain selection line of the memory array in Example 4 of this invention. It is a figure which shows the example of a circuit structure of the memory array in Example 4 of this invention. FIG. 41 is a diagram illustrating an example of a detailed circuit configuration in a part of the memory array illustrated in FIG. 40. It is a figure which shows another example of the circuit structure of the memory array in Example 4 of this invention. FIG. 43 is a diagram showing an example of a detailed circuit configuration in a part of the memory array shown in FIG. 42. It is a figure which shows another example of the circuit structure of the memory array in Example 4 of this invention. FIG. 45 is a diagram showing an example of a detailed circuit configuration in a part of the memory array shown in FIG. 44. It is a figure which shows the example of a structure of the memory bank of Example 5 of this invention. FIG. 47 is a diagram showing an example of an anode driver layout in the memory array drive circuit shown in FIG. 46; It is a figure which shows another example of a structure of the memory bank of Example 5 of this invention. It is a figure which shows another example of a structure of the memory bank of Example 5 of this invention. It is a figure which shows the further another example of a structure of the memory bank of Example 5 of this invention. It is a figure which shows the structural example of the memory module using the phase change memory in the semiconductor device of this invention. It is a figure which shows the structural example of the memory module using the phase change memory in the semiconductor device of this invention. It is a figure which shows the structural example of the applied apparatus using the phase change memory in the semiconductor device of this invention. It is a figure which shows the structural example of the phase change memory in the semiconductor device of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. In addition, it is to be noted in advance that the portions that describe the characteristic configuration are not limited to the respective embodiments, and that similar effects can be obtained when a common configuration is adopted. In addition, the circuit elements constituting each memory cell of the embodiment are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor) when not particularly limited.

<< Memory array and memory array drive circuit configuration >>
FIG. 1 shows a memory array and a memory array drive circuit group (hereinafter referred to as a memory array drive circuit) according to this embodiment. The memory array MA is configured as follows. First, a matrix of m rows and n columns is constituted by m anode lines ANL0 to ANL (m−1) and n bit lines BL0 to BL (n−1) (m and n are natural numbers). Then, memory cell groups MB00 to MB (m−1) (n−1) are arranged at the intersections of the matrix of m rows and n columns (this memory cell group MB is hereinafter referred to as “memory block”). Each memory block MB includes two pairs of cell chains. In FIG. 1, each of two ellipses provided at each intersection of the anode line ANL and the bit line BL corresponds to one cell chain, and a memory block is a set of two ellipses. In FIG. 1, the memory block MB00 provided at the intersection of the anode line ANL0 and the bit line BL0 is clearly shown as a representative example.

  Details of each memory block MB are as follows. First, a diode PD is connected to each of the m anode lines (see FIG. 2). Two pairs of cell chains are connected in series with the diode. In this embodiment, a cell chain refers to a structure in which k memory cells are connected in series in the z-axis direction (although it is represented as one ellipse in FIG. 1) (the z-axis direction is This is a height direction with respect to the substrate and a direction perpendicular to both the anode line ANL and the bit line BL). Therefore, in each of the m × n memory blocks MB, k × 2 memory cells corresponding to two pairs of cell chains are connected in series to the diode PD described above. As a result, the memory array MA in this embodiment has m × n × k × 2 memory cells. Each of the memory cells is provided with a transistor TG whose source-drain path is provided in series with respect to the diode PD and the bit line BL, and in parallel with the transistor TG, as indicated by MC in FIG. A storage element STG into which information is written by current.

  Next, the cell chain selection line CSL and the cell selection gate line group MCGL will be described. As described above, since the memory array in the present embodiment has two pairs of cell chains (that is, 2k memory cells) in each of the m rows and n columns matrix, only by specifying m rows and n columns, The selection / non-selection of the memory cell cannot be specified. A wiring group for specifying this is the cell chain selection line CSL and the selected cell gate line group MCGL.

First, one of two cell chains is selected by the cell chain selection line CSL. In FIG. 1, an arrow is shown for one of the two ellipses from each of the cell chain selection lines CSL. This arrow corresponds to selecting one from two pairs of cell chains. Here, the cell chain selection line CSL is commonly connected to two adjacent cell chains. For example, the x-th cell chain selection line CSLx selects both the cell chain connected to the anode line ANL (x-1) and the cell chain connected to the anode line ANLx. That is, the cell chain selection line CSLx is selected from the cell chain selection gate CCG included in the cell chain CCO connected to the anode line ANL (x-1) and the cell chain selection included in the cell chain CCE connected to the anode line ANLx. The gates CCG are connected to both gates (x is an integer satisfying 1 ≦ x ≦ (m−1)). Similarly, the cell selection gate line group MCGLy includes the transistor TG of the memory cell MC included in the cell chain CCO connected to the anode line ANL (x-1) and the memory included in the cell chain CCE connected to the anode line ANLx. It is connected to both gates of the transistor TG of the cell (y is an integer satisfying 1 ≦ y ≦ (m−1)). With such a wiring structure, two pairs of cell chains can be formed within an area of 4F ² with respect to the minimum processing dimension F. Details thereof will be described with reference to FIGS.

  Even if one is selected from two pairs of cell chains, the cell chain includes k memory cells. Therefore, the selected cell gate line group MCGL specifies which memory cell is selected from the k memory cells included in the cell chain. In FIG. 1, each of the selected cell gate line groups MCGL is represented as one wiring. However, this is a notation for simplification, and is actually a group of k wirings as shown in FIG. By applying a selection or non-selection voltage to each of the k wirings, the memory cell can be selected / unselected. In FIG. 1, from each of the selected cell gate line groups MCGL, an arrow is shown for one of the two ellipses. This arrow indicates which of the k memory cells in the cell chain is selected / unselected. It indicates whether or not. The detailed configuration of these cell chains will be described later.

  The anode lines ANL0 to ANL (m−1) are driven by the anode driver group ANDBK. The cell selection gate line groups MCGL0 to MCGLm are driven by the cell selection gate driver group MCGDBK. Further, the cell chain selection lines CSL0 to CSLm are driven by a cell chain selection driver group CSDBK. Here, different anode drivers ANDBK are connected to each of the anode lines ANL. The same applies to the cell chain selection line CSL and the cell selection gate line group MCGL.

  Here, although the detailed structure of the wiring will be described later, each of the anode lines ANL0 to ANL (m-1), the cell selection gate line groups MCGL0 to MCGLm, and the cell chain selection lines CSL0 to CSLm has a minimum width and interval. A wiring structure patterned in the shape of dimension F is formed. Also, anode lines ANL0 to ANL (m−1), cell selection gate line groups MCGL0 to MCGLm, and cell chain selection lines CSL0 to CSL0m are formed in this order on the silicon substrate.

  A bit line selection circuit BSLC and a non-selection bit line voltage power supply circuit USBVS are connected to both ends of each bit line to the bit lines BL0 to BL (n-1), respectively. The former bit line selection circuit BSLC selects any one of the bit lines BL0 to BL (n-1) and electrically connects it to the common data line CBL. The common data line CDL is connected to a rewrite circuit WC and a sense amplifier SA for rewriting information of a memory cell selected from the memory array MA and reading the information. The latter non-selected bit line voltage power supply circuit USBVS supplies non-selected voltages to all bit lines in the standby state and (n−1) bit lines excluding the selected bit lines in the read / write operation. Although details will be described when the operation of the memory array is described, erroneous writing to other than the selected cell chain can be avoided by this power feeding mechanism.

<Circuit configuration of cell chain>
FIG. 2 is a diagram showing details of the circuit configuration at the intersection of the anode line ANL0 and the bit line BL0 in the memory array shown in FIG. In this circuit configuration, two cell chains PCCE and PCCO arranged in parallel are connected in series to a polysilicon diode PD connected to the anode line ANL0.

  Each of the cell chains PCCE and PCCO has a configuration in which k memory cells MC0 to MC (k−1) and a cell chain selection gate CCG are connected in series. The memory cells MC0 to MC (k-1) are composed of a MOS transistor TG serving as a transmission gate and a variable resistance type storage element STD. In each memory cell MC, the source-drain path of the MOS transistor TG and the storage element STD are connected in parallel to each other. One of the cell selection gate line groups is connected to the gate electrode of the transmission gate TG of these memory cells. A cell chain selection line is connected to the cell chain selection gate CCG.

  More specifically, for example, in one cell chain PCCE, each of the memory cells MC0 to MC (k−1) is a cell selection gate line CGL00 to CGL0 (k−) that is a component of the cell selection gate line group MCGL0. Controlled by 1). The cell chain selection gate CCG is controlled by a cell chain selection line CSL0. Similarly, in the other cell chain PCCO, each of the memory cells MC0 to MC (k−1) is a cell selection gate line CGL10 to CGL1 (k−1) which is a component of the cell selection gate line group MCGL1. Be controlled. The cell chain selection gate CCG is controlled by the cell chain selection line CSL1.

《Memory array structure》
FIG. 3 is a bird's-eye view particularly showing a part of the memory array MA extracted from FIG. Polysilicon diodes PD are periodically formed in the extending direction of the anode lines 2 on the plurality of anode lines 2 formed by patterning the metal film at a pitch twice the minimum processing dimension F. Here, although omitted in the figure, the metal film forming the anode line is formed on the insulating film deposited on the silicon substrate. The polysilicon diode PD has a structure in which a polysilicon layer 4p doped with p-type impurities, a polysilicon layer 5p doped with low-concentration impurities, and a polysilicon layer 6p doped with n-type impurities are stacked.

  The stacked films of the gate polysilicon layers 21p, 22p, 23p, 24p, 61p and the insulating film layers 11, 12, 13, 14, 15, 71 are patterned in a stripe shape in a direction parallel to the anode line 2, The stripe polysilicon line portions of the polysilicon films 21p, 22p, 23p, 24p, 61p and the insulating film layers 11, 12, 13, 14, 15, 71 are arranged immediately above the space between the anode lines, and the gate polysilicon layer Space portions of stripes of the laminated film of 21p, 22p, 23p, 24p, 61p and insulating film layers 11, 12, 13, 14, 15, 71 are formed immediately above the anode line. The bit line 3 has a stripe shape formed by patterning a metal film at a pitch twice as large as the minimum processing dimension F, and extends in a direction perpendicular to the anode line 2, and n-type polysilicon 38 p is formed on the insulating film 71. Is arranged through.

  Below the bit line 3 in the space portion of the laminated film of the gate polysilicon layers 21p, 22p, 23p, 24p, 61p and the insulating film layers 11, 12, 13, 14, 15, 71, the gate polysilicon layers 21p, 22p, The gate insulating film 9, the channel polysilicon layer 8p, the diffusion prevention film 10, and the phase change material layer 7 are formed on the side walls 23p and 24p, the side walls of the insulating film layers 11, 12, 13, 14 and the lower side wall of the insulating film 15. Laminated sequentially. Diffusion prevention film 10 is a layer for preventing diffusion between phase change material layer 7 and channel polysilicon layer 8p. An insulating film layer 91 is embedded between the facing phase change material layers 7. A gate insulating film layer 9 and a channel polysilicon layer 8p are stacked on the upper side wall of the insulating film layer 15 and the gate polysilicon layer 61p, and on the lower side wall of the insulating film layer 71. An insulating film layer 92 is buried between the channel polysilicon layers 8p facing each other, and a gate insulating film layer 9 and a polysilicon layer 38p are stacked above the insulating film layer 71. At the bottom of the lower portion of the bit line 3 in the space portion of the laminated film of the gate polysilicon layers 21p, 22p, 23p, 24p, 61p and the insulating film layers 11, 12, 13, 14, 15, 71, The surface and channel polysilicon layer 8p are in contact. The metal wiring layer 3 serving as the bit line and the polysilicon diode PD are connected to the gate polysilicon layers 21p, 22p, 23p, 24p, 61p and the insulating film layer via the polysilicon layer 38p, the channel polysilicon layer 8p, and the polysilicon diode PD. 11, 12, 13, 14, 15, 71 are connected by opposing side surfaces of the laminated film pair.

  Under the space portion of the laminated film of the gate polysilicon layers 21p, 22p, 23p, 24p, 61p and the insulating film layers 11, 12, 13, 14, 15, 71, and the lower portion of the space portion of the metal wiring 3 serving as the bit line, The channel polysilicon layer 8p, the polysilicon layer 38p, the phase change material layer 7, and the diffusion prevention film 10 are removed, and become a space portion of the polysilicon diode PD on the metal wiring layer 2 serving as the anode line. An insulating film 33 is embedded in this space portion. That is, the polysilicon layers 8p and 38p, the phase change material layer 7 and the diffusion preventing film 10 are formed of the gate polysilicon layers 21p, 22p, 23p, 24p and 61p and the insulating film layers 11, 12, 13, 14, 15, 71. It is formed in a region surrounded by the laminated film and the insulating layer 33 (hereinafter referred to as “connection hole” in this specification).

  In such a structure, a device group formed on one side wall of the connection hole corresponds to the cell chain CCE or CCO shown in FIG. That is, the gate electrodes of the transmission gates TG of the memory cells MC0 to MC (k−1) (here, k = 4) are formed by the gate polysilicon layers 21p, 22p, 23p, and 24p shown in FIG. The Therefore, the memory cells MC0 to MC (k−1) are formed on the sidewalls of these gate polysilicon layers 21p, 22p, 23p, and 24p. More specifically, the gate insulating film 9 and the channel deposited on the side walls of the gate polysilicon layers 21p, 22p, 23p, 24p, the side walls of the insulating film layers 11, 12, 13, 14 and the side walls of the insulating film 15 are formed. A transmission gate TG is formed by the polysilicon layer 8p. Further, at the same height as the gate polysilicon layers 21p, 22p, 23p, and 24p, the channel polysilicon layer 8p becomes a channel of the transmission gate TG in the memory cells MC0 to MCk. Further, the channel polysilicon layer 8p serves as a drain electrode or a source electrode of each transmission gate TG at the same height as the side walls of the insulating film layers 11, 12, 13, 14 and the lower part of the side wall of the insulating film 15.

  By corresponding to the position where the transmission gate TG is formed, the position where the storage element STD is formed can be easily understood. That is, the storage elements STD of the memory cells MC0 to MCk are formed by the diffusion prevention film 10 and the phase change material layer 7 in regions corresponding to the same height as the gate polysilicon layers 21p, 22p, 23p, and 24p. Accordingly, the portion functioning as the storage element STD is a region having the same height as the gate polysilicon layers 21p, 22p, 23p, and 24p. Therefore, the current path flowing through the memory element STD is formed in the order of the diffusion prevention film 10 -phase change material layer 7 -diffusion prevention film 10 between the drain electrode and the source electrode of the transmission gate TG.

  The gate electrode of the cell chain selection gate CCG is formed by the gate polysilicon layer 61p shown in FIG. Therefore, the cell chain selection gate CCG is formed on the side wall of the gate polysilicon layer 61p. More specifically, the channel polysilicon layer 8p becomes the channel of the cell chain selection gate CCG at the same height as the gate polysilicon layer 61p. Further, the channel polysilicon layer 8p serves as a source electrode or a drain electrode of the cell chain selection gate CCG at the same height as the side wall of the insulating film layer 71 and the upper part of the side wall of the insulating film 15. In order to suppress contact resistance with the metal film 3 serving as the bit line, the polysilicon layer 38p serving as the source electrode exhibits n-type conductivity by diffusing impurities such as phosphorus.

  FIG. 4 is a cross-sectional view showing the overall structure of the memory array including the AA ′ cross section shown in FIG. 3. A feature of this structure is that the memory array MA shown in FIG. 1 is stacked on a MOS transistor formed on the semiconductor substrate 1. In particular, this transistor is used to connect the metal wiring layer 3 which is a bit line in the memory array MA and the common data line CDL. In the figure, an element isolation trench STI, a transistor gate GATE, a gate insulating film GOX, and a diffusion layer DIF are shown for the MOS transistor. In addition, as a structure for connecting the transistor and the metal wiring layer 3 as a bit line, the interlayer insulating films ILD1, ILD2, ILD3, ILD4, ILD5, wiring layers M1, M2, and devices on the semiconductor substrate and M1 are connected. Contact hole C1, a contact hole C2 connecting M1 and M2, a contact hole BLC connecting a metal wiring layer 3 serving as a bit line and a MOS transistor formed on the semiconductor substrate 1, and an interlayer embedded between polysilicon diodes PD A portion composed of the insulating film 31 is shown in FIG.

With the above configuration, to face the side wall of the connection hole formed in the cross-sectional area of 4F ^2, two phase-change chain cells are formed. Therefore, the cross-sectional area necessary for forming the phase change chain cell can be 2F ² . Thus, the bottom area required for forming one memory cell is smaller than the conventional, it can be one of the k component of 2F ^2. Here, the value of k is the same as the number of stacked memory cells, and in the case of FIG. 3, k = 4.

《Memory array wiring structure》
Next, the wiring structure of the memory array will be described. 1 to 4, the anode lines ANL0 to ANL (m−1) and the bit lines BL0 to BL (n−1) are arranged to cross each other. Here, paying attention to one memory block MB00, the gate electrode of each transmission gate TG in the memory cells MC0 to MC (k−1) (here, k = 4) constituting the cell chains CCE and CCO is an anode line. The gate polysilicon layers 21p, 22p, 23p and 24p are individually deposited in a stripe shape in the extending direction. That is, as shown in FIG. 5, when the direction in which m anode lines ANL0 to ANL (m-1) extend is defined as the Y direction and the direction in which the bit lines extend is defined as the X direction, The (m + 1) cell selection gate lines CGL00 to CGLm0 to which the gate electrode of the transmission gate TG is connected are extended in the Y direction as shown in FIG. Further, the cell selection gate lines CGL01 to CGLm1, CGL02 to CGLm2 to which the gate electrodes of the transmission gates TG in the second to fourth memory cells MC1 to MC (k−1) (here, k = 4) are connected. , CGL03 to CGLm3 also have the same wiring structure as FIG.

  Furthermore, the gate electrode of the cell chain selection gate CCG is also formed by the gate polysilicon layer 61p deposited individually in stripes in the direction in which the anode line extends. That is, (m + 1) cell chain selection lines CSL0 to CSLm to which the gate electrode of the cell chain selection gate CCG is connected are extended in the Y direction as shown in FIG.

  As described above, the cell selection gate lines CGL0 (k−1) to CGLm (k−1) (here, k = 1 to 4) and the cell chain selection lines CSL0 to CSLm have the same wiring pattern. Thus, the connection holes described in FIGS. 3 to 4 can be formed by a single etching process. The polysilicon layer 8p, the phase change material layer 7, the insulating layer 9, and the diffusion prevention film 10 in the connection hole are each formed in a single step. That is, a plurality (eight in this case) of memory cells can be formed at one time in the connection hole. Therefore, it is possible to realize a three-dimensional memory with fewer steps or manufacturing costs than before, and the bit cost can be reduced.

  The relationship between the number of memory blocks and the number of cell chains in the memory array and the number of wirings is as follows. When m memory blocks (where m is an integer of 1 or more) are arranged in the direction in which the bit lines extend (that is, the X direction), as shown in FIG. 5, m anode lines ANL0 to ANL. (M-1) A wiring pattern of the metal layer 2 is necessary. Since one memory block has two cell chains, cell chains CCE and CCO are formed immediately above the respective anode lines. However, as will be described later, the cell selection gate lines CGL1 (k−1) to CGL (m−1) (k−1) (where k = 1 to 4) and the cell chain selection lines CSL1 to CSL (m− Since each of 1) is connected to two memory blocks adjacent in the bit line direction, every two cell chains CCE and CCO are arranged. For example, as shown in the figure, when attention is paid to the bit line in the y column, the cell chains CCO of the memory blocks MB0y and MB1y are arranged adjacent to each other, and the cell chains CCE of the memory blocks MB1y and MB2y are arranged adjacent to each other. .

  Next, cell selection gate lines CGL0 (k-1) to CGLm (k-1) (k = 1 to 4) and cell chain selection lines CSL0 to CSLm connected to the cell chain are shown in FIGS. Thus, (m + 1) lines are required. This is because the polysilicons 21p, 22p, 23p, 24p forming the cell selection gate lines CGL0 (k-1) to CGLm (k-1) (where k = 1 to 4) and the cell chain selection lines CSL0 to CSL0. This is because the polysilicon 61p forming the CSLm is formed immediately above the space portion of the wiring pattern of the metal layer 2 as the anode lines ANL0 to ANL (m-1), as described with reference to FIGS.

  First, polysilicon cells 21p, 22p, 23p, and 24p forming cell selection gate lines CGL0 (k-1) to CGLm (k-1) (where k = 1 to 4) have memory cells on both side walls. It is formed. Among these, cell select gate lines CGL0 (k−1) and CGLm (k−1) (where k = 1 to 4) formed on the outer peripheral portion of the memory array have memory as shown in FIG. Memory cells formed on the inner sidewalls of the array are used. These memory cells are constituent elements of the cell chain CCE in the memory blocks MB0y and MB (m−1) y when attention is paid to the bit line in the y-th column as shown in FIG. 6, for example. For the other cell selection gate lines CGL1 (k-1) to CGL (m-1) (k-1) (where k = 1 to 4), the memory cells formed on both sidewalls are memory blocks. It is used as a component of cell chain CCO in MB0y and MB (m-1) y or cell chain CCE and CCO in memory blocks MB1y and MB (m-2) y.

  Next, cell chain selection gates CCG are formed on both sidewalls of polysilicon 61p forming cell chain selection lines CSL0 to CSLm. Among these, cell chain selection lines CSL0 (k-1) and CGLm (k-1) (where k = 1 to 4) formed on the outer periphery of the memory array are shown in FIG. A MOS transistor formed on the inner side wall of the array is used. These MOS transistors are, for example, the cell chain selection gate CCG of the cell chain CCE in the memory blocks MB0y and MB (m−1) y when attention is paid to the bit line in the y-th column as shown in FIG. For the other cell chain select lines CSL1 to CSL (m−1), the MOS transistors formed on both side walls are the cell chains CCO in the memory blocks MB0y and MB (m−1) y, or the memory blocks MB1y and MB. (M-2) Cell chain CCE in y, used as CCO cell chain selection gate CCG.

  As described so far, the memory array in this embodiment has three systems of control lines extending in the Y direction. In order to distinguish these control lines from the viewpoint of function, they are referred to as anode lines ANL0 to ANL (m−1), cell selection gate line groups MCGL0 to MCGLm, and cell chain selection lines CSL0 to CSLm, respectively. Since these control lines are orthogonal to the bit lines, any one system can be called a word line as in the conventional memory.

《Memory array operation》
As shown in FIG. 1, the memory array of this embodiment is composed of memory blocks formed at intersections of a plurality of bit lines and a plurality of anode lines. Hereinafter, the reset operation, the set operation, and the read operation of the memory array will be described with reference to FIGS.

  FIG. 8 shows a part of the memory array shown in FIG. For the sake of simplicity, only the memory blocks formed at the intersections of the bit lines BL0 and BL1 and the anode lines ANL0 to ANL3 are shown in FIG. Further, the cell selection gate lines CGS00 to CGS40 are indicated by a one-dot chain line, and the cell chain selection lines CSL0 to CSL4 are indicated by a two-dot chain line. Here, for the sake of simplicity, the cell selection gate lines CGS0 (k-1) to CGS4 (k-1) (where k = 2 to 4) are omitted, but these are the cell selection gate lines CGS00 to CGS40. The wiring structure is made in the same way as. Assuming that the lowermost memory cell MC0 in the cell chain CCE of the memory block MB00 is selected, the reset operation, the set operation, and the read operation are performed as follows.

  First, as shown in FIG. 9, the bit line BL0 to be selected and the anode lines ANL1 to ANL3 held in the non-selected state are set to 0 V in any operation. Further, the anode line ANL0 to be selected and the bit line BL1 held in a non-selected state are driven to 5V during the reset operation, 4V during the set operation, and 2V during the read operation. In such a voltage application state, paying attention to the potential difference between the anode line and the bit line with respect to the diode in the memory block, the anode line ANL0 is driven to a positive voltage, and the bit line BL0 is held at the ground voltage. Only the memory block MB00 is in the forward bias state. That is, the memory block MB00 is selected. On the other hand, in the memory blocks MB10 to MB30 in which both the anode lines ANL1 to ANL3 and the bit line BL0 are held at the ground voltage (0 V), the potential difference is zero. Therefore, the non-selected state is maintained. Similarly, the potential difference of the memory block MB01 in which both the anode line ANL0 and the bit line BL1 are driven to the same positive voltage is zero. Therefore, the non-selected state is maintained. On the other hand, the memory lines MB11 to MB31 in which the anode lines ANL1 to ANL3 are held at the ground voltage and the bit line BL1 is driven to a positive voltage are in a reverse bias state. Here, the breakdown voltage of the polysilicon diode PD can be made larger than 5V. Therefore, even if any cell chain is conducted, the diode current is suppressed. Therefore, these memory blocks MB11 to MB31 are also kept in a non-selected state.

  Next, as shown in FIG. 10, the cell chain CCE in the memory block MB00 is selected by driving the cell chain selection line CSL0 to 5V and the other cell chain selection lines CSL1 to CSL4 to 0V. As shown in FIGS. 11 to 14, the cell selection gate line CGL00 is set to 0V, the other cell selection gate lines CGL10 to CGL (k−1) 0, CGL01 to CGL (k−1) 1, CGL02 to CGL ( k-1) 2, CGL03 to CGL (k-1) 3, GL04 to CGL (k-1) 4 (where k = 4) are driven to 5 V, so that the memory cell MB00 in the cell chain CCE Only the lower layer memory cell MC0 is selected.

  Here, according to FIG. 15, the state of each element in the selected memory block MB00 will be described in detail. FIG. 15 is a cross-sectional view of memory block MB00 corresponding to the circuit configuration shown in FIG. In FIG. 8, the operating voltages of the respective terminals are shown in the order of the reset operation, the set operation, and the read operation based on FIGS. The insulating film layer 32 is an insulating film embedded between adjacent polysilicon diodes PD, although omitted in FIGS. 3 to 4 for easy understanding.

  First, 0 V is applied to the bit line BL0, and 5, 4, and 2 V are applied to the anode line ANL0 during a reset operation, a set operation, and a read operation, respectively. In one cell chain CCE, 0V is applied to the cell selection gate line CGL00 to which the memory cell MC0 to be selected is connected to cut off the transistor having the polysilicon layer 8p as a channel. 5 V is applied to the cell selection gate lines CGL01 to CGL0 (k-1) (here, k = 4) to which the other memory cells MC1 to MC (k-1) (here, k = 4) are connected. Then, the transistor is turned on. Further, 5V is applied to the polysilicon 61p serving as the cell chain selection line CSL0, and the cell chain selection gate CCG is made conductive. By such control, in the cell chain CCE, in the memory cells MC1 to MC (k−1) (here, k = 4) in the non-selected state, the transmission gate TG becomes conductive, and the channel resistance is reduced. Lower. Further, since the cell chain selection gate CCG is also turned on, the resistance of the polysilicon layer 8p in the gate is also low. Therefore, in memory cells MC1 to MC (k−1) (here, k = 4), it is possible to cause substantially the same current to flow through transmission gate TG regardless of the state of phase change material layer 7. it can. In the memory cell MC0 in the selected state, the transmission gate TG is cut off, so that a current flows through the phase change material layer 7. That is, during the reset operation and the set operation, the resistance value of the phase change material 7 is changed using Joule heat generated by the current flowing through the phase change material layer 7 itself. During the read operation, the current value flowing through the phase change material layer 7 is measured to separate the stored information.

  In the other cell chain CCO, cell selection gate lines CGL10 to CGL1 (k−1) (here, k = 4) to which the memory cells MC0 to MC (k−1) (here, k = 4) are connected. 5V is applied to make the transistor conductive. Further, the polysilicon 61p serving as the cell chain selection line CSL1 is held at the ground voltage 0V, and the cell chain selection gate CCG is kept in the cut-off state. By such control, in the cell chain CCO, the transmission gate TG is in the conductive state in the memory cells MC0 to MC (k−1) (here, k = 4) in the non-selected state. Since the selection gate CCG is cut off, no current flows. With the control as described above, an operation of selectively applying a current to the phase change material layer 7 of the memory cell MC0 in the cell chain CCE in the memory block MB00 becomes possible.

<< Effects of the present embodiment >>
From the configuration and operation of the memory array described above, the following three effects can be obtained. The first effect is that the effective memory cell area can be halved. That is, one of the features of the structure of the memory block in this memory array is that, as shown in FIGS. 2 to 4 and 15, the polysilicon layer 8p and the phase are formed by the insulating layer 91 formed inside the connection hole. The change material layer 7 is separated into a first region included in the cell chain CCE and a second region included in the other cell chain CCO facing each other. Furthermore, a switch (here, a cell chain selection gate CCG) for independently controlling the current flowing in these layers is provided on each current path. With such a configuration, when the transmission gate TG in the memory cell formed on one side wall is cut off, a current is passed through the phase change material layer 7 in the region to which the memory cell belongs, but the other region facing each other. It is possible to prevent current from flowing through the phase change material layer 7 in FIG. Therefore, it is possible to store twice as much information in one connection hole.

  Further, when the memory block is viewed from the viewpoint of the circuit configuration, two cell chains CCE and CCO are connected to one polysilicon diode PD. The polysilicon diode PD serves as one end of an element for selecting a cell chain in the memory block according to the potential relationship between the anode line and the bit line. Therefore, it can be said that this memory block has a configuration in which two cell chain memories share one selection diode. With such a configuration, the number of bits for one polysilicon diode PD can be increased. Therefore, twice as much information can be stored as compared with the memory array of Patent Document 2, and the effective cell area can be reduced.

  The second effect is that the effective memory cell area can be reduced even when miniaturization is advanced by the structure in which each layer formed on the side wall of the connection hole is in contact with the insulating layer separating the connection hole. is there. That is, the phase change material layer 7 and the like are formed on the side wall of the polysilicon layer 24p, but the direction in which the film thickness increases by crystal growth is the direction in which the two surfaces face each other. Therefore, the film to be formed thereafter is formed in a direction filling the space between the two facing surfaces. With such a configuration, unlike the memory cell of Patent Document 2, the film is not filled from all directions toward the center of the hole. Therefore, the direction in which the film thickness is increased by crystal growth is only the direction in which the two surfaces face each other. Therefore, in the direction orthogonal to the direction in which the two surfaces face each other, the thickness of the connection hole is taken into consideration. There is no need to set dimensions or process connection holes. That is, the size of the connection hole in the direction orthogonal to the direction in which the two surfaces face each other can be made the same as the minimum processing dimension regardless of the thickness of the film to be formed. That is, the density of memory cells per unit area can be increased by miniaturization. In consideration of this feature, it is not necessary to divide the phase change regions on the left and right sides using the insulating layer 91. That is, even when the phase change material layer 7 is formed as one region, the size in the word line direction can be maintained at the minimum processing size, and the density of the memory cell is improved as compared with Patent Document 2. can do.

  The third effect is that different drive circuits for supplying a drive voltage are connected to each of the anode line and the chain selection line. As described above, the anode line and the chain selection line are independently controlled, so that only one cell chain and memory cell is selected. With such a selection method, it is possible to minimize the number of times an unnecessary current is applied in a non-selected cell, and it is possible to suppress deterioration of the storage element STD.

  A fourth effect is that a different drive circuit for supplying a drive voltage is connected to each cell selection gate line. Such a selection method further improves the effect of suppressing the deterioration of the storage element described above.

  In this embodiment, another example of the wiring structure of the anode line, the cell selection gate line, and the cell chain selection line will be described. 5 to 7 of the first embodiment, a wiring structure is shown in which each of the anode line, the cell selection gate line, and the cell chain selection line is extended one by one in the Y direction and a driver is disposed in each. In such a structure, these wirings are not short-circuited with each other and are independent wirings. Such a structure is hereinafter referred to as “independent type”. However, the wiring structure exists in addition to the independent type.

  An example of a different wiring structure is shown in FIG. In this structure, the even-numbered wiring patterns are short-circuited at one end of the memory array to form the wiring CBL0. At the same time, on the opposite side of the memory array, the odd-numbered wiring patterns are short-circuited to form the wiring CBL1. With such a wiring structure, the same wiring can be driven by a plurality of drivers. Therefore, when such a wiring structure is applied particularly to the anode line, it becomes possible to supply a rewrite current or a read current to a plurality of memory cells, thereby doubling the number of memory cells driven simultaneously. There is a possibility of improving the rewrite data transfer rate and the read data transfer rate. Alternatively, there is a possibility that the number of wirings and the number of drive circuits arranged for each wiring, that is, the area of the driver circuit can be suppressed by sharing a part of the wiring, not limited to the anode line. In this embodiment, the outermost wiring (the uppermost and lowermost wirings in FIG. 16) is CBL0 on one side and CBL1 on the other side. However, the present invention is not limited to this. Absent. Both outermost wirings may be CBL0, or vice versa.

  In this way, among the plurality of wiring patterns, odd-numbered wiring patterns are short-circuited to each other, even-numbered wiring patterns are short-circuited to each other, and wiring patterns that are not short-circuited between the odd-numbered and even-numbered wiring patterns It will be called “comb”.

  An example of another wiring structure is shown in FIG. In this structure, all the wiring patterns are short-circuited at both ends of the memory array. In particular, when such a wiring structure is applied to an anode line, the same anode line can be driven by a plurality of anode line drivers as compared with the structure shown in FIG. Therefore, it is possible to supply a rewrite current or a read current to a plurality of memory cells, which may further improve the rewrite data transfer rate and the read data transfer rate. Alternatively, it is possible to further reduce the number of wirings and further reduce the number of drive circuits arranged for each wiring, that is, the driver circuit area, by sharing the wiring not only for the anode line but for the entire surface. is there.

  Such a structure in which all the wiring patterns are short-circuited to each other is hereinafter referred to as a “common type”.

  Each of the two wiring structures of the comb type and the common type can be formed by a cell selection gate line or a cell chain selection line. Therefore, it can be considered that there are 27 (= 3 to the third power) wiring structures in the memory array shown in FIGS. However, in consideration of the rewrite operation and the read operation in the memory array, the wiring structure capable of correctly selecting an arbitrary memory cell is limited. Here, “correctly” selection means that when a certain memory cell is selected, other memory cells that should not be selected are not selected at the same time.

  Therefore, in the following, the requirements for the wiring structure required for the memory cell selection operation will be described first. Next, the memory array structure and operation with different wiring structures will be described.

  As another wiring structure, a remainder obtained by dividing the wiring number by 4 (for example, CSL0 in FIG. 7) and a remainder obtained by dividing the wiring number by 4 (for example, FIG. 7). And the remainder obtained by dividing the wiring number by 4 (for example, CSL2 in FIG. 7) and the remainder obtained by dividing the wiring number by 4 (for example, CSL3 in FIG. 7). There is a method of short-circuiting every other wiring. As a modified example, a case where the remainder obtained by dividing the wiring number by 4 becomes 1 (for example, CSL1 in FIG. 7) and a case where the remainder obtained by dividing the wiring number by 4 becomes 2 (for example, CSL2 in FIG. 7). Short-circuit between the one whose remainder is divided by 3 (for example, CSL3 in FIG. 7) and the one whose remainder is divided by 4 (for example, CSL4 in FIG. 7). There is also a method like this. Hereinafter, these wiring structures are referred to as “remainder short circuit type”. In the remainder short circuit type wiring structure, the number of wires to be short-circuited is not limited to two. For example, there may be a case where four wires are short-circuited such that the remainder of dividing the wiring number by 8 is 0 to 3, and 4 to 7. Such a structure falls into a common category in that adjacent wires are shorted. However, while the common type requires only one drive circuit, at least two remainder short-circuit types are required. Therefore, from the viewpoint of reducing the number of drive circuits, the common type is superior, and therefore the remainder short-circuit type is excluded in FIG.

《Requirements for cell chain selection line》
First, consider the requirements for cell chain selection lines. FIG. 19 is a principal block diagram of the memory block MB00. The configuration shown in the figure follows the circuit configuration shown in FIG. However, in order to briefly describe the cell chain selection operation, the memory cells MC0 to MCk are collectively shown, and the cell selection gate line groups MCGL0 and MCGL1 are omitted.

  The memory block in this embodiment has three selection elements in order to activate one cell chain. The first selection element SD0 is a polysilicon diode PD. The second to third selection elements SD10 and SD11 are a cell chain selection gate CCG included in the cell chain CCE and a cell chain selection gate CCG included in the cell chain CCO. Therefore, the cell chain CCE is activated when the first and second selection elements are activated simultaneously. On the other hand, when the first to third selection elements are simultaneously activated, the cell chain CCO is activated.

  Next, the requirements for activating one cell chain in the memory block in this embodiment will be described.

  First, consider a case where the cell chain selection lines CSL0 and CSL1 are short-circuited at, for example, the end of the memory array, and the second to third selection elements SD10 and SD11 are controlled to the same state. The states of the cell chains CCE and CCO in this case are shown in the second and third rows from the left in FIG. In particular, when the polysilicon diode PD which is the first selection element SD0 is activated in the forward bias state, and the two cell chain selection gates which are the second to third selection elements SD10 and SD11 are simultaneously activated. Both cell chains CCE and CCO are in a selected state (in the figure, a state surrounded by a one-dot chain line). That is, since two current paths are formed from the anode line ANL0 to the bit line BL0, an appropriate voltage or current cannot be applied only to an arbitrary memory cell, which may cause a malfunction.

  As another example, consider a case where the cell chain selection lines CSL0 and CSL1 are separated and the second to third selection elements SD10 and SD11 are individually controlled. The state in this case is shown in the fourth to sixth columns from the left in FIG. In this case, a desired selection operation is possible. That is, when the first selection element SD0 and the second selection element SD10 are simultaneously activated, only the cell chain CCE is activated. Alternatively, when the first selection element SD0 and the third selection element SD11 are activated at the same time, only the cell chain CCO is activated (in a state surrounded by a dotted line in the figure). From the above, the requirements for selecting an arbitrary cell chain in the memory block are as follows.

  [Requirement 1] Adjacent cell chain selection lines must be separated from each other and controlled independently.

《Anode wire requirements》
Next, requirements for the anode wire will be described. FIG. 21 shows a main block configuration of the memory blocks MB00 and MB10 for explaining a requirement for selecting an arbitrary cell chain from two memory blocks MB00 and MB10 adjacent on the selected bit line BL0. The configuration of the memory block in the figure follows FIG. As shown in FIG. 1 and FIGS. 3 to 4, the feature of the figure is that the cells of the memory blocks MB00 and MB01 are due to the restrictions on the memory array structure in which the memory cells are formed on both side walls of the stacked polysilicon. A chain CCO (a cell chain surrounded by a two-dot chain line in FIG. 21) is controlled by a common cell chain selection line CSL1. For this reason, the wiring structure of the anode line is limited.

  For example, when the anode lines ANL0 and ANL1 are short-circuited somewhere in the memory array, it becomes impossible to select an arbitrary memory cell. That is, as shown in the second row of FIG. 22 (that is, “ANL0 / ANL1 common” row), when both anode lines ANL0 and ANL1 are activated simultaneously, the first selection in the memory blocks MB00 and MB01 is performed. The polysilicon diode which is the element SD0 is in the forward bias state. Further, when the cell chain selection line CSL1 is activated, the cell chain selection gate CCG as the second selection element SD11 in the cell chain CCO in the memory blocks MB00 and MB01 becomes conductive. Therefore, the cell chain CCO in the memory blocks MB00 and MB01 is selected (in the figure, the state surrounded by the one-dot chain line).

  On the other hand, when the anode lines ANL0 and ANL1 are separated and independently controlled, an arbitrary memory cell can be selected. That is, as shown in the third row of FIG. 22 (that is, the row of “ANL0 / ANL1 separation”), when one of the anode lines ANL0 and ANL1 is activated, one of the memory blocks MB00 and MB01 is activated. The polysilicon diode which is the first selection element SD0 is in the forward bias state. Therefore, when the cell chain selection line CSL1 is activated, the cell chain selection gate which is the second selection element SD11 in the cell chain CCO in either one of the memory blocks MB00 and MB01 becomes conductive, and only the cell chain CCO is in the conductive state. It is selected (in the figure, it is surrounded by a dotted line). From the above, the second requirement is derived.

  [Requirement 2] Adjacent anode wires must be separated from each other and controlled independently.

  This requirement 2 is due to the fact that the cell chain selection line CSL1 simultaneously selects the cell chain CCO in the memory block MB00 and the cell chain CCO in MB10. Based on this, it seems that the requirement 2 is not necessary if the cell chain selection line CSL is configured such that the two cell chains can be selected independently. However, in order to realize such a cell chain selection line, a cell chain selection line for the cell chain CCO of the memory block MB00 and a cell chain selection line for the cell chain CCO of the memory block MB10 are separately provided. Further, an insulating layer must be provided between them, and an area three times the minimum processing dimension F is required for the two wirings and the insulating layer. For this reason, this requirement 2 is necessary because the area is lost instead.

《Requirements for the relationship between anode line and cell chain selection line》
Next, requirements required for the relationship between the anode line and the cell chain selection line will be described with reference to FIG. In the figure, for simplification of description, memory blocks MB00 to MB30 arranged in an area of four rows and one column from the memory array are shown. The feature of the anode lines in the figure is that the even-numbered and odd-numbered anode lines in the memory array shown in FIG. 1 are short-circuited at one end of the memory array to form comb-shaped anode lines ANL0 and ANL1. In the point.

  Here, for the sake of simplifying the explanation, consider a case where every other cell chain selection line is short-circuited, similarly to the anode line. In FIG. 23, even-numbered cell chain selection lines and odd-numbered cell chain selection lines in the memory array shown in FIG. 1 are short-circuited at one end of the memory array, respectively, so-called comb-shaped cell chain selection lines CSL0, CSL1 is assumed.

  Now, the anode line ANL0 is driven to 5V / 4V / 2V (reset operation / set operation / read operation), and the cell chain select line CSL0 is driven to 5V / 5V / 5V (reset operation / set operation / read operation). Assume that the anode line ANL1, the cell chain selection line CSL1, and the bit line BL0 are each driven to 0V / 0V / 0V (reset operation / set operation / read operation). In this case, in the memory blocks MB00 and MB20, the polysilicon diode PD (SD0) as the first selection element is in the forward bias state, and the cell chain selection gate CCG (SD10) in the cell chain CCE as the second selection element is in the conductive state. It becomes. Therefore, the cell chain CCE in the memory blocks MB00 and MB20 is selected. In this state, two current paths are generated from the anode line ANL0 to the bit line BL0 via the cell chain CCE in the memory blocks MB00 and MB20. This corresponds to a selection state of a plurality of elements and causes a malfunction in the memory array.

  As another example of the operation, as shown in FIG. 24, the anode line ANL0 is driven to 5V / 4V / 2V (reset operation / set operation / read operation), and the cell chain selection line CSL1 is 5V / 5V / 5V ( Reset line / set operation / read operation), and anode line ANL1, cell chain selection line CSL0, and bit line BL0 are each driven to 0V / 0V / 0V (reset operation / set operation / read operation) And In this case, in the memory blocks MB00 and MB20, the polysilicon diode PD (SD0) as the first selection element is in the forward bias state, and the cell chain selection gate CCG (SD11) in the cell chain CCO as the third selection element is in the conductive state. It becomes. Therefore, the cell chain CCO in memory blocks MB00 and MB20 is selected. In this state, two current paths are generated from the anode line ANL0 to the bit line BL0 via the cell chain CCO in the memory blocks MB00 and MB20. This also corresponds to a selection state of a plurality of elements, and causes a malfunction in the memory array. In order to avoid the above malfunction, the third requirement is derived.

  [Requirement 3] Both the anode line and the cell chain selection line must not have a comb-shaped wiring structure.

《Wiring structure realizing selection operation》
Now, in the combination of the 27 wiring structures of the anode line, the cell selection gate line, and the cell chain selection line shown in FIG. 18, the common cell chain selection line according to the requirement 1 for realizing the selection operation described above. Wiring formats 1 to 9 including are excluded. Next, requirement 2 excludes wiring types 10, 13, 16, 19, 22, and 25 including the common type anode line as shown in FIG. Finally, requirement 3 excludes wiring types 11, 14, and 17 when the cell chain selection line and the anode line are both comb-shaped.

  From the above, it is possible to perform the selection operation in the memory array in the wiring formats 12, 15, 18, 20, 21, 23, 24, 26, and 27. Here, Requirement 1 to Requirement 3 are determined based on whether or not the cell chain can be selected. Therefore, if the cell chain is correctly selected, a desired memory cell can be selected regardless of the wiring structure of the cell selection gate line. In addition, as an aid to understanding, there are three systems of nine wiring formats, such as 18 systems of wiring formats 12, 15, and 18, 26 systems of wiring formats 20, 23, and 26, and 27 systems of wiring formats 21, 24, and 27. Classify into: In this embodiment, a 27-line wiring format will be described.

<< Memory array 1 by 27 wiring formats 1: Wiring format 27 >>
The memory array of the wiring form 27 has been described with reference to FIGS. Therefore, the description of the memory array of this wiring type is omitted here.

<< Memory array 2: 27 wiring systems: wiring system 24 >>
The wiring format 24 is a modification of the wiring format 27. The feature of this wiring type is that the wiring structure of the cell selection gate line is changed from the independent type shown in FIG. 6 to the comb type shown in FIG.

  In a memory array to which this structure is applied, when m = 2k memory blocks (k is an integer of 1 or more) are arranged in the direction in which the bit line extends, in order to form 2m cell chains, FIG. As shown in FIG. 5, (m + 1) gate polysilicon layers (21p, 22p, 23p, and 24p shown in FIGS. 3 to 4) deposited in stripes are required. Then, a comb wiring pattern having (m / 2 + 1) stripes of gate polysilicon layers and a comb wiring pattern having (m / 2) stripes of gate polysilicon layers. Are shorted so that they are placed face to face. Then, (m / 2 + 1) comb-shaped wiring patterns are used for cell selection gate lines CGL00 to CGL03, and (m / 2) comb-shaped wiring patterns are used for cell selection gate lines CGL10 to CGL13, respectively.

  With such a structure, the memory cells in the cell chain CCE of the memory blocks MB0y to MB (m-1) y are cell select gate lines CGL00 to CGL03, and the memory cells in the cell chain CCO are also cell select gate lines CGL10 to CGL13. , Each can be selected. That is, of the (m + 1) gate polysilicon layers, for the stacked gate polysilicon at both ends, the memory cells formed on the inner sidewalls of the memory array are the cells of the memory blocks MB0y, MB (m-1) y. Used as a memory cell in a chain CCE. On the other hand, the memory cells formed on the side walls of the other stacked gate polysilicon used as the cell selection gate lines CGL00 to CGL03 are memory cells in the cell chain CCE of the memory blocks MB1y to MB (m-2) y. used. The memory cells formed on the side walls of the cell selection gate lines CGL10 to CGL13 are used as memory cells in the cell chain CCO of the memory blocks MB0y to MB (m−1) y. Here, y indicates the column number of the memory chain of interest, and is 0 to (n−1) according to the memory array configuration shown in FIG.

  In the comb-shaped wiring pattern combination structure as shown in FIG. 25, the cell selection gate lines CGL00 to CGL03 and CGL10 to CGL13 are stored in the memory in the anode line region formed at a 2F pitch as shown in FIG. It is possible to pull out in the same direction outside the array (in the figure, in the right direction of the word line and on the opposite side of the anode line driver group ANDBK). FIG. 27 shows a detailed circuit configuration of the memory array MA shown in FIG.

  In such a wiring structure, it is possible to reduce the number of drive circuits (here, cell selection line drivers) by grouping a plurality of wiring patterns and to suppress the circuit area. Here, the number of drivers arranged in each cell selection gate line is not particularly limited. That is, it is possible to arrange a number of drivers corresponding to the permitted circuit area. For example, as shown in FIG. 26, for cell selection gate line group MCGL0 (cell selection gate lines CGL00 to CGL03), cell selection driver groups MCGD0 and MCGD2 are arranged at both ends of the comb, respectively, and cell selection gate line group MCGL1 With regard to (cell selection gate lines CGL10 to CGL13), the cell selection driver groups MCGD1 and MCGD3 are arranged at both ends of the comb, respectively, thereby making it possible to suppress the drive time of the desired cell selection gate line. Here, in order to make the drawing easy to see, the cell selection gate lines CGL0 (k−1) to CGL1 (k−1) (k = 2 to 4) are omitted. It has the same structure as CGL00 to CGL10.

<< Memory array 3 with 27 wiring systems: Wiring system 21 >>
The wiring format 21 is yet another modification of the wiring format 27. A feature of this wiring format is that the wiring structure of the cell selection gate line is changed from the independent type shown in FIG. 6 to the common type shown in FIG. In the memory array to which this structure is applied, when m = 2k memory blocks (k is an integer of 1 or more) are arranged in the direction in which the bit line extends, gate polysilicon deposited in (m + 1) stripes Each of the layers (21p, 22p, 23p, 24p shown in FIGS. 3 to 4) is connected at both ends of the memory array to realize a cell selection gate line group MCGL that forms a common wiring structure.

  In such a wiring structure, it is possible to further reduce the number of drive circuits (here, cell selection line drivers) by combining all the wiring patterns formed in the same layer. The circuit area can be suppressed more than the case. For example, comparing FIG. 26 with FIG. 29, the number of cell selection gate line group drivers can be halved by this wiring format. FIG. 30 shows a detailed circuit configuration of the memory array MA shown in FIG. Here, in order to make the drawing easy to see, the cell selection gate line CGL (k−1) (k = 2 to 4) is omitted, but these wirings have the same structure as the cell selection gate line CGL0. .

  In the present embodiment, a 26-line wiring format will be described.

<< Memory array with 26 wiring types 1: Wiring type 26 >>
As shown in FIG. 18, there are three types of memory arrays of 26 types of wiring formats, ie, wiring types 20, 23, and 26. Among these, the memory array of the wiring format 26 is characterized in that it has an anode line structure different from that of the wiring format 27. That is, as already described in FIG. 16, the anode line of the wiring form 26 has a comb-shaped wiring structure as shown in FIG.

  In a memory array to which this structure is applied, when m = 2k memory blocks (k is an integer of 1 or more) are arranged in the direction in which the bit line extends, in order to form 2m cell chains, FIG. As shown in FIG. 4, m stripe-shaped metal wiring layers 2 are formed. A comb-shaped wiring pattern having (m / 2) metal wirings formed at even-numbered positions and a comb-shaped wiring pattern having (m / 2) metal wirings formed at odd-numbered positions. Are shorted so that they are placed face to face. The former (m / 2) comb-shaped wiring pattern is used for the anode line ANL0, and the latter (m / 2) comb-shaped wiring pattern is used for the anode line ANL1. With this structure, among the memory blocks MB0y to MB (m-1) y, even-numbered memory blocks can be selected by the anode line ANL0, and odd-numbered memory blocks can be selected by the anode line ANL1. .

  The effect by this structure is the following two. The first effect is that the same anode line can be driven by a plurality of anode line drivers. Accordingly, since the rewrite current or the read current can be supplied to a plurality of memory cells, the rewrite data transfer speed and the read data transfer speed can be improved by doubling the number of memory cells driven simultaneously. it can.

  As shown in FIG. 33 and FIG. 34, the second effect is that by sharing a part of the anode line, the number of anode lines can be suppressed and the number of drive circuits arranged for each anode line can be reduced. In the point. That is, the area can be suppressed by suppressing the number of anode driver circuits. Here, in FIG. 34, cell selection gate lines CGL0 (k−1) to CGL4 (k−1) (k = 2 to 4) are omitted for easy understanding of the drawing. The structure is the same as that of the cell selection gate lines CGL00 to CGL40.

  The anode line structure described above and its effect are common to the wiring type 23 and the wiring type 20 described below. Further, the number of drivers arranged on each anode line is not particularly limited. That is, it is possible to arrange a number of drivers corresponding to the permitted circuit area. For example, as shown in FIG. 33, when m = 2k memory blocks (k is an integer of 1 or more) are arranged in the direction in which the bit line extends, in order to form 2m cell chains, FIG. (M + 1) striped metal wiring layers 2 are formed as shown in FIG. A comb-shaped wiring pattern having (m / 2 + 1) metal wirings formed at even-numbered positions and a comb-shaped wiring pattern having (m / 2) metal wirings formed at odd-numbered positions. Are shorted so that they are placed face to face. The former (m / 2 + 1) comb-shaped wiring patterns are used for the anode line ANL0, and the latter (m / 2) comb-shaped wiring patterns are used for the anode line ANL1, respectively. With such a wiring structure, as shown in FIG. 33, the anode drivers AND0 and AND2 are arranged at both ends of the comb for the anode line ANL0, and the anode drivers AND1 and AND3 are arranged at both ends of the comb for the anode line ANL1. It becomes easy to arrange in each part. In addition, it is possible to suppress the time required to drive the anode line and to suppress a voltage drop due to wiring resistance.

<< Memory array 2 with 26 wiring types: wiring type 23 >>
The wiring format 23 is a modification of the wiring format 26. FIG. 35 to FIG. 36 show the memory array driving circuit configuration by the wiring form 23. FIG. That is, the wiring format 23 is characterized in that the wiring structure of the cell selection gate line is changed from the independent type shown in FIG. 6 to the comb type shown in FIG. In such a wiring structure, as described in “Memory array 2: 27 wiring formats: wiring format 24” in the second embodiment, a plurality of cell selection gate lines are grouped to form a drive circuit (here Then, the number of cell selection line drivers) can be reduced, and the circuit area can be further reduced. In FIG. 36, cell selection gate lines CGL0 (k−1) to CGL1 (k−1) (k = 2 to 4) are omitted for easy understanding of the drawing. The structure is the same as that of the select gate lines CGL00 to CGL10.

<< Memory array 3: 26 wiring systems: wiring system 20 >>
The wiring format 20 is another modification of the wiring format 26. 37 to 38 show the memory array driving circuit configuration by the wiring format 20. FIG. That is, the wiring type 20 is characterized in that the wiring structure of the cell selection gate line is changed from the independent type shown in FIG. 6 to the common type shown in FIG. In such a wiring structure, as described in “Memory array 3: 27 wiring patterns of the 27 systems: wiring format 21” in the second embodiment, all the cell selection gate lines are brought together to form a driving circuit (here. Then, the number of cell selection line drivers) can be further reduced, and the circuit area can be further suppressed. Here, in FIG. 38, cell selection gate lines CGL (k−1) to CGL (k−1) (k = 2 to 4) are omitted for easy understanding of the drawing. The structure is the same as that of the cell selection gate line CGL0.

  In this embodiment, an 18-line wiring format will be described.

<< Memory array with 18 wiring types 1: Wiring type 18 >>
As shown in FIG. 18, there are three types of memory arrays in the 18 wiring systems, namely wiring systems 12, 15, and 18. Among these, the memory array of the wiring format 18 is characterized in that it has a cell chain selection line structure different from that of the wiring format 27. That is, as shown in FIG. 39, the cell chain selection line of the wiring type 18 has a comb-shaped wiring structure.

  In the memory array to which this structure is applied, when m = 2k memory blocks (k is an integer of 1 or more) are arranged in the direction in which the bit line extends, in order to form 2m cell chains, FIG. As shown in FIG. 4, (m + 1) gate polysilicon layers (61p shown in FIGS. 3 to 4) deposited in stripes are required. Then, a comb wiring pattern having (m / 2 + 1) stripes of gate polysilicon layers and a comb wiring pattern having (m / 2) stripes of gate polysilicon layers. Are shorted so that they are placed face to face. Then, (m / 2 + 1) comb-shaped wiring patterns are used for the cell chain selection line CSL0, and (m / 2) comb-shaped wiring patterns are used for the cell chain selection line CSL1, respectively.

  With such a structure, the cell chain CCE of the memory blocks MB0y to MB (m-1) y can be selected by the cell chain selection line CSL0, and the cell chain CCO can be selected by the cell chain selection line CSL1. That is, of the (m + 1) gate polysilicon layers, the MOS transistors formed on the inner sidewalls of the memory array are connected to the cell chains of the memory blocks MB0y and MB (m-1) y for the gate polysilicon at both ends. Used as cell chain selection gate in CCE. On the other hand, the MOS transistor formed on the side wall of the other gate polysilicon used as the cell chain selection line CSL0 is used as the cell chain selection gate in the cell chain of the memory blocks MB1y to MB (m-2) y. The The MOS transistor formed on the side wall of the cell chain selection line CGL1 is used as a cell chain selection gate in the cell chain of the memory blocks MB0y to MB (m-1) y. Here, y indicates the column number of the memory chain column of interest, and is 0 to (n−1) according to the memory array configuration shown in FIG.

  In the comb-shaped wiring pattern combination structure as shown in FIG. 39, cell chain selection lines CSL0 and CSL1 are arranged outside the memory array in the anode line region formed at a 2F pitch as shown in FIG. Can be pulled out in the same direction (in the figure, to the right of the word line and on the opposite side of the anode line driver group ANDBK). FIG. 41 shows a detailed circuit configuration of the memory array MA shown in FIG. Here, in FIG. 41, cell selection gate lines CGL0 (k−1) to CGL4 (k−1) (k = 2 to 4) are omitted for easy understanding of the drawing. The structure is the same as that of the cell selection gate lines CGL00 to CGL40.

  The chain selection line structure described above and its effects are common to the wiring type 18 and the wiring type 15 described below. In addition, the number of drivers arranged on each cell chain selection line is not particularly limited. That is, it is possible to arrange a number of drivers corresponding to the permitted circuit area. For example, as shown in FIG. 40, for the cell chain selection line CSL0, cell chain selection drivers CSD0 and CSD2 are arranged at both ends of the comb, respectively, and for the cell chain selection line CSL1, cell chain selection drivers CSD1 and CSD3 are installed. By disposing each at both ends of the comb, it is possible to suppress the drive time of a desired cell chain selection line.

<< Memory array 2 with 18 wiring types: Wiring format 15 >>
The wiring format 15 is a modification of the wiring format 18. 42 to 43 show memory array driving circuit configurations according to the wiring format 15. FIG. That is, the wiring format 15 is characterized in that the wiring structure of the cell selection gate line is changed from the independent type shown in FIG. 6 to the comb type shown in FIG. In such a wiring structure, as described in “Memory array 2: 27 wiring patterns: wiring type 24”, a plurality of cell selection gate lines are grouped to form a drive circuit (here, cell selection). The number of line drivers) can be reduced, and the circuit area can be further reduced. In FIG. 43, cell select gate lines CGL0 (k−1) to CGL1 (k−1) (k = 2 to 4) are omitted for easy understanding of the drawing. The structure is the same as that of the select gate lines CGL00 to CGL10.

<< Memory array 3 with 18 wiring types: Wiring format 12 >>
The wiring format 12 is another modification of the wiring format 18. 44 to 45 show memory array driving circuit configurations according to the wiring format 12. FIG. That is, the feature of the wiring format 12 is that the wiring structure of the cell selection gate line is changed from the independent type shown in FIG. 6 to the common type shown in FIG. In such a wiring structure, as described in “Memory array 3: 27 wiring formats: wiring format 21”, all the cell selection gate lines are combined to form a drive circuit (here, cell selection). The number of line drivers can be further reduced, and the circuit area can be most suppressed. In FIG. 45, cell selection gate lines CGL (k−1) to CGL (k−1) (k = 2 to 4) are omitted for easy understanding of the drawing. The structure is the same as that of the select gate line CGL0.

  As explained above, in the 18 and 26 wiring types and the wiring types 21 and 24, it is possible to efficiently arrange the drivers by appropriately introducing a comb type or common type wiring structure. The driver area can be suppressed. That is, the bit cost can be suppressed. In addition, in the 26-line wiring format in which a comb-type or common-type wiring structure is introduced to the anode line, the same anode line can be driven by a plurality of drivers. That is, since a rewrite current or a read current can be supplied to a plurality of memory cells, the rewrite data transfer speed and the read data transfer speed can be improved by doubling the number of memory cells driven simultaneously. it can.

  46 shows a matrix of memory array MA and the memory array driving circuit composed of various driving circuits shown in FIGS. 1, 26, 29, 33, 35, 37, 40, 42, and 44. 2 shows an example of the configuration of memory banks MBK formed in a shape. In the figure, for the sake of simplicity, the memory array driving circuits MAC00 to MAC22 of 2 rows and 2 columns are clearly shown. In these memory array drive circuits MAC00 to MAC22, the part in which the circuit block symbols indicating the bit line selection circuit BSLC and the unselected bit line voltage power supply circuit USBVS are included in the area indicating the memory array MA is the bit line selection circuit. FIG. 4 shows that the MOS transistors constituting the BSLC and the non-selected bit line voltage power supply circuit USBVS are formed on the silicon substrate immediately below the memory array MA as shown in FIG.

  The memory bank MBK shown in FIG. 46 is characterized in that the memory array driving circuits are arranged in such a direction that the same driving circuits are in contact with each other. With such an arrangement, a layout area can be reduced by sharing a contact for connecting to a common control line or power supply line. Further, by forming the drive circuits in the common well, the well isolation region can be reduced, and as a result, the areas of various drive circuits can be suppressed.

  Each of the memory array drive circuits MAC00 to MAC22 has the following two characteristics. The first feature is that the anode driver group ANDBK, the cell selection gate driver group MCGDBK, and the cell chain selection driver group CSDBK are arranged facing each other across the memory array MA. As described above, by disposing various drive circuits around the memory array MA, the cell selection gate line groups MSGL0 to MSGLm and the cell chain selection lines CSL0 to CSLm are removed from the anode driver group ANDBK. Therefore, it is easy to locally form a plurality of contacts connecting the power supply wiring passing over the memory array and the anode driver group ANDBK, and a voltage drop due to wiring resistance in the anode driver group ANDBK serving as a current source is suppressed. This makes it possible to apply a desired voltage to the selected memory cell. That is, the operational stability of the memory array driving circuit can be improved.

  As an example, FIG. 47 shows a layout example of the anode driver. In the figure, in particular, the PMOS transistor portions constituting the anode drivers AND0 to AND7 for driving the anode lines ANL0 to ANL7 are shown. Reference numerals 700 to 707 denote metal wiring patterns that become the anode lines ANL0 to ANL7. Reference numerals 710 to 713 denote P-type diffusion layer regions serving as the source electrode and the drain electrode of the PMOS transistor formed on the silicon substrate. Reference numerals 720 to 727 denote first X-system contacts CNTX1 for connecting the anode lines ANL0 to ANL7 and the PMOS transistor. Reference numerals 730 and 731 are through-holes connecting the power supply wiring not shown in the figure and the local wiring 740 formed by the wiring layer M1 shown in FIG. Further, reference numerals 750 to 753 denote second X-type contacts CNTX2 for connecting the local wiring 740 and the P-type diffusion layer regions 710 to 713. In the figure, the gate electrode pattern of the transistor is omitted for the sake of simplicity, but the transistor for driving the anode lines ANL0 to ANL7 is connected to the first X-system contact CNTX1 and the second electrode. It is formed between the X-type contacts CNTX2. Such a regular layout makes it possible to form contacts efficiently while suppressing the area of the memory chip.

  The second feature is that the cell selection gate driver group MCGDBK is arranged between the memory array MA and the cell chain selection driver group CSDBK. This is because the contact between each signal line and the corresponding driver is formed at a position where the contact of the lower signal line is closest to the memory array, and the contact of the upper signal line is formed at a position away from the memory array. Arrangement based on constraints.

  As another method of distributed arrangement of various drive circuits, as shown in FIG. 48, the anode driver group ANDBK, the cell selection gate driver group MCGDBK, and the cell chain selection driver group CSDBK face each other across the memory array MA. There may also be a method arranged in a way. Further, as shown in FIG. 49, there may be a method in which the anode driver group ANDBK, the cell chain selection driver group CSDBK, and the cell selection gate driver group MCGDBK are arranged to face each other across the memory array MA. In the case of these arrangement methods, it is possible to arrange the cell selection gate driver group MCGDBK face to face in adjacent memory array drive circuits. In particular, in the wiring types 18, 26, and 27 having an independent cell selection gate line structure, it is suitable for efficiently arranging contacts that connect a large number of decode signals to the driver.

As shown in FIG. 50, the anode driver group ANDBK, the cell selection gate driver group MCGDBK, and the cell chain selection driver group CSDBK can be arranged in this order toward the outside of the memory array MA. In the case of such an arrangement method, it is possible to arrange the memory arrays MA facing each other in adjacent memory array driving circuits. Since the memory array is not divided, the shape of the memory block in this portion (here, the cell chain and the polysilicon diode) can be formed uniformly, and a memory chip with high operational reliability can be realized. Can do.

  FIG. 51 is a diagram showing a configuration example of a memory module using the memory array MA in the semiconductor device according to the present invention. The phase change memory module PCMMDL shown in FIG. 51 includes a phase change memory PCM, an external random access memory RAM1, and a controller block CTLRBLK. The phase change memory PCM is a large-capacity nonvolatile memory chip composed of the memory array MA on which the present invention is based. The external random access memory RAM1 is an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory). The controller block CTLRBLK includes a microprocessor unit MPU, a random access memory RAM0, a read only memory (read only memory) ROM, a phase change memory interface PCMIF, and a host device interface HOSTIF.

  The random access memory RAM0 is SRAM or DRAM. The external random access memory RAM1 and the random access memory RAM0 temporarily store storage information read from the phase change memory PCM and information to be newly written to the phase change memory PCM. A program for performing wear leveling and error correction is stored in a read-only memory ROM. The microprocessor unit MPU reads this program and executes Wear leveling. Each unit of the controller block CTLBLK is connected to the phase change memory PCM from the phase change memory interface PCMIF via the phase change memory signal group PCMSIG. Further, it is connected to an external random access memory RAM1 via a RAM signal group RAMSIG. Further, the host device interface HOSTIF is connected to the host device HOST via the host device signal group HOSTSIG.

  FIG. 52 shows a configuration example of another phase change memory module PCMMDL1 according to the present invention. The feature of this configuration is that the host device HOST and the controller block CTLBLK shown in FIG. 51 are integrated in the controller CTLR of the same chip.

  More specifically, the controller CTLR includes a microprocessor unit MPU1, a built-in random access memory RAM2, a built-in read-only memory (read-only memory) ROM1, a built-in phase change memory interface PCMIF1, and a built-in host device interface. In addition to HOSTIF1, it is composed of an integrated circuit SPIC for specific use. The number of integrated circuits SPIC for a specific application is not limited to one, and a plurality of circuits having different functions may be mounted depending on the application. With this configuration, the number of devices can be reduced, and the cost of the system using the phase change memory PCM can be suppressed. Further, if the controller CTLR, the phase change memory PCM, and the external random access memory RAM1 are enclosed in one package, the mounting area can be further reduced and the system cost can be further suppressed.

  FIG. 53 shows a configuration example of a portable music playback device as an example of an application device using the phase change memory according to the present invention. This equipment includes a microprocessor unit MPU, audio codec ACD, read only memory ROM, dynamic random access memory DRAM, controller CTRL, phase change memory PCM, liquid crystal panel LCPNL, driver integrated circuit DRVIC , A touch sensor TCHSNSR, a DC-DC converter DCDCC, a power control integrated circuit VCTL, a lithium ion secondary battery BTLY, a universal serial bus terminal USB, and a headphone terminal HDPHN. In such a configuration, a large amount of information can be processed by using the phase change memory according to the present invention.

  FIG. 54 illustrates a configuration example of the phase change memory PCM1 when the phase change memory modules shown in FIGS. 51 to 52 are integrated on one chip. This chip includes a phase change memory array PCMARY that requires a plurality of memory arrays MA on which the present invention is based, a built-in random access memory RAM3, a register REG, a built-in host device interface HOSTIF2, a state machine SM, error correction and wearleveling logic. The circuit EWL is composed of a microprocessor unit MPU2. Each of MA, SM, EWL, MPU2, RAM3, and REG is connected by an input / output line group IOBUS. The MPU 2 is also connected to the data signal group DTBUS and the command signal group CMDBUS, and exchanges stored information and commands with external devices.

  The phase change memory array PCMARY stores, in addition to a table for managing defective bit information, addresses, and the like, an execution program related to a process for leveling the number of rewrites of memory cells. The built-in random access memory RAM3 is, for example, a static random access memory. The built-in random access memory RAM 3 temporarily holds storage information read from the phase change memory array PCMARY and information to be newly written to the phase change memory array PCMARY. The register REG temporarily stores an address, a command, and the like. The built-in random access memory RAM 3 exchanges stored information with the external host device via the built-in host device interface HOSTIF 2 from the data signal group DTBUS. The register REG exchanges addresses and commands with the external host device via the built-in host device interface HOSTIF2 from the command signal group CMDBUS.

  The state machine SM arbitrates the operation of the phase change memory PCM1 according to the command received from the external host device. Further, the error correction & wear leveling logic circuit EWL specializes mainly in the replacement process in the wear leveling process in addition to the error correction process. The microprocessor unit MPU2 mainly executes the aforementioned execution program stored in the phase change memory array PCMARY, and performs wear leveling using EWL as appropriate.

  By using such a configuration, the number of chips can be reduced, and a system using the highly reliable large-capacity phase change memory PCM1 to which the wear leveling described above is applied can be realized at low cost. In addition, by executing error correction processing and wear leveling processing within the same chip, it is possible to omit read / write operations with devices outside the chip, thereby realizing reduction in processing time.

  Although the present invention has been described on the assumption of a phase change memory using a chalcogenide material for the memory element, the material of the memory element is not limited and is not limited to the phase change memory, but a magnetoresistive random access memory or a resistive element. The present invention can also be applied to various semiconductor memories whose electrical characteristics are changed by passing a current through the element, such as a memory.

  The present invention has been described on the premise that polysilicon is used for a gate polysilicon layer for performing a gate operation and a channel polysilicon layer 8p serving as a source / drain path. However, the gate polysilicon layer and the channel polysilicon layer have been described. The material is not limited, and the present invention can be realized by applying a semiconductor material capable of performing a gate operation.

  Further, in this specification, for the sake of easy understanding, the wiring formed by the metal wiring layer 2 is referred to as an anode line, and the wiring formed from the metal wiring layer 3 is referred to as a bit line. This is a selection line used to select one vertical chain memory. Therefore, the role of wiring may be interchanged. At this time, a read circuit such as a sense amplifier is connected to the wiring formed of the metal wiring layer 2.

  As another example, as disclosed in Patent Document 1, a phase change memory device in which memory cells are stacked, the present invention is also applicable to a phase change memory device having a structure in which a large number of memory blocks according to the present invention are stacked. Is possible.

MA memory array,
MB00 to MB (m−1) (n−1) memory block,
CCE, CCO cell chain,
BL0 to BL (n-1) bit lines,
ANL0 to ANL (m-1) anode wire,
CGL0k to CGL (m−1) k, k = 0 to 3 cell selection gate line,
MCGL0 to MCGL (m-1) cell selection gate line group,
CSL0 to CSL (m−1), k = 0 to 3 cell chain selection line,
CDL common data line,
MCk (k = 0-3) memory cell,
TG transmission gate (MOS transistor),
STD storage element,
CCG cell chain selection gate,
PD polysilicon diode,
SA sense amplifier,
WC rewrite circuit,
ANDBK Ano drivers,
MCGDBK cell selection gate driver group,
CSDBK cell chain selection driver group,
BSLC bit line selection circuit,
USBVS unselected bit line voltage power supply circuit,
SD0, SD10, SD11 selection element,
A few metal wiring layers,
4a amorphous silicon layer doped with p-type impurities,
5a an amorphous silicon layer doped with a low concentration of impurities,
6a an amorphous silicon layer doped with n-type impurities,
A polysilicon layer doped with 4p p-type impurities;
5p polysilicon layer doped with low concentration impurities,
A polysilicon layer doped with 6pn type impurities;
7 Phase change material layer,
8a Amorphous silicon layer,
8p channel polysilicon layer,
9 Gate insulation film,
10 Diffusion prevention film,
11, 12, 13, 14, 15 insulating film,
21p, 22p, 23p, 24p polysilicon layer,
31, 32, 33 insulating film,
A polysilicon layer doped with 38pn type impurities;
61p polysilicon layer,
71 insulating film,
91, 92 insulating film,
STI element isolation groove,
The gate of the GATE transistor,
GOX gate insulating film,
DIF diffusion layer,
ILD1, ILD2, ILD3, ILD4, ILD5 interlayer insulating film,
M1, M2 wiring layer,
C1, C2, BLC contact hole,
CBL0, CBL1 comb wiring,
CML common wiring,
700 to 707 A metal wiring pattern to be an anode line,
710-713 P-type diffusion layer region,
720-727 first X-type contact CNTX1,
730, 731 through hole,
750 to 753 Second X-type contact CNTX2,
PCM, PCM1 phase change memory,
PCMARY phase change memory array,
PCMMDL, PCMMDL1 phase change memory module,
CTRBLK controller block,
CTLR controller,
MPU, MPU1, MPU2 Microprocessor unit,
RAM0 random access memory,
RAM1 external random access memory,
RAM2, RAM3 built-in random access memory,
ROM read only memory (read only memory),
ROM1 built-in read-only memory (read-only memory),
PCMIF phase change memory interface,
HOSTIF host device interface,
HOSTIF1, HOSTIF2 built-in host device interface,
PCMIF1 built-in phase change memory interface,
PCMSIG phase change memory signal group,
RAMSIG RAM signal group,
HOSTSIG host device signal group,
SPIC special purpose integrated circuit,
ACD audio codec,
DRAM dynamic random access memory,
LCPNL LCD panel,
DRVIC driver integrated circuit,
TCHSNSR touch sensor,
DCDCC DC-DC converter,
VCTL power control integrated circuit,
BTLY lithium ion secondary battery,
USB universal serial bus terminal,
HDPHN headphone jack,
PCMARY phase change memory array,
REG register,
SM state machine,
EWL error correction and wearleveling logic,
IOBUS I / O line group.

Claims (15)

A plurality of first wires extending in a first direction;
A plurality of second wirings extending in a second direction different from the first direction;
A plurality of first diodes connected to the plurality of first wirings;
A plurality of first memory cells connected in series to the plurality of first diodes;
A plurality of first transistors having source-drain paths provided between the plurality of first memory cells and the plurality of second wirings;
A plurality of second memory cells connected in series to the plurality of first diodes;
A plurality of second transistors having source-drain paths provided between the plurality of second memory cells and the plurality of second wirings;
A plurality of third wirings connected to an x th gate of the plurality of second transistors and a (x + 1) th gate of the plurality of first transistors (x is a natural number);
A plurality of first drive circuits for supplying a drive voltage to the plurality of first wirings;
A plurality of second drive circuits for supplying a drive voltage to the plurality of third wirings,
Each of the plurality of first memory cells includes a third transistor having a source-drain path provided between the plurality of first diodes and the plurality of second wirings, and the source-drain path of the third transistor. A first storage element connected in parallel to which the storage information is written by current,
Each of the plurality of second memory cells includes a fourth transistor whose source-drain path is provided between the plurality of first diodes and the plurality of second wirings, and the source-drain path of the fourth transistor. A second storage element connected in parallel to which the storage information is written by current,
Different drive circuits among the plurality of first drive circuits are connected to each of the plurality of first wirings,
2. A semiconductor memory device, wherein different drive circuits among the plurality of second drive circuits are connected to each of the plurality of third wirings. In claim 1,
The gates of the plurality of fourth transistors connected to the yth one of the plurality of first diodes and the gate connected to the (y + 1) th one of the plurality of first diodes. A plurality of fourth wirings connected to respective gates of the plurality of third transistors (y is a natural number);
A plurality of third drive circuits for supplying a drive voltage to the plurality of fourth wirings;
2. A semiconductor memory device, wherein different drive circuits among the plurality of third drive circuits are connected to each of the plurality of fourth wirings. In claim 1,
The gates of the plurality of fourth transistors connected to the yth one of the plurality of first diodes and the gate connected to the (y + 1) th one of the plurality of first diodes. A plurality of fourth wirings connected to respective gates of the plurality of third transistors (y is a natural number);
A plurality of third drive circuits for supplying a drive voltage to the plurality of fourth wirings;
Of the plurality of fourth wires, odd-numbered wires are short-circuited with each other,
Even numbers of the plurality of fourth wires are short-circuited to each other,
2. A semiconductor memory device, wherein different drive circuits among the plurality of third drive circuits are connected to odd and even lines among the plurality of fourth wirings. In claim 1,
The gates of the plurality of fourth transistors connected to the yth one of the plurality of first diodes and the gate connected to the (y + 1) th one of the plurality of first diodes. A plurality of fourth wirings connected to the respective gates of the plurality of third transistors, all of which are short-circuited to each other;
And a third drive circuit for supplying a drive voltage to the plurality of fourth wirings. In claim 1,
The gates of the plurality of fourth transistors connected to the yth one of the plurality of first diodes and the gate connected to the (y + 1) th one of the plurality of first diodes. A plurality of fourth wirings connected to respective gates of the plurality of third transistors (y is a natural number);
A third drive circuit for supplying a drive voltage to the plurality of fourth wirings;
The plurality of first drive circuits and the plurality of second drive circuits and the third drive circuit are disposed at positions facing each other with the plurality of first memory cells and the plurality of second memory cells as a reference. A semiconductor memory device. In claim 1,
The gates of the plurality of fourth transistors connected to the yth one of the plurality of first diodes and the gate connected to the (y + 1) th one of the plurality of first diodes. A plurality of fourth wirings connected to respective gates of the plurality of third transistors (y is a natural number);
A third drive circuit for supplying a drive voltage to the plurality of fourth wirings;
The plurality of second drive circuits, and the plurality of first drive circuits and the third drive circuit are disposed at positions facing each other with the plurality of first memory cells and the plurality of second memory cells as a reference. A semiconductor memory device. In claim 1,
The gates of the plurality of fourth transistors connected to the yth one of the plurality of first diodes and the gate connected to the (y + 1) th one of the plurality of first diodes. A plurality of fourth wirings connected to respective gates of the plurality of third transistors (y is a natural number);
A third drive circuit for supplying a drive voltage to the plurality of fourth wirings;
The plurality of first drive circuits, the plurality of second drive circuits, and the third drive circuit are arranged in the same direction with respect to the plurality of first memory cells and the plurality of second memory cells. A semiconductor memory device. A plurality of first wires extending in a first direction;
A plurality of second wirings extending in a second direction different from the first direction;
A plurality of first diodes connected to the plurality of first wirings;
A plurality of first memory cells connected in series to the plurality of first diodes;
A plurality of first transistors having source-drain paths provided between the plurality of first memory cells and the plurality of second wirings;
A plurality of second memory cells connected in series to the plurality of first diodes;
A plurality of second transistors having source-drain paths provided between the plurality of second memory cells and the plurality of second wirings;
A plurality of third wirings connected to an x th gate of the plurality of second transistors and a (x + 1) th gate of the plurality of first transistors (x is a natural number);
A plurality of first drive circuits for supplying a drive voltage to each of the plurality of first wirings;
A plurality of second drive circuits for supplying a drive voltage to each of the plurality of third wirings,
Each of the plurality of first memory cells includes a third transistor having a source-drain path provided between the plurality of first diodes and the plurality of second wirings, and the source-drain path of the third transistor. A first storage element connected in parallel to which the storage information is written by current,
Each of the plurality of second memory cells includes a fourth transistor whose source-drain path is provided between the plurality of first diodes and the plurality of second wirings, and the source-drain path of the fourth transistor. A second storage element connected in parallel to which the storage information is written by current,
An odd number of the plurality of first wires is short-circuited with each other,
Even numbers among the plurality of first wires are short-circuited to each other,
Different drive circuits among the plurality of first drive circuits are connected to the odd-numbered and even-numbered ones of the plurality of first wirings,
2. A semiconductor memory device, wherein different drive circuits among the plurality of second drive circuits are connected to each of the plurality of third wirings. In claim 8,
The gates of the plurality of fourth transistors connected to the yth one of the plurality of first diodes and the gate connected to the (y + 1) th one of the plurality of first diodes. A plurality of fourth wirings connected to respective gates of the plurality of third transistors (y is a natural number);
A plurality of third drive circuits for supplying a drive voltage to the plurality of fourth wirings;
2. A semiconductor memory device, wherein different drive circuits among the plurality of third drive circuits are connected to each of the plurality of fourth wirings. In claim 8,
The gates of the plurality of fourth transistors connected to the yth one of the plurality of first diodes and the gate connected to the (y + 1) th one of the plurality of first diodes. A plurality of fourth wirings connected to respective gates of the plurality of third transistors (y is a natural number);
A plurality of third drive circuits for supplying a drive voltage to the plurality of fourth wirings;
Of the plurality of fourth wires, odd-numbered wires are short-circuited with each other,
Even numbers of the plurality of fourth wires are short-circuited to each other,
2. A semiconductor memory device, wherein different drive circuits among the plurality of third drive circuits are connected to odd and even lines among the plurality of fourth wirings. In claim 8,
The gates of the plurality of fourth transistors connected to the yth one of the plurality of first diodes and the gate connected to the (y + 1) th one of the plurality of first diodes. A plurality of fourth wirings connected to the respective gates of the plurality of third transistors, all of which are short-circuited to each other;
And a third drive circuit for supplying a drive voltage to the plurality of fourth wirings. A plurality of first wires extending in a first direction;
A plurality of second wirings extending in a second direction different from the first direction;
A plurality of first diodes connected to the plurality of first wirings;
A plurality of first memory cells connected in series to the plurality of first diodes;
A plurality of first transistors provided with source-drain paths between the plurality of first diodes and the plurality of second wirings;
A plurality of second memory cells connected in series to the plurality of first diodes;
A plurality of second transistors whose source-drain paths are provided between the plurality of first diodes and the plurality of second wirings;
A plurality of third wirings connected to the mth gate of the plurality of second transistors and the (m + 1) th gate of the plurality of first transistors (m is a natural number);
A plurality of first drive circuits for supplying a drive voltage to each of the plurality of first wirings;
A plurality of second drive circuits for supplying a drive voltage to each of the plurality of third wirings,
Each of the plurality of first memory cells includes a third transistor whose source-drain path is provided in series between the plurality of first diodes and the plurality of second wirings, and the source of the third transistor— A first storage element that is provided in parallel to the drain path and in which stored information is written by current,
Each of the plurality of second memory cells includes a fourth transistor having a source-drain path provided in series between the plurality of first diodes and the plurality of second wirings, and the source of the fourth transistor A second storage element that is provided in parallel to the drain path and in which stored information is written by current.
Different drive circuits among the plurality of first drive circuits are connected to each of the plurality of first wirings,
An odd number of the plurality of third wirings are short-circuited to each other,
Even numbers of the plurality of third wirings are short-circuited to each other,
2. A semiconductor memory device, wherein different drive circuits among the plurality of second drive circuits are connected to odd and even lines among the plurality of third wirings. In claim 12,
The gates of the plurality of fourth transistors connected to the yth one of the plurality of first diodes and the gate connected to the (y + 1) th one of the plurality of first diodes. A plurality of fourth wirings connected to respective gates of the plurality of third transistors (y is a natural number);
A plurality of third drive circuits for supplying a drive voltage to the plurality of fourth wirings;
2. A semiconductor memory device, wherein different drive circuits among the plurality of third drive circuits are connected to each of the plurality of fourth wirings. In claim 12,
The gates of the plurality of fourth transistors connected to the yth one of the plurality of first diodes and the gate connected to the (y + 1) th one of the plurality of first diodes. A plurality of fourth wirings connected to respective gates of the plurality of third transistors (y is a natural number);
A plurality of third drive circuits for supplying a drive voltage to the plurality of fourth wirings;
Of the plurality of fourth wires, odd-numbered wires are short-circuited with each other,
Even numbers of the plurality of fourth wires are short-circuited to each other,
2. A semiconductor memory device, wherein different drive circuits among the plurality of third drive circuits are connected to odd and even lines among the plurality of fourth wirings. In claim 12,
The gates of the plurality of fourth transistors connected to the yth one of the plurality of first diodes and the gate connected to the (y + 1) th one of the plurality of first diodes. A plurality of fourth wirings connected to the respective gates of the plurality of third transistors, all of which are short-circuited to each other;
And a third drive circuit for supplying a drive voltage to the plurality of fourth wirings.

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