JP5413371B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a multilayer wiring structure.

  In recent years, with the rapid demand for miniaturization and thinning of electronic devices, there has been a demand for thinning and high density especially in semiconductor devices. In addition, with the demand for higher performance of electronic devices, it is necessary to increase the number of terminals in a semiconductor device as the speed and functionality of semiconductor elements increase.

  Conventionally, WLP (Wafer Level Package) technology has been used to reduce the thickness and increase the density of semiconductor devices. However, since the WLP technology provides a wiring layer only on one side of a semiconductor device, it is difficult to further expand the terminal pitch, to reduce the thickness, and to increase the density in terms of cost and warpage. Yes.

  On the other hand, a technique using both sides of a semiconductor device has been studied.

  Japanese Patent Laid-Open No. 2004-274035 (Patent Document 1) has a structure in which an electronic component such as a transistor or a capacitor is embedded in an insulating layer between a pair of wiring boards, and vias are provided to connect wirings between the boards. An electronic component built-in module is disclosed.

  Japanese Unexamined Patent Application Publication No. 2007-096030 (Patent Document 2) and Japanese Unexamined Patent Application Publication No. 2008-103387 (Patent Document 3) disclose semiconductor devices based on CSP (Chip Size Package) technology.

  A semiconductor device described in Patent Document 2 includes an electronic circuit formed on a substrate surface, a pad electrode connected to the electronic circuit and formed on the substrate surface, a via hole penetrating the semiconductor substrate, and the pad electrode through the via hole. A wiring layer on the back surface of the substrate connected to the substrate, and ball-shaped conductive terminals are provided on the back surface of the substrate so as to be electrically connected to the wiring layer. These via holes, pad electrodes, and wiring layers are arranged outside the formation area of the electronic circuit on the substrate plane.

  The semiconductor device described in Patent Document 3 includes a circuit unit formed on a substrate surface, a surface wiring connected to the circuit unit and formed on the substrate surface, a via hole penetrating the semiconductor substrate, and the surface wiring through the via hole. And external connection bumps are provided on the back surface of the substrate so as to be electrically connected to the back surface wiring. These via holes and backside wiring are arranged outside the circuit portion formation region on the substrate plane.

  However, the techniques described in the above-mentioned patent documents have the following problems.

  In the technique described in Patent Document 1, the connection points between the embedded electronic component and the wiring board are made finer and higher in density than the technique of directly forming the wiring layer on the wafer on which the semiconductor element is formed. It is difficult and the function of the semiconductor element included in the electronic component is limited. Moreover, since the difference in thermal expansion coefficient between the electronic component and the material used for the wiring board is large, the direction and amount of warpage differ between the portion where the electronic component is embedded and the portion where it is not embedded due to the thinning. Warping occurs.

  In the techniques described in Patent Documents 2 and 3, since there is a difference in thickness or formation of an insulating layer or a protective layer between the front side and the back side of the semiconductor device, there is a gap between the front side and the back side of the semiconductor device. Therefore, stress is biased and warping occurs. In particular, when a semiconductor substrate is thinned in order to achieve a reduction in thickness, warping due to stress bias increases. Further, if the support is provided on one side for the purpose of warpage correction and surface protection, the effective wiring accommodation rate is lowered.

  An object of the present invention is to solve the above-described problems, and is to provide a high-density semiconductor device.

According to the present invention, a substrate including an element;
A first insulating layer and a first structure layer provided on one side of the substrate, including a first wiring electrically connected to the element;
A second structural layer including a first insulating layer and a second wiring electrically connected to the first wiring, the second structural layer being stacked on the first structural layer and being thicker than the first structural layer;
A semiconductor device including a third insulating layer and a third wiring and having a third structural layer provided on a surface opposite to the surface on which the first structural layer of the substrate is provided is provided.

  According to the invention, the first structural layer has a multilayer wiring structure in which the first insulating layer and the first wiring are alternately stacked, and the second structural layer includes the second insulating layer and the second insulating layer. The semiconductor device according to claim 1, wherein the semiconductor device has a multilayer wiring structure in which the second wirings are alternately stacked, and the third structure layer has a multilayer wiring structure in which the third insulating layers and the third wirings are alternately stacked. Is provided.

  In addition, according to the present invention, there is provided any one of the above semiconductor devices, wherein the second wiring is thicker than the first wiring.

  In addition, according to the present invention, there is provided any one of the above semiconductor devices, wherein the second insulating layer is thicker than the first insulating layer.

  In addition, according to the present invention, there is provided any one of the above semiconductor devices, wherein the third wiring is thicker than the first wiring.

  In addition, according to the present invention, there is provided any one of the above semiconductor devices, wherein the third insulating layer is thicker than the first insulating layer.

  According to the invention, in the second structural layer, the power supply system wiring is formed so that the number of terminals is reduced by combining a plurality of power supply system wirings in the first structure layer. A semiconductor device is provided.

  According to the invention, in the second structural layer, the ground wiring is formed so as to reduce the number of terminals by combining a plurality of ground wirings in the first structural layer. A semiconductor device is provided.

  In addition, according to the present invention, there is provided any one of the above semiconductor devices having a through via that penetrates the substrate and electrically connects the first wiring or the second wiring to the third wiring. The

  According to the present invention, there is provided the above semiconductor device, wherein in the third structure layer, the power supply system wiring is formed so as to reduce the number of terminals by combining a plurality of power supply system wirings in the first structure layer. Provided.

  According to the invention, in the third structure layer, the ground wiring is formed so that the number of terminals is reduced by combining a plurality of ground wirings in the first structural layer. A semiconductor device is provided.

  Furthermore, according to the present invention, there is provided any one of the above semiconductor devices, wherein the number of the second wirings in the second structural layer is the same as the number of the third wirings in the third structural layer. The

  According to the invention, there is provided the semiconductor device according to any one of the above, wherein the number of the second insulating layers of the second structural layer is the same as the number of the third insulating layers of the third structural layer. Provided.

  Further, according to the present invention, there is provided a semiconductor device characterized in that a plurality of the same or different semiconductor devices described above are stacked.

According to the present invention, there is also provided a manufacturing method for manufacturing any one of the above semiconductor devices,
Preparing a substrate on which a plurality of elements are formed;
Forming the first structure layer on one side of the substrate;
Forming the second structure layer on the first structure layer;
Forming a third structure layer on a surface opposite to the surface of the substrate on which the first structure layer is provided.

  According to the invention, in the formation of the second structure layer and the third structure layer, the formation of the second wiring is performed simultaneously with the formation of the second insulation layer and the formation of the third insulation layer in the same process. And the method of manufacturing the semiconductor device, wherein the third wiring is simultaneously formed in the same process.

  According to the invention, in the formation of the second structural layer and the third structural layer, the formation of the second insulating layer and the second wiring, the formation of the third insulating layer, and the third wiring There is provided a method for manufacturing the semiconductor device described above, wherein the formation of the semiconductor device is alternately performed.

  In addition, according to the present invention, there is provided a method for manufacturing any one of the above semiconductor devices, wherein a via penetrating the substrate is formed before or after the step of forming the first structure layer.

  In addition, according to the present invention, there is provided a method for manufacturing any one of the above semiconductor devices, wherein a via penetrating the substrate is formed during the step of forming the second structural layer.

  According to the invention, the via of penetrating the substrate is formed after the step of forming the second structural layer and before the step of forming the third structural layer. A manufacturing method is provided.

  In addition, according to the present invention, there is provided a method for manufacturing any one of the above semiconductor devices, wherein a via penetrating the substrate is formed during the step of forming the third structure layer.

  According to the invention, in any one of the above semiconductor devices, the step of thinning the substrate is performed after the step of forming the first structural layer or the step of forming the second structural layer. It relates to a manufacturing method.

  According to the invention, a plurality of multilayer wiring structures including the first structural layer, the second structural layer, and the third structural layer are formed on a semiconductor wafer including the substrate, and then the multilayer wiring structures are respectively formed. A method of manufacturing any one of the above semiconductor devices is provided, which is divided into individual pieces.

  Further, according to the present invention, there is provided a method for manufacturing a semiconductor device, including a step of forming a plurality of semiconductor devices of the same type or different types by any one of the above methods and a step of stacking these semiconductor devices.

  According to the present invention, a high-density semiconductor device can be provided.

1 is a perspective view showing an example of a semiconductor device according to a first embodiment of the present invention. It is a fragmentary sectional view of the semiconductor device shown in FIG. FIG. 3 is a partial cross-sectional view showing a first structure layer of the semiconductor device shown in FIG. 2. It is a fragmentary sectional view showing other examples of the semiconductor device by a 1st embodiment of the present invention. It is a fragmentary sectional view showing an example of structure of an electrode part of a semiconductor device by a 1st embodiment of the present invention. It is a fragmentary sectional view showing an example of a semiconductor device by a 2nd embodiment of the present invention. It is a fragmentary sectional view which shows the other example of the semiconductor device by 2nd Embodiment of this invention. It is a fragmentary sectional view showing an example of a semiconductor device by a 3rd embodiment of the present invention. It is a fragmentary sectional view which shows the other example of the semiconductor device by 3rd Embodiment of this invention. It is a fragmentary sectional view which shows the other example of the semiconductor device by 3rd Embodiment of this invention. It is a fragmentary sectional view for explaining a manufacturing method of a semiconductor device by one embodiment of the present invention. FIG. 12 is a diagram for further explaining the manufacturing method described with reference to FIG. 11. It is a fragmentary sectional view for explaining a manufacturing method of a semiconductor device by other embodiments of the present invention. It is a fragmentary sectional view for explaining a manufacturing method of a semiconductor device by other embodiments of the present invention. It is a fragmentary sectional view for explaining a manufacturing method of a semiconductor device by other embodiments of the present invention. It is a fragmentary sectional view for explaining a manufacturing method of a semiconductor device by other embodiments of the present invention. It is a fragmentary sectional view for explaining a manufacturing method of a semiconductor device by other embodiments of the present invention. It is a fragmentary sectional view for explaining a manufacturing method of a semiconductor device by other embodiments of the present invention. It is a fragmentary sectional view for explaining a manufacturing method of a semiconductor device by other embodiments of the present invention.

  In the semiconductor device according to an embodiment of the present invention, a first structure layer and a second structure layer stacked on the first structure layer and thicker than the first structure layer are provided on one surface of a substrate including a plurality of elements. A third structure layer is provided on a surface opposite to the surface of the substrate on which the first structure layer is provided. The first structural layer includes a first insulating layer and a first wiring electrically connected to the element. The second structural layer includes a second wiring electrically connected to the second insulating layer and the first wiring. The third structure layer includes a third insulating layer and a third wiring.

  The first structure layer has a first via for connecting an upper layer side wiring and a lower layer side wiring when a plurality of first wirings are stacked via an interlayer insulating film. The second structure layer has a second via for connecting the upper layer side wiring and the lower layer side wiring when a plurality of second wirings are stacked via the interlayer insulating film. The third structure layer has a third via for connecting the upper layer side wiring and the lower layer side wiring when a plurality of third wirings are stacked via the interlayer insulating film. Wirings and vias in the first structural layer are collectively referred to as “first wiring” and “first via”, respectively, and wirings and vias in the second structural layer are collectively referred to as “second wiring” and “second via”, respectively. The wirings and vias in the third structure layer are collectively referred to as “third wiring” and “third via”, respectively.

  Since such a semiconductor device has the second structure layer and the third structure layer, the wiring accommodation rate of the semiconductor device can be increased, and further, other semiconductor devices and chip components are provided on both sides of the substrate of the semiconductor device. It becomes possible to mount electronic parts such as high density.

  In addition, due to the action of each insulating layer included in the second structure layer and the third structure layer, it is possible to prevent chipping and cracks generated by receiving an impact, and to improve impact resistance.

  In addition, stable power supply can be realized by making both or one of the wiring layer of the second structure layer and the wiring layer of the third structure layer thicker than the wiring layer of the first structure layer, and moreover than the first structure layer. Low-loss signal transmission can be achieved.

  Also, it occurs when the semiconductor device is connected to a mounting board or another component by making the insulating layer of the second structural layer and / or the insulating layer of the third structural layer thicker than the insulating layer of the first structural layer. Stress can be relaxed more sufficiently, and connection reliability can be improved.

  In the semiconductor device of the above embodiment, by providing a structural layer including an insulating layer and a wiring layer on both sides of the substrate, the stress on one side of the substrate and the stress on the opposite side can be made uniform. Even if the substrate is thin, the amount of warpage can be suppressed. Specifically, as described above, by providing the second structural layer on one side of the substrate and providing the third structural layer on the opposite side, the stress generated on both sides of the substrate can be offset and warped. A semiconductor device with a small amount can be realized, and a thinner semiconductor device can be provided. From such a viewpoint, it is preferable that the thickness of the second structure layer and the third structure layer is sufficiently thicker than that of the first structure layer. The thicker the second structure layer and the third structure layer, the greater the thickness of the first structure layer. The influence of stress can be made relatively small, and the stress can be made uniform by the second structure layer and the third structure layer without being greatly affected by the structure of the first structure layer. When the thicknesses of the second structural layer and the third structural layer are not so large with respect to the thickness of the first structural layer, the balance between the total thickness of the first structural layer and the second structural layer and the third thickness It is desirable to set the thicknesses of the second structure layer and the third structure layer in consideration of the above.

  By reducing the number of both or one of the wiring layer and the insulating layer between the second structure layer and the third structure layer of the semiconductor device of the above embodiment, the warp amount reduction effect can be further enhanced.

  From the viewpoint of obtaining the above-described effect more sufficiently, the thickness of the second structure layer and the third structure layer is preferably at least twice the thickness of the first structure layer, more preferably at least three times, and further suppress warpage. From the viewpoint, 5 times or more is preferable. The ratio (T2 / T3) of the thickness T2 of the second wiring layer and the thickness T3 of the third structure layer is preferably in the range of 0.7 to 1.3, and in the range of 0.8 to 1.2. It is more preferable. The thickness of the first wiring is preferably 0.1 to 1.6 μm, more preferably 0.2 to 1.2 μm, and the thickness of the second wiring and the third wiring is preferably 3 to 12 μm, more preferably 5 to 10 μm. preferable. The thickness of the first insulating layer is preferably 0.1 to 1.6 μm, more preferably 0.2 to 1.2 μm, and the thickness of the second insulating layer and the third insulating layer is preferably 5 to 50 μm, 30 μm is more preferable.

  In the above-described embodiment, the first structure layer corresponds to the insulating layer in contact with the substrate to the layer including the uppermost layer wiring, and the second structure layer is in contact with the uppermost layer wiring of the first structure layer. It corresponds to a layer (insulating layer or wiring) to an insulating layer in contact with the uppermost wiring of the second structural layer, and the third structural layer is from a layer (insulating layer or wiring) in contact with the opposite surface of the substrate. This corresponds to the insulating layer in contact with the uppermost wiring of the third structure layer.

  Preferred embodiments of the present invention will be specifically described below with reference to the drawings.

First Embodiment First, a first embodiment of the present invention will be described.

  1 is a perspective view showing a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a partial sectional view showing a part of the semiconductor device, and FIG. 3 is a first view of the semiconductor device shown in FIG. 3 is an enlarged cross-sectional view of a structural layer 13. FIG. In FIG. 1, the first structure layer 13 is omitted.

  As shown in FIG. 1, the semiconductor device 11 of the present embodiment is provided with a second structure layer 14 on one side of the semiconductor substrate 12 and a third structure layer 19 on the opposite side. As shown in FIG. 2, the first structure layer 13 is provided on one surface of the semiconductor substrate 12, and the second structure layer 14 is directly provided thereon. As shown in FIG. 3, an element 30 is provided on the semiconductor substrate 12. The semiconductor substrate 12 is formed of, for example, Si, germanium, gallium arsenide (GaAs), gallium arsenide phosphorus, gallium nitride (GaN), silicon carbide (SiC), II-VI group compound, III-V group compound, diamond, or the like. Yes. You may use the board | substrate with which the semiconductor layer which consists of these semiconductor materials was provided on the support substrate which consists of sapphire, glass, etc.

  As shown in FIG. 2, the second structure layer 14 includes a second wiring 15, a second insulating layer 16, and a second via 17, and the second wiring 15 and the second insulating layer 16 are alternately stacked. In this laminated structure, the second wiring on the upper layer side and the second wiring on the lower layer side are connected by a second via penetrating the second insulating layer between these wiring layers, and the second wiring on the lowermost layer side is connected to the lowermost layer side. Are connected to the wiring layer 31 on the surface side of the first structural layer by a second via penetrating through the second insulating layer (second insulating layer on the first structural layer). The second structure layer is not limited to the structure shown in FIG. 2, and the second insulating layer 16 provided on the first structure layer, and the second wiring 15 provided on the second insulating layer, As long as it has at least the second via 17 that connects the second wiring and the wiring 31 on the surface side of the first structure layer, the number of layers may be greater than that shown in FIG.

  A second electrode 18 is provided on the surface side of the second structure layer 14 and is electrically connected to the second wiring 15.

  As shown in FIG. 2, the third structure layer 19 is provided on the surface opposite to the surface on which the first structure layer 13 of the semiconductor substrate 12 is provided, and the third wiring 20, the third insulating layer 21, and the third via 22. The third wirings 20 and the third insulating layers 21 are alternately stacked. In this laminated structure, the third wiring on the upper layer side and the third wiring on the lower layer side are connected by a third via penetrating the third insulating layer between these wiring layers. The third structure layer is not limited to the structure shown in FIG. 2, and has at least a third insulating layer 21 provided on the semiconductor substrate and a third wiring 20 provided on the third insulating layer. It may be sufficient and it may be laminated more than the number of layers shown in FIG.

  A third electrode 23 is provided on the surface side of the third structure layer 19 and is electrically connected to the third wiring 20.

  In the structure shown in FIG. 2, the number of stacked layers of the second wiring 15 and the third wiring 20 is the same, and the number of stacked layers of the second insulating layer 16 and the third insulating layer 21 is the same. The number of layers may be different. However, from the viewpoint of reducing the amount of warpage, one or both of the number of stacked layers of the second wiring 15 and the third wiring 20 and the number of stacked layers of the second insulating layer 16 and the third insulating layer 21 are the same number of layers. It is desirable to be.

  The second electrode 18 and the third electrode 23 that are external terminals are each configured by wiring on the surface layer side, and the position may be changed according to the connection method, or on the second via 17 and the third via 22, respectively. You may provide directly.

  As shown in FIG. 3, the first structure layer is provided on the semiconductor substrate 12 on which the plurality of semiconductor elements 30 are formed. In the present embodiment, a MOS transistor (Metal Oxide Semiconductor: metal oxide semiconductor) is provided as the semiconductor element 30. This MOS transistor includes a source region 25 and a drain region 26 provided on the surface of the semiconductor substrate 12, and a gate electrode 24 provided on a region sandwiched between these regions via a gate insulating film (not shown). It is configured. Instead of such a planar MOS transistor, a vertical transistor having a three-dimensional structure, a Fin-type FET, or a transistor using an organic material may be used.

  An interlayer insulating film 29 is provided on the semiconductor substrate 12 so as to cover these semiconductor elements 30, and a wiring 31 (first wiring) is provided on the interlayer insulating film 29. A space between the wirings 31 is filled with an insulating film 32, and a wiring layer 28 composed of the inter-wiring insulating film 32 and the wirings 31 is formed. Such a wiring layer 28 (first wiring 31 and inter-wiring insulating film 32) and interlayer insulating film 29 (first insulating layer) are alternately laminated to form a multilayer wiring structure. The lowermost wiring 31 is electrically connected to the source region 25 or the drain region 26 through a plug 27 formed in the lowermost interlayer insulating film 29. The upper layer side wiring 31 and the lower layer side wiring 31 in this multilayer wiring structure are electrically connected through a via 33 formed in the interlayer insulating film 29 between these wirings.

  Examples of the wiring material for the first structural layer 13 include copper and aluminum. The wiring of the first structure layer can be formed by, for example, a damascene method. The formation of wiring by the damascene method can be performed as follows, for example. First, an insulating film is formed, and a groove (trench) corresponding to a desired wiring pattern or a hole corresponding to a via pattern is formed in the insulating film using a lithography technique and a dry etching technique. Next, a barrier metal layer is formed on the entire surface including the inside of the groove or hole by a sputtering method, a CVD (Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method or the like, and a power feeding layer for electrolytic plating is formed by a sputtering method or the like. Then, a copper film is formed so as to fill the groove or hole by electrolytic copper plating. Next, the copper film is polished by CMP (Chemical Mechanical Polishing) so that copper remains only in the groove or hole.

  The thickness of the interlayer insulating film 29 in the first structure layer 13 can be set in a range of 0.2 to 2 μm, for example, 0.2 to 1.6 μm. Of the plurality of interlayer insulating films 29, at least one interlayer insulating film provided near the semiconductor substrate 12 is preferably formed of a low-k material. As the low-k material, for example, a porous silicon oxide film is exemplified, and a material having an elastic modulus at 25 ° C. in the range of 4 to 10 GPa is desirable.

  The second wiring 15 of the second structure layer 14 and the third wiring 20 of the third structure layer 19 can be formed using, for example, copper, and the thickness thereof is, for example, 5 μm. The second wiring 15 and the third wiring 20 can be formed by a wiring forming method different from the wiring of the first structure layer 13 such as a subtractive method, a semi-additive method, and a full additive method. In the subtractive method, for example, as described in JP-A-10-51105, a copper foil provided on a substrate or a resin is etched using a resist having a desired pattern as a mask, and then the resist is applied. In this method, a desired wiring pattern is obtained by removal. For example, as described in Japanese Patent Application Laid-Open No. 9-64493, the semi-additive method is a resist in which a power supply layer is formed by electroless plating, sputtering, CVD, aerosol, or the like, and then opened in a desired pattern. Is formed, electrolytic plating is deposited in the resist opening, and after removing the resist, the power feeding layer is etched to obtain a desired wiring pattern. In the full additive method, for example, as described in JP-A-6-334334, a resist having a desired pattern is formed after adsorbing an electroless plating catalyst on the surface of a substrate or a resin, and this resist is formed into an insulating layer. In this method, the catalyst is activated as it is, and a desired wiring pattern is obtained by depositing metal in the opening of the insulating layer by electroless plating.

  The second wiring 15 and the second electrode 18 of the second structure layer 14 and the third wiring 20 and the third electrode 23 of the third structure layer 19 are respectively connected to the semiconductor substrate 12 side via an adhesion layer via the second insulating layer. 16 and the third insulating layer 21 may be provided. The adhesion layer may be any material having adhesion to the material of the second insulating layer 16 or the third insulating layer 21. For example, titanium, tungsten, nickel, tantalum, vanadium, chromium, molybdenum, copper, aluminum, These alloys are mentioned, and among these, titanium, tungsten, tantalum, chromium, molybdenum, and alloys thereof are preferable, and titanium, tungsten, and alloys thereof are more preferable. The surface of the second insulating layer 16 or the third insulating layer 21 may be a roughened surface having fine irregularities, and in this case, good adhesion can be easily obtained even with copper or aluminum. Further, as a means for improving the adhesion, it is desirable to form a wiring material by sputtering.

  The second wiring 15 of the second structural layer 14 is thicker than the wiring layer 28 of the first structural layer 13, that is, thicker than the first wiring 31. The thickness of the 2nd wiring 15 is 3-12 micrometers, for example, and 5-10 micrometers is desirable. If the second wiring is too thin, the wiring resistance increases and the electrical characteristics of the power supply circuit of the semiconductor device are degraded. If the thickness of the second wiring is too large, a large undulation reflecting the unevenness of the wiring layer is likely to occur on the surface of the insulating layer covering the wiring layer, the number of laminations is limited, or the thickness of the second structure layer 14 itself increases. However, warpage of the entire semiconductor device becomes large, and manufacturing becomes difficult due to process restrictions.

  The third wiring 20 of the third structure layer 19 is thicker than the wiring layer 28 of the first structure layer 13, that is, thicker than the first wiring 31. The thickness of the 3rd wiring 20 is 3-12 micrometers, for example, and 5-10 micrometers is desirable. If the third wiring is too thin, the wiring resistance increases and the electrical characteristics of the power supply circuit of the semiconductor device deteriorate. If the third wiring is too thick, the surface of the insulating layer covering the wiring layer is liable to generate large undulations reflecting the irregularities of the wiring layer, limiting the number of layers, and increasing the thickness of the third structure layer 19 itself. However, warpage of the entire semiconductor device becomes large, and manufacturing becomes difficult due to process restrictions.

  The second insulating layer 16 of the second structure layer 14 and the third insulating layer 21 of the third structure layer 19 are made of, for example, an organic material. Examples of the organic material include epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, BCB (Benzocyclobutene), PBO (Polybenzoxole), and polynorbornene resin. In particular, since polyimide resin and PBO have excellent mechanical properties such as film strength, tensile elastic modulus, and elongation at break, high reliability can be obtained. As the organic material, either a photosensitive material or a non-photosensitive material may be used. When a photosensitive organic material is used, the opening to be the second via 17 or the third via 22 can be formed by a photolithography method. When a non-photosensitive organic material or a photosensitive organic material having a low pattern resolution is used, the opening can be formed by a laser method, a dry etching method, a blast method, or the like.

  By using an organic material for the second insulating layer 16 and the third insulating layer 21, when the semiconductor device is mounted on the mounting substrate, the stress applied to the semiconductor device from the second electrode 18 or the third electrode 23 is mainly increased. The stress propagation to the first structure layer 13 can be effectively reduced by relaxing the deformation of the second insulating layer 16 and the third insulating layer 21. The elastic modulus at 25 ° C. of the material of the second insulating layer 16 and the third insulating layer 21 is desirably in the range of 0.15 to 8 GPa, for example. If the elastic modulus of the insulating material is too low, the amount of deformation of the second insulating layer 16 and the third insulating layer 21 during stress relaxation is large, and most of the stress is applied to the second wiring 15 and the third wiring 20. The disconnection of the second wiring 15 and the third wiring 20 and the breakdown at the second wiring 15 / second via 17 interface and the third wiring 20 / third via 22 interface are likely to occur. If the elastic modulus of the insulating material is too high, the deformation amount of the second insulating layer 16 and the third insulating layer 21 is insufficient, and the stress relaxation in the second structural layer 14 and the third structural layer 19 becomes insufficient, and the first structural layer In FIG. 13, delamination, insulation film breakdown, etc. are likely to occur. Further, the second insulating layer 16 and the second insulating layer 16 can be combined with an insulating material in which the elastic modulus of the second insulating layer 16 and the third insulating layer 21 is lower than the elastic modulus of the interlayer insulating film 29 of the first structural layer 13. The stress can be relaxed more effectively by the three insulating layers 21, and the protective effect of the first structure layer 13 can be enhanced.

  In FIG. 2, the second structure layer 14 is electrically connected to the first structure layer 13 through the second via 17, and the third structure layer 19 has the third insulating layer 21 in contact with the semiconductor substrate 12. However, as shown in FIG. 4, the second structure layer 14 may be electrically connected to the first structure layer 13 through the second wiring 15, and the third structure layer 19 has its third structure. The wiring 20 may be provided on the semiconductor substrate 12. When the third wiring 20 of the third structure layer 19 is provided on the semiconductor substrate 12, it is desirable that the surface of the semiconductor substrate 12 is insulative.

  The second electrode 18 of the second structure layer may have the structure shown in FIGS.

  In FIG. 5A, when the connection is made using a solder material, an opening through which the second electrode 18 is exposed is formed by the second insulating layer 16 on the surface side so that the solder is supplied only to the second electrode 18. Restricted. The restriction by the second insulating film 16 restricts the amount of solder flow, so that the mounting height when the semiconductor device is connected to the mounting substrate or another component can be stabilized. 5A shows a structure in which the second insulating layer 16 covers the periphery of the second electrode 18, but a structure that is not covered by the second insulating layer 16 may be used. In the structure shown in FIG. 5B, when connecting using wire bonding, the connection to the electrode portion can be made favorable. In the structure shown in FIG. 5C, the lower part of the electrode is provided in the opening of the second insulating layer 16 on the surface side, and according to this structure, when the connection by the solder material is performed at a narrow pitch, the connection Reliability can be improved.

  The second electrode 18 is made of, for example, a laminate, and in consideration of wettability of solder balls formed on the surface of the second electrode 18 and connectivity with bonding wires, the surface of the second electrode 18 is made of, for example, copper. And a layer of at least one metal or alloy selected from the group consisting of aluminum, gold, silver and solder materials. The second electrode 18 is, for example, a nickel layer and a gold layer laminated on a copper layer and having the gold layer as a surface. The nickel layer has a thickness of 3 μm, for example, and the gold layer has a thickness of 1 μm, for example.

  The third electrode 23 of the third structure layer 19 can have the same structure as the second electrode 18 of the second structure layer 14. The second electrode 18 and the third electrode 23 may be appropriately selected from structures having a desired effect on the connection, and need not have the same structure.

  In FIG. 2, three layers of the second wiring 15 and four layers of the second insulating layer 16 are shown, but the present invention is not limited to this, and the number of layers can be set as necessary. In FIG. 3, the eight wiring layers 28 and the eight interlayer insulating films (first insulating layers) 29 are shown, but the present invention is not limited to this, and the number of layers can be set as necessary.

  The first wiring 31, the second wiring 15, and the third wiring 20 are made of at least one kind of metal or alloy selected from the group consisting of copper, aluminum, nickel, gold and silver, for example. In particular, copper is preferable from the viewpoint of electrical resistance value and cost. Nickel can prevent an interfacial reaction with other materials such as an insulating material, can be used as a barrier film, has characteristics as a magnetic material, and can be used as an inductor or a resistance wiring.

  The second wiring 15 of the second structural layer 14 has a larger allowable current amount than the first wiring 31 because the thickness thereof is thicker than the first wiring 31 of the first structural layer 13. Further, the third wiring 20 of the third structure layer 19 has a larger allowable current amount than the first wiring 31 because the thickness thereof is thicker than that of the first wiring 31 of the first structure layer 13. For this reason, in one or both of the second structure layer 14 and the third structure layer 19, a plurality of power supply system wirings and ground system wirings using the same voltage can be bundled to reduce the number of wirings. By combining these plural wirings, the number of the second electrodes 18 and the third electrodes 23 can be reduced as compared with the case where they are not combined. By reducing the number of the second electrodes 18 and the third electrodes 23, the size and interval (pitch) of the second electrodes 18 and the third electrodes 23 can be increased, so that the connection area between the mounting substrate and the semiconductor device increases. Stable mounting and high connection reliability can be realized.

  As described above, in the semiconductor device of this embodiment, since the second structure layer 14 and the third structure layer 19 are provided on both side surfaces of the semiconductor substrate 12, the semiconductor substrate 12 and the layers stacked thereon are provided. The stress generated by the difference in thermal expansion can be offset, and the amount of warpage can be suppressed even if the semiconductor substrate 12 is thinned. In particular, between the second structure layer 14 and the third structure layer 19, both or one of the wiring layers and the insulating layers has the same number, so that the effect of reducing the warpage can be further enhanced.

  Further, the second structural layer 14 and the third structural layer 19 provided on both sides of the semiconductor substrate can increase the wiring accommodation rate of the semiconductor device, and further, electronic components such as other semiconductor devices and chip components on the both sides of the substrate. Can be mounted at high density.

  Further, the action of each organic insulating layer included in the second structure layer 14 and the third structure layer 19 can soften the impact received by the semiconductor device, prevent chipping and cracks, and improve impact resistance. it can.

  By making the thickness of the second wiring 15 of the second structural layer 14 and the third wiring 20 of the third structural layer 19 larger than the thickness of the wiring 31 of the first structural layer 13, the second wiring 15 and the third wiring 20. Can be prevented, and the wiring resistance of the second wiring 15 and the third wiring 20 can be made smaller than that of the first wiring 31. Further, as the thicknesses of the second wiring 15 and the third wiring 20 are increased, the thickness of each layer of the second insulating layer 16 and the third insulating layer 21 is also increased, so that the effect of relaxing the stress is enhanced.

  Further, when the second wiring 15 and the third wiring 20 are thick, in the second structure layer 14 and the third structure layer 19, respectively, a plurality of power supply systems and ground wirings using the same voltage are combined into one wiring. Can be summarized. In the wafer level CSP in which rewiring is performed on the surface of the semiconductor element, the wiring when provided in the semiconductor component is simply changed in the one-to-one relationship without reducing the number of connection terminals. doing. In a semiconductor component having about 500 or more external terminals, particularly 1500 or more, about 60 to 80% of the number of terminals is a power supply system and ground system terminal in order to maintain the performance of the element. By consolidating the power supply line and the ground line, the number of the second electrodes 18 of the second structure layer 14 can be greatly reduced as compared with the number of electrical connection points formed on the surface of the first structure layer 13. Can do. Furthermore, the number of the third electrodes 23 can be reduced also in the third structure layer 19. For this reason, since the size and interval (pitch) of the second electrode 18 and the third electrode 23 can be increased, stable mounting property and high connection reliability of the semiconductor device can be realized.

  As described above, the second structure layer 14 and the third structure layer 19 are thin and less warped, and the propagation of stress and impact to the first structure layer 13 is reduced, so that the connection reliability at the time of mounting is high. A high-density semiconductor device can be realized.

Second Embodiment Next, a second embodiment of the present invention will be described.

  FIG. 6 is a partial cross-sectional view showing an example of a semiconductor device according to the second embodiment of the present invention. The semiconductor device according to the first embodiment is different in that a through via 34 is provided so as to penetrate the semiconductor substrate 12. Hereinafter, parts different from the semiconductor device according to the first embodiment will be described. Portions not specifically described are the same as those of the semiconductor device according to the first embodiment. The second electrode 18 and the third electrode 23 in FIG. 6 may have the structure shown in FIGS.

  The through via 34 allows the first structure layer 13 and the second structure layer 14 provided on one surface of the semiconductor substrate 12 and the third structure layer 19 provided on the other surface to be provided according to a required function. Connect them electrically. That is, one or both of the first structure layer 13 and the second structure layer 15 are electrically connected to the third structure layer 19 through the through via 34.

  The through via 34 can be formed as follows. First, a through hole is formed in the semiconductor substrate 12 by dry etching or wet etching. Next, an inorganic or organic insulating film is formed on the inner wall of the through hole by thermal oxidation, CVD, ALD, spin coating, laminating, or printing. If necessary, the insulating film may be processed by photolithography, laser, dry etching, or wet etching. Next, a through via 34 is formed in the through hole by forming a conductor by CVD, sputtering, electrolytic plating, electroless plating, printing, vapor deposition, ink jet, or the like. As the material of the through via 34, at least one conductive material selected from the group consisting of copper, aluminum, tungsten, gold, silver, nickel, and impurity-containing polysilicon, or an alloy containing any metal can be used. . From the viewpoint of cost and electrical characteristics, copper or a copper alloy is preferable.

  FIG. 7 is a partial cross-sectional view showing another example of the semiconductor device according to the second embodiment. In FIG. 7, the pitch of the through vias 34 is smaller than the pitch of the second electrode 18 and the third electrode 23. A plurality of through vias 34 are bundled by the second wiring 15 and the third wiring 20. This is because the second wiring and the third wiring are sufficiently thick and the wiring resistance is small, and thus such a wiring structure is possible.

  In the semiconductor device according to the second embodiment, in addition to the effects of the semiconductor device according to the first embodiment, the wiring structure layers provided on both surfaces of the substrate are electrically connected through the through vias. Furthermore, the degree of freedom in wiring design is further improved, and a higher density than that of the semiconductor device according to the first embodiment can be realized. In addition, since the electronic components provided on one surface side and the other surface side of the substrate can be connected with a short distance, the performance of the semiconductor device can be improved.

Third Embodiment Next, a third embodiment of the present invention will be described.

  8 to 10 are partial sectional views showing specific examples of the semiconductor device according to the third embodiment of the present invention. In the third embodiment, the semiconductor device according to the first embodiment and the semiconductor device according to the second embodiment are stacked. 8 and 9, the semiconductor device according to the first embodiment is stacked on the semiconductor device according to the second embodiment. In FIG. 10, two semiconductor devices according to the second embodiment are stacked. The stacked form of the semiconductor device is not limited to these. Moreover, the 2nd electrode 18 and the 3rd electrode 23 of FIGS. 8-10 are good also as a structure shown by FIG.5 (b) and (c). The semiconductor device according to the third embodiment will be described below. Portions that are not particularly described are the same as those of the semiconductor device according to the first embodiment or the second embodiment.

  In the structure shown in FIG. 8, the semiconductor device shown in FIG. 2 is stacked on the semiconductor device shown in FIG. The second electrode 18 of the semiconductor device shown in FIG. 6 and the third electrode 23 of the semiconductor device shown in FIG. 2 are connected by a connection portion 35 provided between the two semiconductor devices. A solder ball 36 is provided on the third electrode 23 on the lower surface side. The connecting portion 35 can be formed of at least one material selected from the group consisting of solder material, tin, gold, silver, palladium, copper, and aluminum. In order to further improve the reliability of the connecting portion 35, an underfill resin may be injected between the semiconductor devices to increase the strength.

  9 is different from the structure shown in FIG. 8 in that the second electrode 18 of the semiconductor device shown in FIG. 6 is connected to the second electrode 18 of the semiconductor device shown in FIG. Is different. In other words, the first structure layers of the two semiconductor devices are stacked so as to face each other. High-speed and high-speed data communication between semiconductor devices facing each other is possible, and high performance can be realized.

  In the structure shown in FIG. 10, two semiconductor devices shown in FIG. 6 are stacked, an electronic component 37 is provided on the upper surface side, and a solder ball 36 is provided on the lower surface side. The electronic component is electrically connected to the second electrode 18 on the upper surface side via the connection portion 38. The solder ball 36 is directly connected to the third electrode 23 on the lower surface side. Examples of the electronic component 37 include other semiconductor devices, chip capacitors, chip resistors, discretes, diodes, LEDs, sensors, MEMS, and optical components. The connecting portion 38 can be formed of at least one material selected from the group consisting of solder material, tin, gold, silver, palladium, copper, and aluminum. By providing other electronic components, the circuit operation can be stabilized and the function of the system can be improved.

  8 to 10 show the structure in which two semiconductor devices are stacked, the present invention is not limited to this, and three or more semiconductor devices may be stacked. Further, the structure having the solder ball 36 is shown in the lowermost layer of the stack, but the present invention is not limited to this, and pins, Au bumps, copper bumps, spare solder, metal pearls, ACF, NCF, etc. are used. A structure based on a connection method may be used.

  In the semiconductor device according to the third embodiment, in addition to the effects of the semiconductor device according to the first embodiment and the semiconductor device according to the second embodiment, the footprint is increased by stacking a plurality of semiconductor devices and electronic components. It is possible to realize a high-density system with a minimum of.

In the first to third embodiments described above, a circuit noise filter or the like is provided at a desired position of the laminated circuit composed of the semiconductor substrate 12, the first structural layer 13, the second structural layer 14, and the third structural layer 19. A capacitor that plays the role of decoupling may be provided. Examples of the dielectric material constituting the capacitor include metal oxides such as titanium oxide, tantalum oxide, Al ₂ O ₃ , SiO ₂ , ZrO ₂ , HfO ₂ , and Nb ₂ O ₅ ; BST (Ba _x Sr _1-x TiO _{3 ), PZT (PbZr x Ti 1} -x O 3), PLZT (Pb 1-y La y Zr x Ti 1-x O 3) perovskite such material (0 ≦ x ≦ 1,0 <y <1); Bi-based layered compounds such as SrBi ₂ Ta ₂ O ₉ are listed. Further, as a dielectric material constituting the capacitor, an organic material mixed with an inorganic material or a magnetic material may be used.

Further, the counter electrode is disposed at a desired position of one or a plurality of upper and lower wiring layers of the insulating layers in the second structural layer 14 and the third structural layer 19 via a dielectric having a dielectric constant of 9 or more. A capacitor that plays the role of a circuit noise filter or decoupling may be provided by forming. The dielectric material constituting the _{capacitor, Al 2 O 3, ZrO 2} , HfO 2, Nb metal oxides such as _{2 O 5; BST (Ba x} Sr 1-x TiO 3), PZT (PbZr x Ti 1- _x O ₃ ), perovskite materials such as PLZT (Pb _1-y La _y Zr _x Ti _1-x O ₃ ) (0 ≦ x ≦ 1, 0 <y <1); Bi such as SrBi ₂ Ta ₂ O ₉ System layered compounds are mentioned. Further, as a dielectric material constituting the capacitor, an organic material mixed with an inorganic material or a magnetic material may be used.

Semiconductor Device Manufacturing Method Hereinafter, a semiconductor device manufacturing example according to an embodiment of the present invention will be specifically described with reference to the drawings.

First Manufacturing Example First, a first manufacturing example will be described with reference to FIG. FIG. 11 is a partial cross-sectional view for explaining the present manufacturing example.

  In each step described below, cleaning or heat treatment may be appropriately performed. Further, the semiconductor substrate 12 may be ground to a thickness of less than 300 μm as necessary. When the thin semiconductor substrate 12 is used, a support member made of the same material or metal as that of the semiconductor substrate 12 may be used in order to improve handling properties.

  First, as illustrated in FIG. 11A, as described in the first embodiment, the element and the first structure layer 13 are formed on the semiconductor substrate 12. As described above, the first wiring 31 in the first structure layer 13 can be formed by the damascene method, and the insulating layers 28 and 29 can be formed by, for example, a CVD method or a spin coating method.

  Next, as illustrated in FIG. 11B, as described in the first embodiment, the second structure layer 14 is formed so as to be in direct contact with the first structure layer 13.

  The second wiring 15 of the second structure layer 14 can be formed as described above, and is made of, for example, copper and has a thickness of, for example, 5 μm. When forming fine wiring, the semi-additive method is preferable.

  The second insulating layer 16 of the second structure layer 14 can be formed by a CVD method or a spin coating method when an inorganic material is used as an insulating material. The opening serving as the second via 17 can be formed by dry etching. When an organic material is used as the insulating material, either photosensitive or non-photosensitive can be used, and the second insulating layer can be formed by a spin coating method, a laminating method, a pressing method, or a printing method. As described above, the opening serving as the second via 17 can be formed by a photolithography method when a photosensitive resin is used, and a non-photosensitive organic material or an organic material having a low pattern resolution even when photosensitive is used. In such a case, it can be formed by a laser method, a dry etching method, a blast method, or the like. The second via 17 can be formed by filling the opening formed in this way with a conductive material. In addition, a metal post is formed in a portion to be the second via 17 by a plating method or a printing method, and after the second insulating layer 16 is formed, a second etching method, a CMP method, a grinding method, a lapping method, or the like is performed. The second via 17 can also be formed by removing a portion of the insulating layer 16 on the metal post and exposing the metal post.

  In the structure shown in FIG. 11, the opening of the second via 17 is indicated by a vertical wall, but a taper angle may be provided. By providing a taper angle to the second via 17 connected to the wiring of the first structural layer, the connection area between the second via 17 and the wiring of the first structural layer 13 can be reduced. The surface wiring density can be increased. In addition, since the junction area between the second via 17 and the second wiring 15 can be increased, connection reliability can be improved. Furthermore, since the second via 17 has a taper angle, wiring formation is facilitated.

  Next, as shown in FIG. 11C, as described in the first embodiment, the third structure layer 19 is placed on the opposite surface of the surface of the semiconductor substrate 12 on which the first structure layer 13 is formed. Form directly.

  The third wiring 20, the third insulating layer 21, and the third via 22 of the third structural layer 19 are formed in the same manner as the second wiring 15, the second insulating layer 16, and the second via 17 of the second structural layer described above. can do. If necessary, the aforementioned adhesion layer or roughened surface is formed.

  The manufacturing method described with reference to FIG. 11 has been described as an example of the manufacturing method of the structure illustrated in FIG. 2, but the structure illustrated in FIG. 4 can be manufactured using a similar method. The second electrode 18 and the third electrode 23 may be manufactured to have the structure shown in FIG. 5B or 5C depending on the connection method employed.

  According to the first manufacturing example, the semiconductor device according to the first embodiment can be efficiently formed. Also, as shown in FIG. 12A, a plurality of semiconductor devices 11 are formed on the wafer 39, and along the solid line in FIG. 12A and the broken line in FIG. 12B, blade dicing, laser dicing, The semiconductor device 11 may be cut into pieces by cutting with a water cutter, dry etching, wet etching, or the like.

Second Manufacturing Example A second manufacturing example will be described with reference to FIG. FIG. 13 is a partial cross-sectional view for explaining the present manufacturing example.

  The second production example is different from the first production example in that the second structure layer 14 and the third structure layer 19 are formed by being laminated simultaneously. Hereinafter, differences from the first manufacturing example will be described. Parts not particularly described are the same as those in the first production example.

  After the elements and the first structural layer 13 are formed on the semiconductor substrate 12 as shown in FIG. 13A, the substrate side portion (wiring 15 and insulation) of the second structural layer 14 as shown in FIG. 13B. The layer 16 and the via 17) are formed so as to be in direct contact with the first structural layer 13, and the substrate side portion (the wiring 20 and the insulating layer 21) of the third structural layer 19 is the substrate surface on which the first structural layer 13 is formed. Directly formed on the opposite surface. Subsequently, an upper layer side portion of the second structure layer and an upper layer side portion of the third structure layer are formed to form a desired structure shown in FIG. At that time, the formation of the second insulating layer and the formation of the third insulating layer are simultaneously performed in the same process, and the formation of the second wiring and the formation of the third wiring are simultaneously performed in the same process. The insulating layer can be formed on both sides by attaching an insulating sheet on both sides and performing heat treatment. Wiring can be formed by forming electroless plating on both sides, forming a resist pattern on both sides, performing electrolytic plating on both sides simultaneously, and etching on both sides simultaneously.

  The manufacturing method described with reference to FIG. 13 has been described as an example of the manufacturing method of the structure illustrated in FIG. 2, but the structure illustrated in FIG. 4 can be manufactured using a similar method. The second electrode 18 and the third electrode 23 may be manufactured to have the structure shown in FIG. 5B or 5C depending on the connection method employed.

  According to the second manufacturing example, the semiconductor device according to the first embodiment can be efficiently formed. In particular, as compared with the first manufacturing example, the semiconductor substrate 12 can be manufactured stably even if it is thin.

Third Manufacturing Example A third manufacturing example will be described with reference to FIG. FIG. 14 is a partial cross-sectional view for explaining the present manufacturing example.

  The third manufacturing example is different from the first manufacturing example in that the second structural layer 14 and the third structural layer 19 are alternately stacked in units of combinations of insulating layers and wirings. ing. Hereinafter, differences from the first manufacturing example will be described. Parts not particularly described are the same as those in the first production example.

  After forming the element and the first structural layer 13 on the semiconductor substrate 12 as shown in FIG. 14A, as shown in FIG. 14B, the substrate side portion of the second structural layer 14 (wiring 15 and insulation). The layer 16 and the via 17) are formed so as to be in direct contact with the first structural layer 13.

  Next, as shown in FIG. 14C, the substrate side portion (the wiring 20 and the insulating layer 21) of the third structure layer 19 is directly formed on the opposite surface of the substrate surface on which the first structure layer 13 is formed.

  Next, an upper layer side portion of the second structure layer and an upper layer side portion of the third structure layer are formed to form a desired structure shown in FIG. At that time, the formation of the second insulating layer and the second wiring, and the formation of the third insulating layer and the formation of the third wiring are performed alternately.

  The manufacturing method described with reference to FIG. 14 has been described as an example of the manufacturing method of the structure illustrated in FIG. 2, but the structure illustrated in FIG. 4 can be manufactured using a similar method. The second electrode 18 and the third electrode 23 may be manufactured to have the structure shown in FIG. 5B or 5C depending on the connection method employed.

  According to the third manufacturing example, the semiconductor device according to the first embodiment can be efficiently formed. In particular, as compared with the first manufacturing example, the semiconductor substrate 12 can be stably manufactured even if it is thin, and the positional accuracy between the second structure layer 14 and the third structure layer 19 can be further increased.

Fourth Manufacturing Example A fourth manufacturing example will be described with reference to FIG. FIG. 15 is a partial cross-sectional view for explaining the present manufacturing example.

  The fourth manufacturing example is different from the first, second, and third manufacturing examples in that the through via 34 is formed in the semiconductor substrate 12. Hereinafter, differences from the first, second, and third production examples will be described. Parts not particularly described are the same as those in the first, second, and third production examples.

  As shown in FIG. 15, the element and the first structure layer 13 are formed on the semiconductor substrate 12, and the through via 34 is formed. The through via 34 can be formed by the method described in the second embodiment, and may be formed after the first structure layer 13 is formed, or may be formed before the first structure layer 13. In addition, the semiconductor substrate 12 is provided with a recess serving as a through via 34 and filled with a conductor, and then the first structure layer 13 is formed, and the surface of the semiconductor substrate 12 where the first structure layer 13 is not formed is ground or A method of exposing the through via 34 by etching may be performed. The through via 34 has a function necessary for the first structural layer 13 and the second structural layer 14 provided on one surface side of the semiconductor substrate 12 and the third structural layer 19 provided on the other surface side. It forms so that it may electrically connect according to. That is, one or both of the first structure layer 13 and the second structure layer 15 are electrically connected to the third structure layer 19.

  In the step after the structure shown in FIG. 15 is formed, the second structure layer 14 and the third structure layer 19 can be formed by the steps described with reference to FIGS.

  According to the fourth manufacturing example, in addition to the effects of the first, second, and third manufacturing examples, the semiconductor according to the second embodiment in which the wiring on one surface side of the substrate and the wiring on the other surface side are connected. The apparatus can be manufactured efficiently.

Fifth Manufacturing Example A fifth manufacturing example will be described with reference to FIG. FIG. 16 is a partial cross-sectional view for explaining the present manufacturing example.

  The fifth manufacturing example is different from the fourth manufacturing example in that the through via 34 is formed in the semiconductor substrate 12 during the manufacturing process of the second structural layer 14. Below, a different point from the 4th manufacture example is explained. Parts not particularly described are the same as in the fourth production example.

  As shown in FIG. 16A, the substrate side portion (the wiring 15, the insulating layer 16, and the via 17) of the second structural layer 14 is formed on the first structural layer 13 according to the above-described manufacturing method.

  Next, as shown in FIG. 16B, a through via 34 is formed in the semiconductor substrate 12. The through via 34 can be formed using the method described in the second embodiment.

  In addition, a recess is provided in a portion of the semiconductor substrate 12 where the through via 34 is formed, and after filling the conductor, a part of the first structure layer 13 and the second structure layer 14 is formed, and the first structure layer of the semiconductor substrate 12 is formed. You may perform the method of exposing the through-via 34 by grinding or etching the surface of the side in which 13 is not formed.

  The through via 34 has a function necessary for the first structure layer 13 and the second structure layer 14 provided on one surface side of the semiconductor substrate 12 and the third wiring structure 19 provided on the other surface side. It forms so that it may electrically connect according to. That is, one or both of the first structure layer 13 and the second structure layer 15 are electrically connected to the third structure layer 19.

  After the through via 34 is formed, the remaining portion of the second structure layer 14 and the third structure layer 19 are formed according to the above-described manufacturing method.

  According to the fifth manufacturing example, in addition to the effects of the first, second, and third manufacturing examples, the semiconductor according to the second embodiment in which the wiring on one surface side of the substrate and the wiring on the other surface side are connected. The apparatus can be manufactured efficiently. Furthermore, it is easy to form the through via 34 that is directly connected to both the first structure layer 13 and the second structure layer 14, and a higher-density semiconductor device can be manufactured.

Sixth Manufacturing Example A sixth manufacturing example will be described with reference to FIG. FIG. 17 is a partial cross-sectional view for explaining the present manufacturing example.

  The sixth manufacturing example is different from the fifth manufacturing example in that the through via 34 is formed in the semiconductor substrate 12 after the formation process of the second structural layer 14 is completed. Hereinafter, differences from the fifth manufacturing example will be described. Parts not particularly described are the same as those in the fifth production example.

  As shown in FIG. 17A, the second structural layer 14 is formed on the first structural layer 13 in accordance with the manufacturing method described above.

  Next, as shown in FIG. 17B, a through via 34 is formed in the semiconductor substrate 12. The through via 34 can be formed using the method described in the second embodiment. In addition, a recess is formed in a portion of the semiconductor substrate 12 where the through via 34 is formed, and after filling the conductor, the first structure layer 13 and the second structure layer 14 are formed, and the first structure layer 13 of the semiconductor substrate 12 is formed. You may perform the method of exposing the penetration via 34 by grinding or etching the surface of the side which is not carried out.

  After the through via 34 is formed, the third wiring structure 19 is formed as shown in FIG.

  The second structure layer 14 and the third structure layer 19 shown in FIG. 17 are similar to the structure shown in FIG. 2, but the same method is used even if the structure is similar to the structure shown in FIG. It can be manufactured by a method. Moreover, you may produce the 2nd electrode 18 and the 3rd electrode 23 so that it may become a structure shown in FIG.5 (b) or (c) according to the connection method.

  According to the sixth manufacturing example, in addition to the effects of the first, second, and third manufacturing examples, the semiconductor according to the second embodiment in which the wiring on one surface side of the substrate and the wiring on the other surface side are connected. The apparatus can be manufactured efficiently. Furthermore, it is easy to form the through via 34 that is directly connected to the second wiring 15 of the second structure layer 14, and a higher-density semiconductor device can be manufactured.

Seventh Manufacturing Example A seventh manufacturing example will be described with reference to FIG. FIG. 18 is a partial cross-sectional view for explaining the present manufacturing example.

  In the seventh manufacturing example, the through via 34 is formed in the semiconductor substrate 12 after the formation of the third insulating layer 21 on the substrate side in the step of forming the third structure layer 19 as compared with the sixth manufacturing example. Is different. Hereinafter, differences from the sixth production example will be described. Portions not particularly described are the same as in the sixth manufacturing method.

  As shown in FIG. 18A, after the first structure layer 13 and the second structure layer 14 are formed on one surface of the semiconductor substrate 12, the third insulation of the third structure layer 19 is formed on the other surface of the semiconductor substrate 12. The layer 21 is formed, and an opening corresponding to the through via 34 to be formed is provided. Next, as shown in FIG. 18B, a through via 34 is formed in the semiconductor substrate 12 in accordance with the opening.

  After the through via 34 is formed, the remaining part of the third structure layer 19 is formed as shown in FIG.

  According to the seventh manufacturing example, in addition to the effects of the first, second, and third manufacturing examples, the semiconductor according to the second embodiment in which the wiring on one surface side of the substrate and the wiring on the other surface side are connected. The apparatus can be manufactured efficiently. Furthermore, the accuracy of the formation position of the through via 34 connected to the third structure layer 19 can be increased, and a higher density semiconductor device can be manufactured.

Eighth Manufacturing Example An eighth manufacturing example will be described with reference to FIG. FIG. 19 is a partial cross-sectional view for explaining the present manufacturing example.

  The eighth manufacturing example is different from the other manufacturing examples described above in that a plurality of semiconductor devices according to any of the above-described embodiments are stacked. The eighth production example will be described below. Portions that are not particularly described are the same as in the manufacturing method described above.

  First, as shown in FIG. 19A, a plurality of semiconductor devices are connected by a connecting portion 35. Connection of a plurality of semiconductor devices may be performed by connecting semiconductor device portions in a wafer state, connecting individual semiconductor devices, or connecting a semiconductor device portion in a wafer state and individual semiconductor devices. It doesn't matter. The semiconductor device portion in the wafer state can be divided after connection. From the viewpoint of yield, it is preferable that the semiconductor device as the lowermost layer is in a wafer state and the stacked semiconductor devices are connected as individual semiconductor devices.

  Next, as shown in FIG. 19B, solder balls 36 as external terminals are formed on the lower surface side of the lowermost semiconductor device. Instead of such solder balls 36, a connection structure using pins, Au bumps, copper bumps, spare solder, metal pearls, ACF, NCF, or the like may be formed.

  The stacked semiconductor device shown in FIG. 19B corresponds to the stacked semiconductor device shown in FIG. 8, but the semiconductor device shown in FIGS. 9 and 10 can be manufactured by using a similar method. . Further, the present invention is not limited to the stacked structure of two semiconductor devices, and three or more semiconductor devices may be stacked.

  According to the eighth manufacturing example, the semiconductor device according to the third embodiment can be manufactured efficiently.

  The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

  This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2008-271187 for which it applied on October 21, 2008, and takes in those the indications of all here.

Claims (25)

A substrate including the element;
A first insulating layer and a first structure layer provided on one side of the substrate, including a first wiring electrically connected to the element;
A second structural layer including a second insulating layer and a second wiring electrically connected to the first wiring, the second structural layer being stacked on the first structural layer and being thicker than the first structural layer;
Includes a third insulating layer and the third wiring, we have a third structure layer in which the first structural layer of the substrate is provided on the opposite surface of the surface provided,
The thickness of the second structural layer and the third structure layer state, and are more than 2 times the thickness of the first structural layer,
A semiconductor device , wherein a ratio (T2 / T3) of a thickness (T2) of the second structure layer and a thickness (T3) of the third structure layer is in a range of 0.7 to 1.3 .   The first structural layer has a multilayer wiring structure in which the first insulating layer and the first wiring are alternately stacked, and the second structural layer has the second insulating layer and the second wiring alternately. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a laminated multilayer wiring structure, and the third structural layer has a multilayer wiring structure in which the third insulating layer and the third wiring are alternately laminated.   The semiconductor device according to claim 1, wherein the second wiring is thicker than the first wiring.   The semiconductor device according to claim 1, wherein the second insulating layer is thicker than the first insulating layer.   The semiconductor device according to claim 1, wherein the third wiring is thicker than the first wiring.   The semiconductor device according to claim 1, wherein the third insulating layer is thicker than the first insulating layer. The thickness of the first wiring is in the range of 0.1 to 1.6 μm, and the second wiring and the third wiring The thickness of the wiring is in the range of 3-12 μm,
The thickness of the first insulating layer is in the range of 0.1 to 1.6 μm, and the second insulating layer and the The thickness of the third insulating layer is in the range of 5 to 50 μm,
The semiconductor according to claim 1, wherein the thickness of the substrate is less than 300 μm. Body equipment. The second structural layer, the number of terminals together multiple power system wires of the first structural layer is formed the power supply system line so as to reduce, according to any one of claims 1 to 7 Semiconductor device.   9. The ground wiring is formed on the second structural layer so as to reduce the number of terminals by combining a plurality of ground wiring in the first structural layer. 9. Semiconductor device. Penetrating the substrate, wherein the first wiring and the second wiring for connecting the third and the wiring electrically, having a through via, a semiconductor device according to any one of claims 1 to 9. 11. The semiconductor device according to claim 10 , wherein the third structure layer is formed with power supply system wiring so that a plurality of power supply system wirings in the first structure layer are combined to reduce the number of terminals. It said third structural layer, the number of terminals together multiple ground based wires of the first structural layer is a ground-based wiring is formed so as to reduce, the semiconductor device according to claim 10 or 11. The second said the number of layers of the second wiring structure layer third structural layer a is a third and the number of layers of wiring are the same, a semiconductor device according to any one of claims 1 to 12. The number of layers of the second insulating layer of the second structural layer and the layer number of the third insulating layer of the third structure layer are the same, a semiconductor device according to any one of claims 1 to 13 . Wherein a plurality of semiconductor devices of the same type or different types according to any one of claims 1 to 14 are laminated. A manufacturing method for manufacturing the semiconductor device according to claim 1,
Preparing a substrate on which a plurality of elements are formed;
Forming the first structure layer on one side of the substrate;
Forming the second structure layer on the first structure layer;
Forming a third structure layer on a surface of the substrate opposite to the surface on which the first structure layer is provided. In the formation of the second structure layer and the third structure layer, the formation of the second insulating layer and the formation of the third insulating layer are simultaneously performed in the same process, and the formation of the second wiring and the formation of the third wiring are performed. The method of manufacturing a semiconductor device according to claim 16 , wherein the steps are performed simultaneously in the same process. In the formation of the second structure layer and the third structure layer, the formation of the second insulation layer and the formation of the second wiring, and the formation of the third insulation layer and the formation of the third wiring are performed alternately. A method for manufacturing a semiconductor device according to claim 16 . Wherein in the step before or after forming the first structural layer, to form vias through the substrate, a manufacturing method of a semiconductor device according to any one of claims 16 18. Wherein in the middle step of forming a second structural layer, to form vias through the substrate, a manufacturing method of a semiconductor device according to any one of claims 16 19. After the step of forming the second structural layer, before the step of forming the third structure layer, forming a via through the substrate, the semiconductor device according to any one of claims 16 20 Manufacturing method. The method of manufacturing a semiconductor device according to any one of claims 16 to 21 , wherein a via penetrating the substrate is formed during the step of forming the third structure layer. After the step of forming the first structural layer, or after the step of forming the second structural layer, a step of thinning the substrate, the semiconductor device according to any one of claims 16 22 Manufacturing method. A plurality of multilayer wiring structures including the first structural layer, the second structural layer, and the third structural layer are formed on a semiconductor wafer including the substrate, and then divided into individual pieces each including the multilayer wiring structure; the method of manufacturing a semiconductor device according to any one of claims 16 23. Forming a plurality of semiconductor devices of the same type or different by the method according to claims 16 to any one of 24, comprising the step of laminating these semiconductor devices, a method of manufacturing a semiconductor device.

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