JP5411959B2 - DC-DC converter and control method thereof - Google Patents

Description

  The present invention relates to a DC-DC converter and a control method thereof, and more particularly to a DC-DC converter whose high side is constituted by an nch FET and a control method thereof.

  FIG. 10 is a circuit diagram showing a configuration of a conventional DC-DC converter 100. The DC-DC converter 100 is a DC-DC converter of a synchronous rectification type, and the high side is constituted by an nch FET. For this reason, the high level of the driver that applies the gate voltage of the high-side transistor FET1 is configured to be the input voltage Vin + the power supply voltage VB in the bootstrap circuit including the capacitor C1 and the diode D1.

  In the bootstrap circuit, one end of the capacitor C1 is connected to a connection point LX between the source of the high side transistor FET1 and the drain of the low side transistor FET2, and the other end of the capacitor C1 is connected to the cathode of the diode D1. The anode of the diode D1 is connected to the power supply voltage VB.

  In the case where the DC-DC converter 100 operates in a continuous conduction mode (CCM), the connection point voltage VLX at the connection point LX becomes the voltage of the input voltage Vin when the high-side transistor FET1 is turned on. When the low side transistor FET2 becomes conductive, the voltage becomes 0V. When the low-side transistor FET2 becomes conductive and the connection point voltage VLX becomes 0V, the potential difference between both ends of the capacitor C1 becomes the power supply voltage VB.

  Next, when the high-side transistor FET1 becomes conductive, the connection point voltage VLX becomes the input voltage Vin. Therefore, the voltage value of the drive voltage VDVDD becomes the voltage value of the power supply voltage VB + the input voltage Vin due to the capacitive coupling of the capacitor C1. Since the voltage value of the power supply voltage VB + the input voltage Vin is applied to the gate of the transistor FET1, the high side transistor FET1 can be conducted with low impedance.

  Patent Documents 1 to 3 disclose techniques related to such a DC-DC converter.

Japanese Patent Laying-Open No. 2005-065393 US Pat. No. 5,814,972 US Pat. No. 5,705,919

  By the way, the case where the DC-DC converter 100 operates in a discontinuous energization mode (DCM: Discontinuous Conduction Mode) will be considered. FIG. 11 is a timing chart showing the operation of the conventional DC-DC converter 100 when operating with DCM.

  When there is no electromagnetic energy stored in the coil L operating with DCM, the voltage of the node voltage VLX is output at the timing when both the high-side transistor FET1 and the low-side transistor FET2 are non-conductive (timing (100) in FIG. 11). The voltage Vo becomes the voltage difference, and the potential difference between both ends of the capacitor C1 becomes the power supply voltage VB-the output voltage Vo.

  Therefore, in (101) of FIG. 11, when the high side transistor FET1 is turned on next time, even if the connection point voltage VLX becomes the input voltage Vin, the voltage value of the drive voltage VDVDD is the power supply voltage VB−the output voltage Vo +. The input voltage Vin. Compared to the case of CCM, a voltage value lower by the output voltage Vo is applied to the gate of the high-side transistor FET1.

  As a result, the conduction impedance of the high-side transistor FET1 may become high, or the high-side transistor FET1 may become non-conductive in spite of the timing at which the high-side transistor FET1 should be conductive.

  The present invention has been made in view of the above-described background art, and an object thereof is to provide a DC-DC converter that sufficiently conducts the high side even when operated by DCM, and a control method thereof.

  The solution includes a switch connected between the source-side terminal of the high-side nchFET and a ground potential of a coupling capacitor connected between the path leading to the first voltage and the path leading to the source of the high-side nchFET. And a switch control unit that conducts the switch unit prior to conduction of the high-side nchFET and makes the switch unit non-conducting in synchronization with conduction of the high-side nchFET. The switch control unit includes a prediction unit that detects that the high-side nchFET is conductive, and a low-side nchFET control unit that controls the conduction of the low-side nchFET according to a result of the prediction unit. The prediction unit is configured to output the error amplifier output signal and the three in the voltage mode. An offset unit that offsets at least one of the output signal of the error amplifier and the output signal of the triangular wave oscillator such that the output signal of the wave oscillator intersects at a second timing earlier than the first timing at which the wave oscillator output signal intersects And a detection unit for detecting the second timing.

  Another solution is to connect between the source-side terminal of the high-side nchFET of the coupling capacitance connected between the path leading to the first voltage and the path leading to the source of the high-side nchFET and the ground potential. In the control method of the DC-DC converter including the switch unit, the step of conducting the one end of the coupling capacitor on the high side nchFET side and the ground potential in the switch unit prior to the conduction of the high side nchFET, In synchronization with conduction of the side nchFET, the switch unit includes a step of making the one end of the coupling capacitor on the high side nchFET side and the ground potential nonconductive, and the switch unit is the low side nchFET. The control of conduction / non-conduction of the switch part is controlled by the Predicting and detecting the conduction of the side nchFET, and controlling the conduction of the low side nchFET according to the result of the prediction detection, and the result of the prediction detection is the output signal of the error amplifier and An offset is applied to at least one of the output signal of the error amplifier and the output signal of the triangular wave oscillator so that the output signal of the triangular wave oscillator intersects at a second timing earlier than the first timing at which the triangular wave oscillator intersects, A control method for a DC-DC converter, characterized in that a second timing is detected.

  In the DC-DC converter and the control method thereof according to the present invention, the switch portion is turned on prior to the conduction of the high-side nchFET, and the switch portion is turned off in synchronization with the conduction of the high-side nchFET. Thereby, prior to the conduction of the high-side nchFET, one end on the source side of the high-side nchFET of the coupling capacitance is connected to the ground potential. For this reason, the potential difference between both ends of the coupling capacitor becomes the first voltage. When the high-side nchFET is turned on, the voltage value applied to the gate of the high-side nchFET becomes the input voltage + the first voltage due to the capacitive coupling of the coupling capacitor, so that the high-side nchFET is turned on reliably. Can do. Thereby, even if it enters into DCM, it can prevent that the conduction impedance of high side nchFET becomes high, or it becomes non-conduction even if it is the timing which high side nchFET should conduct.

  According to the present invention, it is possible to provide a DC-DC converter that sufficiently conducts the high side even when operated by DCM, and a control method thereof.

It is a circuit diagram which shows the structure of the DC-DC converter concerning 1st Embodiment. It is a block diagram which shows the structure of a low side nchFET control circuit. It is a circuit diagram which shows the structure of the high side nchFET conduction | electrical_connection prediction part. It is a circuit diagram which shows the structure of a low side nchFET conduction | electrical_connection control part. It is a timing chart which shows operation | movement of the DC-DC converter concerning 1st Embodiment. It is a circuit diagram which shows another example of the high side nchFET conduction | electrical_connection prediction part. It is a timing chart which shows operation | movement of the circuit of another example of the high side nchFET conduction | electrical_connection estimation part. It is a circuit diagram which shows the structure of the DC-DC converter concerning 2nd Embodiment. It is a circuit diagram which shows the structure of the DC-DC converter concerning 3rd Embodiment. It is a circuit diagram which shows the structure of the DC-DC converter of a prior art. It is a timing chart which shows operation | movement of the DC-DC converter of a prior art.

  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying a DC-DC converter and a control method thereof according to the present invention will be described below in detail with reference to FIGS.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a DC-DC converter 1 according to the first embodiment. The DC-DC converter 1 includes an anti-shoot through AST1, a driver DRV1, a driver DRV2, a high side transistor FET1, a low side transistor FET2, a diode D1, capacitors C1 and Co, a coil L, and a low side nchFET control circuit. 10.

  The anti-shoot-through AST1 is supplied with a high-side transistor control signal ASTih that instructs switching control of the high-side transistor FET1 and an output signal of the low-side nchFET control circuit 10. The anti-shoot-through AST1 is applied to the gate of the low-side transistor FET2 after the input signal to the gate of the high-side transistor FET1 transitions from the high level to the low level so that the high-side transistor FET1 and the low-side transistor FET2 do not conduct simultaneously. Has a function of shifting the timing of transition of the input signal from low level to high level later.

  A driver DRV1 is connected to the output of the anti-shoot through AST1 on the high side transistor FET1 side. The high level of the output of the driver DRV1 is the drive voltage VDVDD, and the low level is the connection point voltage VLX of the connection point LX between the high side transistor FET1 and the low side transistor FET2.

  A driver DRV2 is connected to the output of the anti-shoot through AST1 on the low-side transistor FET2 side. The high level of the output of the driver DRV2 is the power supply voltage VB, and the low level is the ground potential.

The output of the driver DRV1 is connected to the gate of the high side transistor FET1, and the input voltage Vin is connected to the drain.
The output of the driver DRV2 is connected to the gate of the low-side transistor FET2, and the ground potential is connected to the source.
The source of the high side transistor FET1 and the drain of the low side transistor FET2 are connected to form a connection point LX. Furthermore, one end of the coil L and one end of the capacitor C1 are connected to the connection point LX.

  The other end of the capacitor C1 is a drive voltage node DVDD, to which the cathode of the diode D1 is connected. A power supply voltage VB is connected to the anode of the diode D1. Therefore, drive voltage VDVDD of drive voltage node DVDD is always equal to or higher than power supply voltage VB.

  The other end of the coil L is an output voltage Vo, and a smoothing capacitor Co is connected thereto.

  FIG. 2 is a block diagram showing a configuration of the low-side nchFET control circuit 10. The low-side nchFET control circuit 10 includes a high-side nchFET conduction prediction unit 30 and a low-side nchFET conduction control unit 40.

  The high-side nchFET conduction predicting unit 30 is a part that predicts that the high-side transistor FET1 is conducting. In the current mode DC-DC converter, an RS flip-flop (not shown) is set at the rising edge of the oscillator, and a high-side transistor control signal ASTih is generated. For this reason, it can be predicted that the high-side transistor FET1 is turned on by using the falling signal of the oscillator.

  FIG. 3 is a circuit diagram of the high-side nchFET conduction prediction unit 30 in the current mode. In the high side nchFET conduction prediction unit 30, the input terminal of the inverter 31 is connected to the oscillator signal OSC, and the high side on signal HON is output from the output terminal of the inverter 31.

  The low-side nchFET conduction control unit 40 is a part that controls conduction of the low-side transistor FET2. FIG. 4 is a circuit diagram showing a configuration of the low-side nchFET conduction control unit 40.

  The low-side nchFET conduction control unit 40 includes a delay element 41, an AND gate 42, a one-shot multivibrator 43, and an OR gate 44.

A high-side on signal HON is connected to one input of the AND gate 42, and a high-side on signal HON is connected to the other end via a delay element 41.
Thus, when the high side on signal HON transitions from the low level to the high level, the high level is output to the output terminal of the AND gate 42 after the delay time of the delay element 41 has elapsed. That is, the delay element 41 and the AND gate 42 constitute a one-shot multivibrator.

  In the one-shot multivibrator 43, when the input signal becomes a high level, a pulse having a predetermined width is generated.

  In the OR gate 44, the low-side AST input signal ASTil is connected to one end of the input, and the output of the one-shot multivibrator 43 is connected to the other end. As a result, the low-side AST input signal ASTil is transmitted to the output, and the pulses generated by the delay element 41, the AND gate 42 and the one-shot multivibrator 43 based on the high-side on signal HON are output to the low-side AST input signal ASTil2. .

  Next, the operation of the DC-DC converter according to the first embodiment will be described. FIG. 5 is a timing chart showing the operation of the DC-DC converter according to the first embodiment.

(1) Since the coil current ILX is 0 before, the node voltage VLX = the output voltage Vo.
In (1), the low-side DRV input voltage is changed from the low level to the high level by the one-shot multivibrator 43. Then, the low-side transistor FET2 becomes conductive, and the node voltage VLX changes from the output voltage Vo to 0V. Thereby, in the coil L, the coil current ILX flows with a negative slope, and electromagnetic energy in the negative direction is accumulated.

  In (2), the output of the one-shot multivibrator 43 transitions to a low level, and the low-side transistor FET2 turns off. Then, in order to release the electromagnetic energy in the negative direction accumulated in the coil L, a current flows from the coil L to the input voltage Vin via the connection point LX and the body diode (not shown) of the high side transistor FET1. Thereby, the connection point voltage VLX becomes the input voltage Vin. Further, the drive voltage VDVDD becomes a voltage value of the power supply voltage VB + the input voltage Vin due to the capacitive coupling of the capacitor C1.

  In (3), the high-side DRV input voltage transitions from a low level to a high level. Since the drive voltage VDVDD is a voltage value of the power supply voltage VB + the input voltage Vin, the high side transistor FET1 becomes conductive. Once conducting, the voltage value of the connection point voltage VLX becomes the input voltage Vin, so that the drive voltage VDVDD holds the voltage value of the power supply voltage VB + the input voltage Vin. At this time, VGS of the high-side transistor FET1 is the power supply voltage VB. Further, in the coil L, the coil current ILX flows with a positive slope, and electromagnetic energy in the positive direction is accumulated.

  In (4), when the high-side DRV input voltage transitions from a high level to a low level, the high-side transistor FET1 turns off. In the coil L, the accumulated electromagnetic energy in the positive direction is released through the body diode of the low-side transistor FET2 (not shown). That is, the coil current ILX turns to a negative slope. As a result, the node voltage VLX transitions to a voltage value of 0V, and the drive voltage VDVDD transitions to the voltage value of the power supply voltage VB.

  In (5), when the low-side DRV input voltage transitions from the low level to the high level, the low-side transistor FET2 becomes conductive. In the coil L, ILX changes with a negative slope.

  In (6), when the low-side DRV input voltage transitions from the high level to the low level, the low-side transistor FET2 becomes non-conductive. Since the electromagnetic energy stored in the coil L at this time becomes 0, the connection point voltage VLX becomes the voltage value of the output voltage Vo again.

As described above, in the DC-DC converter 1 according to the first embodiment, prior to turning on the high side transistor FET1, the drive sufficient to turn on the low side transistor FET2 and drive the high side transistor FET1. A voltage is applied to the gate of the high side transistor FET1.
As a result, it is possible to prevent the conduction impedance of the high-side transistor FET1 from becoming high, and the high-side transistor FET1 from becoming non-conductive despite the timing at which the high-side transistor FET1 should be conducted.

(First modification)
In the current mode, the high-side nchFET conduction prediction unit 30 can be completed with one inverter, but the voltage-mode DC-DC converter may not be able to obtain the oscillator signal OSC.

  In the voltage mode, the high-side nchFET conduction control signal transitions from the high level to the low level and from the low level to the high level at the first timing when the output signal of the error amplifier and the output signal of the triangular wave oscillator intersect. (See FIG. 7). Therefore, the high-side nchFET conduction prediction can be performed by offsetting at least one of the output signal of the error amplifier and the triangular wave oscillator so as to intersect at a second timing earlier than the first timing.

  In the first modification, the high-side nchFET conduction prediction unit 30 is replaced with a high-side nchFET conduction prediction unit 30A. FIG. 6 is a circuit diagram showing the high-side nchFET conduction prediction unit 30A. The high-side nchFET conduction prediction unit 30A includes a known voltage offset circuit 32 and a comparator 33.

  In the voltage offset circuit 32, the triangular wave oscillator output signal DO is connected to the input, and a positive voltage value is added to the non-inverting input of the comparator 33. The error amplifier output signal EA is input to the inverting input of the comparator 33.

FIG. 7 shows a timing chart showing the operation of the high-side nchFET conduction prediction unit 30A. Here, the triangular waveform of the solid line is the triangular wave oscillator output signal DO, and the triangular waveform of the broken line is a signal obtained by applying a positive offset to the triangular wave oscillator output signal DO, that is, the output signal of the voltage offset circuit 32.
The straight line with a negative slope is the error amplifier output signal EA.

  The high-side nchFET conduction control signal becomes high level when the triangular wave oscillator output signal DO is higher than the error amplifier output signal EA (12), and when the triangular wave oscillator output signal DO is lower than the error amplifier output signal EA. Become low level.

  In the high-side nchFET conduction prediction unit 30A of the first modified example, when the signal obtained by applying a positive offset to the triangular wave oscillator output signal DO is higher than the error amplifier output signal EA (11), the triangular wave When a signal obtained by applying a positive offset to the oscillator output signal DO is a voltage lower than the error amplifier output signal EA, it becomes a low level.

As described above, the high-side on signal HON can be output at the second timing (11) earlier than the first timing (12).
The DC-DC converter according to the first modification operates in the voltage mode, and can output the high side on signal HON even when the oscillator signal OSC cannot be obtained.

  When the error amplifier output signal EA is higher than the triangular wave oscillator output signal DO and the high side nchFET conduction control signal becomes high level, the comparator 33 reaches the error amplifier output signal EA at the non-inverting terminal. What is necessary is just to connect so that it may become a path | route and to become a path | route which reaches the triangular wave oscillator output signal DO to an inversion terminal.

(Second Embodiment)
Next, the DC-DC converter 2 according to the second embodiment will be described. FIG. 8 is a circuit diagram showing a configuration of the DC-DC converter 2 according to the second embodiment. In the DC-DC converter 2, the low-side nchFET control circuit 10 is deleted from the configuration of the DC-DC converter 1 according to the first embodiment, and an inverter INV, an anti-shoot through AST2, and switches SW1 and SW2 are added. It has a circuit configuration. In the following description, different parts will be mainly described, and description of the same parts will be simplified or omitted.

  In the inverter INV, the input is connected to the high side output terminal of the antishoot through AST1, and the output is connected to the high side and low side of the antishoot through AST2.

  In the anti-shoot through AST2, the control terminal of the switch SW1 is connected to the high side output terminal, and the control terminal of the switch SW2 is connected to the low side output terminal.

  The switch SW1 is a switch that performs an inversion operation. The switch SW1 is turned on when a low level is input to the control terminal, and is turned off when a high level is input. In the switch SW1, one end is connected to the terminal on the opposite side to the power supply voltage VB side of the capacitor C1, and the other end is connected to the connection point LX.

  The switch SW2 is a switch that performs forward rotation, and becomes conductive when a high level is inputted to the control terminal, and becomes non-conductive when a low level is inputted. In the switch SW2, one end is connected to a terminal opposite to the power supply voltage VB side of the capacitor C1, and the other end is connected to the ground potential.

  With the above configuration, when the high-side transistor control signal ASThih is at a low level and the high-side transistor FET1 is non-conductive, the switch SW1 is non-conductive and the switch SW2 is conductive. As a result, the potential difference between both ends of the capacitor C1 is set to the power supply voltage VB.

  Next, when the high side transistor control signal ASTih transitions from the low level to the high level and the high side transistor FET1 is turned on, the switch SW1 is turned on and the switch SW2 is turned off.

  Thereby, the connection point LX and the terminal on the opposite side of the power supply voltage VB side of the capacitor C1 are conducted. Since the connection point voltage VLX of the connection point LX becomes the input voltage Vin, the drive voltage VDVDD becomes a voltage value of the power supply voltage VB + the input voltage Vin due to the capacitive coupling of the capacitor C1.

  As a result, the high-side transistor FET1 can maintain conduction more stably, and the conduction impedance of the high-side transistor FET1 becomes high or becomes non-conductive despite the timing when the high-side transistor FET1 should be conducted. Can be prevented.

(Third embodiment)
Next, the DC-DC converter 3 according to the third embodiment will be described. FIG. 9 is a circuit diagram showing a configuration of the DC-DC converter 3 according to the third embodiment. The DC-DC converter 3 has a circuit configuration in which the low-side nchFET control circuit 10 is deleted from the configuration of the DC-DC converter 1 according to the first embodiment, and an inverter INV2 and a high-side transistor FET3 are added. . In the following description, different parts will be mainly described, and description of the same parts will be simplified or omitted.

  In the inverter INV2, the input is connected to the high-side output terminal of the anti-shoot through AST1, and the output is connected to the gate of the high-side transistor FET3.

  The high-side transistor FET3 is a pchFET, and has a source connected to the input voltage Vin and a drain connected to the connection point LX.

  Due to such a configuration, when the high side transistor control signal ASTih transitions from a low level to a high level, the high side transistor FET3 becomes conductive. As a result, even in the case of DCM, it is possible to prevent the high-side transistor FET1 from becoming non-conductive in spite of the timing at which it should be conductive.

Note that the present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention.
For example, in the first modification, an example in which a positive offset is applied only to the triangular wave oscillator output signal DO has been shown, but it goes without saying that the present invention can be similarly applied to a case where a negative offset is applied only to the error amplifier output signal EA. Alternatively, it goes without saying that the present invention can be similarly applied when a positive offset is applied to the triangular wave oscillator output signal DO and a negative offset is applied to the error amplifier output signal EA.

  In the second embodiment, in the DC-DC converter 2, the switch SW2 is turned on while the high-side transistor control signal ASTih is at a low level. However, the low-side in the DC-DC converter 1 according to the first embodiment Needless to say, the present invention can be similarly applied to the case where the switch SW2 is controlled to conduct only just before the high-side transistor control signal ASTih becomes high level, as in the control of the AST input signal ASTil.

  The high side transistor FET1 is an example of a high side nchFET, the low side transistor FET2 is an example of a low side nchFET, the capacitor C1 is an example of a coupling capacitor, and the low side nchFET control circuit 10 is an example of a switch control unit. The high side nchFET conduction prediction unit 30 is an example of a prediction unit, and the low side nchFET conduction control unit 40 is an example of a low side nchFET control unit. The voltage offset circuit 32 is an example of an offset unit, and the comparator 33 is an example of a detection unit. The delay element 41 and the AND gate 42 are an example of a first one-shot multivibrator, the one-shot multivibrator 43 is an example of a second one-shot multivibrator, the switch SW1 is an example of a first switch, and the switch SW2 is a second one. An example of the switch, the inverter INV, is an example of a switch control unit.

  In the DC-DC converter and the control method thereof described in the present application, the switch portion is turned on prior to the conduction of the high-side nchFET, and the switch portion is turned off in synchronization with the conduction of the high-side nchFET. Thereby, prior to the conduction of the high-side nchFET, one end on the drain side of the low-side nchFET of the coupling capacitance is connected to the ground potential. For this reason, the potential difference between both ends of the coupling capacitor becomes the first voltage. When the high-side nchFET conducts, the voltage value applied to the gate of the high-side nchFET becomes the input voltage + the first voltage due to the capacitive coupling of the coupling capacitance, so that the high-side nchFET is sufficiently conducted. Can do. Thereby, even if it enters into DCM, it can prevent that the conduction impedance of high side nchFET becomes high, or it becomes non-conduction even if it is the timing which high side nchFET should conduct.

  In the DC-DC converter described in the present application, a high-side pchFET to which an inverted signal of the control signal of the high-side nchFET is input is connected in parallel with the high-side nchFET. Therefore, even if it enters DCM, the high-side nchFET is sufficiently turned on at the timing when the high-side nchFET is turned on, so that the high-side nchFET is prevented from becoming non-conductive even when it should be turned on. be able to.

Here, the means for solving the problems in the background art according to the technical idea of the present invention are listed below.
(Supplementary Note 1) A switch unit connected between the source-side terminal of the high-side nchFET and the ground potential of a coupling capacitor connected between the path leading to the first voltage and the path leading to the source of the high-side nchFET When,
Prior to conduction of the high side nchFET, a switch control unit that conducts the switch unit, and synchronizes with conduction of the high side nchFET, and switches the switch unit off.
A DC-DC converter comprising:
(Additional remark 2) The said switch part is low side nchFET,
The switch control unit
A prediction unit for detecting that the high-side nchFET is conductive;
A low-side nchFET control unit that controls conduction of the low-side nchFET according to a result of the prediction unit;
The DC-DC converter according to appendix 1, characterized by comprising:
(Additional remark 3) The said estimation part outputs the output signal based on 2nd edge different from the 1st edge of the clock signal used as the origin of the switching control signal of the said high side nchFET, It is characterized by the above-mentioned. DC-DC converter.
(Supplementary Note 4) The prediction unit
In the voltage mode, the output signal of the error amplifier or the output of the triangular wave oscillator is such that the output signal of the error amplifier and the output signal of the triangular wave oscillator intersect at a second timing earlier than the first timing at which they intersect. An offset section for offsetting at least one of the signals;
A detection unit for detecting the second timing;
The DC-DC converter according to appendix 2, characterized by comprising:
(Supplementary Note 5) When the high-side nch FET conducts when the output signal of the triangular wave oscillator is higher in voltage than the output signal of the error amplifier, the offset unit outputs the output signal of the triangular wave oscillator. The DC-DC converter according to appendix 4, wherein an offset is applied.
(Supplementary Note 6) The low-side nchFET control unit is triggered by the output signal of the prediction unit, and after a predetermined period, the low-side nchFET is turned on and the low-side nchFET is turned off in synchronization with the conduction of the high-side nchFET. The DC-DC converter according to any one of appendices 2 to 5, characterized in that:
(Supplementary Note 7) The low-side FET control unit includes a first one-shot multivibrator that outputs a trigger signal after the predetermined period has elapsed using the edge as a trigger;
Using the output of the first one-shot multivibrator as a trigger, a second one-shot multivibrator that conducts the low-side nchFET until just before the high-side nchFET conducts;
The DC-DC converter according to appendix 6, characterized by comprising:
(Appendix 8) The switch part
A first switch connected between one end of the coupling capacitor on the side opposite to the path leading to the first voltage and a ground potential;
A second switch connected between the one end of the coupling capacitor opposite to the path leading to the first voltage and the source of the high-side pchFET;
With
The switch control unit
2. The DC− according to claim 1, wherein the first switch and the second switch are complementary to each other, and the second switch is turned on when the switching control signal of the high-side nchFET is at a high level. DC converter.
(Supplementary Note 9) A DC-DC converter including a high-side pchFET that receives an inverted signal of a control signal of a high-side nchFET and is connected in parallel to the high-side nchFET.
(Supplementary Note 10) A switch unit connected between the source-side terminal of the high-side nchFET and the ground potential of a coupling capacitor connected between the path leading to the first voltage and the path leading to the source of the high-side nchFET In a DC-DC converter comprising:
Prior to conduction of the high side nchFET, one end of the coupling capacitor on the high side nchFET side and the ground potential are conducted in the switch unit,
A method for controlling a DC-DC converter, wherein the one end of the coupling capacitor on the high-side nchFET side and the ground potential are made non-conductive in the switch unit in synchronization with the conduction of the high-side nchFET. .
(Additional remark 11) The said switch part is the said low side nchFET,
When conducting the switch part, it detects that the high-side nchFET is conducted,
11. The method of controlling a DC-DC converter according to appendix 10, wherein when the switch unit is turned off, the low-side nchFET is turned on according to the detection result.
(Supplementary note 12)
A first switch connected between the one end of the coupling capacitor opposite to the side connected to the first voltage and the ground potential;
A second switch connected between the one end of the coupling capacitor opposite to the side connected to the first voltage and a source of the high-side pchFET;
When conducting the switch section, prior to conduction of the first switch, the second switch is turned off,
11. The method of controlling a DC-DC converter according to appendix 10, wherein when the switch unit is turned off, the first switch is turned off before the second switch is turned on.
(Appendix 13)
A first conductivity type first transistor connected to the high potential side power line;
A second transistor of the first conductivity type connected between the first transistor and a low potential side power line;
A DC-DC converter having a bootstrap circuit including a capacitor connected to a connection point between the first transistor and the second transistor,
The DC-DC converter according to claim 1, wherein the potential of the first end of the capacitor connected to the connection point is lowered in accordance with a first control signal for conducting the first transistor.
(Appendix 14)
A detection unit for detecting the first control signal;
14. The DC-DC converter according to appendix 13, wherein the detection unit conducts the second transistor in accordance with the first control signal to lower the potential at the first end.
(Appendix 15)
A detector for detecting the first control signal;
A first switch for connecting / disconnecting the first end of the capacitor and the low-potential side power line;
14. The supplementary note 13, wherein the first switch lowers the potential at the first end by connecting the first end and the low potential side power source in response to the first control signal. DC-DC converter.
(Appendix 16)
The DC-DC according to any one of appendices 13 to 15, wherein the first control signal is a control signal generated when the first transistor and the second transistor are non-conductive. converter.

1, 2, 3 DC-DC converter 10 Low side nchFET control circuit 30 High side nchFET conduction prediction unit 30A High side nchFET conduction prediction unit 31 Inverter 32 Voltage offset circuit 33 Comparator 40 Low side nchFET conduction control unit 41 Delay element 42 AND gate 43 one shot multivibrator 44 OR gate VB power supply voltage VDVDD drive voltage VLX node voltage Vin input voltage

Claims (6)

And low nchFET connected between the source-side terminal and the ground potential of the high side nchFET capacitor connected between the path leading to the source of the route and the high side nchFET reaching the first voltage,
Wherein prior to the conduction of the high-side NchFET, conducts the low side NchFET, in synchronization with the conduction of the high side NchFET, and a switch control unit for the low-side NchFET nonconductive,
Before Symbol switch control unit,
A prediction unit for detecting that the high-side nchFET is conductive;
A low-side nchFET control unit that controls conduction of the low-side nchFET according to a result of the prediction unit;
The prediction unit
In the voltage mode, the output signal of the error amplifier or the output of the triangular wave oscillator is such that the output signal of the error amplifier and the output signal of the triangular wave oscillator intersect at a second timing earlier than the first timing at which they intersect. An offset section for offsetting at least one of the signals;
A detection unit for detecting the second timing ,
The low-side nchFET controller is
A first one-shot multivibrator that outputs a trigger signal after an elapse of a predetermined period triggered by an edge of the output signal of the prediction unit;
A second one-shot multivibrator that conducts the low-side nchFET using the output of the first one-shot multivibrator as a trigger until immediately before the high-side nchFET is conducted. DC converter. A low-side nchFET connected between the source-side terminal of the high-side nchFET and a ground potential of a capacitor connected between a path leading to the first voltage and a path leading to the source of the high-side nchFET;
Prior to the conduction of the high-side nchFET, a switch control unit that conducts the low-side nchFET and makes the low-side nchFET non-conductive in synchronization with the conduction of the high-side nchFET;
An inverted signal of the control signal of the high-side nchFET is input to the gate, and a high-side pchFET connected in parallel with the high-side nchFET,
The switch control unit
A prediction unit for detecting that the high-side nchFET is conductive;
A low-side nchFET control unit that controls conduction of the low-side nchFET according to a result of the prediction unit;
The prediction unit
In the voltage mode, the output signal of the error amplifier or the output of the triangular wave oscillator is such that the output signal of the error amplifier and the output signal of the triangular wave oscillator intersect at a second timing earlier than the first timing at which they intersect. An offset section for offsetting at least one of the signals;
A detection unit for detecting the second timing;
A DC-DC converter comprising: The offset unit applies an offset to the output signal of the triangular wave oscillator when the high-side nch FET conducts when the output signal of the triangular wave oscillator is higher in voltage than the output signal of the error amplifier. The DC-DC converter according to claim 1 or 2 , wherein the DC-DC converter is characterized. The low-site nchFET controller is triggered by the output signal of the prediction unit, and after a predetermined period, the low-side nchFET is turned on, and the low-side nchFET is turned off in synchronization with the conduction of the high-side nchFET. 3. The DC-DC converter according to claim 2 , wherein A DC-DC converter including a low-side nchFET connected between a source-side terminal of the high-side nchFET and a ground potential of a capacitor connected between a path leading to a first voltage and a path leading to a source of the high-side nchFET. a control method,
Prior to conduction of the high-side NchFET, conducting the one end and the ground potential of the high side NchFET side of the capacitor in the low NchFET,
In synchronization with the conduction of the high-side NchFET, the said one end and the ground potential of the high side NchFET side of the capacitor to the non-conductive in the low NchFET,
The conduction and control of non-conduction of the previous SL low-side nchFET,
Detect and predict that the high-side nchFET is conducting,
A trigger signal is output after a predetermined period with the result of the prediction detection as a trigger,
Conducting the low-side nchFET in response to the output trigger signal until just before the high-side nchFET is conducted,
The prediction test knowledge is,
In the voltage mode, the output signal of the error amplifier or the output of the triangular wave oscillator is such that the output signal of the error amplifier and the output signal of the triangular wave oscillator intersect at a second timing earlier than the first timing at which they intersect. Offset at least one of the signals,
Detecting the second timing; and a method for controlling a DC-DC converter, comprising: detecting the second timing. A low-side nchFET connected between a source-side terminal of the high-side nchFET and a ground potential of a capacitor connected between a path leading to the first voltage and a path leading to the source of the high-side nchFET, and the high-side nchFET A control method for a DC-DC converter comprising a high-side pchFET connected to a high-side nchFET in parallel with an inverted signal of a control signal being input to a gate,
Prior to the conduction of the high-side nchFET, one end of the capacitor on the high-side nchFET side and the ground potential are conducted in the low-side nchFET,
In synchronization with the conduction of the high-side nchFET, the one end on the high-side nchFET side of the capacitor and the ground potential are made non-conductive in the low-side nchFET,
Control of conduction / non-conduction of the low-side nchFET is as follows:
Detect and predict that the high-side nchFET is conducting,
Controlling the conduction of the low-side nchFET according to the result of the prediction detection,
The predictive detection
In the voltage mode, the output signal of the error amplifier or the output of the triangular wave oscillator is such that the output signal of the error amplifier and the output signal of the triangular wave oscillator intersect at a second timing earlier than the first timing at which they intersect. Offset at least one of the signals,
Detecting the second timing.
A control method of a DC-DC converter characterized by the above.

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