JP5487956B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a semiconductor substrate having a diode region and an IGBT region.

  Patent Document 1 discloses a semiconductor device in which a diode and an IGBT are formed on the same semiconductor substrate. The drift region of the diode and the drift region of the IGBT are connected at the boundary between the diode and the IGBT.

JP 2008-235405 A

  If the load connected to the IGBT is short-circuited when the IGBT is on, an overcurrent flows through the IGBT. For example, in an IGBT used in an inverter device for driving a motor, when the motor is locked, the motor is short-circuited. For this reason, an overvoltage is applied to the IGBT and an overcurrent flows. If an overcurrent continues to flow through the IGBT for a certain time or longer, the IGBT is damaged. In general, the IGBT is required to have a long time that can withstand a load short-circuit state (a state in which an overcurrent flows) (hereinafter, this characteristic is referred to as a short-circuit tolerance). As a technique for improving the short-circuit tolerance, a technique for forming a solder layer on an IGBT electrode is known. By forming the solder layer, the heat dissipation of the IGBT semiconductor substrate can be improved and the temperature rise of the semiconductor substrate can be suppressed. Thereby, the short circuit tolerance of IGBT can be improved.

  In a semiconductor device in which an IGBT and a diode are formed on the same substrate as in the semiconductor device of Patent Document 1, when an overcurrent flows through the IGBT, some of the holes in the IGBT drift region are part of the diode drift region. Flows in. That is, a high current flows also in a portion near the boundary between the IGBT and the diode in the drift region of the diode. Since there are few holes in the drift region of the diode, the conductivity modulation effect is not sufficiently generated in the drift region of the diode. In other words, the drift region of the diode has a high electrical resistance. Since a high current flows in the drift region of the diode having a high electrical resistance in this way, heat is generated in this region. When such local heat generation occurs, even if a solder layer is formed on the electrode, the temperature rise of the semiconductor substrate cannot be sufficiently suppressed. For this reason, in the semiconductor device in which the IGBT and the diode are formed on the same substrate, there is a problem that the boundary portion between the IGBT and the diode becomes high temperature when the load is short-circuited, and the short-circuit tolerance is low.

  The present invention has been created in view of the above problems. The present invention provides a semiconductor device having an IGBT and a diode and having a high short-circuit tolerance.

The semiconductor device of the present invention includes a semiconductor substrate having a diode region and an IGBT region. An anode region, a diode drift region, and a cathode region are formed in the diode region. The anode region is p-type and is formed in a range including the upper surface of the semiconductor substrate. The diode drift region is n-type and is formed below the anode region. The cathode region is n-type, has an n-type impurity concentration higher than that of the diode drift region, and is formed in a range below the diode drift region including the lower surface of the semiconductor substrate. Within the IGBT region, an emitter region, a body region, an IGBT drift region, a collector region, and a gate electrode are formed. The emitter region is n-type and is formed in a range including the upper surface of the semiconductor substrate. The body region is p-type and is formed in a range including the upper surface of the semiconductor substrate and a range below the emitter region, and is in contact with the emitter region. The IGBT drift region is n-type, is formed below the body region, and is separated from the emitter region by the body region. The collector region is p-type and is formed in a range below the IGBT drift region including the lower surface of the semiconductor substrate. The gate electrode faces the body region in a range separating the emitter region and the IGBT drift region via an insulating film. The cathode region and the collector region are adjacent. A common electrode extending continuously from the diode region to the IGBT region and electrically connected to the anode region, the emitter region, and the body region is formed on the upper surface of the semiconductor substrate. A solder layer is formed from the common electrode in the diode region to the common electrode in the IGBT region . An insulating layer is formed between the upper surface of the common electrode above the boundary between the cathode region and the collector region and the solder layer above the boundary .

In this semiconductor device, since the common electrode in the diode region and the common electrode in the IGBT region are covered with the solder layer, even if heat is generated in the semiconductor substrate, heat is conducted from the semiconductor substrate to the solder layer. Therefore, the temperature rise of the semiconductor substrate is suppressed. Further, in this semiconductor device, an insulating layer is formed between the upper surface of the common electrode above the boundary between the cathode region and the collector region and the solder layer above the boundary. That is, the common electrode is not directly conducted to the solder layer above the boundary portion. Therefore, when the IGBT is turned on, it is difficult for a current to flow in a region near the boundary (that is, a region near the boundary between the diode drift region and the IGBT drift region). For this reason, when an overcurrent flows through the IGBT, heat generation at the boundary between the diode region and the IGBT region is suppressed. For this reason, this semiconductor device has a high short circuit tolerance.

In addition, a semiconductor device according to an embodiment disclosed in the present specification includes a semiconductor substrate having a diode region and an IGBT region. An anode region, a diode drift region, and a cathode region are formed in the diode region. The anode region is p-type and is formed in a range including the upper surface of the semiconductor substrate. The diode drift region is n-type and is formed below the anode region. The cathode region is n-type, has an n-type impurity concentration higher than that of the diode drift region, and is formed in a range below the diode drift region including the lower surface of the semiconductor substrate. Within the IGBT region, an emitter region, a body region, an IGBT drift region, a collector region, and a gate electrode are formed. The emitter region is n-type and is formed in a range including the upper surface of the semiconductor substrate. The body region is p-type and is formed in a range including the upper surface of the semiconductor substrate and a range below the emitter region, and is in contact with the emitter region. The IGBT drift region is n-type, is formed below the body region, and is separated from the emitter region by the body region. The collector region is p-type and is formed in a range below the IGBT drift region including the lower surface of the semiconductor substrate. The gate electrode faces the body region in a range separating the emitter region and the IGBT drift region via an insulating film. The cathode region and the collector region are adjacent. On the upper surface of the semiconductor substrate, an anode electrode that is electrically connected to the anode region and an emitter electrode that is electrically connected to the emitter region and the body region are formed. A solder layer is formed from the anode electrode to the emitter electrode. An insulating layer is formed between the upper surface of the semiconductor substrate above the boundary between the cathode region and the collector region and the solder layer above the boundary.
The insulating layer may be formed in contact with the upper surface of the semiconductor substrate above the boundary portion. Alternatively, the anode electrode and the emitter electrode may be connected at a position in contact with the upper surface of the semiconductor substrate above the boundary portion, and the insulating layer may be formed on the electrode.
In this semiconductor device, since the anode electrode and the emitter electrode are covered with the solder layer, even if heat is generated in the semiconductor substrate, heat is conducted from the semiconductor substrate to the solder layer. Therefore, the temperature rise of the semiconductor substrate is suppressed. Furthermore, in this semiconductor device, an insulating layer is formed between the upper surface of the semiconductor substrate above the boundary between the cathode region and the collector region and the solder layer above the boundary. That is, the semiconductor substrate is not directly connected to the solder layer above the boundary. Therefore, when the IGBT is turned on, it is difficult for a current to flow in a region near the boundary (that is, a region near the boundary between the diode drift region and the IGBT drift region). For this reason, when an overcurrent flows through the IGBT, heat generation at the boundary between the diode region and the IGBT region is suppressed. For this reason, this semiconductor device has a high short circuit tolerance.
In the semiconductor device described above, it is preferable that the insulating layer is in contact with the upper surface of the semiconductor substrate, and the anode electrode and the emitter electrode are separated by the insulating layer.
According to such a configuration, the current is less likely to flow at the boundary between the diode region and the IGBT region. As a result, heat generation at the boundary between the diode region and the IGBT region can be further suppressed.

  In the semiconductor device described above, the semiconductor substrate includes a p-type isolation region above the boundary between the cathode region and the collector region and in a range from the upper surface of the semiconductor substrate to a depth deeper than the anode region and the body region. Is preferably formed. The insulating layer preferably covers the upper surface of the isolation region.

1 is a longitudinal sectional view of a semiconductor device of Example 1. FIG. FIG. 5 is a longitudinal sectional view of a semiconductor device according to a second embodiment. FIG. 6 is a longitudinal sectional view of a semiconductor device according to a modification of the first embodiment. FIG. 10 is a longitudinal sectional view of a semiconductor device according to a modification of the second embodiment.

(Structure of semiconductor device)
FIG. 1 is a sectional view of a semiconductor device 10 according to the first embodiment. As shown in FIG. 1, the semiconductor device 10 includes a semiconductor substrate 12 and a metal layer, an insulating layer, and the like formed on the upper surface and the lower surface of the semiconductor substrate 12. A diode region 20 and an IGBT region 40 are formed in the semiconductor substrate 12.

  An anode electrode 22 is formed on the upper surface of the semiconductor substrate 12 in the diode region 20. An emitter electrode 42 is formed on the upper surface of the semiconductor substrate 12 in the IGBT region 40. A common electrode 60 is formed on the lower surface of the semiconductor substrate 12.

  In the diode region 20, an anode layer 26, a diode drift layer 28, and a cathode layer 30 are formed.

The anode layer 26 includes an anode contact region 26a and a low concentration anode layer 26b.
The anode contact region 26a is a p-type region and has a high impurity concentration. The anode contact region 26 a is formed in an island shape in a range including the upper surface of the semiconductor substrate 12. The anode contact region 26 a is ohmically connected to the anode electrode 22.
The low concentration anode layer 26b is a p-type region. The impurity concentration of the low concentration anode layer 26b is lower than the impurity concentration of the anode contact region 26a. The low concentration anode layer 26b is formed on the lower side and the side of the anode contact region 26a and covers the anode contact region 26a.

  The diode drift layer 28 is an n-type region, and its impurity concentration is low. The diode drift layer 28 is formed below the low concentration anode layer 26b.

  The cathode layer 30 is an n-type region. The impurity concentration of the cathode layer 30 is higher than the impurity concentration of the diode drift layer 28. The cathode layer 30 is formed below the diode drift layer 28. The cathode layer 30 is formed in a range including the lower surface of the semiconductor substrate 12 and is ohmically connected to the common electrode 60.

  A diode is formed in the diode region 20 by the anode layer 26, the diode drift layer 28, and the cathode layer 30. Hereinafter, the diode formed in the diode region 20 is referred to as a diode 20.

  In the IGBT region 40, an emitter region 44, a body layer 46, an IGBT drift layer 50, a collector layer 52, a gate electrode 54, and the like are formed.

  A plurality of trenches are formed on the upper surface of the semiconductor substrate 12 in the IGBT region 40. A gate insulating film 56 is formed on the inner surface of each trench. A gate electrode 54 is formed inside each trench. The upper surface of the gate electrode 54 is covered with an insulating film 58. The gate electrode 54 is insulated from the emitter electrode 42 by the insulating film 58.

  The emitter region 44 is an n-type region and has a high impurity concentration. The emitter region 44 is formed in an island shape in a range including the upper surface of the semiconductor substrate 12. The emitter region 44 is formed in a range in contact with the gate insulating film 56. The emitter region 44 is ohmically connected to the emitter electrode 42.

The body layer 46 includes a body contact region 46a and a low concentration body layer 46b.
The body contact region 46a is a p-type region and has a high impurity concentration. The body contact region 46 a is formed in an island shape in a range including the upper surface of the semiconductor substrate 12. The body contact region 46 a is formed between the two emitter regions 44. The body contact region 46 a is ohmically connected to the emitter electrode 42.
The low concentration body layer 46b is a p-type region. The impurity concentration of the low-concentration body layer 46b is lower than that of the body contact region 46a. The low concentration body layer 46b is formed below the emitter region 44 and the body contact region 46a. The emitter region 44 is separated from the IGBT drift layer 50 by the low concentration body layer 46b. The gate electrode 54 is opposed to the low-concentration body layer 46 b in a range separating the emitter region 44 and the IGBT drift layer 50 through the gate insulating film 56.

The IGBT drift layer 50 is an n-type region. The IGBT drift layer 50 is formed below the body layer 46. The IGBT drift layer 50 includes a drift layer 50a and a buffer layer 50b.
The drift layer 50 a is formed below the body layer 46. The impurity concentration of the drift layer 50 a is substantially equal to that of the diode drift layer 28. The drift layer 50 a is a layer that is continuous with the diode drift layer 28.
The buffer layer 50b is formed below the drift layer 50a. The buffer layer 50b has a higher impurity concentration than the drift layer 50a.

  The collector layer 52 is a p-type region and has a high impurity concentration. The collector layer 52 is formed below the IGBT drift layer 50. The collector layer 52 is formed in a range including the lower surface of the semiconductor substrate 12 and is ohmically connected to the common electrode 60.

  In the IGBT region 40, an IGBT is formed by the emitter region 44, the body layer 46, the IGBT drift layer 50, the collector layer 52, and the gate electrode 54. Hereinafter, the IGBT formed in the IGBT region 40 is referred to as an IGBT 40.

  An isolation region 70 is formed in a range including the upper surface of the semiconductor substrate 12 between the diode region 20 and the IGBT region 40. The isolation region 70 is a p-type region. The impurity concentration of the isolation region 70 is higher than the impurity concentration of the low concentration anode layer 26b and the low concentration body layer 46b. The isolation region 70 is in contact with the low concentration anode layer 26b on the diode region 20 side. Isolation region 70 is in contact with body layer 46 on the IGBT region 40 side. The lower end of the isolation region 70 is deeper than the lower end of the gate electrode 54.

  The cathode layer 30 in the diode region 20 extends to the lower part of the isolation region 70, and the collector layer 52 of the IGBT region 40 extends to the lower part of the isolation region 70. The cathode layer 30 is in contact with the collector layer 52 below the isolation region 70. That is, the boundary 72 between the cathode layer 30 and the collector layer 52 is located below the separation region 70.

  Below the isolation region 70, the diode drift layer 28 and the IGBT drift layer 50 are connected. That is, the diode drift layer 28 and the IGBT drift layer 50 are continuous n-type layers. Hereinafter, a region where the diode drift layer 28 and the IGBT drift layer 50 are continuous (that is, the n-type region above the boundary 72) may be referred to as a drift layer 62.

An insulating film 90 (SiO ₂ film) is formed on the isolation region 70. A gate wiring 88 is formed on the insulating film 90. The gate wiring 88 is connected to each gate electrode 54 at a location not shown. The gate wiring 88 is covered with an insulating film 92. The insulating film 92 is composed of NSG (non-doped silicate glass), BPSG (borophosphosilicate glass), SInSiN (semi-insulating silicon nitride), or the like, or a laminate thereof. The insulating film 92 is covered with an insulating film 94. The insulating film 94 is made of polyimide. The anode electrode 22 is separated from the emitter electrode 42 by the insulating films 90, 92 and 94 on the separation region 70.

  The surface of the anode electrode 22, the insulating film 94, and the surface of the emitter electrode 42 are covered with a solder layer 96. A metal block 98 is present on the solder layer 96. That is, the anode electrode 22 and the emitter electrode 42 are joined to the metal block 98 by the solder layer 96. The anode electrode 22 and the emitter electrode 42 are electrically connected via the solder layer 96.

(Operation of Semiconductor Device 10)
First, the operation of the diode 20 will be described. When a voltage that is positive for the anode electrode 22 (ie, forward voltage) is applied between the anode electrode 22 and the common electrode 60, the diode 20 is turned on. That is, a current flows from the anode electrode 22 toward the common electrode 60.

  Next, the operation of the IGBT 40 will be described. When an ON potential is applied to the gate electrode 54 in a state where a voltage that makes the common electrode 60 positive is applied between the emitter electrode 42 and the common electrode 60, the IGBT 40 is turned on. That is, when an on potential is applied to the gate electrode 54, electrons gather in a region of the body layer 46 in contact with the gate insulating film 56, and a channel is formed. Then, electrons flow from the emitter electrode 42 toward the common electrode 60 via the emitter region 44, the channel, the IGBT drift layer 50, and the collector layer 52. At the same time, holes flow from the common electrode 60 toward the emitter electrode 42 via the collector layer 52, the IGBT drift layer 50, and the body layer 46. That is, a current flows from the common electrode 60 toward the emitter electrode 42. Since electrons and holes are present in the IGBT drift layer 50, the electrical resistance of the IGBT drift layer 50 decreases due to the conductivity modulation phenomenon. Therefore, the loss generated in the IGBT 40 when a current flows is small.

When a load (for example, a motor or the like) connected to the IGBT 40 is short-circuited, an overvoltage is applied to the IGBT 40. When an overvoltage is applied to the IGBT 40 in the on state, an overcurrent flows through the IGBT 40. At this time, since the IGBT drift layer 50 has a low resistance due to the conductivity modulation effect, heat generation does not occur so much even if a high current flows through the IGBT drift layer 50.
On the other hand, since there are almost no holes in the drift layer 62 between the IGBT region 40 and the diode region 20, the electrical resistance of the drift layer 62 is high. For this reason, if a high current flows through the drift layer 62, the drift layer 62 locally becomes a high temperature.
However, the surface of the isolation region 70 above the drift layer 62 is covered with the insulating films 90 to 94. For this reason, even if an overvoltage is applied to the IGBT 40, it is difficult for a high current to flow through the isolation region 70. That is, a high current does not flow through the drift layer 62 below the isolation region 70. Thereby, the temperature rise of the drift layer 62 is suppressed.

  The emitter electrode 42 and the anode electrode 22 are joined to the metal block 98 by a solder layer 96. For this reason, the heat generated in the semiconductor substrate 12 is conducted to the metal block 98 through the solder layer 96. As described above, the heat dissipation of the semiconductor substrate 12 is promoted by the solder layer 96 and the metal block 98. Also by this, the temperature rise of the semiconductor substrate 12 is suppressed.

  As described above, in the semiconductor device 10, since the upper surface of the isolation region 70 above the boundary 72 between the cathode layer 30 and the collector layer 52 is covered with the insulating films 90 to 94, an overcurrent flows through the IGBT 40. However, it is difficult for current to flow through the drift layer 62 between the diode region 20 and the IGBT region 40. For this reason, the temperature of the drift layer 62 is difficult to increase. Further, the temperature rise of the entire semiconductor substrate 12 is suppressed by the solder layer 96 and the metal block 98. Therefore, the semiconductor device 10 has a high short-circuit tolerance.

(Structure of semiconductor device)
FIG. 2 is a cross-sectional view of the semiconductor device 100 according to the second embodiment. In the semiconductor device 100 according to the second embodiment, an IGBT structure is formed over the entire upper surface side of the semiconductor substrate 112. That is, the emitter region 144, the body layer 146 (that is, the body contact region 146 a and the low concentration body layer 146 b), and the gate electrode 154 are formed on the upper surface side of the semiconductor substrate 112. Under the body layer 146, the drift layer 150 (that is, the drift layer 150a and the buffer layer 150b) is formed. In the range including the lower surface of the semiconductor substrate 112 of the semiconductor device 100, the cathode layer 130 and the collector layer 152 are formed adjacent to each other. The semiconductor substrate 112 in the range where the cathode layer 130 is formed is a diode region 120 that functions as a diode. That is, a diode is formed in the diode region 120 by the body layer 146, the drift layer 150, and the cathode layer 130. On the other hand, the semiconductor substrate 112 in the range where the collector layer 152 is formed is an IGBT region 140 that functions as an IGBT. That is, an IGBT is formed in the IGBT region 140 by the emitter region 144, the body layer 146, the drift layer 150, the collector layer 152, and the gate electrode 154.

  In the semiconductor device 100, the common electrode 122 is formed on the upper surface of the semiconductor substrate 112 from the diode region 120 to the IGBT region 140. That is, in the semiconductor device 100, the anode electrode of the diode and the emitter electrode of the IGBT are not separated but are shared. A common electrode 160 is formed on the lower surface of the semiconductor substrate 112.

  An insulating film 192 is formed on the surface of the common electrode 122 above the boundary 172 between the cathode layer 130 and the collector layer 152. The insulating film 192 is composed of NSG, BPSG, SInSiN, or the like, or a stacked body thereof. The insulating film 192 is covered with the insulating film 194. The insulating film 194 is made of polyimide.

  The surface of the common electrode 122 and the surface of the insulating film 194 are covered with a solder layer 196. A metal block 198 is present on the solder layer 196. That is, the common electrode 122 is joined to the metal block 198 by the solder layer 196.

(Operation of Semiconductor Device 100)
The diode in the diode region 120 operates in the same manner as the semiconductor device 10 of the first embodiment.
On the other hand, the IGBT in the IGBT region 140 operates as follows. When an ON potential is applied to the gate electrode 154 in a state where a voltage that makes the common electrode 160 positive is applied between the common electrode 122 and the common electrode 160, a channel is formed in the body layer 146 in the IGBT region 140, The IGBT in the IGBT region 140 is turned on. That is, the drift layer 150a in the IGBT region 140 has a low resistance due to the conductivity modulation effect, and a current flows in the IGBT region 140 from the common electrode 160 toward the common electrode 122.
At this time, an ON potential is also applied to the gate electrode 154 in the diode region 120, so that a channel is also formed in the body layer 146 in the diode region 120. However, since almost no holes flow into the drift layer 150a in the diode region 120, the conductivity modulation effect hardly occurs. Therefore, almost no current flows through the diode region 120.

When a load (for example, a motor or the like) connected to the IGBT of the semiconductor device 100 according to the second embodiment is short-circuited, an overvoltage is applied to the IGBT. When an overvoltage is applied to the IGBT in the on state, an overcurrent flows through the IGBT. At this time, since the drift layer 150a in the IGBT region 140 has a low resistance due to the conductivity modulation effect, heat generation does not occur so much even when a high current flows.
On the other hand, since there are not many holes in the drift layer 150a between the IGBT region 140 and the diode region 120 (drift layer 150a near the upper portion of the boundary 172), the electrical resistance of the drift layer 150a near the upper portion of the boundary 172 is high. . Therefore, if a high current flows through the drift layer 150a near the upper portion of the boundary 172, the temperature rises locally.
However, in the semiconductor device 100, the upper surface of the common electrode 122 above the boundary 172 is covered with the insulating film 192 and is not directly bonded to the solder layer 196. Since the common electrode 122 is thin and the current path from the common electrode 122 covered with the insulating film 192 to the solder layer 196 is long, the common electrode 122 covered with the insulating film 192 includes other electrodes. Compared with the common electrode 122 in the range, the current hardly flows. For this reason, a high current does not flow through the drift layer 150a above the boundary 172. As a result, the temperature rise of the drift layer 150a above the boundary 172 is suppressed.

  As described above, even in the semiconductor device 100 of the second embodiment, when an overcurrent flows through the IGBT, heat generation in the drift region at the boundary between the diode region 120 and the IGBT region 140 can be suppressed. Furthermore, the temperature rise of the entire semiconductor substrate 112 is suppressed by the solder layer 196 and the metal block 198. Therefore, the semiconductor device 100 has a high short-circuit tolerance.

  In the drift layer in the diode region, carrier lifetime control regions 39 and 139 may be formed as shown in FIGS. The carrier lifetime control region is a region under which crystal defects are formed by implanting charged particles into the semiconductor substrate. The carrier lifetime control region functions as a carrier recombination center. By forming the carrier lifetime control region, the recovery surge current of the diode can be suppressed.

  Further, as shown in FIG. 3, the body layer may be separated into an upper body layer 46 and a lower body layer 49 by an n-type hole stopper layer 48. Thus, by providing the hole stopper layer 48, it is possible to prevent the holes from flowing toward the upper body layer 46 when the IGBT is turned on. As a result, the hole concentration in the drift layer 50a can be increased, and the loss generated in the drift layer 50a can be further reduced.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

10: Semiconductor device 12: Semiconductor substrate 20: Diode region 22: Anode electrode 26: Anode layer 26a: Anode contact region 26b: Low concentration anode layer 28: Diode drift layer 30: Cathode layer 39: Diode carrier lifetime control region 40: IGBT region 42: emitter electrode 44: emitter region 46: body layer 46a: body contact region 46b: low-concentration body layer 50: IGBT drift layer 50a: drift layer 50b: buffer layer 52: collector layer 54: gate electrode 56: gate insulation Film 58: Insulating film 60: Common electrode 62: Drift layer 70: Isolation region 72: Boundary 88: Gate wiring 90: Insulating film 92: Insulating film 94: Insulating film 96: Solder layer 98: Metal block

Claims (1)

A semiconductor device comprising a semiconductor substrate having a diode region and an IGBT region,
In the diode area,
an anode region which is p-type and formed in a range including the upper surface of the semiconductor substrate;
a diode drift region that is n-type and is formed below the anode region;
a cathode region that is n-type, has a higher n-type impurity concentration than the diode drift region, and is formed in a range below the diode drift region including the lower surface of the semiconductor substrate;
Is formed,
In the IGBT region,
an n-type emitter region formed in a range including the upper surface of the semiconductor substrate;
a body region that is p-type and is formed in a range including the upper surface of the semiconductor substrate and in a range below the emitter region, and in contact with the emitter region;
an IGBT drift region that is n-type, formed below the body region and separated from the emitter region by the body region;
a collector region that is p-type and is formed in a lower range of the IGBT drift region including the lower surface of the semiconductor substrate;
A gate electrode facing the body region in a range separating the emitter region and the IGBT drift region through an insulating film;
Is formed,
On the upper surface of the semiconductor substrate, a common electrode is formed which extends continuously from the diode region to the IGBT region and is electrically connected to the anode region, the emitter region, and the body region .
A solder layer is formed from the common electrode in the diode region to the common electrode in the IGBT region ,
An insulating layer is formed between the upper surface of the common electrode above the boundary between the cathode region and the collector region and the solder layer above the boundary.
A semiconductor device.

Images