JP5456113B2 - 樹脂封止パッケージ - Google Patents
樹脂封止パッケージ Download PDFInfo
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- JP5456113B2 JP5456113B2 JP2012179403A JP2012179403A JP5456113B2 JP 5456113 B2 JP5456113 B2 JP 5456113B2 JP 2012179403 A JP2012179403 A JP 2012179403A JP 2012179403 A JP2012179403 A JP 2012179403A JP 5456113 B2 JP5456113 B2 JP 5456113B2
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- 239000011347 resin Substances 0.000 title claims description 72
- 229920005989 resin Polymers 0.000 title claims description 72
- 238000007789 sealing Methods 0.000 claims description 46
- 230000003014 reinforcing effect Effects 0.000 claims description 12
- 239000000853 adhesive Substances 0.000 claims description 7
- 230000001070 adhesive effect Effects 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 27
- 239000012790 adhesive layer Substances 0.000 description 19
- 238000004519 manufacturing process Methods 0.000 description 13
- 238000000034 method Methods 0.000 description 10
- 238000007796 conventional method Methods 0.000 description 5
- 230000017525 heat dissipation Effects 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000002349 favourable effect Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
支持体と素子との間の仮接着を、後の工程で支持体を素子を含むパッケージから剥離する必要があることを考慮して、予め弱くしておくと、素子を支持体に仮接着した後樹脂封止する際に、端子と支持体との間に樹脂が混入して端子が汚染されたり、樹脂の注入時の圧力によって素子の位置が支持体に対して所定の位置からずれることがある。
また、従来の封止樹脂パッケージの製造方法によると、樹脂の凹凸や反りによって後に形成される絶縁樹脂を平坦に形成できず、精度の良い配線形成が困難となり、配線のファインピッチ化が妨げられる、という問題がある。
図2(a)〜図2(d)及び図3(a)〜図3(c)は、本発明の樹脂封止パッケージの製造方法の実施形態を示す。
12、14、16 電子部品
12a、14a、16a 端子
20 第1の接着剤層
22 封止樹脂
24 絶縁樹脂層
26 ビア
28 配線層
30 ソルダレジスト
32 外部端子
40 第2の支持体
42 第2の接着剤層
Claims (4)
- 電子部品は、複数の端子を有する第一面と、該第一面とは反対側の第二面と、該第一面及び該第二面間を連接する側面と、からなり、高さの異なる複数の前記電子部品を備え、
複数の前記電子部品の端子の表面を所定の平面上に揃えるように、前記電子部品の端子の表面を露出し、且つ表面が前記電子部品の端子の表面と同一面となるように形成され、前記電子部品の側面の一部及び前記第二面を露出して封止する封止樹脂と、
前記電子部品及び前記封止樹脂上に形成され、絶縁樹脂層と前記電子部品の端子に電気的に接続する配線層とからなる積層構造体と、
前記積層構造体と前記封止樹脂の間において、前記封止樹脂に埋め込まれ、前記積層体の対向面が、前記電子部品の端子の表面及び前記封止樹脂の表面と同一面となり、且つ複数の前記電子部品の間に配置された補強部材と、
を有することを特徴とする樹脂封止パッケージ。 - 前記補強部材は補強板であることを特徴とする請求項1に記載の樹脂封止パッケージ。
- 前記補強部材は、導電性補強層であることを特徴とする請求項1又は2に記載の樹脂封止パッケージ。
- 封止樹脂から露出している電子部品の第二面に接着剤を介してヒートシンクが接続され、該ヒートシンクの電子部品の第二面に対向する面と前記各電子部品の第二面との間の距離は、各電子部品ごとに異なることを特徴とする請求項1〜3のいずれか1項に記載の樹脂封止パッケージ。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012179403A JP5456113B2 (ja) | 2012-08-13 | 2012-08-13 | 樹脂封止パッケージ |
Applications Claiming Priority (1)
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---|---|---|---|
JP2012179403A JP5456113B2 (ja) | 2012-08-13 | 2012-08-13 | 樹脂封止パッケージ |
Related Parent Applications (1)
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JP2008328365A Division JP5147677B2 (ja) | 2008-12-24 | 2008-12-24 | 樹脂封止パッケージの製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2012216878A JP2012216878A (ja) | 2012-11-08 |
JP5456113B2 true JP5456113B2 (ja) | 2014-03-26 |
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JP2012179403A Active JP5456113B2 (ja) | 2012-08-13 | 2012-08-13 | 樹脂封止パッケージ |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10615103B2 (en) | 2018-03-23 | 2020-04-07 | Kabushiki Kaisha Toshiba | Semiconductor device |
Families Citing this family (1)
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JP6712051B2 (ja) * | 2016-06-22 | 2020-06-17 | 富士通株式会社 | 半導体装置、半導体装置の製造方法及び電子装置 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2008502158A (ja) * | 2004-06-03 | 2008-01-24 | インターナショナル レクティファイアー コーポレイション | 平面性と放熱性の良好な高出力マルチチップモジュールパッケージ |
JP2006278771A (ja) * | 2005-03-29 | 2006-10-12 | Nec Corp | 半導体装置及びその製造方法 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US10615103B2 (en) | 2018-03-23 | 2020-04-07 | Kabushiki Kaisha Toshiba | Semiconductor device |
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