JP5322457B2 - Voltage comparison device, electronic system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage comparator that handles the voltage drop of an input voltage. <P>SOLUTION: The voltage comparator includes a comparator 2, which compares a predetermined reference voltage VREF with an input voltage VCCIN and outputs a detection signal VCCOK, by which it gets in the first state when the input voltage VCCIN is lower than the reference voltage VREF and gets in the second state when the input voltage VCCIN is higher than the reference voltage VREF, and an input voltage generating circuit 3, which enables it to output a plurality of candidate voltages V1-V5 that become the candidates of the input voltage VCCIN and outputs a candidate voltage lower than the input voltage VCCIN, as an input voltage VCCIN, to the comparator 2 when the detection signal VCCOK is in the first state and outputs a candidate voltage higher than the input voltage VCCIN, as an input voltage VCCIN, to the comparator 2 when the detection signal VCCIN is in the second state. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a voltage comparison device that detects whether or not a power supply voltage is higher than a reference voltage by comparing a power supply voltage applied to a semiconductor device including a large number of elements such as a memory with a reference voltage, and this The present invention relates to an electronic system including such a voltage comparison device.

  As a conventional voltage comparison device, for example, there is one that compares a power supply voltage input to a semiconductor device with a predetermined reference voltage to detect whether the power supply voltage is sufficient for normal operation of the semiconductor device. The detection signal representing the detection result can be used as a lockout signal of a semiconductor device, for example. If the power supply voltage is sufficient for normal operation by the lockout signal, the semiconductor device enters an operating state, and if the power supply voltage is insufficient for normal operation, the semiconductor device enters a non-operating state.

  When the power supply voltage is applied to a semiconductor device having a large number of elements such as a flash memory, it may be unstable. For example, when the semiconductor device is brought into an operating state by a lockout signal, the load is rapidly increased, so that the power supply voltage is decreased. Since the semiconductor device enters an operating state when the power supply voltage becomes equal to or higher than the reference voltage, such a voltage drop occurs immediately after the power supply voltage becomes equal to or higher than the reference voltage. Due to the voltage drop, the power supply voltage becomes lower than the reference voltage again. When the voltage comparator detects this, the lockout signal switches immediately. As a result, the semiconductor device enters a non-operating state immediately after entering the operating state, and the operation becomes unstable, causing a malfunction of the semiconductor device. The same thing occurs when the power supply voltage is lowered to place the semiconductor device in a non-operating state.

In order to prevent such unstable operation of the semiconductor device due to the power supply voltage, the inventions of Patent Documents 1 and 2 have been proposed. Patent Documents 1 and 2 describe a technique in which two types of reference voltages are prepared and used by switching them. In Patent Documents 1 and 2, when the power supply voltage becomes equal to or higher than the reference voltage, the reference voltage is lowered. Thereby, even if there is a voltage drop of the power supply voltage, the power supply voltage is prevented from being lower than the reference voltage, and the detection signal is not switched.
JP 2005-141811 A JP 2007-306648 A

  In the inventions of Patent Documents 1 and 2, only two predetermined reference voltages can be taken. Therefore, if the voltage drop of the power supply voltage is higher than expected, the above problem cannot be solved and the operation of the semiconductor device cannot be stabilized.

  In view of such problems, it is a main object of the present invention to provide a voltage comparison device that can cope with a voltage drop and a voltage rise of an input voltage such as a power supply voltage.

  The voltage comparison device of the present invention that solves the above problems compares a predetermined reference voltage with an input voltage, and enters the first state when the input voltage is lower than the reference voltage. A comparator that outputs a detection signal that enters a second state when it is higher than a reference voltage, and a plurality of candidate voltages that are candidates for the input voltage can be output, and when the detection signal is in the first state, the plurality of A candidate voltage lower than the input voltage is output to the comparator as a new input voltage, and when the detection signal is in the second state, the candidate voltage is higher than the input voltage among the plurality of candidate voltages An input voltage generation circuit that outputs the candidate voltage as a new input voltage to the comparator.

As described above, this type of conventional voltage comparison device lowers the reference voltage when the power supply voltage becomes higher than the reference voltage, and the power supply voltage becomes lower than the reference voltage even if the power supply voltage drops. To prevent that.
Contrary to the conventional case, the voltage comparison apparatus of the present invention further increases the input voltage when the input voltage is higher than the reference voltage. As a result, even if the input voltage has a voltage drop similar to the power supply voltage, it can be prevented that the input voltage becomes lower than the reference voltage. Further, when the input voltage is lower than the reference voltage, the input voltage is further lowered. As a result, even if the input voltage increases, it can be prevented that the input voltage exceeds the reference voltage.

In the present invention, the input voltage generation circuit, for example, a voltage dividing circuit that divides a power supply voltage and outputs the plurality of candidate voltages, and the lowest candidate voltage when the detection signal is in the first state. And a switching circuit that outputs one of the remaining candidate voltages that is higher than the input voltage when the detection signal is in the second state. In order to generate a candidate voltage by dividing the power supply voltage, it is possible to easily obtain a candidate voltage whose voltage value changes in accordance with a change in the power supply voltage.
The switching circuit includes, for example, a first transfer gate that receives one of the remaining candidate voltages that is higher than the input voltage, and a second transfer gate that receives the lowest candidate voltage. Have. When the detection signal is in the first state, the second transfer gate is in a conductive state, and when the detection signal is in the second state, the first transfer gate is in a conductive state.

The input voltage generation circuit may further include a selection circuit that selects one candidate voltage higher than the input voltage among the remaining candidate voltages and inputs the selected candidate voltage to the switching circuit.
Such a selection circuit includes, for example, the same number of transfer gates as the remaining candidate voltages to which the remaining candidate voltages are input one by one, and any one transfer gate is always in a conductive state. Is done.

  An electronic system of the present invention includes the voltage comparison device of the present invention as described above and a semiconductor device that is in an operating state when the detection signal is in the second state. Since the voltage comparison device as described above is used, the detection signal is stable without being affected by the instability of the power supply voltage, and the malfunction of the semiconductor device can be prevented. The semiconductor device may be any device such as a memory device or a CPU (Central Processing Unit).

  According to the present invention as described above, when the input voltage becomes higher than the reference voltage, the input voltage is switched to a higher input voltage, and when the input voltage becomes lower than the reference voltage, the input voltage is switched to a lower input voltage. The influence of voltage drop or voltage rise can be suppressed. Therefore, the operation of the semiconductor device that operates with the power supply voltage can be stabilized.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of an electronic system according to an embodiment of the present invention.
This electronic system includes a comparator 2 and a voltage comparison device 1 including an input voltage generation circuit 3 for generating an input voltage VCCIN, a reference voltage generation circuit 4 for generating a reference voltage VREF used in the electronic system, and a large number of memories. The memory device 5 is an example of a semiconductor device having a memory cell array of cells 6.
In this example, the voltage comparison device 1, the reference voltage generation circuit 4, and the memory device 5 will be described as being formed on one semiconductor substrate.

  The voltage comparison device 1 compares the reference voltage VREF generated by the reference voltage generation circuit 4 with the input voltage VCCIN generated by the input voltage generation circuit 3 by the comparator 2. The voltage value of the input voltage VCCIN changes according to the change of the power supply voltage VCC. The comparator 2 outputs a detection signal VCCOK as a comparison result. The detection signal VCCOK can be used as a lockout signal for the memory device 5.

  The reference voltage generation circuit 4 generates a reference voltage VREF from the power supply voltage VCC. The reference voltage VREF is supplied to other devices (not shown) in the electronic system in addition to the voltage comparison device 1 and the memory device 5.

In addition to the memory cell 6, the memory device 5 includes a peripheral circuit (not shown) for writing data to each memory cell 6 or reading data from the memory cell 6. The memory cell 6 and its peripheral circuits are switched between an operating state and a non-operating state by a detection signal VCCOK. A part of the memory device 5 stores setting information such as first to fourth control signals described later. Such setting information is read out in the operating state.
When the detection signal VCCOK indicates that the input voltage VCCIN is lower than the reference voltage VREF (first state), the memory device 5 becomes inoperative. In the non-operating state, the power supply voltage VCC is not applied to the memory device 5. When the detection signal VCCOK indicates that the input voltage VCCIN is higher than the reference voltage VREF (second state), the memory device 5 is in an operating state. In the operating state, the power supply voltage VCC is applied to all the memory cells 6 and peripheral circuits.

FIG. 2 is a detailed configuration diagram of the input voltage generation circuit 3 included in the voltage comparison device 1.
The input voltage generation circuit 3 includes a load circuit 31 and a voltage dividing circuit 30 in which first to sixth resistors R1 to R6 are connected in series, a first and second transfer gates 33 and 34, and a first inverter 35. A section 32 and a selection circuit 36 are provided.

  The voltage dividing circuit 30 divides the power supply voltage VCC and outputs a candidate voltage that is a candidate for the input voltage VCCIN. In this embodiment, the first to fifth candidate voltages V1 to V5 are output. The voltage dividing circuit 30 divides the power supply voltage VCC dropped by the load circuit 31 by the first to sixth resistors R1 to R6. First to fifth candidate voltages V1 to V5 are generated at nodes N1 to N5 between the resistors. The first to fourth candidate voltages V <b> 1 to V <b> 4 are input to the selection circuit 36. The fifth candidate voltage V5 having the lowest voltage value is input to the switching circuit 32. The first to fifth candidate voltages V1 to V5 satisfy, for example, the relationship of FIG. The first to sixth resistors R1 to R6 have such resistance values that satisfy the relationship between the first to fifth candidate voltages V1 to V5.

  The switching circuit 32 selects one of the fifth candidate voltage V5 and the selection voltage VDID selected from the first to fourth candidate voltages V1 to V4 by the selection circuit 36 according to the detection signal VCCOK. Output as VCCIN. Each of the first and second transfer gates 33 and 34 is configured by connecting an n-type MOS (Metal Oxide Semiconductor) transistor and a p-type MOS transistor in parallel. The sources of the MOS transistors constituting the first transfer gate 33 are connected to the selection circuit 36. The selection voltage VDID is input to the first transfer gate 33. The source of the MOS transistor constituting the second transfer gate 34 is connected to the node N5 of the voltage dividing circuit 30. The second candidate gate V5 is input to the second transfer gate 34.

  The detection signal VCCOK is input to the gate of the n-type MOS transistor of the first transfer gate 33 and the gate of the p-type MOS transistor of the second transfer gate 34. The detection signal VCCOK is inverted in logic by the first inverter 35 and input to the gate of the p-type MOS transistor of the first transfer gate 33 and the gate of the n-type MOS transistor of the second transfer gate 34.

  Due to such a configuration, when the detection signal VCCOK is at the logic level “H”, the switching circuit 32 makes the first transfer gate 33 conductive and outputs the selection voltage VDID as the input voltage VCCIN. When the detection signal VCCOK is at the logic level “L”, the switching circuit 32 makes the second transfer gate 34 conductive and outputs the fifth candidate voltage V5 as the input voltage VCCIN.

The configuration of the selection circuit 36 will be described with reference to the configuration diagram of FIG.
The selection circuit 36 includes second to fifth inverters 360 to 363 and third to sixth transfer gates 364 to 367. Similarly to the first and second transfer gates 33 and 34, the third to sixth transfer gates 364 to 367 are configured by connecting an n-type MOS transistor and a p-type MOS transistor in parallel.
The source of each MOS transistor constituting the third transfer gate 364 is connected to the node N1. The sources of the MOS transistors constituting the fourth transfer gate 365 are connected to the node N2. The source of each MOS transistor constituting the fifth transfer gate 366 is connected to the node N3. The sources of the MOS transistors constituting the sixth transfer gate 367 are connected to the node N4.

Any one of the first to fourth control signals is input to the second to fifth inverters 360 to 363 one by one. The first to fourth control signals are normally stored in the memory device 5 and read out to a control device (not shown) in which the memory device 5 is in an operating state. The first to fourth control signals are input to the second to fifth inverters 360 to 363 from the control device. The first to fourth control signals can be set by the user. Any one of the first to fourth control signals is at the logic level “L” and the rest is at the logic level “H”.
When the memory device 5 is in a non-operating state, the control device sets any one of the first to fourth control signals to the logic level “L” as an initial setting. Therefore, even when the memory device 5 is in the non-operating state, the first to fourth control signals are at the logic level “H” except for one.

  The second to fifth inverters 360 to 363 and the third to sixth transfer gates 364 to 367 are each configured as a “set”. The third to sixth transfer gates 364 to 367 receive the inverted signals of the first to fourth control signals from the second to fifth inverters 360 to 363 in pairs, respectively, and are input to the gates of the n-type MOS transistors. The first to fourth control signals are input to the p-type MOS transistor gate.

  Among the first to fourth control signals, the transfer gate to which the logic level “L” is input is turned on. Therefore, any one of the third to sixth transfer gates 364 to 367 is always in a conductive state.

FIG. 4 is a diagram illustrating each of the first to fifth candidate voltages V1 to V5, the power supply voltage VCC, and the reference voltage VREF, which are voltages of the nodes N1 to N5.
The reference voltage VREF is displaced following the power supply voltage VCC, but does not exceed a predetermined voltage value (1.2 V in this embodiment). The reference voltage VREF ideally has the same value as the power supply voltage VCC below a predetermined voltage value. However, actually, the voltage value is 0.2 to 0.3 V lower than the power supply voltage VCC. When the predetermined voltage value is 1.2 V, the reference voltage VREF is constant at the predetermined voltage value if the power supply voltage is 1.4 to 1.5 V or higher.
On the other hand, since the first to fifth candidate voltages V1 to V5 are obtained by dividing the power supply voltage VCC, they are always displaced following the power supply voltage VCC. As can be seen from FIG. 2, the first candidate voltage V1 is the highest voltage, and the voltage values are in the order of the second candidate voltage V2, the third candidate voltage V3, the fourth candidate voltage V4, and the fifth candidate voltage V5. Becomes lower.
In the example of FIG. 4, when the first candidate voltage V1 is equal to the reference voltage VREF, the power supply voltage VCC is 2.20V. When the second candidate voltage V2 is equal to the reference voltage VREF, the power supply voltage VCC is 2.25V. When the third candidate voltage V3 is equal to the reference voltage VREF, the power supply voltage VCC is 2.30V. When the fourth candidate voltage V4 is equal to the reference voltage VREF, the power supply voltage VCC is 2.35V. When the fifth candidate voltage V5 is equal to the reference voltage VREF, the power supply voltage VCC is 2.40V.

  FIG. 5a is a time chart for explaining the movement of the detection signal VCCOK in accordance with the transition of the power supply voltage VCC by this type of conventional voltage comparison device. FIGS. 5B and 5C are time charts for explaining operations of the reference voltage VREF, the input voltage VCCIN, and the detection signal VCCOK that change in accordance with the transition of the power supply voltage VCC by the voltage comparison device 1 of the present embodiment.

In FIG. 5a, when the power supply voltage VCC becomes higher than the reference voltage VREF, the detection signal VCCOK becomes the logic level “H”.
Supply of the power supply voltage VCC is started at time t0. At time t1, the power supply voltage VCC becomes higher than the reference voltage VREF. As a result, the detection signal VCCOK becomes the logic level “H”, and the memory device 5 enters the operating state. Since the memory device 5 is in an operating state, the power supply voltage VCC drops, and the power supply voltage VCC becomes lower than the reference voltage VREF at time t2. As a result, the detection signal VCCOK becomes the logic level “L”, and the memory device 5 becomes inoperative. Thereafter, since the power supply voltage VCC rises, the voltage again becomes higher than the reference voltage VREF, and the memory device 5 enters an operating state. Thus, the operation of the memory device 5 is unstable. The same thing occurs when the supply of the power supply voltage VCC is terminated (time t3, t4).
In Patent Documents 1 and 2, when the detection signal VCCOK is at the logic level “H”, the reference voltage VREF is lowered to prevent the detection signal VCCOK from having the logic level “L”. Stabilize the operation.

  In FIG. 5b, when the supply of the power supply voltage VCC is started at time t0, the reference voltage VREF becomes a predetermined voltage value after a predetermined time. The input voltage VCCIN is the fifth candidate voltage V5 because the detection signal VCCOK is at the logic level “L”. When the input voltage VCCIN rises as the power supply voltage VCC rises and becomes equal to or higher than the reference voltage VREF at time t1, the detection signal VCCOK becomes a logic level “H”. Taking FIG. 4 as an example, when the power supply voltage VCC becomes 2.40 V or more, the input voltage VCCIN becomes more than the reference voltage VREF.

When the detection signal VCCOK becomes the logic level “H”, the switching circuit 32 is switched, and any one of the first to fourth candidate voltages V1 to V4 becomes the input voltage VCCIN. In this embodiment, the second candidate voltage V2 becomes the input voltage VCCIN as an initial setting. With the transition of the detection signal VCCOK, the memory device 5 enters an operating state, and the power supply voltage VCC drops as in the conventional case. However, since the input voltage VCCIN is switched from the fifth candidate voltage V5 to the second candidate voltage V2, which is higher than the fifth candidate voltage V5, the input voltage VCCOK does not become lower than the reference voltage VREF. Using FIG. 4 as an example, even if there is a voltage drop, if the power supply voltage VCC is 2.25 V or higher, the input voltage VCCOK will not be lower than the reference voltage VREF.
Therefore, there is no transition of the logic level of the detection signal VCCOK due to the voltage drop of the power supply voltage VCC. Therefore, the operation of the memory device 5 becomes stable.

  In order for the memory device 5 to be in an operating state, data relating to the first to fourth control signals is read from the memory device 5. When the reading is completed, the first to fourth control signals are input to the selection circuit 36. In response to this, the selection circuit 36 outputs any one of the first candidate voltage V1 to the fifth candidate voltage V5 as the selection voltage VDID. The switching circuit 32 outputs the selection voltage VDID as the input voltage VCCIN in response to the detection signal VCCOK.

In FIG. 5c, the supply of the power supply voltage VCC ends. When the input voltage VCCIN becomes equal to or lower than the reference voltage VREF at time t3 as the power supply voltage VCC decreases due to the termination, the detection signal VCCOK transitions to the logic level “L”. Thereby, the switching circuit 32 is switched, and the fifth candidate voltage V5 becomes the input voltage VCCIN. The power supply voltage VCC rises when the memory device 5 is deactivated by the detection signal VCCOK. However, since the input voltage VCCIN is switched to the fifth candidate voltage V5, the input voltage VCCIN does not become higher than the reference voltage VREF. Therefore, there is no transition of the detection signal VCCOK. Therefore, the operation of the memory device 5 ends stably.
FIG. 5c is an exemplary diagram when the input voltage VCCIN is the second candidate voltage V2. When the input voltage VCCIN is the first candidate voltage V1, the time t3 is delayed, and when the input voltage VCCIN is the fourth candidate voltage V4, the time t3 is advanced.

  As described above, by using the voltage comparison device 1 of the present embodiment, the operation of the memory device 5 does not become unstable at the start and end of the supply of the power supply voltage VCC as in the prior art. Further, since an optimum voltage value can be selected from the first to fifth candidate voltages V1 to V5, the voltage comparison device 1 is redesigned even when the power supply voltage VCC varies due to noise or the like of the entire electronic system. It is possible to cope without it.

  In the above embodiment, when the detection signal VCCOK is the logic level “L”, the fifth candidate voltage V5 becomes the input voltage VCCIN, and when the detection signal VCCOK is the logic level “H”, any one of the first to fourth candidates V1 to V4. However, the present invention is not limited to this. For example, when the logical level of the detection signal VCCOK becomes “L”, the same effect as described above can be obtained by switching the input voltage VCCIN to a candidate voltage lower than the candidate voltage that has been the input voltage VCCIN until then. . Further, when the logic level of the detection signal VCCOK becomes “H”, the same effect as described above can be obtained by switching the input voltage VCCIN to a candidate voltage higher than the candidate voltage that has been the input voltage VCCIN until then. .

It is a block diagram of the electronic system of this invention. It is a detailed block diagram of an input voltage generation unit. It is a detailed block diagram of a selection part. It is an illustration figure of each voltage value of the 1st-5th candidate voltage, a power supply voltage, and a reference voltage. It is a time chart for demonstrating the motion of the detection signal according to the transition of the power supply voltage by the conventional voltage comparison apparatus. FIG. 5B is a time chart for explaining the operations of the reference voltage, the input voltage, and the detection signal that change in accordance with the transition of the power supply voltage by the voltage detection unit of the present embodiment. FIG. 5C is a time chart for explaining operations of the reference voltage, the input voltage, and the detection signal that change in accordance with the transition of the power supply voltage by the voltage detection unit of the present embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Voltage comparison apparatus, 2 ... Comparator, 3 ... Input voltage generation circuit, 30 ... Voltage dividing circuit, 31 ... Load circuit, 32 ... Switching circuit, 33, 34 ... 1st, 2nd transfer gate, 35 ... 1st Inverter, 36 ... selection circuit, 360-363 ... 2nd to 5th inverter, 364-367 ... 3rd-6th transfer gate, 4 ... reference voltage generation circuit, 5 ... memory device, 6 ... memory cell, R1-R6 ... 1st to 6th resistor, VCC ... Power supply voltage, VREF ... Reference voltage, VCCIN ... Input voltage, VCCOK ... Detection signal, VDID ... Selection voltage

Claims (6)

Compares the criteria voltage and the input voltage becomes the first state when the input voltage is lower than the reference voltage, a detection signal by the input voltage becomes the second state is higher than the reference voltage A comparator to output;
It has a switching circuit, and can output an input voltage generation circuit the input voltage to the comparator
With
The switching circuit, when the detection signal of the first state, the lowest among the plurality of candidate voltages, and outputs to the comparator a first candidate voltage lower than the input voltage as a new input voltage,
The switching circuit, wherein when the detection signal is in the second state, wherein from among two or more candidates voltage which does not contain the first candidate voltages, new input high second candidate voltage than the input voltage you output to the comparator as the voltage,
Voltage comparison device. The input voltage generation circuit, Ru includes a voltage dividing circuit which outputs a plurality of candidate voltages supply voltage divide,
The voltage comparison apparatus according to claim 1. The switching circuit includes a first transfer gate to which the second candidate voltage is input, and a second transfer gate to which the first candidate voltage is input, the detection signal is the first The second transfer gate is in a conductive state in the state, and the first transfer gate is in a conductive state in the case where the detection signal is in the second state;
The voltage comparison apparatus according to claim 2. The input voltage generation circuit includes:
From among two or more candidate voltage that does not include the first candidate voltage, further comprising a selection circuit for the high second candidate voltage than the input voltage select one input to the switching circuit,
The voltage comparison apparatus according to any one of claims 1 to 3 . The selection circuit comprises a first of said two or more candidates voltage candidate voltage does not contain 2 or more candidate voltages are one by one input each the same number of transfer gates,
Any one of the transfer gates is configured to be always conductive.
The voltage comparison apparatus according to claim 4. A voltage comparison device according to any one of claims 1 to 5, and a semiconductor device that enters an operating state when the detection signal is in the second state.
Electronic systems.

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