JP5306487B2 - Magnetoresistive effect memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a magnetoresistive memory reducing read disturbance. <P>SOLUTION: A magnetoresistive memory comprises: a magnetoresistive element 1 having a first magnetic layer not changing magnetizing direction, a second magnetic layer changing the magnetizing direction, and an intermediate layer between the first magnetic layer and the second magnetic layer; and a read circuit 2 for distinguishing data stored in the magnetoresistive element by allowing a read pulse current to flow in the magnetoresistive element 1. The read pulse current width is smaller than a period until magnetization in the second magnetic layer starts coherent precession together from an initial state. <P>COPYRIGHT: (C)2012,JPO&amp;INPIT

Description

  The present invention relates to a magnetoresistive effect memory using a magnetoresistive effect element.

  So far, various types of magnetoresistive effect memory have been proposed. In recent years, a magnetoresistive effect memory using a ferromagnetic tunnel junction element exhibiting a tunneling magnetoresistive (TMR) effect, such as a magnetoresistive random access memory (MRAM), has attracted attention. . As the TMR effect element, an MTJ (magnetic tunnel junction) element using a change in magnetoresistance due to the spin-polarized tunnel effect is generally used. The MTJ element takes a low resistance state and a high resistance state according to the relative magnetization arrangement of the two ferromagnetic layers, and stores data by corresponding “0” or “1” to these resistance states. .

  As one of data writing methods of the magnetoresistive effect memory, there is a spin injection writing method in which the magnetization direction of the magnetic layer is changed by the spin torque of current (electrons). In the spin injection writing method, a write current greater than or equal to the current value in the MTJ element is directly passed. Then, depending on the direction in which the write current flows through the MTJ element, the relative magnetization arrangement of the two ferromagnetic layers constituting the MTJ element is changed from the parallel state to the antiparallel state, or from the antiparallel state to the parallel state, Write data. In reading data from the magnetoresistive effect memory, the data is discriminated using the resistance difference between the high resistance state and the low resistance state of the MTJ element. In the data reading, a current (reading current) is directly passed through the MTJ element as in the data writing.

Conventionally, it has been considered that the magnetization reversal probability of an MTJ element by spin injection can be represented by a simple thermal activation process as represented by (Equation 1) (for example, see Non-Patent Document 1).

  In the magnetization reversal model represented by (Equation 1), the probability that the magnetization is not reversed by spin injection (1-P (τ)) decreases exponentially with respect to the current supply time τ for the MTJ element. Further, in the model shown in (Equation 1), the reversal of magnetization due to spin injection occurs with a finite probability immediately after supplying a pulse current, that is, in the limit where the pulse width τ of the current is zero. become.

On the other hand, in Non-Patent Document 2, as shown in the following (Equation 2) and (Equation 3), immediately after starting the supply of current to the MTJ element, there is a time when the inversion probability is substantially zero, It is described that the reversal probability increases after a certain period of time.

In the spin injection type MRAM, the current value of the write current is set to a current value larger than a threshold value (hereinafter referred to as an inversion threshold value) at which magnetization reversal is caused by the spin injection, and the current value of the read current is A current value smaller than the inversion threshold is set.
However, the inversion threshold value also varies due to the characteristic variation of the MTJ elements constituting the memory cell array. Even when data is repeatedly written to the same element, there is a phenomenon that the inversion threshold value for the element fluctuates.

  Therefore, when the current value of the read current is set close to the average value of the inversion threshold value in the memory cell array, the MTJ element having a small inversion threshold value may be erroneously inverted by the read current and read disturb may occur. There is sex.

  In order to prevent the occurrence of read disturb, it is necessary to make the read current sufficiently smaller than the inversion threshold current. However, when the read current is reduced, the read signal (bit line potential fluctuation) becomes small, and sufficient read sensitivity cannot be obtained.

Z. Li and S. Zhang, Physical Review B, Vol. 69, 134416 (2004) H. Tomita et al., Applied Physics Express, Vol. 1 (2008) 061303

  The present invention proposes a magnetoresistive effect memory that reduces read disturb.

A magnetoresistive effect memory according to an embodiment of the present invention includes a reference layer formed of a first magnetic layer whose magnetization direction is unchanged, a storage layer formed of a second magnetic layer whose magnetization direction is variable, A magnetoresistive effect element having a tunnel barrier layer provided between the reference layer and the storage layer, and a pulse-shaped read current is passed through the magnetoresistive effect element to store the magnetoresistive effect element. A readout circuit for discriminating data, wherein the magnetization of the storage layer is formed by spins respectively possessed by a plurality of magnetic grains in the second magnetic layer, and the pulse width of the readout current is the memory It is shorter than the period from the state in which each of the plurality of spins forming the magnetization of the layer precesses at a random phase to the time when the plurality of spins cooperate and coherently precess.

  According to the present invention, it is possible to provide a magnetoresistive effect memory that reduces read disturb.

The figure for demonstrating the magnetoresistive effect memory which concerns on this embodiment. The figure which shows an example of the structure of a magnetoresistive effect element. The figure for demonstrating the spin injection magnetization reversal model described in this embodiment. The figure for demonstrating the spin injection magnetization reversal model described in this embodiment. The figure for demonstrating the spin injection magnetization reversal model described in this embodiment. The figure for demonstrating the spin injection magnetization reversal model described in this embodiment. The figure for demonstrating the specific example of the magnetoresistive effect memory which concerns on this embodiment. The figure for demonstrating the specific example of the magnetoresistive effect memory which concerns on this embodiment. The figure for demonstrating the specific example of the magnetoresistive effect memory which concerns on this embodiment. The figure which shows the characteristic of the magnetization reversal time with respect to a current density. The figure which shows the characteristic of the magnetization reversal time with respect to a current density. The figure which shows the characteristic of the magnetization reversal time with respect to a current density. The figure which shows the characteristic of the magnetization reversal time with respect to a current density. The figure which shows the dependence of the read disturbance of the parameter containing magnetization reversal time. The figure which shows the dependence of the attenuation constant of a magnetic layer with respect to magnetization reversal time. The figure which shows the example of application of the magnetoresistive effect memory which concerns on this embodiment. FIG. 9 shows an example of a structure of a memory cell. FIG. 10 is a diagram illustrating a configuration example of a reading circuit used in a memory according to an application example. FIG. 10 is a diagram illustrating a configuration example of a reading circuit used in a memory according to an application example. FIG. 10 is a diagram illustrating a configuration example of a reading circuit used in a memory according to an application example. FIG. 20 is a waveform diagram showing a read operation of the memory shown in FIGS. 18 and 19. FIG. 10 is a diagram illustrating a configuration example of a reading circuit used in a memory according to an application example. FIG. 22 is a waveform diagram showing a read operation of the memory shown in FIG. 21. The figure which shows the time change of the read-out voltage when wiring is precharged. The figure for demonstrating the correlation of read-out current and the number of memory cells. The figure for demonstrating the correlation of read-out current and the number of memory cells.

  Hereinafter, embodiments for carrying out examples of the present invention will be described in detail with reference to the drawings.

[Embodiment]
A magnetoresistive effect memory according to an embodiment of the present invention will be described with reference to FIGS.

  FIG. 1A shows a configuration example of the magnetoresistive effect memory according to the present embodiment.

  As shown in FIG. 1A, the magnetoresistive effect element 1 is connected to two bit lines BL. One end of the magnetoresistive effect element 1 is connected to the bit line BL, and the other end of the magnetoresistive effect element 1 is connected to the bit line bBL via the switch Tr.

  The switch Tr is, for example, a field effect transistor (FET). Hereinafter, the switch Tr is referred to as a selection transistor Tr. One end (source / drain) of the current path of the selection transistor Tr is connected to the other end of the magnetoresistive effect element 1, and the other end (source / drain) of the current path of the selection transistor Tr is connected to the bit line bBL. . A control terminal (gate) of the selection transistor Tr is connected to the word line WL. For example, the word line WL extends in a direction crossing the extending direction of the bit lines BL and bBL.

  FIG. 2 is a cross-sectional view showing a configuration of one magnetoresistive element 1 included in the magnetoresistive effect memory according to the present embodiment. As the magnetoresistive effect element 1, an MTJ (magnetic tunnel junction) element using a change in magnetoresistance due to the spin-polarized tunnel effect is used. Hereinafter, the magnetoresistive effect element 1 is referred to as an MTJ element 1.

  The MTJ element 1 has a stacked structure in which reference layers (also referred to as magnetization invariant layers) 11A and 11B, intermediate layers (nonmagnetic layers) 12A and 12B, and storage layers (also referred to as magnetization free layers) 13A and 13B are sequentially stacked. Have. The reference layers 11A and 11B and the memory layers 13A and 13B may be stacked in reverse order.

In the MTJ element 1 shown in FIG. 2A, the easy magnetization directions of the reference layer 11A and the storage layer 13A are parallel to the film surface. The MTJ element 1 shown in FIG. 2A is called an in-plane magnetization type MTJ element.
In the MTJ element 1 shown in FIG. 2B, the easy magnetization directions of the reference layer 11B and the storage layer 13B are perpendicular to the film surface (or laminated surface). The MTJ element shown in FIG. 2B is called a perpendicular magnetization type MTJ element.
The magnetic layer with in-plane magnetization has a magnetic anisotropy in the in-plane direction, and the magnetic layer with perpendicular magnetization has a magnetic anisotropy in the direction perpendicular to the film surface. When the perpendicular magnetization type is used for the MTJ element 1, it is not necessary to control the element shape to determine the magnetization direction as in the in-plane magnetization type, and there is an advantage that it is suitable for miniaturization.

  The storage layers 13A and 13B have variable (reversed) magnetization (or spin) directions. The reference layers 11A and 11B have the same magnetization direction (fixed). “The magnetization directions of the reference layers 11A and 11B are unchanged” means that the magnetization reversal current (inversion threshold) used to reverse the magnetization directions of the storage layers 13A and 13B is applied to the reference layers 11A and 11B. This means that the magnetization directions of the reference layers 11A and 11B do not change when they are flowed. Therefore, in the MTJ element 1, by using a magnetic layer having a large inversion threshold as the reference layers 11A and 11B and using a magnetic layer having a smaller inversion threshold than the reference layers 11A and 11B as the storage layers 13A and 13B, It is possible to realize the MTJ element 1 including the storage layers 13A and 13B whose magnetization directions are variable and the reference layers 11A and 11B whose magnetization directions are unchanged.

  As a method of fixing the magnetization of the reference layers 11A and 11B, an antiferromagnetic layer (not shown) is provided adjacent to the reference layers 11A and 11B, and the reference layers 11A and 11B are exchanged with the antiferromagnetic layer. The magnetization direction of the reference layers 11A and 11B can be fixed by the coupling. However, in the perpendicular magnetization type MTJ element, an antiferromagnetic layer (not shown) may not be provided adjacent to the reference layer 11A. The planar shape of the MTJ element 1 is not particularly limited, and any of a circle, an ellipse, a square, a rectangle, and the like may be used. Also, a square or rectangular shape with rounded corners or a shape with missing corners may be used.

The reference layers 11A and 11B and the storage layers 13A and 13B are made of a magnetic material having a high coercive force, and preferably have a high magnetic anisotropic energy density of, for example, 1 × 10 ⁶ erg / cc or more.

  The intermediate layers 12A and 12B are made of a nonmagnetic material, and for example, an insulator, a semiconductor, a metal, or the like can be used. The intermediate layer 13 is called a tunnel barrier layer when an insulator or a semiconductor is used.

  Note that each of the reference layers 11A and 11B and the storage layers 13A and 13B is not limited to a single layer as illustrated, and may have a laminated structure including a plurality of ferromagnetic layers. Each of the reference layers 11A and 11B and the storage layers 13A and 13B includes three layers of a first ferromagnetic layer / a nonmagnetic layer / a second ferromagnetic layer. An antiferromagnetic coupling structure in which the magnetization directions are in an antiparallel state (magnetic coupling (exchange coupling)) may be used, or the first and second ferromagnetic layers may have a magnetization direction in a parallel state. A (exchange-coupled) ferromagnetic coupling structure may be used.

  The MTJ element 1 may have a double junction structure. The MTJ element 1 having a double junction structure has a stacked structure in which a first reference layer, a first intermediate layer, a storage layer, a second intermediate layer, and a second reference layer are stacked in this order. Such a double junction structure has an advantage that it is easy to control the magnetization reversal of the storage layers 13A and 13B by spin injection.

For example, the read circuit 2 is connected to the bit line BL. The read circuit 2 includes a current source or a voltage source and a sense amplifier. The read circuit 2 outputs a read current I _READ during a read operation.
The read circuit 2 is electrically isolated from the bit line BL when the switch 30 is turned off. When the switch 30 is turned on, it is electrically connected to the bit line BL. When reading data from the MTJ element 1, the switch 30 is turned on, and the read circuit 2 and the MTJ element 1 are electrically connected.

  Hereinafter, the low resistance state and the high resistance state of the MTJ element 1 and data writing by spin injection will be described.

  A parallel state (low resistance state) in which the magnetization directions of the reference layers 11A and 11B and the storage layers 13A and 13B are parallel will be described.

  Of the electrons that have passed through the reference layers 11A and 11B, the majority electron has a spin parallel to the magnetization direction of the reference layers 11A and 11B. When the majority electron spin angular momentum moves to the storage layers 13A and 13B, spin torque is applied to the storage layers 13A and 13B, and the magnetization directions of the storage layers 13A and 13B are the magnetization directions of the reference layers 11A and 11B. Aligned in parallel. With this parallel arrangement, the MTJ element 1 has the smallest resistance value. This case is treated as “0” data, for example.

  Next, an antiparallel state (high resistance state) in which the magnetization directions of the reference layers 11A and 11B and the storage layers 13A and 13B are antiparallel will be described.

  Of the electrons reflected by the reference layers 11A and 11B, the majority electron has a spin antiparallel to the magnetization direction of the reference layers 11A and 11B. When the majority electron spin angular momentum moves to the storage layers 13A and 13B, spin torque is applied to the storage layers 13A and 13B, and the magnetization directions of the storage layers 13A and 13B are the magnetization directions of the reference layers 11A and 11B. And anti-parallel. In the antiparallel arrangement, the MTJ element 1 has the largest resistance value. This case is treated as “1” data, for example.

Data is read by supplying a read current I _READ to the MTJ element 1. When the resistance value in the parallel state is R0 and the resistance value in the antiparallel state is R1, the value defined by “(R1−R0) / R0” is called a magnetoresistance ratio (MR ratio). The magnetoresistance ratio varies depending on the material constituting the MTJ element 1 and the process conditions, but can take a value of several tens to several hundreds.

  Information stored in the MTJ element 1 is read by detecting the fluctuation amount of the read current (bit line potential) caused by the MR ratio.

When reading data stored in the MTJ element 1, the read circuit 2 supplies a pulse-shaped read current I _READ as illustrated in FIG. 1B to the MTJ element 1, for example.

Features In the magnetoresistive memory of the present embodiment, the pulse width T _P of the read current I _READ is shorter than the time to the magnetization of the storage layer from the initial state to the coherent precession cooperates, that And

Further, the maximum value of the current value i _R of the read current I _READ is set to a value smaller than, for example, an inversion threshold i _{th at} which the magnetization is inverted. For example, the current value i _R of the read current I _READ is constantly output during a period from a time t ₂ when the pulse current rise ends to a time t ₃ when the fall starts.

In the present embodiment, the pulse width _{T P} of the read current _{I READ,} the pulse full width at half maximum: defined by (FWHM Full width at half maximum) . Specifically, the pulse width T _P is a pulse width relative to the half value i _{R /} 2 of the maximum current value i _R, the time t ₁ and rising to the rise of the pulse current is started ends it is a period between the middle of the time period t ₄ when time and falling time t ₂ intermediate falls to the time t ₃ when initiating ends to.

  As a result, the magnetoresistive effect memory according to the present embodiment reduces the occurrence of read disturb.

Thus, the pulse width T _P of the read current I _READ is, the magnetization of the storage layer that is set shorter than the time to initiate a coherent precession cooperates, read disturb is prevented Is based on the spin injection magnetization reversal model described below.

  FIG. 3 shows the time dependence of the magnetization reversal probability in the spin injection magnetization reversal model described in the present embodiment. The horizontal axis of FIG. 3 indicates time (unit: nsec (nanosecond)). The vertical axis in FIG. 3 corresponds to the magnetization reversal probability. However, when the magnetization reversal probability is indicated by “P”, the vertical axis in FIG. 3 indicates Log (1-P). “1-P” indicates a probability that magnetization is not reversed (data is not written). The magnetization reversal probability is the probability that the magnetization direction of the storage layer is reversed when a certain current is passed through a certain MTJ element.

Each characteristic curve shown in FIG. 3 is a result obtained by a micromagnetic simulation using an LLG (Landau-Liftshitz-Gilbert) equation. Each parameter used for this simulation is as follows.
The MTJ element used for the simulation is a perpendicular magnetization type MTJ element. The film thickness of the MTJ element is set to 2.2 nm, and the diameter of the MTJ element is set to 30 nm. The magnetization of the storage layer is perpendicular to the film surface, the magnetic layer has a magnetic anisotropy energy Ku of 3.5 Merg / cc, and the storage layer has a saturation magnetization Ms of 500 emu / cc. Energy barrier Delta] E _{a is,} 86k B T: a _{(k B} Boltzmann constant). “T” indicates an absolute temperature. The energy barrier ΔEa indicates the size of the energy barrier that must be exceeded in the process of reversing the MTJ element from the parallel state to the antiparallel state or from the antiparallel state to the parallel state. The temperature (absolute temperature) T is set to 300K. The range of the current density J flowing through the MTJ element is set to 2.8 to 4 MA / cm ² . The simulation is executed using the current density ratio J / J _C (22 nsec, midpoint) within the range of 0.934 to 1.436. “J” indicates the current density of the pulse current, and “J _C (22 nsec, midpoint)” indicates that the MTJ element has a write width of 22 nsec when data is written to the MTJ element. The current density at which the magnetization reversal probability of the storage layer is 0.5 is shown.

  FIG. 3 also shows first-order approximate characteristic lines for characteristic curves obtained from simulations using current density ratios of 0.934 to 1.436.

Based on the characteristic curves shown in FIG. 3, the spin injection magnetization reversal probability P (t) can be approximately expressed as (Equation 4).

“P (t)” indicates the probability that a current pulse having a pulse width t is inverted by flowing through the MTJ element. “F ₀ ” is the frequency at which the MTJ element receives thermal energy (phonon) per unit time. “F ₀ ” is about 1 × 10 ⁹ Hz. “I” indicates the current value of the pulse current, and “I _C0 ” indicates the magnetization reversal current at 0 K (absolute temperature) when the pulse width is set in the time for receiving one phonon (about 1 ns). Current value. In (Formula 4), “n” is a constant of 1.5-2.

As shown in FIG. 3, the probability Log (1-P) shows a negative value with respect to a change in time. As shown in Non-Patent Document 2 and (Equation 2), immediately after the pulse current is applied to the MTJ element, the magnetization of the memory layer does not reverse, and after time t ₀ , the magnetization reversal does not occur. Be started.

  In the present embodiment, the time from the start of applying the pulse current to the start of magnetization reversal is within the storage layer of the MTJ element, within the magnetic grains (crystal grains) constituting the storage layer. Magnetization reversal is started by the thermal activation process after realizing the coherent precession in which the phases of the magnetizations in the differential motion are not aligned and the magnetization phases are aligned. Such a magnetization reversal model was verified by FIG. 3 and the following experiments and simulations.

FIG. 4A is a graph obtained by analyzing one of the simulation results based on the LLG equation of the spin injection magnetization reversal of the perpendicular magnetization type MTJ element used in FIG.
The simulation was performed using, for example, a cell showing 32 magnetizations in the storage layer (magnetic layer). The cell corresponds to a magnetic grain contained in the magnetic layer. In FIG. 4A, the horizontal axis indicates time (unit: nsec). In FIG. 4A, a characteristic line indicated by a broken line corresponds to the left axis Mz-ave. 4A represents the average value Mz-ave (unit: au (arbitrary unit)) of the z component (vertical component) of the magnetization. In Mz-ave of the z component of magnetization, “1” indicates a state in which the magnetization is directed upward with respect to the film surface of the storage layer, and “−1” indicates that the magnetization is with respect to the film surface of the storage layer. It shows a state of facing down.
In the simulation shown in FIG. 4A, in the initial state (0 nsec), the average value Mz-ave of the magnetization is substantially 1, and the magnetization is in the upward direction perpendicular to the film surface of the MTJ element. . Then, at 0 nsec, supply of a magnetization reversal current to the storage layer was started, and the process until the magnetization was reversed by spin injection and the average value Mz-ave became approximately −1 was verified.

  As shown in FIG. 4A, the magnetization average value Mz-ave hardly changes during the period from 0 nsec to 3 nsec. This can be regarded as a period in which the magnetization (spin) of the storage layer is not reversed.

In FIG. 4A, the characteristic curve indicated by the solid line corresponds to the right axis σΦ, and shows the phase variation of the precession of 32 magnetizations in the storage layer.
As shown in FIG. 4B, the magnetization direction can be expressed by polar coordinates using two declination angles θ and declination Φ. The magnetization of the perpendicular magnetization film precesses about the film surface perpendicular direction (z axis) as a rotation axis. The phase of precession in the equatorial plane c is defined as the declination angle Φ. In addition, the angle formed by the inclination of the magnetization M and the z-axis during precession is defined as a declination angle θ.
The phase variation of the precession is obtained by examining the variation of the declination Φ. However, the argument Φ shown in polar coordinates becomes discontinuous or multivalued with a period of + π or −π. For this reason, if the phase dispersion (phase variation) is calculated simply by using the declination Φ, an accurate calculation result cannot be obtained at a portion where the numerical values are discontinuous.
Therefore, in this embodiment, the phase variance σΦ is calculated by expressing the phase of the precession as a complex number, that is, “Φ = cosφ + isinφ”, instead of the declination Φ, and the phase variation is obtained. Thus, by expressing the argument Φ using complex numbers, the problem caused by numerical discontinuity is solved, and phase variations can be calculated easily. The phase dispersion σΦ is expressed by the following (Expression 5) and (Expression 6).

  “N” in (Expression 5) and (Expression 6) indicates the number of magnetizations (number of cells) included in the storage layer, which is 32 in this example. “Σ” in (Expression 5) and (Expression 6) indicates that the sum (total value) of all the magnetizations (32 in this example) included in the storage layer is calculated. “*” In (Expression 5) indicates a conjugate complex number. “￣” in (Expression 5) and (Expression 6) indicates the average value of all the magnetization cells (32 in this example) in the storage layer. Therefore, “μ” in (Expression 5) indicates an average value of “Φ” of all the magnetizations in the storage layer.

  FIG. 5 schematically shows a magnetization cell arranged in the storage layer 17. FIG. 5 shows an example in which a plurality of cells 18 are two-dimensionally arranged. However, this is for simplification of the description, and it is needless to say that the present invention is not limited to this.

For example, as shown in FIG. 5A, when the phases of the magnetizations 19 of the cells 18 in the storage layer 17 are all random, the phase dispersion σΦ indicates “1”. On the other hand, as shown in FIG. 5B, when the phases of all the magnetizations 19 in the storage layer 14 are completely aligned and the value of the declination “Φ” is the same, the phase dispersion σΦ Indicates “0”.
In the present embodiment, the magnetization phase of each magnetic grain in the magnetic layer is aligned and precesses by co-operation is called “coherent precession”.
As shown in FIG. 4A, when the phase dispersion σΦ of the magnetization in the storage layer decreases and the magnetization becomes a coherent precession, the magnetization moves to a thermal activation process and the magnetization is reversed. Begin to. Then, the average value Mz-ave of magnetization starts to decrease.
A period t ′ in FIG. 4A corresponds to a time until a coherent precession movement is reached. However, even when the simulation is repeated under the same conditions, the period t ′ from the initial state until the coherent precession is realized varies. However, the phenomenon that magnetization reversal is started when the phase of magnetization in the storage layer is aligned and coherent precession is realized is reproduced.

From the above, the time t ′ in the spin injection magnetization reversal is the time of the precession of the magnetization 18 from the state where the phase of the precession of the magnetization 18 is not aligned in the storage layer 17 (see FIG. 5A). It can be regarded as the time until transition to a coherent state (see FIG. 5B) in which the phases are aligned. Therefore, it can be said that when the time until the coherent precession elapses, the process proceeds to the thermal activation process, and the spin inversion of the storage layer of the MTJ element is started.
When the phase dispersion σΦ is about 0.5, the average value Mz-ave of magnetization decreases to about 95% of the initial state (1). As a typical example, the time until the phase dispersion σΦ reaches 0.5 can be regarded as the time until the magnetization starts coherent precession.

  The time until the magnetization precession becomes a coherent motion depends on the magnitude of the current I. When the magnitude of the current I decreases, the time until the magnetization precession becomes a coherent motion is To increase.

There is a time t ′ until the coherent precession is realized, and after the coherent precession is realized, there is a finite time from the start of the spin inversion to the completion of the spin inversion. . Therefore, considering the time t ′, the time t ₀ in (Equation 4) is included in the parameters of the spin injection magnetization reversal model described in this embodiment.
Here, the condition for completing the spin injection magnetization reversal is that the spin of the memory layer does not return to the original state even when the current (pulse current) is turned off, and is reversed to the end. This means that in FIG. 4B, the magnetization direction rotates to the equatorial plane c, and the perpendicular component Mz of the magnetization becomes “0”.

  FIG. 6 shows the time dependence of the magnetization reversal probability, and shows the time dependence of the magnetization reversal probability of the MTJ element under the same conditions as in FIG. The result shown in FIG. 6 is calculated by micromagnetic simulation using the LLG equation. The horizontal axis in FIG. 6 indicates time, and the vertical axis in FIG. 6 indicates Log (1-P), as in FIG.

  FIG. 6 also shows that after the magnetization of the storage layer becomes a coherent precession, the movement of the magnetization transitions to a thermal activation process and the magnetization of the storage layer is reversed. A characteristic line A shown in FIG. 6 is an approximate straight line representing a magnetization reversal model in the thermal activation process, and is a straight line represented by (Equation 4).

  As described above, the magnetizations existing in the storage layers 13A and 13B of the MTJ element 1 co-operate and precess, and then the magnetization directions in the storage layers 13A and 13B are reversed.

In the magnetoresistive memory according to the present embodiment, the pulse width T _P of the read current I _READ supplied to the MTJ element is shorter than the time to begin to coherent precession cooperates magnetization of the storage layer is .
According to this, the time during which the read current is supplied to the MTJ element is shorter than the time required for the magnetization to be reversed, and the read current is supplied before the magnetization in the storage layer undergoes coherent precession. Is stopped. As a result, it is possible to suppress magnetization reversal due to the read current, that is, data writing due to the read current.

  Therefore, according to the magnetoresistive effect memory of this embodiment, occurrence of read disturb can be reduced.

[Concrete example]
Hereinafter, a specific example of the magnetoresistive effect memory according to the embodiment of the present invention will be described with reference to FIGS. 7A and 14.

  Although not expressed in the approximate expression of (Expression 4), as described above, the time t ′ until the coherent precession shown in FIG. 4A is actually realized is the operating state of the MTJ element, It varies depending on the film quality of the storage layer, the degree of variation in the phase of magnetization in the storage layer, and the like.

Therefore, it is set below the read current I constant time t ₀ with a pulse width T _P of _READ, and the inverted probability is zero does not necessarily say.

That is, when a certain current I is supplied to the MTJ element, the time t _sw required for magnetization reversal (hereinafter referred to as magnetization reversal time or switching time) fluctuates even in the same MTJ element. This magnetization reversal time t _sw shows a value close to time t ₀ in (Equation 4) or time t ′ until a coherent precession motion is reached.

FIG. 7A is a diagram for explaining the distribution of fluctuations in the magnetization reversal time t _sw of the MTJ element. The vertical axes of (a) and (b) of FIG. 7A indicate the Z value (standardization coefficient), and the horizontal axes of (a) and (b) of FIG. 7A indicate the magnetization reversal time t _sw . The conditions of the MTJ element used to obtain the distribution of FIG. 7A are the same as the conditions shown in FIG.

As shown in FIG. 7A, the fluctuation distribution of the magnetization reversal time t _sw approximates the log normal distribution shown in FIG. 7A (b) rather than the normal distribution shown in FIG. 7A (a). In other words, Ln (t _sw ) representing the distribution of the magnetization reversal time t _sw using the natural logarithm (Ln) indicates a normal distribution.

The Z value in the distribution Ln (t _sw ) of the magnetization reversal time t _sw is expressed by the following equation.

Here, “E (I)” and “F (I)” in (Expression 7) are constants depending on the current I. Further, when (Equation 7) is modified, it becomes as (Equation 8).

As shown in FIG. 7A (b), the distribution Ln (t _sw ) of the magnetization reversal time t _sw has a normal distribution. Therefore, as shown in the probability density distribution with respect to the Z value in FIG. 7B, the cumulative probability in a range from −∞ (minus infinity) to a predetermined Z value can be obtained. In other words, the Z value can be determined by setting the cumulative probability to a certain value.
Here, the current I in (Equation 8) is a read current. The probability that a read disturb occurs when a certain read current I is supplied to one MTJ element is a read disturb occurrence probability q. In this case, in the magnetization reversal time distribution Ln (t _sw ) shown in FIG. 7B, the cumulative probability corresponds to the read disturb occurrence probability of 1 bit (one MTJ element).

Therefore, as shown in FIG. 7B, for example, when the read disturb occurrence probability q is set to 0.001 (= 1 × 10 ⁻³ ), the Z value is −3.09. By substituting this Z value (−3.09) for the coefficient Z in (Equation 8), the magnetization reversal time t _sw (q = 1 × 10 ⁻³ ) at which the read disturb occurrence probability q becomes 0.001 is obtained. It can be calculated. The read current pulse width _TP is set to be equal to or shorter than the obtained magnetization reversal time t _sw (q = 1 × 10 ⁻³ ). As a result, in the magnetoresistive effect memory using the read current, the read disturb occurrence probability can be made 0.001 or less.

When the read disturb occurrence probability q at a certain read current is set to 1 × 10 ⁻⁹ or less, Z value = −6.00 is obtained from FIG. 7B. Then, by substituting this Z value into the coefficient Z in (Equation 8), the magnetization reversal time t _sw (q = 1 × 10 ⁻⁹ ) is calculated. Then, the pulse width T _P of the read current time _{t sw (q = 1 × 10} -9) By setting below the magnetoresistive memory using the read current, the read disturb occurrence probability of 1 × 10 ^{- 9} or less.

Similarly, in order to set the read disturb occurrence probability q to 1 × 10 ⁻¹² or less, Z value = −7.03 is substituted for the coefficient Z in (Expression 8), and the time t _sw (q = 1 × 10 ^-12) is calculated, under this time _{t sw (q = 1 × 10} -12), may be set the pulse width T _P of the read current. When the read disturb occurrence probability q is set to 4 × 10 ⁻¹⁴ or less, Z value = −7.47 is substituted for the coefficient Z in (Equation 8), and the time t _sw (q = 4 × 10 ^-14) is calculated, under this time _{t sw (q = 4 × 10} -14), may be set the pulse width T _P of the read current.

  The Z value is a value representing a standard deviation from the average value, and does not depend on conditions such as components of the MTJ element.

Hereinafter, a more specific example according to the use form of the magnetoresistive effect memory will be presented, and an allowable read disturb occurrence probability and a required read current I _READ pulse width T _P (t _sw or), explain.

Note that a reference current (current density) is required in order to obtain the conditions required for the pulse width of the read current. Here, “current density J _C (10 nsec, midpoint)” is used as the reference current.
The current density J _C (10 nsec, midpoint) will be described with reference to FIG. FIG. 8 shows the dependence of the magnetization reversal probability P on the current density ratio J / J _C0 . “J” indicates the current density of the pulse current, and “J _C0 ” is the current density of the inversion threshold when the pulse width is set at the time of receiving one phonon.

  When a current having a fixed pulse width is passed through the MTJ element to reverse the magnetization of the MTJ element, the magnetization reversal probability P is uniquely determined according to the current density of the magnetization reversal current supplied to the MTJ element.

When the magnetization reversal probability P (t) shown in (Expression 2) is expressed using current density, the following expression (Expression 9) is obtained.

  As shown in FIG. 8 and (Equation 9), by calculating the magnetization reversal probability P (t) using a plurality of current densities for a certain MTJ element, the current density that achieves a certain magnetization reversal probability is obtained. Can do.

  The current density at which the magnetization reversal probability P (t) becomes 0.5 is the midpoint of the vertical axis of the characteristic curve indicating the magnetization reversal probability P (t), and the magnetization reversal probability using other current densities. A more accurate value can be obtained with a relatively small number of experiments than the calculation of.

  Therefore, hereinafter, in this specific example, the reference current (current density) is a current at which the magnetization reversal probability is 0.5.

The reference pulse width is as follows.
For example, when the current pulse width is about 1 nsec, the magnetization reversal of the magnetic layer becomes a magnetization reversal in a region called a dynamic region or a precession region. The magnetization reversal in that region shows a magnetization reversal process different from the case where a current having a pulse width of 10 nsec or more is used, and the magnetization reversal process becomes an adiabatic process. Therefore, when a current having a pulse width of about 1 nsec is used as the read current, it is different from the situation where the read disturb is dominated by the thermal disturbance. As a typical example of the write current used in the magnetoresistive effect memory, a pulse width of 10 nsec is used. Therefore, using a write current having a pulse width of 10 nsec as a reference is practical and easy to verify.

Therefore, in each of the following specific examples, the read current pulse width is required using a current density J _C (10 nsec, midpoint) having a pulse width of 10 nsec and a magnetization reversal probability P of 0.5. Find the conditions to be met. That is, the current density J _C (10 nsec, midpoint) is a parameter of “I” in (Equation 8).

Hereinafter, the conditions required according to the usage pattern of the magnetoresistive effect memory will be described using the current density J _C (10 nsec, midpoint).

(A) Specific example 1
Hereinafter, an example in which the magnetoresistive effect memory according to the present embodiment is used in a power usage meter will be described with reference to FIG.

  A magnetoresistive effect memory (for example, MRAM) used in a power usage meter has a storage capacity of about 512 kbit, for example.

  The magnetoresistive effect memory of this specific example 1 is used as data for storing the power consumption record, and the data is written frequently at high speed. On the other hand, the frequency of reading data is very low, and the magnetoresistive effect memory reads, for example, a record of power consumption once a month. That is, data reading is performed 12 times in one year.

  As described above, when the magnetoresistive effect memory is used for the power consumption meter, if the 1-bit read disturb occurrence probability is 0.001 or less, the read disturb does not occur during the 20-year use period. Can be used in

  Further, in order to set the read disturb occurrence probability q to 0.001 or less, −3.09 is used as the Z value in FIG. 7B as described above.

FIG. 9 shows the result of obtaining the magnetization reversal time t _sw (q = 1 × 10 ⁻³ ) with respect to the current density ratio J / J _C (10 nsec, midpoint) when the read disturb occurrence probability q is 0.001. It is shown with a solid line. The vertical axis in FIG. 9 represents the magnetization reversal time t _sw, and the horizontal axis in FIG. 9 represents the ratio between the current density J of the current supplied to the MTJ element and the current density J _C (10 nsec, midpoint). In addition, the characteristic line shown with the broken line in FIG. 9 is based on the magnetization reversal model shown in (Formula 1) when the same current density ratio J / J _C (10 nsec, midpoint) is used.

The magnetization inversion time t _sw of the indicated value or less by the solid line in FIG. 9, using the pulse width T _P of the read current I _READ, by reading the memory, read disturb occurrence probability is 0.001 or less Become.
As a result, as a magnetoresistive effect memory used as a power consumption meter, the operation is guaranteed and it can withstand practical use. Moreover, it can be seen from the difference in the shape of the obtained characteristic lines that the magnetization reversal model (see (Equation 4)) described in the embodiment of the present invention is different from the magnetization reversal model shown in (Equation 1).

In view of this, the condition allowed as the pulse width T _P (= t _sw ) (unit: nsec) of the read current is expressed as a function of the current density J _read of the read current as shown in (Expression 10). .

Since the variation of the read current between bits due to the variation of the circuit is expected to be about several percent, the current density ratio J / J _C (10 nsec, midpoint) is 0.9 times or less, that is, the current density of the read current is the current density J _C ( (10nsec, midpoint) must be set to 0.9 times or less. As shown in FIG. 9, when the current density ratio J / J _C (10 nsec, midpoint) is 0.9, it can be seen that the pulse width of the read current is 8 nsec or less.

  In this specific example, the case where the magnetoresistive effect memory according to the present embodiment is used for a power consumption meter has been described. However, the present invention is not limited to this, and may be used for a gas or water usage meter.

(B) Specific example 2
Hereinafter, a specific example 2 of the magnetoresistive effect memory according to the present embodiment will be described with reference to FIG. Here, a case where the magnetoresistive effect memory is used as a work memory of a computer will be described.
Since the work memory of a computer is frequently read, it is susceptible to read disturb.
In the following, a 1 Gbit magnetoresistive effect memory (for example, MRAM) will be described as an example, but of course it does not depend on the memory capacity. Here, the use form of the magnetoresistive effect memory as the work memory will be described by taking as an example a case where one write cycle is set to 50 nsec, one read cycle is set to 50 nsec, and the memory is used for 10 years. When a read disturb occurs, an error (wrong writing) due to the read disturb is corrected by, for example, ECC (Error checking and correcting). For write / read data, for example, 32 bits are set as one unit, 6 bits are further added for error correction with a Hamming code, and 38 bits of data are set as one block. An error in the write / read data is corrected with respect to this one block of data. Then, the read data is subjected to error detection and correction every time by ECC, and then written again in the memory.

In the second specific example, a read disturbance occurs in one read cycle, and a probability p ₂₊ that an error due to the read disturb (erroneous writing) occurs simultaneously in 2 bits or more in one block is 1.59 × 10. Require to be less than ^-16 . In this case, the error due to the read disturb when the magnetoresistive effect memory is used as a work memory for 10 years is less than 0.5 times.

The relational expression between the read disturb occurrence probability q of 1 bit (one MTJ element) and the probability p ₂₊ that an error occurs simultaneously in 2 bits or more in one block is expressed as follows using (Expression 11) to (Expression 13). As shown.

First, the probability p ₀ that an error due to read disturb does not occur in one read cycle can be expressed as (Equation 11).

  Here, in (Equation 11), “j” indicates the number of bits in one block, which is 38 in the second specific example.

The probability p ₁ that an error due to 1-bit read disturb occurs in one block in one read cycle can be expressed as (Equation 12).

The probability p ₂₊ that an error due to read disturb occurs simultaneously in two or more bits in one block is expressed as (Expression 13) using (Expression 11) and (Expression 12).

As described above, in this specific example 2, it is required that the probability p ₂₊ that two or more bits are simultaneously read disturbed is less than 1.59 × 10 ⁻¹⁶ .
Based on (Equation 13), since the 1-bit read disturb occurrence probability q is set to be less than 1 × 10 ⁻⁹ , the probability p _{2+ of} occurrence of errors due to read disturb simultaneously with 2 bits or more is 1.59 ×. Less than ^10-16 .

Therefore, when used as a work memory of a computer and used for 10 years, in order to reduce the occurrence of errors due to read disturb to less than 0.5 times, the 1-bit read disturb occurrence probability q is set to 1 × 10 ^−9. It may be set to less than.

FIG. 10 shows the result of obtaining the magnetization reversal time t _sw (q = 1 × 10 ⁻⁹ ) with respect to the current density ratio J / J _C (10 nsec, midpoint) when the read disturb occurrence probability q is 1 × 10 ^−9. Is shown by a solid line. The characteristic line shown by the broken line in FIG. 10 is based on the magnetization reversal model shown in (Formula 1).

The Z value at which the read disturb occurrence probability q is 1 × 10 ⁻⁹ is −6.00 as described above.

Values following magnetization inversion time _{t sw} indicated by solid lines, with the pulse width _{T P} of the read current _{I READ,} by reading the memory, the read disturb occurrence probability q is the 1 × ^{10 -9} or less Become.
As a result, as a magnetoresistive effect memory used as a work memory, the operation is guaranteed and can be practically used. Further, as shown in FIG. 10, the magnetization reversal model (Equation 4) described in the embodiment of the present invention has the magnetization shown in Eq. 1 because of the difference in tendency indicated by the obtained characteristic line. It turns out that it is different from the inversion model.

As in the example shown in FIG. 9, the condition that acceptable pulse width T _P of the read current, expressed as expressed as a function of current density J _read the read current (Equation 14).

(C) Specific example 3
A specific example 3 of the magnetoresistive effect memory according to this embodiment will be described with reference to FIG.
Here, as in the case of the specific example 2, a case where it is used as a work memory of a computer will be described. In the third specific example, consider a case where the frequency of occurrence of a defect that causes an error due to read disturbance about 0.5 times in a 10-year usage period is 1 ppm (1 × 10 ⁻⁶ ) or less. In this case, the 1-bit read disturb occurrence probability q may be less than 1 × 10 ⁻¹² .

FIG. 11 shows the result of obtaining the magnetization reversal time t _sw (q = 1 × 10 ⁻¹² ) with respect to the current density ratio J / J _C (10 nsec, midpoint) when the read disturb occurrence probability q is 1 × 10 ^−12. Is shown by a solid line. The characteristic line shown by the broken line in FIG. 11 is based on the magnetization reversal model shown in (Formula 1). The Z value at which the read disturb occurrence probability q is 1 × 10 ⁻¹² is −7.03 as described above.

Similar to that described in FIGS. 9 and 10, the value following the magnetization inversion time t _sw indicated by solid lines, with the pulse width T _P of the read current I _READ, by reading the memory, reading The disturb occurrence probability q is 1 × 10 ⁻¹² or less.
As a result, during a 10-year period of use, the frequency of occurrence of failures that cause errors due to read disturbance about 0.5 times is 1 ppm or less, and operation is guaranteed as a magnetoresistive effect memory used as a work memory. Can withstand practical use. Further, as shown in FIG. 11, the magnetization reversal model described in the embodiment of the present invention (see (Equation 4)) is different from the tendency shown by the obtained characteristic line, as shown in (Equation 1). It turns out that it is different from the model.

Similar to the example shown in FIGS. 9 and 10, in this example 3, the conditions allowed for the pulse width T _P of the read current, expressed as a function of current density J _read of the read current, ( It can be expressed as Equation 15).

(D) Specific example 4
A specific example 4 of the magnetoresistive effect memory according to the present embodiment will be described with reference to FIG. In specific example 4, as in specific example 2 and specific example 3, the case where it is used as a work memory of a computer will be described.
In specific example 4, every time data is read, ECC is performed every time, and the data is not verified and corrected. Instead, the data is corrected about once for 1000 reading operations, and the corrected data is written to the memory. Think about returning.
Then, in a 10-year usage period, the frequency of occurrence of defects in which errors due to read disturb occur about 0.5 times is set to 1 ppm or less. In this case, the 1-bit read disturb occurrence probability q should be less than 4 × 10 ⁻¹⁴ .

In FIG. 12, the result of obtaining the magnetization reversal time t _sw (q = 4 × 10 ⁻¹⁴ ) with respect to the current density ratio J / J _C (10 nsec, midpoint) when the read disturb occurrence probability q is 4 × 10 ^−14. Is shown by a solid line. In addition, the characteristic line shown with the broken line in FIG. 12 is based on the magnetization reversal model shown by (Formula 1). The Z value at which the read disturb occurrence probability q is 4 × 10 ⁻¹⁴ is −7.47 as described above.

As with other examples, the value following the magnetization inversion time t _sw indicated by solid lines, with the pulse width T _P of the read current I _READ, by reading the memory, the read disturb occurrence probability q is, 4 × 10 ⁻¹⁴ or less.
As a result, when data is corrected once for 1000 reading operations within a 10-year period of use, the frequency of occurrence of defects that cause errors due to reading disturbance about 0.5 times is reduced to 1 ppm or less. Become. Also in the example shown in FIG. 12, it can be seen that the magnetization reversal model (see (Equation 4)) described in the embodiment of the present invention is different from the magnetization reversal model shown in (Equation 1).

Also in this example 4, similarly to the other examples, the conditions allowed for the pulse width T _P of the read current, expressed as a function of current density J _read of the read current can be expressed as (Equation 16).

(E) Summary
(About pulse width of read current)
As described in the specific examples 1 to 4, in the memory chip, the allowable value for the read disturb occurrence probability q for one bit (one MTJ element) is the guaranteed value of the occurrence frequency of defects and the operation of the number of read times. It can be uniquely determined according to the usage status of the memory chip, such as conditions and application of error correction technology such as ECC.

To allowable value or less according to the usage pattern read disturb occurrence probability q, if other conditions are constant, it must be below a certain value the pulse width T _P of the read current.
Based on the conditions allowed as the pulse width T _P (magnetization reversal time t _sw ) of the read current I _READ such as (Expression 10), (Expression 14), (Expression 15), and (Expression 16), the read current I Doing normalized for pulse width _{T P} of _READ, it is expressed by the following equation.

  The coefficient “A” and the coefficient “B” in (Expression 17) are parameters that depend on one bit, that is, the read disturb occurrence probability q for one MTJ element. The coefficient “A” and the coefficient “B” are parameters that depend on the material characteristics and dimensions of the memory layer. In particular, the coefficient “A” strongly depends on the attenuation constant and saturation magnetization of the storage layer. The dependence of the coefficients “A” and “B” on other material properties and dimensions of the storage layer is small.

FIG. 13 shows the dependence of the parameters “A” and “B” included in (Equation 16) on the read disturb occurrence probability q from simulations and experiments. Note that the attenuation constant α _damp of the storage layer used in the simulation and experiment is set to 0.01, and the saturation magnetization Ms of the storage layer is set to 500 emu / cc.

In FIG. 13, the horizontal axis represents the read disturb occurrence probability q. In FIG. 13, the left vertical axis indicates the value of parameter A, and the right vertical axis indicates the value of parameter B. The solid line indicates the characteristic line of parameter A, and the broken line indicates the characteristic line of coefficient B. The characteristic lines of the parameters A and B shown in FIG. 13 can be expressed as, for example, (Equation 18) and (Equation 19) below. In (Equation 18) and (Equation 19), “Ln” represents a natural logarithm.

  By using the above (Equation 17) to (Equation 19) and setting the pulse width of the read current more precisely, it is possible to provide a magnetoresistive effect memory that reduces read disturb.

(Dependence of damping constant on magnetization reversal time)
Here, the dependence of the attenuation constant of the storage layer on the magnetization reversal time (read current pulse width) of the MTJ element will be described.
The magnetization reversal time of the MTJ element becomes longer as the saturation magnetization of the storage layer becomes larger, and becomes longer as the attenuation constant of the storage layer becomes smaller.

FIG. 14 shows the magnetization reversal time t _sw for the current density ratio J / J _C (10 nsec, midpoint) when the damping constant of the storage layer is set to α _damp = 0.01 and α _damp = 0.03, respectively. Shows changes. In FIG. 14, the read disturb occurrence probability q is set to 1 × 10 ⁻³ . The horizontal axis in FIG. 14 indicates the current density ratio J / J _C (10 nsec, midpoint), and the vertical axis in FIG. 14 indicates the magnetization reversal time t _sw (= pulse width T _P ).

As shown in FIG. 14, when the attenuation constant α _damp of the storage layer is 0.01, the magnetization reversal speed t _sw is compared with the magnetization reversal speed when the attenuation constant α _damp is 0.03. 2.3 times larger.

Based on the dependence of the magnetization reversal time obtained from FIG. 14 on the storage layer, the parameter A can be expressed by the following (formula 20).

Each constant shown in (Formula 20) is as follows. “Α _damp ” indicates the attenuation constant of the storage layer, and is, for example, a value of 0.05 to 0.01. “MS” indicates the saturation magnetization of the storage layer, and its unit is emu / cc. The saturation magnetization Ms of the storage layer is, for example, 500 to 1000 emu / cc. “Ln” indicates a natural logarithm. “Q” is a read disturb occurrence probability of 1 bit (one MTJ element).

Thus, the coefficient A shown in (Equation 20) can be expressed using the attenuation constant and saturation magnetization of the storage layer. Thus, the pulse width T _P of the read current shown in (Equation 20) is a damping constant and a value that depends on the saturation magnetization of the storage layer.

As described above, by taking into account the damping constant and the saturation magnetization of the storage layer of the MTJ element can be set the pulse width T _P more preferred read current.

Thus, as described in the specific example of the present embodiment, the use of (Formula 17) to by setting the pulse width T _P of the read current using (Equation 20), the magnetoresistive memory (e.g., MRAM) It can be set preferably pulse width T _P in accordance with the embodiment.
Therefore, read disturb of the magnetoresistive effect memory can be reduced.

[Application example]
An application example of the embodiment of the present invention will be described.
The magnetoresistive effect memory according to the embodiment of the present invention is used for a spin injection type magnetoresistive random access memory (MRAM). Hereinafter, the configuration of the MRAM will be described with reference to FIGS.

(1) Overall configuration
FIG. 15 is a diagram showing a circuit configuration in the vicinity of the memory cell array of the MRAM.

  The plurality of memory cells MC are arranged in an array in the memory cell array 20.

  FIG. 16 is a diagram showing an example of the structure of the memory cell MC provided in the memory cell array 20. The upper end of the MTJ element 1 is connected to the upper bit line 32 via the upper electrode 31. The lower end of the MTJ element 1 is connected to the source / drain diffusion layer 37a of the select transistor ST via the lower electrode 33, the lead-out wiring 34, and the plug 35. The source / drain diffusion layer 37 b of the selection transistor ST is connected to the lower bit line 42 via the plug 41.

On the semiconductor substrate (channel region) 36 between the source / drain diffusion layer 37a and the source / drain diffusion layer 37b, a gate electrode (word line) 39 is formed via a gate insulating film 38.
Note that at least one of the lower electrode 33 and the extraction electrode 34 may be omitted. For example, when the lower electrode 33 is omitted, the MTJ element 1 is formed on the lead wiring 34. When the lead wiring 34 is omitted, the lower electrode 33 is formed on the plug 35. Further, when the lower electrode 33 and the extraction electrode 34 are omitted, the magnetoresistive effect element 1 is formed on the plug 35.

  The word line WL extends in the row direction and is connected to the gate of the selection transistor Tr constituting the memory cell MC.

  One end of the word line WL is connected to the row control circuit 4. The row control circuit 4 performs a selection operation on the word line WL.

  The bit lines BL and bBL extend in the column direction. One end of the MTJ element 1 is connected to the bit line BL, and the bit line bBL is connected to one end of the current path of the selection transistor Tr. Two bit lines BL and bBL constitute a bit line pair.

  Column control circuits 3A and 3B are connected to one end and the other end of the bit lines BL and bBL. The write circuits 5A and 5B are connected to one end and the other end of the bit line via the column control circuits 3A and 3B. Each of the write circuits 5A and 5B includes a source circuit such as a current source and a voltage source for generating a write current, and a sink circuit for absorbing the write current.

  The read circuits 2A and 2B are connected to one end and the other end of the bit lines BL and bBL via the column control circuits 3A and 3B. The read circuits 2A and 2B include a voltage source or current source that generates a read current, a sense amplifier that detects and amplifies a read signal, a latch circuit that temporarily holds data, and the like.

  In the column control circuits 3A and 3B, a switch circuit for controlling the conduction state between the bit lines BL and bBL and the write circuits 5A and 5B, and a conduction state between the bit lines BL and bBL and the read circuits 2A and 2B are controlled. A switch circuit is provided.

  During the write operation, in the column control circuits 3A and 3B, the switch circuit connected to the memory cell MC to be written is turned on, and the other switch circuits are turned off. In addition, the row control circuit 2 turns on the selection transistor ST in the selected memory cell MC. Then, a write current having a direction corresponding to the write data is supplied to the selected memory cell MC. When writing data, one of the write circuits 5A and 5B is on the source side, and the other write circuit 5A and 5B is on the sink side, depending on the direction of current flow.

  Hereinafter, a configuration example and a read operation example of the read circuit of the MRAM will be described in detail.

(2) Reading circuit
(A) Basic configuration
FIG. 17 is a diagram illustrating a configuration example of the sense amplifier 21 and the latch circuit 22 included in the read circuits 2A and 2B.
As shown in FIG. 17A, the operation of the sense amplifier 21 is controlled by control signals (hereinafter referred to as S / A drive signals) EN and bEN. A reference signal REF and an input signal (read signal) IN are input to the two input terminals of the sense amplifier 21, respectively. The read signal IN is the value of the potential of the bit line that varies according to the MR ratio (data) of the MTJ element when the read current I _READ flows through the MTJ element. The reference signal REF is a constant potential that serves as a reference for determining the potential level of the read signal.

The output terminal of the sense amplifier 21 is connected to the input terminal of the latch circuit 22.
The operation of the latch circuit 22 is controlled by a control signal (hereinafter referred to as a data capture signal) LCH. The latch circuit 22 temporarily holds the signal output from the sense amplifier 21 and outputs the held signal as the output signal OUT. The output signal OUT corresponds to data read from the memory cell.

  FIG. 17B shows an example of a circuit in which the sense amplifier 21 and the latch circuit 22 are combined.

In the example shown in FIG. 17B, a flip-flop circuit FF composed of two CMOS inverters is provided. A power supply potential Vdd is supplied to the flip-flop circuit FF via a P-channel field effect transistor (FET) 24B. A control signal bEN is input to the gate of the P-channel FET 24B, and on / off of the FET 24B is controlled by the control signal bEN.
Further, the ground potential Vss (GND) is supplied to the flip-flop circuit FF via the N-channel FET 24A. A control signal EN is input to the gate of the FET 24A, and on / off of the FET 24A is controlled by the control signal EN.
The control signal EN and the control signal bEN have a complementary relationship, and when the control signal EN is at the “H (high)” level, the control signal bEN indicates the “L (low)” level. When the control signal EN is at “L” level, the control signal bEN indicates “H” level.

  N-channel FETs 23A and 23B are connected to the two nodes n1 and n2 of the flip-flop circuit FF, respectively.

One end of the current path of the N-channel FET 23A is connected to the node n1. A reference signal REF is input to the other end of the current path of the N-channel FET 23A. A data capture signal LCH is input to the gate of the N-channel FET 23A, and on / off of the FET 23A is controlled by the data capture signal LCH.
One end of the current path of the N-channel FET 23B is connected to the node n2. The read signal IN is input to the other end of the current path of the N-channel FET 23B. A data capture signal LCH is input to the gate of the N-channel FET 23B, and on / off of the FET 23B is controlled by the data capture signal LCH.
The data capture signals LCH input to the two FETs 23A and 23B have the same signal level and are input to the FETs 23A and 23B, respectively.

  A node n3 is provided between the node n1 and the FET 23A, and the output terminal bOUT is connected to the node n3. A node n4 is provided between the node n2 and the FET 23B, and the output terminal OUT is connected to the node n4.

(B) Configuration example 1
(Circuit configuration)
An example of a read circuit and a read operation used in the MRAM according to this application example will be described with reference to FIGS. Here, constituent elements necessary for explaining the reading circuit and the reading operation are extracted and described, and illustration and description of other constituent elements are omitted. In addition, the same code | symbol is attached | subjected about the same element as the component demonstrated using FIG.15 and FIG.17, and the description is performed as needed.

  FIG. 18 and FIG. 19 are schematic diagrams showing constituent elements for explaining a read circuit and a read operation of the MRAM according to this application example. FIGS. 18 and 19 illustrate a 2 × 2 memory cell array in which four memory cells are arranged in a matrix along the row direction and the column direction for the sake of simplicity.

  In the following, a case where a memory cell Selected_MC surrounded by a broken line in FIGS. 18 and 19 is selected and data stored in an MTJ element in the memory cell (hereinafter referred to as a selected cell) is read will be described.

  In the memory cell array, four bit lines BL <0>, bBL <0>, BL <1>, bBL <1> are provided. The two bit lines BL <0> and bBL <0> form a pair of bit lines. Similarly, the two bit lines BL <1> and bBL <1> form a pair of bit lines. In addition, two word lines WL <0> and WL <1> are provided in the memory cell array.

  The selected cell Selected_MC is connected between the bit line pair BL <0>, bBL <0>. One end of the MTJ element 1 is connected to the bit line BL <0>. The other end of the MTJ element 1 is connected to one end of the current path of the selection transistor Tr. The other end of the current path of the selection transistor Tr is connected to the bit line bBL <0>.

  In the example shown in FIGS. 18 and 19, the storage layer 13B of the MTJ element 1 is connected to the bit line BL <0>, and the reference layer 11B of the MTJ element 1 is connected to the bit line bBL <0> via the selection transistor Tr. It is connected. The MTJ element 1 may be a perpendicular magnetization type or an in-plane magnetization type. Further, the connection relationship of the reference layer / storage layer with respect to the bit line may be opposite to the example shown in FIGS.

  A word line WL <1> is connected to the gate of the selection transistor Tr in the selected cell Selected_MC. That is, the word line WL <1> becomes the selected word line (hereinafter, selected word line). Other word lines WL <0> are non-selected word lines.

  The read circuit 2A is connected to the bit lines BL <0> and BL <1> via column control switches (for example, FETs) 30A and 31A, respectively. The read circuit 2B is connected to the bit lines bBL <0> and bBL <1> via column control switches 30B and 31B, respectively.

The column control switches 30A, 30B, 31A, 31B are provided, for example, in the column control circuits 3A, 3B.
The column control switches 30A and 30B connected to one end and the other end of the bit line pair BL <0> and bBL <0> are controlled (on / off) by a column control signal CS <0>. The column control signal CS <0> having the same signal level is input to the column control switch 30A and the column control switch 30B.

  The column control switches 31A and 31B connected to one end and the other end of the bit line pair BL <1> and bBL <1> are controlled by a column control signal CS <1>. The column control signal CS <1> having the same signal level is input to the column control switch 31A and the column control switch 31B.

When the column control signals CS <0> and CS <1> are at “H (high)” level (Vdd level), the column control switch is turned on and the column control signals CS <0> and CS <1> are set to “L ( low) ”level (Vss level), the column control switch is turned off.
Column control switches connected to selected bit lines (hereinafter referred to as selected bit lines) are turned on, and column control switches connected to bit lines other than selected bit lines (hereinafter referred to as non-selected bit lines) Turned off.

When the column control switch is turned on, the selected cell Selected_MC and the read circuits 2A and 2B are electrically connected.
Here, the selected bit lines are the bit line BL <0> and the bit line bBL <0>, and the column control switches to be turned on are the switch 30A and the switch 30B.

In the read circuits 2A and 2B, in addition to the sense amplifier 21 and the latch circuit 22 shown in FIG. 17, power sources (voltage sources) Vdd and Vss (GND) for generating a read current I _READ and switches 25A and 25B , 26. 18 and 19, the sense amplifier 21 and the latch circuit 22 are provided in one readout circuit 2B. However, the sense amplifier 21 and the latch circuit 22 may be provided in both the read circuit 2A and the read circuit 2B in order to suppress a reduction in read sensitivity due to the bit line wiring length.

  The switch 25A is, for example, a P-channel field effect transistor (FET). The power supply voltage Vdd is supplied to one end of the current path of the switch 25A. The other end of the current path of the switch 25A is connected to the common wiring DQ1. The operation of the switch 25A is controlled by a control signal (hereinafter referred to as a read current drive signal) bRB.

  The switch 25B is, for example, an N channel field effect transistor (FET). A ground potential Vss (GND) is supplied to one end of the current path of the switch 25B. The other end of the current path of the switch 25B is connected to the common wiring DQ2. The operation of the switch 25B is controlled by the control signal RB.

  In the first configuration example, the read current drive signal bRB is described as a signal controlled separately from the control signal RB. However, the read current drive signal bRB and the control signal RB may be complementary to each other. Good. In other words, when the signal levels are complementary to each other, when the read current drive signal bRB is at the “L” level, the control signal RB indicates an inverted signal (“H” level) of the read current drive signal bRB. Thus, control can be performed so that the switch 25B, which is an N-channel FET, is turned on at the same time as the switch 25A of the P-channel FET is turned on.

  In FIGS. 18 and 19, one switch 25A and 25B are shown in each of the readout circuit 2A and the readout circuit 2B. However, both the switch 25A and the switch 25B are included in the readout circuits 2A and 2B. It may be provided and connected to the common wirings DQ1 and DQ2, respectively.

  A switch 26 is provided in the readout circuit 2B. The switch 26 is, for example, an N channel field effect transistor (FET). One end of the current path of the switch 26 is connected to the input terminal of the sense amplifier 21, and the other end of the current path of the switch 26 is connected to the common wiring DQ1. A control signal Vcl is input to the gate of the switch 26, and the operation (on / off) of the switch 26 is controlled by the signal Vcl. The switch 26 adjusts so that the potential applied to the MTJ element becomes a predetermined value during reading.

As shown in FIG. 18, when the read current I _READ flows from the read circuit 2B toward the read circuit 2A, the switch 25A in the read circuit 2B is turned on, and the power supply potential Vdd is supplied to the common wiring DQ1. . Further, the switch 25B in the read circuit 2A is turned on, and the ground potential Vss is supplied to the common wiring DQ2. In the example shown in FIG. 18, the read current I _READ flows from the reference layer 11B of the MTJ element 1 to the storage layer 13B. Needless to say, the moving direction of the electrons is opposite to the direction in which the read current I _READ flows.

As shown in FIG. 19, when the read current I _READ flows from the read circuit 2A toward the read circuit 2B, the switch 25A in the read circuit 2A is turned on, and the power supply potential Vdd is supplied to the common wiring DQ2. . Further, the switch 25B in the read circuit 2B is turned on, and the ground potential Vss is supplied to the common wiring DQ1. In the example shown in FIG. 19, the read current I _READ flows from the storage layer 13B of the MTJ element 1 to the reference layer 11B.

18 and 19 show an example in which the read current I _READ is generated using the power supply potential (voltage source) Vdd, but instead of the voltage source, a constant current source is used in the current path of the switch 25A. Of course, the read current I _READ may be generated by connecting to one end.

In the MRAM shown in FIG. 18 and FIG. 19, the pulse width _{T P} of the read current _{I READ} generated by the reading circuit 2A, 2B, the magnetization of the storage layer 13B is than the time until the start of coherent precession Also, the operations of the switches 25A and 25B are controlled so as to be shorter. More specifically, the pulse width _{T P} of the read current _{I READ} is so as to satisfy the conditions shown in (Equation 17) to (Equation 20), it is set and controlled.

(Operation)
The read operation of the circuit (MRAM) shown in FIGS. 18 and 19 will be described with reference to FIG. FIG. 20 shows a timing chart of the read operation of the circuit shown in FIGS. Here, FIG. 18 or FIG. 19 is also used. In the circuits shown in FIGS. 18 and 19, the operation is substantially the same except that the direction of the read current flowing through the MTJ element is different. As described above, the selected cell to be read is the cell Selected_MC surrounded by a broken line in FIGS. 18 and 19, the selected word line is the word line WL <1>, and the selected bit line is the bit. Line BL <0> and bit line bBL <0>.

  First, the potential Vdd (“H” level) is supplied to the selected word line WL <1>, and the selected word line WL <1> is activated. At the same time, the potential of the column control signal SelectedCS (here, CS <0>) for the selected bit lines BL <0> and bBL <0> changes from the potential Vss (“L” level) to the potential Vdd (“H” level). ). As a result, the column control switches 30A and 30B connected to the selected bit lines BL <0> and bBL <0> are turned on, and the bit lines BL <0> and bBL <0> are activated. However, the selected word line WL <1> and the selected bit lines BL <0>, bBL <0> may not be activated at the same time.

  During the read operation for the selected cell, the control signal Vcl of the switch 26 is set to a constant signal level (potential) and turned on. During the read operation, the potential Vss is supplied to the unselected word line WL <0>, and the potential Vss is supplied to the column control signal OtherCS (CS <1> in this case) for the unselected bit line. That is, the non-selected word line WL <0> and the non-selected bit lines BL <1> and bBL <1> are inactivated during the read operation.

  After a predetermined period T1, T2 has elapsed since the selected word line WL <1> and the selected bit lines BL <0>, bBL <0> are activated, the signal level of the read current drive signal bRB changes from the potential Vdd. Transition to the potential Vss. As a result, the switch (P-channel FET) 25A controlled by the read current drive signal bRB is turned on, and the potential Vdd is applied to the bit line bBL <0> (or BL <0>). Further, during the read operation, for example, the signal level of the control signal RB is set to the potential Vdd, and the switch (N-channel FET) 25B is turned on. Therefore, the potential Vss is applied to the bit line BL <0> (or bBL <0>). As described above, the control signal RB may be an inverted signal of the read current drive signal bRB. In this case, in the read operation, the signal level of the control signal RB is set to be constant at the potential Vdd, and the signal level of the read current drive signal bRB is set to be constant at the potential Vss.

As a result, the read current I _READ is supplied to the MTJ element 1 in the selected cell Selected_MC.

After a predetermined period T3 elapses after the signal level of the read current drive signal bRB is changed to the potential Vss, the signal level of the data capture signal LCH is changed from the potential Vss to the potential Vdd.
As described above, after the read current drive signal bRB is driven and the read current I _READ is output, the data capture signal LCH is driven and the latch circuit 22 is turned on. The read current I _READ is the MTJ element. 1 before the latch circuit 22 changes the potential variation of the bit line caused by the flow of 1, that is, the read signal sufficiently reflects the resistance state (MR ratio) of the MTJ element 1. This is to prevent accidental capture as data.

After a predetermined period has elapsed, the signal level of the data capture signal LCH is changed from the potential Vdd to the potential Vss, and the latch circuit 22 stops capturing data.
Thereafter, after the period T4 has elapsed, the signal level of the read current drive signal bRB is changed from the potential Vss to the potential Vdd. The read current I _READ is supplied to the MTJ element in the selected cell during the period T _READ in which the signal level of the read current drive signal bRB is the potential Vss.
The reason why the supply of the read current I _READ is stopped after the latch circuit 22 is stopped is to prevent the latch circuit 22 from taking in erroneous data as described above.

  After a predetermined period T5 has elapsed since the signal level of the data capture signal LCH was set to the potential Vss, the signal level of the S / A drive signal EN is changed from the potential Vss to the potential Vdd. As a result, the sense amplifier 21 is driven, and the sense amplifier 21 compares the read signal (input signal) IN with the reference signal REF, and changes the potential of the bit line corresponding to the resistance state (MR ratio) of the MTJ element 1. Is detected. By driving the sense amplifier 21 after the latch circuit 22 is stopped, the sense amplifier 21 can amplify the fluctuation potential (data) of the bit lines BL <0> and bBL <0> at high speed.

Here, the operations of the sense amplifier 21 and the latch circuit 22 will be described more specifically with reference to FIG.
In a state where the read current I _READ is supplied to the MTJ element 1 in the selected cell Selected_MC, the sense amplifier 21 receives the bit lines BL <0> and bBL <1> affected by the MR ratio of the MTJ element 1. The potential is detected as a read signal IN. The sense amplifier 21 outputs a comparison result (potential difference) between the detected read signal IN and the reference signal REF to the latch circuit 22. The latch circuit 22 holds the output of the sense amplifier 21 and outputs it as data to the outside.
In FIG. 17B, the read current I _READ is output, and the potential difference between the read signal IN and the reference signal REF, which is an input to the sense amplifier 21, has become a value (size) sufficient for detection. When the signal level of the data capture signal LCH is “H (Vdd)” level, the potential corresponding to the read signal IN and the reference signal REF is transferred to the output terminals OUT and bOUT.

Thereafter, even if the data capture signal LCH transitions from the “H” level to the “L (Vss)” level, the potentials at the output terminals OUT and bOUT are caused by the capacitances present at the output terminals OUT and bOUT (nodes n3 and n4). Is retained.
In this holding state, the S / A drive signal EN is set to the “H” level, and the control signal bEN complementary to the S / A drive signal EN is set to the “L” level, whereby the potentials of the output terminals OUT and bOUT are changed to the potential. Amplified to the level of Vdd and the level of potential Vss, respectively. In order to increase the amplification of the potential level, it is preferable that the output terminals OUT and bOUT have the same capacitance.

  Then, after a predetermined period T6 has elapsed since the signal level of the read current drive signal bRB is set to the potential Vdd, the signal level of the selected word line WL <1> is changed from the potential Vdd to the potential Vss, and the selected word line WL <1> is deactivated.

In addition, after a predetermined period T7 has elapsed since the signal level of the read current drive signal bRB is changed to the potential Vss, the signal level of the selected column control signal CS <0> is changed from the potential Vdd to the potential Vss. Bit lines BL <0> and bBL <0> are deactivated. As a result, the selected cell selected_MC and the read circuits 2A and 2B are electrically separated.
This completes the read operation of the MRAM.

As described above, the read current I _READ is supplied to the MTJ element during the period T _READ in which the signal level of the signal bRB is at the potential Vss. Therefore, this period T _READ is made shorter than the time until the magnetization in the storage layer 13B coherently precesses. More specifically, the period T _READ is set to the magnetization reversal time (switching time) t _sw of the MTJ element 1 that satisfies (Expression 17) to (Expression 20).
Thus, the pulse width _{T P} is the read current _{I READ} follows the magnetization inversion time _{t sw,} can be supplied to the MTJ element in the selected cell.

  Therefore, the MRAM according to Configuration Example 1 can provide an MRAM with reduced read disturb.

(C) Configuration example 2
(Circuit configuration)
A configuration example 2 of the MRAM, which is an application example of this embodiment, will be described with reference to FIGS. 21 and 22. Here, differences from the configuration example described in Configuration Example 1 will be mainly described, and description of common components will be given as necessary.

  The MRAM shown in FIG. 21 is different from the MRAM shown in FIGS. 18 and 19 in that precharge circuits 29A to 29C are further provided.

  The precharge circuits 29A to 29C are provided in, for example, the column control circuits 3A and 3B and the read circuits 2A and 2B.

  As shown in FIG. 21, the precharge circuits 29A to 29C are connected to the common wiring DQ1 and the bit lines bBL <0> and bBL <1>. The precharge circuits 29A to 29C are composed of a switch and a power supply Vpre. The switch is, for example, an N-channel FET. One end of the switch current path is connected to the power supply Vpre, and the other end of the switch current path is connected to the bit lines bBL <0>, bBL <1> or the common line DQ1. A precharge drive signal PRE is input to the gate of the switch. By this drive signal PRE, the operation (on / off) of the switches in the precharge circuits 29A to 29C is controlled, and the precharge for the wiring is controlled.

The potential Vpre used for precharging (hereinafter referred to as precharge potential) Vpre is approximately the same as the potential applied to the bit line / common line by the read current I _READ and the supply potential to the switch 26 (for example, Potential Vdd).

When performing a read operation, the precharge circuit 29A~29C, prior to feeding the read current _{I READ} to the MTJ element, the common wiring DQ1 and the bit line bBL <0>, the bBL <1>, the precharge potential Vpre Apply in advance. In the read operation, the precharged bit line is a bit line set to a high potential and a common wiring, and the bit line set to a low potential (Vss) is not precharged. Further, the non-selected bit line may not be precharged.

FIG. 22 is a timing chart showing a read operation of the MRAM shown in FIG.
As shown in FIG. 22, in the second configuration example, first, the signal level of the precharge drive signal PRE is changed from the potential Vss to the potential Vdd, and the precharge circuits 29A to 29C are driven. As a result, the precharge potential Vpre is applied to the bit line and the common wiring.

  After a predetermined period, the signal level of the precharge drive signal PRE is changed from the potential Vdd to the potential Vss, and the switches in the precharge circuits 29A to 29C are turned off. As a result, the precharge circuits 29A to 29C are electrically separated from each wiring, and the precharging of each wiring is completed.

  After a predetermined period T0 has elapsed since the signal level of the precharge drive signal PRE is set to the potential Vss, the potential Vdd is supplied to the selected word line WL <1>, and the signal level of the column control signal CS <0> is The potential is set to Vdd. As a result, the selected word line WL <1> and the selected bit lines BL <0>, bBL <0> are activated. The subsequent operation is the same as the operation shown in FIG.

  As described above, the precharge circuits 29A to 29C precharge the bit line and the common line before the selected word line WL <1> and the selected bit lines BL <0> and BL <1> are activated. A potential Vpre is supplied to precharge each wiring.

In the MRAM shown in FIGS. 18 and 19, the bit line and the common wiring are charged by the read current IREAD and the supply potential of the switch 26. In this case, since the start of the charging of the wiring and the start of the supply of the read current are performed substantially simultaneously, it is caused by the response speed of the read current drive signal bRB (switch 25A) and the wiring capacity of the bit line / common wiring. Thus, the time until the current value of the read current I _READ reaches a predetermined value becomes longer. That is, the rising time _t 1 ~t ₂ read current is increased as shown in FIG. 1 (b), the pulse width _{T P} of the read current _{I READ} is increased.

On the other hand, as shown in FIG. 21, when the precharge circuits 29A to 29C precharge the bit lines and the common wiring, the parasitic capacitances of the bit lines and the common wiring at the rising time t _{1 to} t ₂ of the read current I _READ. The amount of charge of the read current charged to becomes smaller. As a result, it is possible to mitigate the effects of wiring delay, using the read current I _READ shorter pulse width T _P, the read operation can be performed.
FIG. 23 shows a simulation result of the time change of the read signal when the wiring capacitance of the bit line is 200 fF and the total resistance value of the MTJ element 1 and the selection transistor Tr is set to 15 kΩ. 23 represents time (unit: nsec), and the vertical axis of FIG. 23 represents voltage (unit: au) corresponding to the read signal. As shown in FIG. 23, when precharge is not performed, it takes about 7 nsec until the read signal rises and becomes saturated. On the other hand, when the precharge of each wiring is executed as in this example, the read signal reaches a predetermined level in about 2 nsec.

In this way, the time for charging the wiring is shortened, and the data stored in the MTJ element in the selected cell can be read at high speed. Further, since the lower the influence of the wiring capacity can be shorter pulse width T _P of the read current. Further, the fluctuation of the pulse width T _P due to wiring is reduced, MRAM operation is stabilized.

  Therefore, according to the MRAM of Configuration Example 2 shown in FIG. 21, the read disturb can be reduced and the precharge circuits 29A to 20C can be further provided to speed up the read operation.

(D) Effect of the number of memory cells on the read current
The influence of the number of memory cells connected to the bit line on the read current will be examined with reference to FIGS.

If large memory cell array as MRAM is configured as shown in FIG. 15, whether the pulse width T _P of the read current I _READ, can be reduced to what extent, Ya magnitude of the read signal detected by the sense amplifier 21 The delay time t _{1 to} t ₂ of the rise of the read current I _READ shown in FIG.

  For example, the sense amplifier 21 detects a larger read signal in correlation with the magnitude of the MR ratio of the MTJ element 1. For example, when the resistance value of the MTJ element is several kΩ, it is desirable to obtain an MR ratio of 100% or more.

Further, the rise time t _{1 to} t ₂ of the read current pulse is affected by the resistance value and capacitance of the wiring through which the read current I _READ flows, such as the bit line and the common wiring.
However, the resistance values of the bit lines and the common wiring are sufficiently smaller than the resistance values of the MTJ element 1 and the selection transistor Tr constituting the memory cell MC. Therefore, here, in the wiring path through which the read current I _READ flows, the resistance values of the MTJ element 1 and the selection transistor are considered, and the resistance value of the wiring is considered to be substantially zero.

FIG. 24 shows the simulation result of the change with time of the voltage (read signal) generated by the read current I _READ when the total resistance value of the MTJ element 1 and the selection transistor Tr is 15 kΩ. 24 represents time (unit: nsec), and the vertical axis in FIG. 24 represents voltage (unit: au). In the simulation shown in FIG. 24, the wiring capacitance of the bit line BL is set to 20 fF, 50 fF, 100 fF, 200 fF, and 500 fF, respectively. In FIG. 24, the rise time of the read current drive signal bRB is set to 1 nsec.

  As shown in FIG. 24, as the wiring capacitance increases, the rise time of the voltage (readout current) becomes longer. This means that the minimum pulse width capable of reading data is defined by the wiring capacitance such as a bit line.

  The wiring capacity depends on the length and width of the wiring, the interval between adjacent wirings, and the like. For example, when the wiring width is set to 100 nm, the space between adjacent wirings is set to 100 nm, and the thickness of the interlayer insulating film using silicon oxide is set to 2000 nm, the wiring capacitance for a wiring length of 1 μm is about 0.2 fF. .

FIG. 25 shows the relationship between the number of memory cells connected to one bit line and the minimum pulse width of the read current I _READ . The horizontal axis in FIG. 25 indicates the number of memory cells connected to one bit line, and the vertical axis in FIG. 25 indicates the minimum pulse width of the read current. In FIG. 25, verification is performed by setting the size of one memory cell (see FIG. 16) in the extending direction of the bit line to 200 nm. Here, in FIG. 23, if the characteristic line is curved and saturated within a certain pulse width, data can be normally read using a read current having the pulse width.

Pulse width T _P of the read current, depending on the number of memory cells connected to the bit line, it is necessary to be less than or equal to the value indicated by the solid line in FIG. 25.
From the tendency shown in FIG. 25, if the number of memory cells connected to one bit line BL is 5000 or less, the pulse width TP of the read current I _READ can be 8 nsec or less.

Therefore, in the case where the MRAM larger scale of the memory cell array, to consider the number of memory cells, it is possible to set the pulse width T _P of the read current.
Therefore, according to the embodiment of the present invention, a magnetoresistive effect memory with reduced read disturb can be provided.

4). Other
The example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying each component without departing from the gist thereof. Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.

  1: MTJ element (magnetoresistance effect element), 2, 2A, 2B: read circuit, Tr: selection transistor, BL, bBL: bit line, WL: word line, 30: switch (column control switch).

Claims (4)

Provided between the reference layer and the storage layer, the reference layer formed from the first magnetic layer whose magnetization direction is invariable, the storage layer formed from the second magnetic layer whose magnetization direction is variable A magnetoresistive element having a tunnel barrier layer formed;
A read circuit that applies a pulse-shaped read current to the magnetoresistive element to determine data stored in the magnetoresistive element;
Comprising
The magnetization of the storage layer is formed by spins respectively possessed by a plurality of magnetic grains in the second magnetic layer,
Pulse width of the read current precession coherently plurality of spin from a state in which each of the plurality of spins are carried out precess in a random phase forming the magnetization of the storage layer cooperates A magnetoresistive effect memory characterized by being shorter than a period until exercise.   The read current has a current density of 0 when the magnetization reversal probability of the magnetoresistive element is 0.5 or less when data is written to the magnetoresistive element using a write current having a pulse width of 10 nsec. 2. The magnetoresistive effect memory according to claim 1, wherein when it is 9 times or less, a pulse width of the read current is 8 nsec or less. The readout circuit includes
A sense amplifier that amplifies a read signal corresponding to data stored in the magnetoresistive element;
The read signal is output to the wiring that connects the read circuit and the magneto-resistance effect element, and, claims, characterized in that it comprises a latch circuit for holding the read signal amplified by the sense amplifier 3. The magnetoresistive effect memory according to any one of 1 and 2.   4. A precharge circuit for charging a wiring connecting the magnetoresistive effect element and the read circuit before supplying the read current to the magnetoresistive effect element. The magnetoresistive effect memory according to claim 1.

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