JP5386312B2 - Resonant type converter - Google Patents

Description

  The present invention relates to a resonant converter.

  Conventionally, a resonant converter has been used as a switching power supply device (see, for example, Patent Document 1).

[Configuration of Resonant Type Converter 100]
FIG. 9 is a circuit diagram of a resonant converter 100 according to a conventional example. The resonant converter 100 includes a transformer T, a DC power supply VDD, switch elements Q1, Q2, Q3, Q4, Q5, and Q6 configured by N-channel MOSFETs, an inductor Lr, capacitors Cr and C1, a first A control unit 111 and a second control unit 112 are provided, and DC power is supplied to the load Load.

  First, the configuration of the primary side of the transformer T will be described. The drain of the switch element Q1 and the drain of the switch element Q3 are connected to the positive electrode of the DC power supply VDD, and the source of the switch element Q2 and the source of the switch element Q4 are connected to the negative electrode of the DC power supply VDD. Is done. The first control unit 111 is connected to each gate of the switch elements Q1 to Q4. The source of the switch element Q1 and the drain of the switch element Q2 are connected, and these connection points are connected to the primary winding T1 of the transformer T via an inductor Lr and a capacitor Cr that form a resonance circuit. One end is connected. The source of the switch element Q3 and the drain of the switch element Q4 are connected, and the other end of the primary winding T1 of the transformer T is connected to these connection points.

  Next, the configuration of the secondary side of the transformer T will be described. The drain of the switch element Q6 is connected to one end of the first secondary winding T2 of the transformer T. The other end of the first secondary winding T2 of the transformer T is connected to one electrode of the capacitor C1, one end of the load Load, and one end of the second secondary winding T3 of the transformer T. . The other end of the second secondary winding T3 of the transformer T is connected to the drain of the switch element Q5. The other electrode of the capacitor C1 and the other end of the load Load are connected to the source of the switch element Q5 and the source of the switch element Q6. The second controller 112 is connected to the gates of the switch elements Q5 and Q6.

[Operation of Resonant Type Converter 100]
In resonant converter 100 having the above configuration, each of switching elements Q1 to Q4 is controlled by first control unit 111 so that switching elements Q1 and Q4 are in an on state and switching elements Q2 and Q3 are in an off state. Periods and periods in which the switch elements Q1 and Q4 are in the off state and the switch elements Q2 and Q3 are in the on state are alternately provided. According to this, the resonance current by the resonance circuit composed of the inductor Lr and the capacitor Cr flows from one end of the primary winding T1 of the transformer T to the other end, or from the other end of the primary winding T1 of the transformer T. Or flow to one end. When a current flows through the primary winding T1 of the transformer T, an electromotive force is generated in the first secondary winding T2 and the second secondary winding T3 of the transformer T.

  Further, the resonant converter 100 controls the switch elements Q5 and Q6 constituting the rectifier circuit by the second control unit 112, so that the first secondary winding T2 and the second secondary winding T3 of the transformer T are controlled. Synchronous rectification of the electromotive force generated in Then, the synchronously rectified DC power is smoothed by the capacitor C1 and supplied to one end of the load Load.

FIG. 10 is a diagram showing the relationship between the drain current ID _Q5 of the switch element Q5 and the gate-source voltage VG _Q5 of the switch element Q5 when the load Load is full load. In the present embodiment, when the gate-source voltage VG _Q5 is VGH, the switch element Q5 is turned on, and when the gate-source voltage VG _Q5 is VGL, the switch element Q5 is turned off. Shall be.

First, the second control unit 112 detects a drain current ID _Q5 that is a switch current flowing through the switch element Q5. Next, a control signal is generated according to the detection result, and the generated control signal is supplied to the gate of the switch element Q5, so that when the drain current ID _Q5 is greater than or equal to a predetermined threshold value Ith, the gate-source When the inter-voltage VG _{Q5 is set} to VGH and the drain current ID _Q5 is less than a predetermined threshold Ith, the gate-source voltage VG _{Q5 is set} to VGL. According to this, the switch element Q5 is controlled by the second controller 112 in accordance with the drain current ID _Q5 . Note that the switch element Q6 is also controlled by the second controller 112 in accordance with the drain current ID _Q6 , similarly to the switch element Q5.

JP 2007-274789 A

FIG. 11 is a diagram showing the relationship between the drain current ID _Q5 of the switch element Q5 and the gate-source voltage VG _Q5 of the switch element Q5 when the load Load is light or no load.

The drain currents of the switch elements Q5 and Q6 decrease as the load of the load Load becomes lighter. Therefore, in FIG. 11, the peak value of the drain current ID _Q5 is smaller than that in FIG. 10, and the peak value of the drain current ID _Q5 is substantially equal to the threshold value Ith.

According to this, the detection gain of the drain current ID _Q5 by the second control unit 112 increases, and jitter occurs in the control signal of the switch element Q5. As a result, jitter also occurs in the gate-source voltage VG _Q5 . As a result, there is a possibility that the power supply noise increases or the power supply output cannot be stabilized.

  In view of the above-described problems, an object of the present invention is to provide a resonant converter capable of suppressing an increase in power supply noise and stabilizing a power supply output even at a light load or no load.

The present invention proposes the following items in order to solve the above-described problems.
(1) The present invention is a resonant converter that includes a transformer and supplies DC power to a load, and includes at least one switch element that synchronously rectifies an electromotive force generated in a secondary winding of the transformer, and the switch element And a control means for controlling the switch element by supplying a control signal to the switch element, wherein the control means generates a first pulse in accordance with a current flowing through the switch element or a current equivalent to the current, and the load The second pulse having a smaller pulse width than the first pulse that is generated when is fully loaded is generated at a predetermined timing, and the first pulse and the second pulse are combined to generate the second pulse. A resonant converter characterized by generating a control signal is proposed.

  According to the present invention, one or more switch elements and control means are provided in a resonant converter that includes a transformer and supplies DC power to a load. The electromotive force generated in the secondary winding of the transformer is synchronously rectified by one or more switch elements. Further, the control means supplies the control signal to the switch element to control the switch element. Further, the control means generates a first pulse according to a current flowing through the switch element or a current according to a current flowing through the switch element, and generates a second pulse at a predetermined timing. The control signal is generated by synthesizing two pulses. The pulse width of the second pulse is set to be smaller than the pulse width of the first pulse generated when the load is in the full load state. Note that the current corresponding to the current flowing through the switch element is a current having a correlation with the current flowing through the switch element, for example, the current flowing through the primary side of the transformer.

  Therefore, a control signal generated by synthesizing the first pulse and the second pulse is supplied to one or more switch elements that synchronously rectify the electromotive force generated in the secondary winding of the transformer. Here, assuming that one or more switch elements that synchronously rectify the electromotive force generated in the secondary winding of the transformer are secondary side switch elements, the first pulse is the resonance type converter 100 according to the conventional example shown in FIG. Similarly, it is generated according to the current flowing through the secondary side switch element or the current according to the current flowing through the secondary side switch element. Further, the pulse width of the second pulse is smaller than the pulse width of the first pulse when the load is full load.

  From the above, when the load is full load, the pulse width of the first pulse is larger than the pulse width of the second pulse. Therefore, by controlling the timing of generating the second pulse, the entire second pulse is It can be made to overlap with a part of 1st pulse. According to this, the control signal generated by combining the first pulse and the second pulse is equal to the first pulse. Since the first pulse is generated in the same manner as the control signal generated in the resonant converter 100 according to the conventional example shown in FIG. 9, it is the same as the resonant converter 100 according to the conventional example shown in FIG. The secondary side switch element can be driven.

  On the other hand, when the load is light or no load, the current flowing through the secondary side switching element becomes small as in the resonant converter 100 according to the conventional example shown in FIG. It will occur. Therefore, by making the pulse width of the second pulse larger than the pulse width of the first pulse in which jitter occurs, and controlling the timing of generating the second pulse, the entire first pulse in which jitter occurs is second. It is possible to overlap a part of the pulse. According to this, it is possible to drive the secondary side switching element while preventing jitter from occurring in the control signal generated by combining the first pulse and the second pulse. For this reason, even when the load is light or no load, an increase in power supply noise can be suppressed and the power output can be stabilized.

  (2) The present invention relates to the resonant converter according to (1), wherein the control means is configured to control the first based on a current flowing through the switch element or a current equivalent to the current when the load is in a full load state. A resonant converter that generates two pulses has been proposed.

  According to the present invention, the second pulse is generated by the control means based on the current flowing through the switch element when the load is in the full load state or the current equivalent to this current. Therefore, a pulse having a predetermined pulse width can be generated as the second pulse at a predetermined timing.

  According to the present invention, an increase in power supply noise can be suppressed and a power output can be stabilized even during light load or no load.

It is a circuit diagram of the resonance type converter concerning one embodiment of the present invention. It is a figure for demonstrating the production | generation of the control signal in the said resonance type converter. It is a figure for demonstrating the production | generation of the control signal in the said resonance type converter. It is a figure for demonstrating the production | generation of the control signal in the said resonance type converter. It is a figure for demonstrating the production | generation of the control signal in the said resonance type converter. It is a figure for demonstrating the minimum pulse width and the minimum pulse position. It is a figure which shows the relationship between the output noise level according to the minimum pulse position, and loss. It is a figure which shows the relationship between the output noise level according to the minimum pulse width, and loss. It is a circuit diagram of the resonance type converter which concerns on a prior art example. It is a figure for demonstrating the production | generation of the control signal in the said resonance type converter. It is a figure for demonstrating the production | generation of the control signal in the said resonance type converter.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the constituent elements in the following embodiments can be appropriately replaced with existing constituent elements, and various variations including combinations with other existing constituent elements are possible. Accordingly, the description of the following embodiments does not limit the contents of the invention described in the claims.

[Configuration of Resonant Converter 1]
FIG. 1 is a circuit diagram of a resonant converter 1 according to an embodiment of the present invention. The resonant converter 1 is different from the resonant converter 100 according to the conventional example shown in FIG. 9 in that a second control unit 12 as a control unit is provided instead of the second control unit 112. In the resonant converter 1, the same components as those of the resonant converter 100 are denoted by the same reference numerals, and the description thereof is omitted.

[Operation of Resonant Converter 1]
In the resonant converter 1 having the above configuration, the second control unit 12 first detects the drain currents of the switch elements Q5 and Q6 using a current detection element such as a resistor or a current transformer (not shown). Next, gate pulses PG _Q5 and PG _Q6 as first pulses corresponding to the switching elements Q5 and _Q6 are generated by a first method to be described later, and the switching elements Q5 and PG _Q6 are generated by a second method to be described later. Minimum pulses PMIN _Q5 and PMIN _Q6 as second pulses corresponding to _Q6 are generated. Next, the gate pulse PG _Q5 corresponding to the switch element Q5 and the minimum pulse PMIN _Q5 are combined to generate a control signal for the switch element Q5, which is supplied to the gate of the switch element Q5. In addition, the gate pulse PG _Q6 corresponding to the switch element Q6 and the minimum pulse PMIN _Q6 are combined to generate a control signal for the switch element Q6 and supply it to the gate of the switch element Q6.

<First method>
In the first method, a gate pulse corresponding to the switch element Q5 is generated in accordance with the drain current ID _Q5 of the switch element Q5 in the same manner as the resonant converter 100 according to the conventional example shown in FIG. 9 generates the control signal. PG _Q5 is generated, and a gate pulse PG _Q6 corresponding to the switch element _Q6 is generated according to the drain current ID _Q6 of the switch element Q6.

Specifically, when the drain current ID _Q5 is equal to or greater than the threshold value Ith, the gate pulse PG _Q5 becomes VGH, and when the drain current ID _Q5 is less than the threshold value Ith, the gate pulse PG _Q5 becomes VGL. Further, when the drain current ID _Q6 is equal to or greater than the threshold value Ith, the gate pulse PG _Q6 becomes VGH, and when the drain current ID _Q6 is less than the threshold value Ith, the gate pulse PG _Q6 becomes VGL.

According to this, when the load is full, the peak values of the drain currents ID _Q5 and ID _Q6 are sufficiently larger than the threshold value Ith, as will be described later with reference to FIGS. For this reason, the detection gains of the drain currents ID _Q5 and ID _Q6 do not increase, and no jitter occurs in the gate pulses PG _Q5 and PG _Q6 .

On the other hand, when the load Load is light or no load, the peak values of the drain currents ID _Q5 and ID _Q6 are substantially equal to the threshold value Ith, as will be described later with reference to FIGS. For this reason, the detection gains of the drain currents ID _Q5 and ID _Q6 increase, and jitter occurs in the gate pulses PG _Q5 and PG _Q6 .

<Second method>
In the second method, the minimum pulse PMIN _Q5 corresponding to the switch element _Q5 is generated based on the drain current ID _Q5 of the switch element Q5 when the load Load is full load, and the switch when the load Load is full load is generated. Based on the drain current ID _Q6 of the element Q6, the minimum pulse PMIN _Q6 corresponding to the switch element _Q6 is generated.

Specifically, as will be described later with reference to FIGS. 6 and 7, the load load is unloaded on the basis of the timing at which the drain currents ID _Q5 and ID _Q6 are larger than “0” when the load Load is full load. The minimum pulse position Ts is determined in consideration of the output noise level N and the loss Ploss in the state. As will be described later with reference to FIGS. 6 and 8, the output when the load load is unloaded is based on the timing when the drain currents ID _Q5 and ID _Q6 are larger than “0” when the load load is full load. The minimum pulse width Tw is determined in consideration of the noise level N and the loss Ploss.

According to this, even if the load Load is in a full load state, even if the load Load is in a light load or no load state, the minimum pulse PMIN _Q5 , as will be described later with reference to FIGS. The pulse width of PMIN _Q6 is constant. When the load Load is full load, as will be described later with reference to FIGS. 2 and 3, the entire minimum pulse PMIN _Q5 overlaps a part of the gate pulse PG _Q5 , and the entire minimum pulse PMIN _Q6 is This overlaps a part of the gate pulse PG _Q6 . On the other hand, when the load Load is light or no load, as described later with reference to FIGS. 4 and ₅ , the entire gate pulse PG _Q5 in which jitter occurs overlaps a part of the minimum pulse PMIN _Q5 , and the jitter Thus, the entire gate pulse PG _Q6 generated in this manner overlaps a part of the minimum pulse PMIN _Q6 .

FIG. 2 is a diagram illustrating a procedure for generating a control signal to be supplied to the gate of the switch element Q5 based on the gate pulse PG _Q5 and the minimum pulse PMIN _Q5 when the load Load is full load. FIG. 3 is a timing chart of the drain current ID _Q5 , the gate pulse PG _Q5 , the minimum pulse PMIN _Q5, and the gate-source voltage VG _{Q5 of the} switch element Q5 when the load Load is full load. is there.

As shown in FIGS. 2 and 3, in a state where the load Load is full load, the minimum pulse PMIN _Q5 becomes VGH during a part of the period in which the gate pulse PG _Q5 is VGH, and the entire minimum pulse PMIN _Q5 becomes the gate pulse. It will overlap with part of PG _Q5 . For this reason, the waveform of the gate-source voltage VG _Q5 of the switch element Q5 to which the control signal generated by synthesizing the gate pulse PG _Q5 and the minimum pulse PMIN _Q5 is supplied to the gate is the waveform of the gate pulse PG _Q5 . Is equal to In the load Load is fully loaded, the gate of the switching element Q6 - the waveform of the source voltage _{VG Q6} also, the gate of the switching element Q5 - like the waveform of the source voltage _{VG Q5,} the waveform of the gate pulse _{PG Q6} Is equal to

FIG. 4 is a diagram illustrating a procedure for generating a control signal to be supplied to the gate of the switch element Q5 based on the gate pulse PG _Q5 and the minimum pulse PMIN _Q5 when the load Load is light or no load. FIG. 5 shows the drain current ID _Q5 , the gate pulse PG _Q5 , the minimum pulse PMIN _Q5, and the gate-source voltage VG _{Q5 of the} switch element Q5 when the load Load is light or no load. It is a timing chart.

As shown in FIGS. 4 and 5, when the load Load is light or no load, jitter occurs in the gate pulse PG _Q5 . However, the minimum in pulse PMIN _Q5 Some time is VGH, the gate pulse _{PG Q5} is VGH next occurring jitter, the entire gate pulse _{PG Q5} resulting jitter, overlaps a portion of the minimum pulse PMIN _Q5 It becomes. Therefore, the waveform of the gate-source voltage VG _Q5 of the switch element Q5 to which the control signal generated by combining the gate pulse PG _Q5 and the minimum pulse PMIN _Q5 is supplied to the gate is the waveform of the minimum pulse PMIN _Q5 . Is equal to When the load Load is light or no load, the waveform of the gate-source voltage VG _Q6 of the switch element _{Q6 is} the same as the waveform of the gate-source voltage VG _Q5 of the switch element Q5. _It becomes equal to the waveform of _Q6 .

<Minimum pulse>
The minimum pulse generated by the above-described second method will be described in detail below with reference to FIGS.

FIG. 6 is a diagram for explaining the minimum pulse width Tw and the minimum pulse position Ts. Here, the minimum pulse width Tw indicates a period in which the minimum pulse PMIN _Q5 is VGH, and the minimum pulse position Ts indicates that the drain current ID _Q5 is larger than “0” when the load is full. To the minimum pulse PMIN _Q5 to VGH. Note that the period in which the minimum pulse PMIN _Q6 is VGH and the period in which the minimum pulse PMIN _Q5 is VGH are the same. Also, the time from when the drain current ID _Q6 becomes larger than “0” until the minimum pulse PMIN _Q6 becomes VGH and the time after the drain current ID _Q5 becomes larger than “0” until the minimum pulse PMIN _Q5 becomes VGH. The time of is assumed to be equal.

  FIG. 7 is a diagram illustrating a relationship between the output noise level N and the loss Ploss when the minimum pulse position Ts is changed in a state where the load Load is not loaded. Here, the output noise level N indicates the degree of noise included in the DC power supplied from the resonant converter 1 to the load Load, and is a value that increases as the degree increases. The loss Ploss is a loss of the resonant converter 1.

  As shown in FIG. 7, as the minimum pulse position Ts increases, the output noise level N when the load load is no load decreases, and the loss Ploss when the load load is no load increases. For this reason, it is preferable to set the optimum minimum pulse position Ts in consideration of the relationship between the output noise level N and the loss Ploss when the load Load is unloaded.

  FIG. 8 is a diagram showing the relationship between the output noise level N and the loss Ploss when the minimum pulse width Tw is changed in the no load state.

  As shown in FIG. 8, as the minimum pulse width Tw increases, the output noise level N when the load load is unloaded decreases, and the loss Ploss when the load load is unloaded increases. For this reason, it is preferable to set the optimum minimum pulse width Tw in consideration of the relationship between the output noise level N and the loss Ploss when the load Load is unloaded.

  According to the above resonant converter 1, the following effects can be obtained.

When the load Load is full load, the entire minimum pulse PMIN _Q5 overlaps a part of the gate pulse PG _Q5 . For this reason, the waveform of the gate-source voltage VG _Q5 of the switch element Q5 to which the control signal generated by synthesizing the gate pulse PG _Q5 and the minimum pulse PMIN _Q5 is supplied to the gate is the waveform of the gate pulse PG _Q5 . Is equal to The waveform of the gate-source voltage VG _Q6 of the switch element Q6 is also equal to the waveform of the gate pulse PG _Q6 , similarly to the waveform of the gate-source voltage VG _Q5 of the switch element Q5. Since each of the gate pulses PG _Q5 and PG _Q6 is generated in the same manner as the control signal generated in the resonance type converter 100 according to the conventional example shown in FIG. 9, the resonance according to the conventional example shown in FIG. Similarly to the type converter 100, the switch elements Q5 and Q6 can be driven.

On the other hand, when the load Load is light or no load, jitter occurs in the gate pulse PG _Q5 , but the entire gate pulse PG _{Q5 in} which the jitter occurs overlaps a part of the minimum pulse PMIN _Q5 . Therefore, the waveform of the gate-source voltage VG _Q5 of the switch element Q5 to which the control signal generated by combining the gate pulse PG _Q5 and the minimum pulse PMIN _Q5 is supplied to the gate is the waveform of the minimum pulse PMIN _Q5 . Is equal to The waveform of the gate-source voltage VG _Q6 of the switch element Q6 is also equal to the waveform of the minimum pulse PMIN _Q6 , similarly to the waveform of the gate-source voltage VG _Q5 of the switch element Q5. According to this, it is possible to drive the switching elements Q5 and Q6 while preventing the occurrence of jitter in the gate-source voltages VG _Q5 and VG _Q6 . For this reason, even when the load is light or no load, an increase in power supply noise can be suppressed and the power output can be stabilized.

  The present invention is not limited to the above-described embodiment, and various modifications and applications can be made without departing from the gist of the present invention.

For example, in the above-described embodiment, the gate pulses PG _Q5 and PG _Q6 and the minimum pulses PMIN _Q5 and PMIN _Q6 are generated based on the drain currents of the switch elements Q5 and Q6. You may produce | generate based on the electric current according to each drain current of element Q5, Q6. Specifically, the drain current of the switch element Q5 and the current flowing through the second secondary winding T3 of the transformer T are substantially equal, and the drain current of the switch element Q6 and the first secondary winding of the transformer T The current flowing through the line T2 is substantially equal. Further, there is a correlation according to the turn ratio between the current flowing in each of the first secondary winding T2 and the second secondary winding T3 of the transformer T and the primary winding T1 of the transformer T. There is a relationship. From the above, for example, the gate pulses PG _Q5 and PG _Q6 and the minimum pulses PMIN _Q5 and PMIN _Q6 may be generated based on the current flowing through the primary winding T1 of the transformer T.

DESCRIPTION OF SYMBOLS 1,100; Resonance type converter 111; 1st control part 12, 112; 2nd control part Load; Load Q1-Q6; Switch element T;

Claims (2)

A resonant converter that includes a transformer and supplies DC power to a load,
One or more switch elements for synchronously rectifying an electromotive force generated in the secondary winding of the transformer;
Control means for controlling the switch element by supplying a control signal to the switch element,
The control means generates a first pulse according to a current flowing through the switch element or a current corresponding to the current, and a pulse compared to the first pulse generated when the load is in a full load state. A resonant converter, wherein a second pulse having a small width is generated at a predetermined timing, and the control signal is generated by combining the first pulse and the second pulse.   The said control means produces | generates a said 2nd pulse based on the electric current which flows into the said switch element, or the electric current according to the said electric current, when the said load is the state of a full load. Resonant type converter.

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