JP5366297B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving reverse recovery characteristics and reverse recovery resistance of a diode provided side by side with an IGBT and connected in antiparallel to the IGBT on the same semiconductor substrate without deterioration of characteristics of the IGBT, and also improving, in particular, so as to reduce reverse recovery loss. <P>SOLUTION: In the semiconductor device, p-type regions on which a metal electrode is placed via an insulating film and which has high impurity concentration in a gate pad electrode region, are formed into a structure in which the regions are mutually connected on a surface by ion implantation and thermal diffusion from a plurality of isolated surface regions. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to an improvement in a semiconductor device in which an IGBT and a free wheeling diode (hereinafter abbreviated as FWD) connected in reverse parallel to the IGBT are provided on the same semiconductor substrate.

  The inverter circuit that converts direct current into alternating current as shown in FIG. 12 includes a converter unit 100, a brake unit 200, and an inverter unit 300. The inverter unit 300 has a configuration in which an IGBT (Insulated Gate Bipolar Transistor) 301 and an FWD (Free Wheeling Diode) 302 are connected in antiparallel. Usually, the operation of the FWD 302 used in the inverter unit 300 includes a reverse recovery mode for recovering the reverse voltage blocking state from the forward energization state. At this time, since element breakdown is most likely to occur, the FWD 302 is required to have a reverse recovery resistance that makes it difficult to cause element breakdown, and further, it is also required to have a low reverse recovery loss.

  On the other hand, from the viewpoint of downsizing and cost reduction, an integrated reverse conducting IGBT in which an IGBT and an FWD are provided on the same semiconductor substrate has been studied. Some such integrated reverse conducting IGBTs (RC-IGBTs) have already been announced. However, this integrated reverse conducting IGBT is generally manufactured by designing the optimal structure so that the optimal characteristics can be obtained for each of the IGBT and FWD as separate devices due to problems in the manufacturing process. It is extremely difficult. Still, a patent document has already been published for an integrated reverse conducting IGBT that can improve the recovery (reverse recovery) characteristics of the FWD without degrading the characteristics of the IGBT as much as possible (see, for example, Patent Document 1 below). ).

Also, patent documents describing IGBTs, MOSFETs, and the like in which the p ⁺ region immediately below the gate pad electrode is comb-like are disclosed (for example, see Patent Document 2 below). Furthermore, a patent document that describes an IGBT that can ensure a drain-source breakdown voltage without providing a high-concentration p ⁺ region directly under the gate pad electrode is also disclosed (see, for example, Patent Document 3 below). ).

As shown in the cross-sectional view of the main part of the chip shown in FIG. 11, the conventional reverse conducting IGBT chip 50 incorporates an IGBT part 51 and an antiparallel-connected FWD part 52 in the same semiconductor substrate. There are a plurality of parallel trenches 56 that reach the n ⁻ substrate region (n ⁻ drift layer) 55 through the p ⁻ channel formation region 54 from the surface of the n ⁺ emitter region 53 on the substrate surface side (FIG. 11). As shown in FIG. 11, a polysilicon gate electrode 58 is buried in these trenches 56 with a gate insulating film 57 interposed therebetween. The surface layer of the p ⁻ channel forming region 54 between the plurality of trenches 56 includes the n ⁺ emitter region 53 in contact with the trench 56 and a p ⁺ contact region 54 a for making ohmic contact with the aluminum electrode. In order to insulate the polysilicon gate electrode 58 embedded in the trench 56, an interlayer insulating film 59 is formed on the substrate surface. The interlayer insulating film 59 is provided with an opening, and an emitter (anode) electrode 60 such as aluminum is in ohmic contact with the exposed surfaces of the n ⁺ emitter region 53 and the p ⁺ contact region 54a.

The p ^- surrounding the channel forming region 54, the peripheral portion of the reverse conducting IGBT chip 50 the p ^- and deep high impurity concentration high-concentration p ⁺ region 65a than the channel formation region 54, further pressure-resistant structure portion surrounding the outer 66 includes a guard ring 67 formed by ion implantation and thermal diffusion at the same time as the high concentration p ⁺ region 65a. The emitter (anode) electrode 60 is in contact with the high concentration p ⁺ region 65 a through an opening formed in the interlayer insulating film 59. The high-concentration p ⁺ region 65a and the guard ring 67 is p ^- what is the deep diffusion layer from the channel formation region 54, p ^- from the pn junction of the channel forming region 54, when the depletion layer extends when a reverse bias This is to reduce the electric field concentration by increasing the radius of curvature at the end of the pn junction where electric field intensity concentration is likely to occur. Furthermore, by reducing the resistance of the residual holes that tend to concentrate on the peripheral portion of the active region 69 through which the main current flows at the time of OFF, the reverse recovery current is concentrated on the peripheral portion of the pn main junction. It is for suppressing.

A polysilicon gate electrode 58 in the trench 56 in the active region 69 is formed on the surface of the high-concentration p ⁺ region 65a outside the active region 69 via an interlayer insulating film 59 and an aluminum gate. It is connected to the electrode wiring 68a and collected on a wide aluminum gate pad electrode 68 (see FIG. 7) on the substrate surface. Immediately below the aluminum gate pad electrode 68, the high-concentration p ⁺ region 65a formed on the substrate surface layer with the interlayer insulating film 59 interposed therebetween is also wide as shown in the plan view of FIG. It is formed wide corresponding to. FIG. 2 is a plan view showing a planar pattern of the high concentration p ⁺ region of the integrated reverse conducting IGBT chip.

On the other hand, on the back side of the substrate facing the surface of the active region 69 through which the main current flows, the thickness of the n ⁻ drift layer 55 is reduced by suppressing the depletion layer extending from the pn junction when the IGBT is turned off and during reverse biasing. As shown in the plan view of the back side of the chip in FIG. 9, the p ⁺ collector regions 62 and the n ⁺ cathode regions 63 are alternately provided in a parallel pattern with the n-type field stop layer 61 interposed therebetween. Furthermore, a collector (cathode) electrode 64 that is in common contact with both of these regions is provided.

In the conventional reverse conducting IGBT described above, the holes injected from the anode side during the forward operation of the FWD when the IGBT is off, the outer peripheral portion of the active region 69 where the extraction of the holes is particularly likely to concentrate during reverse recovery. The high-concentration p ⁺ region 65a provided in the region can be easily extracted effectively, and the recovery characteristics can be improved.

JP 2007-214541 A (summary) Japanese Patent No. 3391715 (claim 1) JP 2008-85188 A (FIGS. 8 and 9)

However, in the integrated reverse conducting IGBT described in Patent Document 1, the configuration of the gate electrode wiring 68a shown in FIG. 11 and the gate pad electrode 68 (not shown) (see FIG. 7) is not particularly specified. The gate pad electrode 68 having a large area necessary for connecting the gate electrode and the external conductor is required. Further, in order to ensure the RBSOA (safe operation area) of the IGBT immediately below the gate pad electrode 68, it is preferable that the extraction of residual carriers (holes) is not concentrated as described above. A high-concentration p ⁺ region 65a is provided via the interlayer insulating film 59 and connected to the anode electrode.

The reason why when the high concentration p ⁺ region 65a is provided, the concentration of the extraction of residual carriers in the p ⁻ channel formation region (p-type anode diffusion region) 54 can be suppressed will be described. When a high-concentration p ⁺ region 65a connected to the emitter (anode) electrode 60 is provided immediately below the gate pad electrode 68, a high-concentration hole is removed from the high-concentration p ⁺ region 65a during forward operation of the FWD. Injection occurs. Next, when the FWD is reverse-biased, excess minority carriers (holes) and majority carriers (electrons) generated by the conductivity modulation remaining in the n ⁻ drift layer 55 undergo n ⁻ A depletion layer spreads in the drift layer 55. When the depletion layer is fully expanded, the voltage is blocked. This process is called reverse recovery. The aforementioned carrier sweeping process at the time of reverse recovery is macroscopically referred to as reverse recovery current, and is a state in which a transient current flows despite reverse bias. This reverse recovery current has a higher peak current value (also called hard recovery) as the current reduction rate at the time of transition from the forward direction to the reverse direction increases.

In addition, this current is applied to the p ⁻ channel formation region in which electric field concentration of reverse bias is likely to occur when minority carriers (holes) are extracted (or swept out) from the anode electrode on the negative electrode side during reverse bias. p-type anode diffusion region) is concentrated on the curvature portion of the peripheral portion of 54, and it is known that the current density is increased at this portion and causes breakdown (especially when the current reduction rate during the forward / reverse transition described above is large). Yes. In this phenomenon, since the peripheral shape of the p ⁻ channel formation region (p-type anode diffusion region) 54 has a curvature, the equipotential lines tend to become dense, and the main current generally flows in FWD. This is because minority carrier extraction (sweeping) spreading under the pressure-resistant structure portion provided in the surface layer of the outer peripheral portion surrounding the p ⁻ channel formation region (p-type anode diffusion region) 54 is almost concentrated on this portion. . Therefore, as described above, the high-concentration p ⁺ region 65a having a resistance smaller than that of the p ⁻ channel formation region (p-type anode diffusion region) 54 and a large curvature radius so as to have a function of relaxing the concentration of the reverse recovery current. Is provided and connected to the anode electrode.

As for the magnitude of the reverse recovery current, the reverse recovery current increases as the accumulation amount of excess minority carriers on the collector side of the n ⁻ drift layer 55 increases, and it tends to be a hard recovery waveform. In this respect, the reverse conducting IGBT described in Patent Document 1 has room for further improvement.

  The present invention has been made in view of the above points, and the object of the present invention is the reverse of the reverse recovery characteristics of the reverse parallel connected diodes provided on the same semiconductor substrate without degrading the characteristics of the IGBT. It is an object to provide a semiconductor device that can be improved not only to improve the recovery tolerance, but also to reduce the reverse recovery loss.

According to the present invention, on one main surface of the n conductivity type semiconductor substrate, a p-type conductivity of the channel forming region, and the n conductivity type emitter region formed in the channel formation region surface, and said emitter region surface An emitter electrode commonly in ohmic contact with the surface of the channel formation region; and a gate electrode stacked on a surface of the channel formation region sandwiched between the surface of the emitter region and the surface of the semiconductor substrate via a gate insulating film and the active region, wherein a gate electrode is substantially the same potential, the channel formation region is electrically connected to the emitter electrode via, p conductivity type region of high impurity concentration than before Eat Yaneru formation region surface is provided via an insulating film, and the gate pad electrode region for placing a metal electrode for connecting the gate external conductors, said active territory with the gate pad electrode area Ohmic contact periphery and a pressure-resistant structure portion surrounding in a ring shape, the main surface side region of at least the active region p-type conductivity said other and the collector region of which is selectively formed on the other main surface side region facing the with IGBT circuit comprising a collector electrode, and has the active region n-type conductivity region on the other major surface region facing formed selectively alternating the front Kiko collector region, the n conductivity type placing a collector electrode that is in ohmic contact with the area cathode electrode, a semiconductor device and a diode unit to the emitter electrode and the anode electrode, an said gate pad electrode region, the metal electrode through the insulating film the p conductivity type region of high impurity concentrations are, are the structures linked to each other by surface by ion implantation and thermal diffusion from the plurality of separation surface region of said plurality separation Surface area, the object of the present invention is achieved by a semiconductor device is a comb-like surface shape having a stripe-shaped portion extending in a direction toward the outer periphery from the active region.

In the semiconductor device of the present invention, the high concentration p ⁺ region provided with the interlayer insulating film directly under the gate pad electrode has a function of extracting a residual hole at the time of reverse recovery necessary for securing the RBSOA of the IGBT. ,necessary. However, as a result, reverse recovery loss increases. In order to reduce this reverse recovery loss, it is necessary to reduce the hole injection amount during the forward operation of the FWD. Therefore, by forming the p ⁺ region immediately below the gate pad electrode by ion implantation from each surface pattern of the parallel stripe region or interstitial region instead of the entire surface directly below, the entire p ⁺ region immediately below the gate pad electrode is formed. The hole concentration is reduced to suppress reverse recovery current and loss. However, the p ⁺ region immediately below the gate pad electrode in the parallel stripe shape or interstitial region is a pattern at the time of ion implantation, and the diffusion region can be expanded by applying a thermal diffusion treatment. For example, if the stripe width and interval of the ion implantation region pattern are set to about 5 μm, parallel stripe patterns can be brought into contact with each other on the surface due to the expansion of the region due to thermal diffusion. As a result, not only can reverse recovery loss be reduced, but also RBSOA (safe operation area) tolerance can be ensured.

  According to the present invention, not only the reverse recovery characteristics and reverse recovery tolerance of the reverse parallel connection diode formed on the same semiconductor substrate are improved, but also the reverse recovery loss is reduced. A semiconductor device that can be improved to be small can be provided.

It is a top view which shows each different plane pattern (a), (b) of the high concentration p ^<+> area ^| region of the integrated reverse conduction type IGBT chip concerning the semiconductor device of the present invention. It is a top view which shows the plane pattern of the high concentration p ^<+> area | region of the conventional integrated reverse conduction type IGBT chip. It is a reverse recovery current waveform figure which compares and shows the reverse recovery current of this invention and the conventional integrated reverse conduction type IGBT chip. It is sectional drawing corresponding to the B-B 'line | wire of the said FIG.1 (b). It is principal part sectional drawing of the semiconductor substrate for every main manufacturing processes for demonstrating the manufacturing method of reverse conduction | electrical_connection IGBT of the pressure | voltage resistant 600V concerning this invention. It is sectional drawing corresponding to the A-A 'line of the said Fig.1 (a). It is a top view which shows the pattern of the outermost surface of the integrated reverse conduction type IGBT chip concerning the semiconductor device of the present invention. FIG. 8 is a plan view showing a conventional surface pattern excluding an aluminum electrode and an interlayer insulating film from FIG. 7. It is a top view which shows the pattern of the n ^<+> area ^| region and p ^<+> area ^| region formed in the back surface side substrate surface layer except the collector (cathode) electrode of the back surface side of this invention and the conventional integrated reverse conduction type IGBT chip | tip. It is principal part sectional drawing of the integrated reverse conduction type IGBT chip concerning the semiconductor device of the present invention. It is principal part sectional drawing of the conventional integrated reverse conduction type IGBT chip. It is an inverter circuit diagram which converts general direct current into alternating current.

FIGS. 1A and 1B are plan views showing different planar patterns of high-concentration p ⁺ regions of an integrated reverse conducting IGBT chip according to the semiconductor device of the present invention. FIG. 3 is a reverse recovery current waveform diagram comparing the reverse recovery current of the present invention and the conventional integrated reverse conduction type IGBT chip. 4 and 6 are cross-sectional views corresponding to the line BB ′ in FIG. 1B and the line AA ′ in FIG. In each cross-sectional view, however, a metal electrode not shown in FIG. 1 is placed on the surface of the high concentration p ⁺ region via an oxide film. FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate for each main manufacturing process for explaining a method of manufacturing a reverse conducting IGBT having a withstand voltage of 600 V according to the present invention. FIG. 7 is a plan view showing an outermost surface pattern of the integrated reverse conducting IGBT chip according to the semiconductor device of the present invention. FIG. 8 is a plan view showing a surface pattern according to the present invention, excluding the aluminum electrode and the interlayer insulating film from FIG. FIG. 9 is a plan view showing patterns of the n ⁺ region and the p ⁺ region formed on the back side substrate surface layer excluding the collector (cathode) electrode on the back side of the integrated reverse conducting IGBT chip according to the semiconductor device of the present invention. FIG. FIG. 9 is the same as the plan view of the conventional semiconductor device. FIG. 10 is a cross-sectional view of an essential part of an integrated reverse conducting IGBT chip according to the semiconductor device of the present invention.

  Hereinafter, an integrated reverse conducting IGBT which is an embodiment of a semiconductor device of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.

FIG. 5 is a cross-sectional view of the main part of the integrated reverse conducting IGBT according to the embodiment of the semiconductor device of the present invention after the completion of the integrated reverse conducting IGBT chip according to FIG. 5 and the semiconductor device of the present invention; This will be described in detail with reference to FIG. In FIG. 5A, a high-resistance n-type semiconductor substrate (hereinafter abbreviated as a substrate) having a resistivity of 20 Ωcm to 50 Ωcm is prepared using an FZ or CZ substrate instead of a conventional semiconductor substrate on which an epitaxial layer is deposited. . This high resistance n-type semiconductor substrate becomes the n ⁻ drift layer 55.

In FIG. 5B, a high-concentration p ⁺ region 65 surrounding the periphery of the active region 69 and a breakdown voltage structure surrounding the high-concentration p ⁺ region 65 using an initial oxide film pattern having a thickness of 1.2 μm as a mask. The guard ring 67 (see FIG. 7 and FIG. 8) that constitutes 66 is formed at the same depth and the same impurity concentration. In FIG. 5, the guard ring 67 has a structure that surrounds the high-concentration p ⁺ region 65 in a triple manner, but in FIG. 10, the guard ring 67 shows only one ring. Since both have the deepest diffusion depth from the substrate surface, they are formed first in each region forming step. The ion implantation conditions were an acceleration voltage of 45 Kev, a boron (B) dose of 2 × 10 ¹⁵ / cm ² and a thermal diffusion treatment at 1150 ° C. for 5 hours. The diffusion depth is about 8 μm.

The high-concentration p ⁺ region 65 is a region corresponding to a region immediately below a gate pad electrode 68 (see FIGS. 4, 6, and 7), which will be described later, as indicated by reference numerals 65b and 65c in FIGS. The area is wider than other parts. Here, the width means the distance of the region in the direction crossing the outer periphery of the chip at a right angle toward the center. However, unlike the conventional high-concentration p ⁺ region 65a shown in FIG. 2, the high-concentration p ⁺ regions 65b and 65c corresponding to just below these gate pad electrodes 68 are first striped with a width of 5 μm or less by a photo process. Thus, a comb-tooth pattern or a lattice-like pattern with an interval of 5 μm, which is about the same as the diffusion depth of the high-concentration p ⁺ regions 65b and 65c, is formed. The spacing is set to 5 μm when the diffusion depth is 5 μm, since there is a diffusion spread of about 80% of 5 μm in the direction of the substrate surface from the initial ion implantation region, the adjacent comb-like ion implantation region is on the surface. Then, it is because it contacts reliably. Note that the interval between the comb-like ion implantation regions can be changed within a range where they are in contact with each other on the surface after diffusion. In addition, in FIG. 1B, the lattice-like pattern in FIG. 1B crosses the outer periphery of the chip at a right angle and three small areas are drawn in the direction toward the center, but the number is actually not limited to three.

Thus, according to ion implantation and thermal diffusion from the plurality of comb-like regions and interstitial regions, the comb-like patterns and interstitial pattern regions were separated on the substrate surface by diffusion spreading. Each of the plurality of comb teeth and interstitial patterns has a configuration in which they are connected to each other on the substrate surface as shown in the sectional view of FIG. The high-concentration p ⁺ regions 65b and 65c are structured such that they are connected to each other at such a surface and separated in a deep portion, so that the substrate can be more closely connected to the conventional high-concentration p ⁺ region 65a shown in FIG. Even if the surface has the same area, the total amount of impurities can be reduced. As a result, the hole injection level from the high concentration p ⁺ regions 65b and 65c can be reduced as compared with the case of the high concentration p ⁺ region 65a shown in FIG. 2, and the reverse recovery current is reduced accordingly. In particular, in the case of ion implantation patterns separated in a lattice shape, it is necessary to bring the separation patterns into contact with each other at least on the surface after thermal diffusion. This is because the pattern that is separated in a lattice pattern has no effect of pulling out residual holes during reverse recovery, and the possibility of element breakdown is extremely high.

Thereafter, in the active region 69, the p ⁻ channel formation region 54, the p ⁺ contact region 54a, and the n ⁺ emitter region 53 which are lower in concentration and shallower than the high concentration p ⁺ regions 65b and 65c are formed by the same process as the manufacturing process of the normal IGBT. Etc. are formed by ion implantation and thermal diffusion. A trench 56 reaching the n ⁻ semiconductor substrate (n ⁻ drift layer) 55 through the region 53 from the surface of the n ⁺ emitter region 53 is formed. A gate oxide film 57 covering the trench 56 is formed, a conductive polysilicon layer is deposited, the trench 56 is filled with the conductive polysilicon, and etched back to form a polysilicon gate electrode 58 and a gate lead line (see FIG. (Not shown). Next, an interlayer insulating film 59 covering the substrate surface is formed, and openings for exposing the surfaces of the p ⁺ contact region 54a and the n ⁺ emitter region 53 are formed. Then, as shown in FIG. Aluminum is sputter-deposited on the side and processed into an emitter electrode / anode electrode 60, an aluminum gate pad electrode 68, and the like by a photo process to form a surface side MOS device structure.

In FIG. 5C, after the front surface side of the semiconductor substrate is protected by a protective film (not shown) such as a polyimide film, the back surface side of the semiconductor substrate is ground and this substrate is determined to have a predetermined thickness determined by the withstand voltage (600 V). (70 μm to 120 μm). In FIG. 5D, an n-type field stop layer 61 having an impurity concentration higher than that of the n ⁻ drift layer 55 is formed on the back surface side, and further, as shown in FIG. For example, boron is introduced as a p-type impurity by a method such as ion implantation at a high impurity surface concentration that is shallower than the n-type field stop layer 61 and provides an ohmic contact. Similarly, the resist film is opened in parallel stripes again in a pattern that is alternately arranged with the boron stripe ion implantation regions by a photo process, and this is used as an n-type impurity by a method such as ion implantation. Phosphorus, arsenic, or the like is introduced at a high impurity surface concentration that is higher than an ohmic contact.

Thereafter, as shown in FIG. 5E, a heat treatment at about 400 ° C. is performed to thermally activate the introduced impurities to form a p ⁺ -type collector region 62 and an n ⁺ -type cathode region 63. At this time, since the introduced impurity cannot be activated 100% at this temperature, the activation may be performed by, for example, a laser annealing apparatus if necessary to further increase the impurity concentration. After that, in FIG. 5E, a collector electrode / cathode electrode made of a laminated metal film such as Ti / Ni / Au is formed on the back surface side to complete the reverse conducting IGBT chip 80. At this time, it is preferable to use Ti, Al, or the like, which easily obtains good contact with the n-type region, as the metal that directly contacts the back side substrate surface. FIG. 10 shows an enlarged cross-sectional view of FIG.

As described above, the reverse conducting IGBT of the first embodiment described above has a hole from the entire surface of the high-concentration p ⁺ region 65a immediately below the gate pad electrode, as can be seen from the relationship with the reverse recovery current time (μs) shown in FIG. Compared with a conventional reverse conducting IGBT (chain line) having a high concentration of p ⁺ regions 65b and 65c directly under the gate pad electrode, the total impurity amount is reduced compared to the conventional reverse conducting IGBT (chain line) having a stripe or lattice ion implantation region. The reverse recovery current is small in the conductive IGBT (solid line). Therefore, reverse recovery loss is reduced.

DESCRIPTION OF SYMBOLS 50 Conventional reverse conduction IGBT chip 51 IGBT part 52 FWD part 53 n ⁺ emitter area | region 54 p ^- channel formation area 55 n ^- drift layer 56 Trench 57 Gate insulating film 58 Polysilicon gate electrode 59 Interlayer insulating film 60 Emitter (anode) electrode 61 n-type field stop layer 62 collector region 63 cathode region 64 collector (cathode) electrode 65 p ⁺ region 66 breakdown voltage structure 67 guard ring 68a gate electrode wiring 69 active region 80 reverse conducting IGBT chip

Claims (1)

One main surface of a semiconductor substrate of one conductivity type, a base region of another conductivity type, an emitter region of one conductivity type formed on the surface of the base region, the surface of the emitter region and the surface of the base region in common An active region including an emitter electrode in ohmic contact, and a gate electrode stacked on a surface of the base region sandwiched between the emitter region surface and the semiconductor substrate surface via a gate insulating film;
A said gate electrode and substantially the same potential, the base region is electrically connected to the emitter electrode via the insulating the surface of the opposite conductivity type region of high impurity concentration than the previous Kibe over source region layer via provided, the gate pad electrode region for placing a metal electrode for connecting the gate external conductors,
A breakdown voltage structure surrounding the outer periphery of the gate pad electrode region and the active region in a ring shape, a collector region of another conductivity type selectively formed at least on the other main surface side region facing the active region, and A collector electrode in ohmic contact with the other main surface side region;
An IGBT unit comprising:
Said active region having a selectively one conductivity type regions are alternately formed and before Kiko collector region on the other main surface side region facing the cathode electrode collector electrode in ohmic contact with the one conductivity type region, A diode portion having the emitter electrode as an anode electrode;
In a semiconductor device comprising:
A the gate pad electrode region, said another conductive region of high impurity concentration which the metal electrode is placed over the insulating film, the surface by ion implantation and thermal diffusion from the plurality of separation surface regions Are connected to each other ,
The semiconductor device, wherein the plurality of separation surface regions have a comb-like surface shape having a stripe-shaped portion extending in a direction from the active region toward the outer periphery .

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