JP5344502B2 - Power supply - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply device suitable for a parallel operation. <P>SOLUTION: A cyclic signal corresponding to an output signal of an oscillation circuit is conveyed to a pulse generation circuit via a first signal transmission path and to a first external terminal via a second signal transmission path. The cyclic signal input from the first external terminal is conveyed to the pulse generation circuit via a third signal transmission path. A PWM cycle of a switching power supply circuit is set by a timing signal produced by the pulse generation circuit. A power supply device has a first mode that conveys the cyclic signal corresponding to the output signal of the oscillation circuit via the first signal transmission path and the second signal transmission path and a second mode that conveys the cyclic signal input from the first external terminal via the third signal transmission path. <P>COPYRIGHT: (C)2012,JPO&amp;INPIT

Description

The present invention relates to a switching power supply device, a semiconductor integrated circuit device, and a power supply device. For example, the present invention relates to a technique effective when applied to a switching power supply device that converts a high voltage into a low voltage.

  US Pat. No. 6,559,684 is a switching power supply device. As technical literature on switching power supplies, there is "Fundamentals of Power Electricals Second Edition" pp.439-449 published by KLUWER ACADEMIC PUBLISHERS.

US Pat. No. 6,559,684

KLUWER ACADEMIC PUBLISHERS publication `` Fundamentals of Power Electoronics Second Edition '' pp.439-449

  In recent years, PCs (personal computers) and system control units (memory, CPU, GPU) mounted on servers have increased their operating frequencies year by year in order to improve their processing capabilities, and their power supply voltages are becoming lower. . Both current consumption, which increases due to high-frequency operation, and leakage current, which is generated due to lower voltage, tend to increase. For this reason, the power supply circuit is required to have a high-accuracy power supply voltage, a high-speed response to prevent a drop in the power supply voltage when the load suddenly changes, and a stable operation. In order to meet these demands, the design of power supply circuits has become very difficult.

  FIG. 10 shows a schematic configuration of a step-down switching power supply device of a power supply control system examined prior to the present invention, and FIG. 11 shows an operation waveform diagram thereof. In the voltage control method, since only the output voltage Vout is monitored through the feedback circuit CPS, the feedback loop FB is one, the circuit design is easy, and the error amplifier EA is compared with the ramp (RAMP) waveform having a large amplitude level, which is good. There is an advantage that a sufficient noise margin can be taken. However, there is a problem that it is difficult to stabilize the feedback loop system, and at the same time, it is necessary to reduce the loop gain, so that high-speed response cannot be performed.

  FIG. 12 shows a schematic configuration diagram of a peak current control method studied prior to the present invention, and FIG. 13 shows an operation waveform diagram thereof. In this peak current control method, by monitoring the output voltage Vout and the input current IL / N, there are two feedback loops, such as FB1 and FB2, so that unstable elements of the feedback loop system can be canceled and phase compensation is performed. Becomes easier. For this reason, it is not necessary to drop the loop gain more than necessary, so it can be said that the circuit is suitable for the high-speed load response of the power source. However, since the input current is monitored, highly accurate current detection is required, so that the circuit configuration becomes complicated as compared with the voltage control method. Furthermore, since the output current IL is detected from the switch node of the power supply circuit, it is necessary to cancel unnecessary current information such as spike noise.

  FIG. 14 shows a block diagram of a switching power supply device of a peak current control system studied prior to the present invention. By providing the high-side power MOSFET QM with a MOSFET QS having an area of 1 / N (hereinafter referred to as a sense MOSFET), a current 1 / N times the current flowing through the main MOSFET QM is caused to flow through the sense MOSFET QS. For example, when the ratio between the main MOSFET QM and the sense MOSFET QS is 5000: 1, the sense current is 5 mA when the main current is 25 A. This is detected by the voltage Vs across the sense resistor Rs. In this case, in the non-patent document, a source current operational amplifier as shown in FIG. 15 is used to obtain the sense current with high accuracy by making the source potential of the sense MOSFET and the source of the main MOSFET the same potential.

  In order to obtain the sense current, negative feedback control is performed with an operational amplifier as shown in FIG. 15 so that the source potentials of the main MOSFET QM and the sense MOSFET QS become the same potential. Offset needs to be kept to a minimum. Usually, a CMOS process is used for Q1 and Q2 which are MOSFETs in the differential portion in order to suppress manufacturing variation and to operate at high speed. The MOSFET Q3 connected to the OUT terminal is an LD-MOSFET which is a high breakdown voltage process because a high voltage (for example, 0-16V) is applied between the drain and the source. Since the MOSFET Q3 is a high breakdown voltage process as described above, the Vth becomes higher than that of the CMOS process, and the gate-source voltage varies depending on the sense current value.

  The above offset causes a systematic offset as shown in FIG. Further, since this operational amplifier has a source terminal and a low input impedance, it cannot operate normally unless a bias current is supplied from the sense current. This bias current causes further offset. For example, when the bias current of the operational amplifier is 150 uA and the ratio of the main MOSFET QM and the sense MOSFET QS is 5000: 1, when the current of 0 A flows through the main MOSFET QM, 150 uA that is the bias current to the amplifier already flows through the sense MOSFET QS. Therefore, a current of 150 uA × 5000 = 750 mA flows through the main MOSFET, and the amplifier has a constant offset of 750 mA.

  Therefore, in the above amplifier, the detected current is shifted by about 1 A as shown in the characteristic diagram of FIG. 17 due to the systematic offset and the offset due to the bias current, and this amplifier is required for peak current control in which the accuracy of the output current is required. Not available. Further, since the main current IL flows backward to the power source side at a light load such as no load, the sense current also tries to flow backward. However, since there is no supply source of the reverse current, the amplifier is inactive during this period, so that there is a problem that the response at a light load is delayed.

  Further, both the consumption current that increases due to the high-frequency operation as described above and the leakage current that occurs due to the low voltage tend to increase. For this reason, it has become very difficult to design power supply circuits that meet the requirements for high-accuracy power supply voltage, high-speed response to prevent power supply voltage drop during sudden load changes, and stable operation. We examined the parallel operation of multiple power supply units corresponding to the load current. In such a power supply device, it is necessary to provide a new function for parallel operation.

  An object of the present invention is to provide a switching power supply device that performs stable operation with high-speed response and a semiconductor integrated circuit device suitable for the switching power supply device. Another object of the present invention is to provide a power supply device suitable for parallel operation. Another object of the present invention is to provide a power supply device capable of changing and increasing current supply capability. It is still another object of the present invention to provide a power supply device that achieves high speed response and improved efficiency. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, a capacitor is provided between the output side of the inductor where the output voltage is formed and the ground potential. A current is supplied from the input voltage to the input side of the inductor by the first power MOSFET, and the input side of the inductor is set to a predetermined potential by the second power MOSFET that is turned on when the first power MOSFET is turned off. A PWM signal is formed by the control circuit using the first feedback signal corresponding to the output voltage obtained from the output side of the inductor and the second feedback signal corresponding to the current flowing through the first power MOSFET. The first power MOSFET is composed of a plurality of vertical MOS structure cells, the number of cells is reduced to 1 / N, and a detection MOSFET having a common gate and drain or source on the same semiconductor substrate is provided. Two feedback signals are formed.

  The outline of other representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, a periodic signal corresponding to the output signal of the oscillation circuit is transmitted to the pulse generation circuit through the first signal transmission path, and is transmitted to the first external terminal through the second signal transmission path. A periodic signal input from the first external terminal is transmitted to the pulse generation circuit through a third signal transmission path. The PWM cycle of the switching power supply circuit is set by the timing signal formed by the pulse generation circuit. A first mode for transmitting a periodic signal corresponding to the output signal of the oscillation circuit through the first signal transmission path and the second signal transmission path, and a period input from the first external terminal through the third signal transmission path And a second mode for transmitting a target signal.

  The outline of still another representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a periodic signal corresponding to the output signal of the oscillation circuit is transmitted to the pulse generation circuit through the first signal transmission path in the first mode, and is transmitted to the first external terminal through the second signal transmission path. The periodic signal input from the first external terminal is transmitted to the pulse generation circuit through the third signal transmission path in the second mode. The first external terminals of the first power supply device and the second power supply device in which the PWM cycle of the switching power supply circuit is set by the timing signal formed by the pulse generation circuit are connected. The first power supply device is operated in a first mode, and the second power supply device is operated in a second mode.

  Stable operation is possible with the high-speed response of the switching power supply.

  Parallel operation of multiple power supply devices can be easily performed. The parallel operation allows the current supply capacity to be changed and increased. Noise reduction is easy. Fast response and improved efficiency are possible.

It is a principal part schematic circuit diagram which shows one Example of the switching power supply device which concerns on this invention. FIG. 2 is a circuit diagram illustrating an example of the differential amplifier circuit of FIG. 1. FIG. 3 is a characteristic diagram of an offset voltage and an output voltage Vo with respect to a sense current for explaining the operation of the differential amplifier circuit of FIG. 2. BRIEF DESCRIPTION OF THE DRAWINGS It is a whole block diagram which shows one Example of the switching power supply device which concerns on this invention. It is a whole lineblock diagram showing other examples of a switching power unit concerning this invention. 6 is a waveform diagram for explaining the operation of the slope compensation circuit of FIGS. 4 and 5. FIG. FIG. 6 is another waveform diagram for explaining the operation of the slope compensation circuit of FIGS. 4 and 5. It is a block diagram which shows one Example of the semiconductor integrated circuit device used for the switching power supply device concerning this invention. 1 is an element cross-sectional structure diagram showing one embodiment of a vertical power MOSFET used in the present invention. 1 is a schematic configuration diagram of a step-down switching power supply device of a voltage control system studied prior to the present invention. It is an operation | movement waveform diagram of the switching power supply device of FIG. It is a schematic block diagram of the switching power supply device of the peak current control system examined prior to the present invention. It is an operation | movement waveform diagram of the switching power supply device of FIG. It is a block diagram of the switching power supply device of the peak current control system examined prior to the present invention. FIG. 16 is a circuit diagram illustrating an example of the operational amplifier of FIG. 15. FIG. 16 is a characteristic diagram of an offset voltage and an output voltage Vo with respect to a sense current for explaining the operation of the operational amplifier of FIG. 15. FIG. 16 is a characteristic diagram of a sense current and an output voltage with respect to a main current when the operational amplifier of FIG. 15 is used. FIG. 3 is a block diagram showing an embodiment of an oscillation circuit OSC and a pulse generation circuit PG used in the switching power supply device according to the present invention. FIG. 2 is a waveform diagram for explaining operations of an oscillation circuit OSC and a pulse generation circuit PG in FIG. 1. 1 is a partial schematic circuit diagram showing an embodiment of a switching power supply device according to the present invention. FIG. 21 is a main circuit diagram for explaining the operation of the switching power supply device of FIG. 20; It is operation | movement explanatory drawing of FIG. 1 is an overall schematic circuit diagram showing an embodiment of a switching power supply device according to the present invention. It is a wave form diagram explaining operation | movement of the switching power supply device of FIG. It is a principal part schematic circuit diagram which shows one Example of the switching power supply device of FIG. BRIEF DESCRIPTION OF THE DRAWINGS It is a whole block diagram which shows one Example of the switching power supply device which concerns on this invention. It is a block diagram which shows one Example of the semiconductor integrated circuit device used for the switching power supply device concerning this invention. It is a block diagram which shows one Example of the power supply device which concerns on this invention. It is a block diagram which shows another Example of the power supply device which concerns on this invention. FIG. 30 is an operation waveform diagram of the power supply device of FIG. 29.

In order to explain the present invention in more detail, it will be described with reference to the accompanying drawings.

  FIG. 1 shows a schematic circuit diagram of a main part of an embodiment of a switching power supply device according to the present invention. This embodiment is directed to a so-called step-down switching power supply device that forms an output voltage Vout obtained by stepping down an input voltage Vin. Although not particularly limited, the input voltage Vin is a relatively high voltage such as 7V to 16V, and the output voltage Vout is a low voltage of about 1.2V. In the figure, an example in which the input voltage Vin is 12V is shown.

  The input voltage Vin supplies the current IL from the input side of the inductor L via the high potential side switch MOSFETGH. A capacitor C is provided between the output side of the inductor L and the circuit ground potential GND, and the output voltage Vout is formed by being smoothed by the capacitor C. This output voltage Vout is an operating voltage of a load circuit RL such as a microprocessor CPU. A switch MOSFETGL is provided between the input side of the inductor L and the circuit ground potential GND. The MOSFET GL is turned on when the high potential side switch MOSFET GH is turned off to clamp the counter electromotive voltage generated in the inductor L by setting the midpoint voltage VSWH to the ground potential of the circuit. The switch MOSFETs GH and GL are not particularly limited, but are constituted by N-channel vertical power MOSFETs. As described above, the connection point between the switch MOSFETs GH and GL is connected to the input side of the inductor L.

  In this embodiment, the high potential side switch MOSFETGH is composed of two MOSFETs QM and QS. These two MOSFETs QM and QS are formed in one semiconductor chip CP1. The MOSFET QM is a main MOSFET that forms a current IL as the high potential side switch MOSFET GH. On the other hand, the MOSFET QS is a sense MOSFET that monitors the current IL flowing through the MOSFET QM. These are vertical MOSFETs formed on one semiconductor substrate as will be described later. The area ratio is, for example, N: 1 (for example, 5000: 1). Thus, a current such as IL / N (IL / 5000) is caused to flow by the MOSFETQS. Further, the low potential side switch MOSFET GL is also formed by one semiconductor chip CP2.

  In the MOSFETs QM and QS, the drain and the gate are integrally formed on the semiconductor substrate, so that each has the same voltage. Since these MOSFETs QM and QS operate as source follower output MOSFETs, the source potentials of both MOSFETs QM and QS need to be equal in order to obtain current IL / N corresponding to the above area ratio. The source potentials of the MOSFETs QM and QS are respectively supplied to the positive phase input (+) and the negative phase input (−) of the differential amplifier circuit AMP. The output voltage Vo of the differential amplifier circuit AMP is supplied to the gate of the P-channel MOSFET Q3. The source of the MOSFET Q3 is connected to the source of the MOSFET QS. Although not particularly limited, a diode D and a resistor Rs are provided at the drain of the MOSFET Q3. The resistor Rs forms a voltage signal corresponding to the sense current IL / N of the MOSFET QS and serves as one feedback loop signal for forming a PWM signal.

  In this embodiment, although not particularly limited, bias current sources Ib1 and Ib2 are provided on the source side and the drain side of the MOSFET Q3. These bias current sources Ib1 and Ib2 are not particularly limited, but are constituted by current mirror MOSFETs that operate with a common current so that the same bias current flows. By providing such bias current sources Ib1 and Ib2, the drain voltages of the main MOSFET QM and the sense MOSFET QS can be made equal to flow the sense current accurately even when there is no load where the sense current is almost zero. While maintaining, it is possible to avoid an offset caused by the bias current flowing through the MOSFET Q3 flowing into the resistor Rs.

  Although omitted in the figure, a peak current control method using two feedback loops FB1 and FB2 as shown in FIG. 12 is applied. A PWM signal for controlling the output voltage Vout to a voltage of about 1.2V is formed by the peak current control type PWM generation circuit. That is, the resistor Rs divides the peak value (FB2) of the voltage IL / N corresponding to the sense current as shown in FIG. 13 and the output voltage Vout by a voltage dividing circuit (not shown), and the divided voltage is divided. A PWM signal is formed by a comparison signal with the voltage signal EO (FB1) that is input to the compensation circuit CMS and from which the high-frequency component that is the output of the compensation circuit CMS is removed. The PWM signal is input to the control circuit, and the control of the switch MOSFETs GH and GL is performed by the control circuit via the drivers DV1 and DV2.

  In this embodiment, an N-channel power MOSFET GH (QM) having a low on-resistance and a low Qgd is used as the high potential side switching element to operate as a source follower output circuit. In order to obtain the high voltage BOOT corresponding to the input voltage Vin from the midpoint potential, in other words, the midpoint potential VSWH is lowered by the threshold voltage of the MOSFET GH (QM) to cause loss. In order to prevent this, a booster circuit is provided.

  The booster circuit performs an operation of setting the gate voltage when the MOSFETGH is in an on state to a voltage higher than the threshold voltage with respect to the input voltage Vin. That is, the midpoint is connected to one end of a bootstrap capacitor CB as shown. The other end of the bootstrap capacitor CB is connected to a power supply terminal Vcc such as 5V via a switching element such as a Schottky diode SBD. When the low potential side switch MOSFET GL is in an on state and the high potential side switch MOSFET MOSFET GH is in an off state, the bootstrap capacitor CB is charged up from the power supply terminal Vcc. When the MOSFET GL is turned off and the MOSFET GH (QM) is turned on, the gate voltage is boosted by the charge-up voltage (Vin + Vcc) for the bootstrap capacitor CB with respect to the source side potential of the MOSFET GH. In this example, voltage loss due to the Schottky diode SBD is ignored. The boosted voltage BOOT is used as an operating voltage for the driver DV1, the bias current source Ib1, and the differential amplifier circuit AMP.

  FIG. 2 shows a circuit diagram of an embodiment of the differential amplifier circuit of FIG. P-channel MOSFETs Q1 and Q2 are connected in a differential form. A bias current source Ib3 is provided between the sources of the MOSFETs Q1 and Q2 and the boosted voltage BOOT. The gate of the MOSFET Q1 is connected to the positive phase input terminal (+). The gate of the MOSFET Q2 is connected to the negative phase input terminal (-). N channel MOSFETs Q7 and Q8 in the form of current mirrors are provided as load circuits at the drains of the MOSFETs Q1 and Q2. MOSFET Q7 is formed in a diode form with its gate and drain connected. The gate and drain of the MOSFET Q7 are connected to the drain of the MOSFET Q1. The MOSFET Q8 has a current mirror configuration as described above by commonly connecting the gate and source of the MOSFET Q7. The drain of the MOSFET Q8 and the drain of the MOSFET Q2 are connected to the output terminal OUT to form the output voltage Vo.

  In this embodiment, the output voltage Vo is connected to the gate of the N-channel MOSFET Q4. Although not particularly limited, the boosted voltage BOOT is supplied to the drain of the MOSFET Q4. The source of P-channel MOSFET Q5 is connected to the source of MOSFET Q4. The drain and gate of the MOSFET Q5 are commonly connected to form a diode. A bias current source Ib4 is provided between the drain and gate of the MOSFET Q5 and the ground potential VSS. A P-channel MOSFET Q6 connected in a source follower configuration is provided between the commonly connected sources of the MOSFETs Q7 and Q8 and the circuit ground potential VSS.

The MOSFETs Q1, Q2, Q7, and Q8 constitute a general gate input differential amplifier circuit, and the MOSFETs Q4, Q5, and Q6 constitute a systematic offset cancel circuit. When the gate voltage of the MOSFET Q5 is Va and the drain voltage of the MOSFET Q7 is Vb, the following equation is established.
Va = Vout−Vgs4−Vgs5 (1)
Vb = Va + Vgs7 + Vgs6 (2)
When Ib4 = Ib3 / 2, Vgs4 = Vgs7 and Vgs5 = Vgs6, so Vo = Vb from the above equations (1) and (2). Here, Vgs4 to Vgs7 are gate and source voltages of the MOSFETs Q4 to Q7.

  The output voltage Vo of the differential amplifier circuit is connected to the gate of the MOSFET Q13 as shown in FIG. The positive phase input (+) and the negative phase input (−) of the differential amplifier circuit AMP are connected to the sources of the main MOSFET Q10 and the sense MOSFET Q11. In the differential amplifier circuit AMP, the drain voltages of the differential MOSFETs Q1 and Q2 are equal to each other as Vo = Vb, so that the positive phase input (+) and the negative phase input (−) are equal, and the Ib4 = Ib3 / 2 is satisfied. Therefore, the increase / decrease of the sense current (IL / N) and the influence of Vth of the LD-MOSFET Q13 are eliminated, the systematic offset is canceled, and the differential amplifier circuit AMP has high accuracy as small as 5.3 uV (microvolt) at most. Is achieved.

  In this embodiment, the offset voltage can be reduced to a negligible level of 5.3 uV at most regardless of the increase or decrease of the sense current IL as described above. Further, the output voltage Vo of the differential amplifier circuit AMP can be generated when the main current flowing through the main MOSFET Q10 is near zero amperes. Since the output voltage Vo decreases to compensate for the increase of the gate and source voltage Vgs of the MOSFET Q13 corresponding to the increase of the main current IL, the source potentials of the main MOSFET Q10 and the sense MOSFET Q11 are equalized as described above. The PWM control by the peak current control method with accuracy can be realized.

  As shown in FIG. 3, the offset voltage can be reduced to a negligible level of 5.3 uV at most regardless of the increase or decrease of the sense current IL. Further, the output voltage Vo of the differential amplifier circuit AMP can be generated when the main current flowing through the main MOSFET QM is near zero amperes. Since the output voltage Vo decreases so as to compensate for the increase in the threshold voltage Vgs of the MOSFET Q3 corresponding to the increase in the main current IL, the source potentials of the main MOSFET QM and the sense MOSFET QS are equalized as described above. The PWM control by the peak current control method with accuracy can be realized.

  FIG. 4 shows an overall configuration diagram of an embodiment of the switching power supply device according to the present invention. Although not particularly limited, a portion surrounded by an alternate long and short dash line in the figure is a semiconductor integrated circuit device having a multichip configuration. That is, three semiconductor chips comprising two power MOSFETs and their control circuits as shown by dotted lines are mounted on one package. The high potential side switch MOSFETGH is composed of a MOSFETQ10 corresponding to the main MOSFETQM and a MOSFETQ11 corresponding to the sense MOSFETQS. The area ratio (current ratio) of MOSFETs Q10 and Q11 is set to 5000: 1. The low potential side switch MOSFETGL is constituted by a MOSFETQ12. The source of the MOSFET Q12 is connected to an independent ground terminal PGND in order to reduce the influence of switching noise.

  An input voltage such as about 12V is supplied from the terminal VIN. The voltage at the terminal VIN is connected to the drains of the MOSFETs Q10 and Q11 and also to the power supply circuit REG. The power supply circuit REG receives the input voltage VIN such as 12V and forms an internal voltage such as about 5V. The stabilizing capacitor is connected to the terminal REG5, and an internal voltage corresponding to the power supply voltage Vcc is formed. The internal voltage generated by the power supply circuit REG is supplied to the logic circuit LGC that receives the PWM signal and generates a switch control signal for the high potential side switch MOSFET GH and the low potential side switch MOSFET GL, and the gate of the low potential side switch MOSFET Q12. The operating voltage of the internal circuit such as the driver DV2 that forms the drive signal to be generated and the transistor T1 of the slope compensation circuit to be described later.

  The internal voltage formed by the power supply circuit REG is connected to one end of the bootstrap capacitor CB through the Schottky diode SBD and the terminal BOOT constituting the booster circuit. The other end of the bootstrap capacitor CB is connected to the terminal SW. The terminal SW is connected to the source of the MOSFET Q10 and the drain of the MOSFET Q12, and is connected to the input side of the inductor L. A capacitor C is provided between the other end of the inductor L and the ground potential of the circuit, and an output voltage Vout such as 1.2 V is formed and supplied to a load circuit (not shown) or the like.

  The source of the MOSFET Q11 and the source of the MOSFET Q10 are connected to the input terminals (+) and (−) of the differential amplifier circuit AMP. The differential amplifier circuit AMP comprises the circuit as shown in FIG. 2, and operates so as to obtain a highly accurate sense current by equalizing the potentials of the sources of the MOSFETs Q10 and Q11. The MOSFET Q3 through which the sense current formed by the MOSFET Q11 flows is constituted by a high breakdown voltage element such as the LD-MOSFET. Bias current sources Ib corresponding to the bias current sources Ib1 and Ib2 shown in FIG. 2 are provided on the source side and the drain side of the MOSFET Q3. The drain of the MOSFET Q3 is connected to the terminal CS via the diode D, and a resistor Rs for converting it into a voltage signal is connected thereto. The voltage signal generated at the terminal CS is used as a signal of the feedback loop FB2.

  In this embodiment, although not particularly limited, a slope compensation circuit SC is provided. The slope compensation circuit SC forms a current signal corresponding to the ramp waveform and supplies it to a resistance element that converts it into a voltage signal via the terminal RAMP. The voltage signal generated at the terminal RAMP is supplied to the emitter of the transistor T1. A voltage signal corresponding to the sense current IL / 5000 (= N) formed by the resistor Rs is level-shifted by the diode D and supplied to the base of the transistor T1. As a result, the voltage signal formed by the resistor Rs and the voltage signal corresponding to the ramp waveform of the slope compensation circuit SC are added to the emitter of the transistor T1 and transmitted to the voltage comparison circuit VC1.

  The output voltage Vout is divided by a voltage dividing circuit including resistors R1 and R2 and input to the terminal FB. The divided voltage input to the terminal FB is input to the error amplifier EA as a signal of the feedback loop FB1. The error amplifier EA extracts a difference from the reference voltage Vref. The output signal of the error amplifier EA is transmitted to the voltage comparison circuit VC1 after the noise component is removed by a compensation circuit including a resistor and a capacitor provided at the terminal EO. The resistor and the capacitor provided at the terminal TRK form a soft start signal and transmit it to the error amplifier EA. That is, control is performed so that the output voltage Vout immediately after power-on rises gently in response to the soft start signal. The oscillation circuit OSC sets the frequency of the PWM signal by setting the frequency by a capacitor or the like connected to the terminal CT. The pulse formed by the oscillation circuit OSC is used as the reset signal RES of the flip-flop circuit FF that forms the PWM signal.

  In the peak current control method shown in FIG. 13, the reset signal RES formed by the oscillation circuit corresponds to the reset pulse RP shown in FIG. 13, and the PWM obtained from the inverted output / Q by resetting the flip-flop circuit FF. Raise the signal. As a result, the high potential side switch MOSFET Q10 is turned on, and the sense current IL / N is detected by the MOSFET Q11 to be a voltage signal. Then, the divided voltage EO of the output voltage Vout is compared with the voltage comparison circuit VC1, and when the voltage corresponding to the IL / N reaches the voltage EO, the flip-flop circuit FF is set, and the PWM signal is set. Change to low level. Accordingly, the high potential side switch MOSFETs Q10 and Q11 are turned off, and the low potential side MOSFET Q12 is switched to the on state instead.

  MOSFETs Q14 and Q13 provided on the emitter side of the transistor T1 perform a switching operation in response to the output signal Q of the flip-flop circuit FF, and operate so that the voltage comparison circuit VC1 has a hysteresis characteristic. That is, when the flip-flop circuit FF is set as described above, the MOSFETs Q14 and Q15 are turned on to forcibly turn off the transistor T1 and lower the input potential of the voltage comparison circuit VC1, and thus the reset signal. The set state is maintained until the flip-flop circuit FF is reset by RES.

  The logic circuit LGC corresponds to a circuit that sets a dead time so that the high-potential side MOSFET Q10 and the low-potential side MOSFET Q12 are not turned on at the same time, and a control voltage transmitted to the high-potential side MOSFETs Q10 and Q11. There is provided a level shift circuit for converting to the signal level.

  As described above, each of the high potential side switch MOSFET GH and the low potential side switch MOSFET GL is formed by one semiconductor chip as indicated by the dotted line in FIG. The other oscillation circuit OSC, error amplifier EA, flip-flop circuit FF, voltage comparison circuit VC1, transistor T1, and slope compensation circuit SC constitute a PWM control circuit for forming a PWM signal, and include a logic circuit LGC, drivers DV1, DV2. The power supply circuit REG, the differential amplifier circuit AMP, and the MOSFET Q3 constitute a driver circuit and are formed by one semiconductor chip.

  FIG. 5 is an overall configuration diagram of another embodiment of the switching power supply device according to the present invention. In this embodiment, a current limiter circuit using a sense current IL / 5000 formed of MOSFET Q11 is added to the embodiment of FIG. The current limiter circuit is realized by using the terminal voltage of the external resistor Rs. That is, the reference voltage VR corresponding to the limiter current and the voltage at which the resistor Rs is formed are detected by the voltage comparison circuit VC2, the flip-flop circuit FF is set through the OR gate circuit G, and the high potential side switch MOSFET Q10, Q11 and Q12 are turned off. Since the sense current generates noise at the time of switching, a blanking circuit BL of about several tens of ns is provided for detecting the sense current in order to prevent malfunction.

  In this embodiment, when the semiconductor integrated circuit devices according to the present invention are connected in parallel, the outputs of the error amplifier EA can be connected to each other for high-accuracy current sharing. In the current share, the output of the error amplifier EA is connected to the external terminal ISH through a diode (base and emitter of the transistor T2). For example, the external terminals ISH of two switching power supply devices are connected to each other. By connecting the external terminals ISH to each other in this way, the output voltage of the error amplifier EA in the two switching power supply devices is made common to operate so as to form a similar output voltage Vout, so that sharing is possible. The output current supply capability can be doubled.

  FIG. 6 is a waveform diagram for explaining the operation of the slope compensation circuit. In the figure, the case without slope compensation and the case with slope compensation are compared and shown. In the figure, when the duty D of the PWM signal is 60%, the dotted line indicates the ripple current waveform in the steady state, and the case where noise such as Δi is input is indicated by the solid line. As shown in the figure, when slope compensation is not performed, the ripple current deviates from the ripple current in the steady state due to the noise current of Δi and oscillates. However, in the case of slope compensation, even if a noise current such as Δi is input, it converges to a steady ripple current waveform by adding a slope waveform. The voltage Veo in the figure corresponds to the voltage EO in FIG.

  FIG. 7 shows another waveform diagram for explaining the operation of the slope compensation circuit. This figure shows a comparison between the case without slope compensation and the case with slope compensation, as in FIG. 6, with the duty D of the PWM signal being 40% as an example. Thus, even during a stable operation with a duty D of 50% or less, the convergence can be improved by performing the slope compensation as compared with the case where the slope compensation is not performed. Such slope compensation is described in detail in Non-Patent Document 1.

  FIG. 8 is a block diagram showing an embodiment of a semiconductor integrated circuit device used in the switching power supply device according to the present invention. In the same figure, pin arrangement and internal configuration are exemplarily shown corresponding to an actual semiconductor integrated circuit device. In this embodiment, a multichip module integrated circuit is provided in which three semiconductor chips are mounted in one package. The semiconductor chip is composed of the high potential side switch MOSFET GH, the low potential side switch MOSFET GL, and the control circuit DRVC. The high potential side switch MOSFETG includes the main MOSFET QM (Q10) and the sense MOSFET QS (Q11). The low potential side switch MOSFETGL is configured by the MOSFETQ12. Then, as indicated by the dotted line in FIG. 5, like the control circuit DRVC, it is composed of a semiconductor chip comprising the drivers DV1, DV2, logic circuit LGC, differential amplifier circuit AMP, MOSFET Q3, power supply circuit REG, and the like. Therefore, in the case of configuring the switching power supply device as shown in FIG. 5, the circuit of the control part that forms the PWM signal in the control circuit is configured in a separate chip semiconductor integrated circuit device provided outside. .

  In the semiconductor integrated circuit device of this embodiment, 1 to 56 external terminals are provided in the peripheral portion of the chip, and signals or voltages as shown in the figure are supplied to each, or external components are connected. A tab pad (TAB PAD) such as an input terminal VIN, an output terminal SW, and CGND is provided on the back side of the semiconductor integrated circuit device. Note that all of the control circuit shown in FIG. 4 or 5 may be incorporated in the control circuit DRVC.

  In general, when the sense MOS system as described above is adopted, the sense MOSFET QS and the main MOSFET QM must have the same structure because the pair ratio is important. Therefore, the power MOSFET is built in the control IC. The device must be a one-chip device, and the sense current cannot be obtained if the controller and the power MOSFET are separated from each other. Further, when the power MOSFET is built in the control IC with a one-chip configuration, the power MOSFET is greatly deteriorated in characteristics as compared with the discrete power MOSFET, so that it cannot be used in a large current application and the current capacity is limited.

  When a vertical MOSFET as in this embodiment is used and a sense MOSFET QS of 1 / N times the same structure as the high-potential main MOSFET QM is provided on one semiconductor chip CP1, both MOSFETs QM generated by the manufacturing process Variations in QS threshold voltage Vgs and on-resistance pair ratio can be minimized. In addition, the change in on-resistance due to a temperature rise also increases and decreases in the same way in the main MOSFET QM and the sense MOSFET QS, so that the sense current has less temperature dependence. Therefore, by combining these MOSFETs QM and QS with a high-precision differential amplifier circuit as shown in FIG. 2, high-precision sense current detection that can be used for peak current control becomes possible.

  FIG. 9 shows an element cross-sectional structure diagram of one embodiment of the vertical power MOSFETs Q10 to Q12 used as the high potential side switch MOSFET and the low potential side switch MOSFET. In the drawing, one MOSFET (cell) is exemplarily shown. The drain N + region is on the lower side of the silicon substrate. The gate electrode covers the entire surface of the N layer sandwiched between the channels to alleviate electric field concentration under the gate. Electrons travel horizontally through the channel from the source consisting of the N + layer to the N layer. At this time, the surface of the N layer becomes an N + accumulation layer due to the positive voltage under the gate electrode, and electrons flow vertically through the entire surface of the N layer through the N + accumulation layer and reach the drain. The power MOSFET of this embodiment is called a vertical structure because of the above-described electron flow.

  A channel and a source of the N + layer are formed in a ring state so as to surround the N layer in the center. The P layer in which the channel and source (N + layer) are formed functions as a cell isolation region. The source, the channel, and the N layer at the center are formed in a hexagonal shape, and a plurality of cells are arranged in a honeycomb shape. For example, the MOSFET Q10 is formed by 20000 cells, and the MOSFET Q11 is formed by four cells. Thus, MOSFETs Q10 and Q11 have an area ratio (current ratio) of 5000: 1. The drains of the MOSFETs Q10 and Q11 are common on the back surface of the substrate, and the gates are commonly connected on the front surface side by a metal wiring layer. The sources of the 20000 cells are connected in common by a metal wiring layer on the surface shown in the figure, and the four cells are also connected to each other by a metal wiring layer. The MOSFET GL has the same structure as the above except that the sense MOSFET does not exist.

  FIG. 18 is a block diagram showing one embodiment of the oscillation circuit OSC and the pulse generation circuit PG used in the switching power supply circuit according to the present invention. The oscillation circuit OSC includes a capacitor C connected to the external terminal CT, constant current sources I1 and I2, a switch S1, and a hysteresis comparator CP. The constant current source I1 supplies a charging current from the power supply voltage REG5 to the capacitor C. When the switch S1 is turned on, a constant current larger than that of the constant current source I1 is flowed toward the ground potential of the circuit, and the capacitor C is discharged by the differential current (I2-I1). The hysteresis comparator CP has a first state in which the voltage at the external terminal CT transitions from the first threshold voltage V1 to a second threshold voltage V2 lower than the first threshold voltage V1, and the first threshold voltage from the second threshold voltage V2. V1 has a second operation state in which the voltage of the external terminal CT transits. For example, when the hysteresis comparator CP is in the first operation state, the output signal CPout is set to a low level to turn off the switch S1. When the hysteresis comparator CP is in the second operating state, the output signal CPout is set to the high level to turn on the switch S1.

  When the voltage of the capacitor C is low and the hysteresis comparator CP is in the second operating state, the switch S1 is turned off, and the capacitor C is charged by the constant current source I1. When the voltage of the capacitor C reaches the first threshold voltage V1, the output signal CPout of the hysteresis comparator CP changes from the low level to the high level to enter the first operation state, and the switch S1 is turned on correspondingly. Put into a state. The capacitor C is switched to the discharging operation by the difference current according to the ON state of the switch S1. When the voltage of the capacitor C reaches the second threshold voltage V2, the hysteresis comparator CP changes the output signal CPout to the low level to be again in the second operation state, and turns off the switch S1. By repeating such an operation, the potential of the capacitor C changes in the range of the first threshold voltage V1 and the second threshold voltage V2.

  The output signal CPout of the oscillation circuit OSC is frequency-divided by a frequency dividing circuit. This frequency divided output f / 2 is input to the pulse generation circuit PG through the contact a side of the switch S3. The frequency-divided output f / 2 is output from the external terminal SYNC through the output buffer OB and the contact a side of the switch S2. The signal from the external terminal SYNC is input to the pulse generation circuit PG through the contact b side of the switch S2-the inverter circuits IN1, IN2 and the contact a side of the switch S4 and the contact b side of the switch S3. The output signal of the inverter circuit IN1 is input to the pulse generation circuit PG through the contact b side of the switch S4 and the contact b side of the switch S3 that bypass the inverter circuit IN2.

  The switches S2 and S3 are controlled by a control signal CT1, and the switch S4 is controlled by a control signal CT2. The control signals CT1 and CT2 are formed by a voltage determination circuit VD. The voltage determination circuit VD determines whether the potential of the capacitor C is higher than the first threshold voltage V1, lower than the second threshold voltage V2, or otherwise, that is, the first threshold voltage. An operation for determining whether the voltage is within the range of the voltage and the second threshold voltage V2 is performed. For example, the potential of the capacitor C is set to an inverter circuit IN3 having a first logic threshold voltage lower than the first threshold voltage V1, and a second logic threshold voltage higher than the second threshold voltage V2. Is supplied to the logic circuit LO, and the control signals CT1 and CT2 are formed by the combination thereof.

  When the potential of the capacitor C is lower than the determination voltage and higher than the second logic threshold voltage, for example, the control signal CT1 is set to the low level to connect the switches S2 and S3 to the contact a side. When the potential of the capacitor C is higher than the first logic threshold voltage or lower than the second logic threshold voltage, the control signal CT1 is set to high level to connect the switches S2 and S3 to the contact b side. Let Then, when the potential of the capacitor C is lower than the second logic threshold voltage, the control signal CT2 is set to the low level to connect the switch S4 to the contact a side, so that the capacitor C is lower than the first logic threshold voltage. When it is high, the control signal CT2 is set to the high level to connect the switch S4 to the contact b side.

  The pulse generation circuit PG is a PWM signal as will be described later in response to a pulse signal input through the signal output path composed of the switches 2 to 4 and the frequency division output f / 2 of the oscillation circuit or the external terminal SYNC. A reset signal RES and a maximum duty signal MXD are formed.

  FIG. 19 is a waveform diagram for explaining operations of the oscillation circuit OSC and the pulse generation circuit PG of FIG. 3V corresponds to the first threshold voltage V1, and 2V corresponds to the second threshold voltage V2. Further, the current of the constant current source I2 is doubled with respect to the current of the constant current source I1. Therefore, the external terminal CT to which the capacitor C is connected becomes a triangular wave that is charged / discharged by a current corresponding to the constant current I1. The output signal CPout of the hysteresis comparator CP becomes low level during the charging operation and becomes high level during the discharging operation. The frequency F is F (Hz) = I1 (A) / [2 × C (F)] × 1V. Here, C (F) is a capacitance value of the capacitor C. 1V is a potential difference between the first threshold voltage V1 and the second threshold voltage V2.

  The output signal f / 2 of the frequency dividing circuit is a pulse obtained by dividing the output signal CPout of the oscillation circuit OSC by 1/2. The pulse generation circuit generates a maximum duty signal MXD when the frequency-divided output f / 2 rises from a low level to a high level, thereby generating a reset pulse RES at a timing delayed by a time T (for example, 50 ns).

  FIG. 20 is a partial schematic circuit diagram of an embodiment of the switching power supply circuit according to the present invention. This embodiment is directed to a so-called step-down switching power supply circuit that forms an output voltage Vout obtained by stepping down an input voltage Vin. Although not particularly limited, the input voltage Vin is a relatively high voltage such as about 12V, and the output voltage Vout is a low voltage of about 1.2V.

  The input voltage Vin is supplied with current from the input side of the inductor L via the high potential side switch MOSFETQ10. A capacitor CO is provided between the output side of the inductor L and the circuit ground potential GND, and a smoothed output voltage Vout is formed by the capacitor CO. This output voltage Vout is the operating voltage of a load circuit Load such as a microprocessor CPU. A switch MOSFET Q12 is provided between the input side of the inductor L and the circuit ground potential VSS. The MOSFET Q12 is turned on when the switch MOSFET Q10 is turned off, and clamps a counter electromotive voltage generated in the inductor L by setting the input side of the inductor L to the ground potential of the circuit. The switch MOSFETs Q10 and Q12 are N-channel power MOSFETs. As described above, the connection point of the switch MOSFETs Q10 and Q12 is connected to the input side of the inductor L1.

  The output voltage Vout is fed back to the PWM generation circuit PWMC as a feedback signal VF. The PWM generation circuit PWMC receives the feedback signal VF, generates a PWM signal for controlling the output voltage Vout to a voltage such as about 1.2 V, and transmits it to the control circuit Log. The control circuit Log forms a high voltage signal and a low potential side signal corresponding to the PWM signal. A dead time is set for both signals so that the MOSFETs Q10 and Q12 are not turned on simultaneously. The high potential side signal is transmitted to the gate of the high potential side switch MOSFET Q10 through a driver DV1 having a level shift (level conversion) function as described later. The low potential side signal is transmitted to the gate of the low potential side switch MOSFET Q12 through the driver DV2.

  FIG. 21 shows a principal circuit diagram for explaining the operation of the switching power supply circuit of FIG. 20, and FIG. 22 shows an operation waveform diagram thereof. As shown in FIG. 21, the current I1 is supplied to the input side of the inductor L through the high potential side switch MOSFET Q10 that is switch-controlled by the PWM signal (pulse width control signal), and the output side of the inductor L and the ground potential of the circuit An output capacitor CO is provided between them to obtain an output voltage Vout. A low potential side switch MOSFET Q12 is provided between the inductor L and the ground potential. The MOSFET Q12 causes the input side of the inductor L when the MOSFET Q10 is turned off to be voltage clamped to the circuit ground potential VSS, and causes the current I2 corresponding to the current IL supplied to the load through the inductor L to flow. The MOSFETs Q10 and Q12 are alternately turned on, and the midpoint voltage VSWH has a waveform that reciprocates between 0 V (VSS) and the input voltage Vin. Stabilization of the output voltage Vout is achieved by adjusting the PWM duty. In FIG. 22, the average current of the current IL flowing through the inductor L becomes equal to the load current Iout.

  FIG. 23 shows an overall schematic circuit diagram of an embodiment of the switching power supply circuit according to the present invention. The PWM generation circuit PWMC of the switching power supply circuit of this embodiment is a peak current control system. In the peak current control system, in addition to the feedback loop that feeds back the output voltage Vout, a feedback loop that monitors and feeds back the input current IL / N is provided, thereby canceling unstable elements of the feedback loop system and performing phase compensation. make it easier. For this reason, it is not necessary to drop the loop gain more than necessary, so it can be said that the circuit is suitable for the high-speed load response of the power source. The PWM generation circuit PWMC of this embodiment generates a PWM signal from the inverted signal / Q of the flip-flop circuit FF. The flip-flop circuit FF is reset by a reset signal RES formed by the pulse generation circuit PG shown in FIG. The comparator receives the output signal EO of the error amplifier EA that receives the feedback signal VF corresponding to the output voltage Vout and the reference voltage Vref, and the signal CS that is formed by sensing the current flowing through the high potential side switch MOSFET Q10. Set by output signal.

  FIG. 24 is a waveform diagram for explaining the operation of the switching power supply circuit of FIG. In such a peak-to-peak current control system, the flip-flop circuit FF is reset by the arrival of the reset signal RES, the PWM signal becomes high level, and the high potential side switch MOSFET Q10 is turned on. A current corresponding to the current I1 of the MOSFET Q10 is passed through the resistor R to form the monitor voltage CS. The comparator inverts the flip-flop circuit FF to change the PWM signal from the high level to the low level when the monitor voltage CS reaches the output signal EO of the error amplifier EA. As described above, the PWM signal is formed by the monitor voltage CS of the current corresponding to the output current I1, so that a high-speed load response can be realized. In response to the PWM signal being changed from a high level to a low level, the high potential side MOSFET Q10 is turned off, and the low potential side MOSFET Q12 is turned on.

  FIG. 25 shows a schematic circuit diagram of a main part of one embodiment of the switching power supply circuit of FIG. The input voltage Vin is the same as that shown in FIG. 23 for the high potential side switch MOSFET 10, the inductor L, the MOSFET Q12, and the drivers DV1 and DV2. The switch MOSFETs Q10 and Q12 are not particularly limited, but are constituted by N-channel vertical power MOSFETs. As described above, the connection point between the switch MOSFETs Q10 and Q12 is connected to the input side of the inductor L. MOSFETs Q10, Q11, and Q12 in the figure correspond to the MOSFETs QM, QS, and GL in FIG. The capacitor CO corresponds to the capacitor C in FIG.

  In this embodiment, a sensing MOSFET Q11 is provided for the high potential side switch MOSFET Q10. These two MOSFETs Q10 and Q11 are formed in one semiconductor chip CP1. The MOSFET Q10 forms a current IL as a high potential side switch MOSFET. On the other hand, the MOSFET Q11 is a sense MOSFET that monitors the current IL flowing through the MOSFET Q10. These are vertical MOSFETs formed on one semiconductor substrate as will be described later. The area ratio is, for example, N: 1 (for example, 5000: 1). Thus, a current such as IL / N (IL / 5000) is caused to flow by the MOSFETQS. Further, the low potential side switch MOSFET Q12 is also formed by one semiconductor chip CP2.

  In the MOSFETs Q10 and Q11, the drain and the gate are integrally formed on the semiconductor substrate, so that each has the same voltage. Since these MOSFETs Q10 and Q11 operate as source follower output MOSFETs, in order to obtain the current IL / N corresponding to the above area ratio, it is necessary to make the source potentials of both the MOSFETs Q10 and Q11 equal. The source potentials of the MOSFETs Q10 and Q11 are respectively supplied to the positive phase input (+) and the negative phase input (−) of the differential amplifier circuit AMP. The output voltage Vo of the differential amplifier circuit AMP is supplied to the gate of the P-channel MOSFET Q13. The source of the MOSFET Q13 is connected to the source of the MOSFET Q11. Although not particularly limited, a diode D and a resistor Rs are provided at the drain of the MOSFET Q13. The resistor Rs forms a voltage signal corresponding to the sense current IL / N of the MOSFET Q11, and this voltage is used as one feedback signal CS for forming a PWM signal.

  In this embodiment, although not particularly limited, bias current sources Ib1 and Ib2 are provided on the source side and the drain side of the MOSFET Q13. These bias current sources Ib1 and Ib2 are not particularly limited, but are constituted by current mirror MOSFETs that operate with a common current so that the same bias current flows. By providing such bias current sources Ib1 and Ib2, the drain voltages of the main MOSFET Q10 and the sense MOSFET Q11 can be made equal to flow the sense current accurately even when there is no load where the sense current is almost zero. While maintaining, it is possible to avoid an offset caused by a bias current flowing through the MOSFET Q13 flowing into the resistor Rs.

  The voltage formed by the resistor Rs is used as the feedback signal CS of the peak current control method using the two feedback loops VF and CS as shown in FIG. A PWM signal for controlling the output voltage Vout to a voltage of about 1.2 V is formed by the peak current control type PWM generation circuit PWMC shown in FIG. That is, the resistor Rs divides the peak value of the voltage CS (IL / N) corresponding to the sense current as shown in FIG. 24 and the output voltage Vout by a voltage dividing circuit (not shown), and the divided voltage and A PWM signal is formed by a comparison signal with the output signal EO of the error amplifier EA that receives the reference voltage. Switch control of the switch MOSFETs Q10 and Q12 is performed by this PWM signal.

  In this embodiment, an N-channel power MOSFET Q10 having a low on-resistance and a low Qgd is used as the high potential side switching element to operate as a source follower output circuit. In order to obtain the high voltage BOOT corresponding to the input voltage Vin from the midpoint potential, in other words, the midpoint potential VSWH is lowered by the threshold voltage of the MOSFET Q10 and a loss occurs. In order to prevent this, a booster circuit is provided.

  The booster circuit performs an operation of setting the gate voltage when the MOSFET Q10 is in an on state to a high voltage equal to or higher than the threshold voltage with respect to the input voltage Vin. That is, the midpoint is connected to one end of a bootstrap capacitor CB as shown. The other end of the bootstrap capacitor CB is connected to a power supply terminal Vcc such as 5V (REG5) via a switching element such as a Schottky diode SBD. When the low potential side switch MOSFET Q12 is on and the high potential side switch MOSFET MOSFET Q10 is off, the bootstrap capacitor CB is charged from the power supply terminal Vcc. When the MOSFET Q12 is turned off and the MOSFET Q10 is turned on, the gate voltage is boosted by the charge-up voltage (Vin + Vcc) for the bootstrap capacitor CB with respect to the source side potential of the MOSFET Q10. In this example, voltage loss due to the Schottky diode SBD is ignored. The boosted voltage BOOT is used as an operating voltage for the driver DV1, the bias current source Ib1, and the differential amplifier circuit AMP.

  The differential amplifier circuit AMP shown in FIG. 25 uses the circuit shown in FIG. The output voltage Vo of the differential amplifier circuit AMP is connected to the gate of the MOSFET Q13. The positive phase input (+) and the negative phase input (−) of the differential amplifier circuit AMP are connected to the sources of the main MOSFET Q10 and the sense MOSFET Q11. In the differential amplifier circuit AMP, the drain voltages of the differential MOSFETs Q1 and Q2 are equal to each other as Vo = Vb, so that the positive phase input (+) and the negative phase input (−) are equal, and the Ib4 = Ib3 / 2 is satisfied. Therefore, the increase / decrease of the sense current (IL / N) and the influence of Vth of the LD-MOSFET Q13 are eliminated, the systematic offset is canceled, and the differential amplifier circuit AMP has high accuracy as small as 5.3 uV (microvolt) at most. Is achieved.

  In this embodiment, the offset voltage can be reduced to a negligible level of 5.3 uV at most regardless of the increase or decrease of the sense current IL as described above. Further, the output voltage Vo of the differential amplifier circuit AMP can be generated when the main current flowing through the main MOSFET Q10 is near zero amperes. Since the output voltage Vo decreases to compensate for the increase of the gate and source voltage Vgs of the MOSFET Q13 corresponding to the increase of the main current IL, the source potentials of the main MOSFET Q10 and the sense MOSFET Q11 are equalized as described above. The PWM control by the peak current control method with accuracy can be realized.

  FIG. 26 is an overall configuration diagram of an embodiment of the switching power supply device according to the present invention. Although not particularly limited, a portion surrounded by a thick alternate long and short dash line in the figure is a semiconductor integrated circuit device having a multichip configuration. That is, two power MOSFETs GH and GL as shown by dotted lines, a control circuit DVRC thereof, and four semiconductor chips including the other are mounted on one package. The high potential side switch MOSFETGH is configured by the main MOSFETQ10 and the sense MOSFET11. The area ratio (current ratio) of MOSFETs Q10 and Q11 is set to 5000: 1. The low potential side switch MOSFETGL is constituted by a MOSFETQ12. The source of the MOSFET Q12 is connected to an independent external ground terminal PGND in order to reduce the influence of switching noise.

  An input voltage such as about 12 V is supplied from the terminal VIN. The voltage at the terminal VIN is connected to the drains of the MOSFETs Q10 and Q11 and is supplied to the power supply circuit REG. The power supply circuit REG receives the input voltage VIN such as 12V and forms an internal voltage (REG5) such as about 5V. The stabilization capacitor is connected to the terminal REG5. The internal voltage (REG5) forms a drive signal supplied to the logic circuit LGC that forms switch control signals for the high potential side switch MOSFETs 10 and Q11 and the low potential side switch MOSFET Q12, and the gate of the low potential side switch MOSFET Q12. Although not particularly limited, the driver DV2 is an operating voltage of an internal circuit such as a slope compensation transistor T1.

  The internal voltage (REG5) is connected to one end of the bootstrap capacitor CB through a Schottky diode SBD and a terminal BOOT constituting the booster circuit. The other end of the bootstrap capacitor CB is connected to the terminal SW. The terminal SW is connected to the source of the MOSFET Q10 and the drain of the MOSFET Q12, and is connected to the input side of the inductor L. A capacitor CO is provided between the other end of the inductor L and the ground potential of the circuit, and an output voltage Vout such as 1.2 V is formed and supplied to a load circuit such as a CPU (not shown). The

  The source of the MOSFET Q11 and the source of the MOSFET Q10 are connected to the input terminals (+) and (−) of the differential amplifier circuit AMP. The differential amplifier circuit AMP comprises the circuit shown in FIG. 2 and operates so as to obtain a highly accurate sense current by making the potentials of the sources of the MOSFETs Q10 and Q11 equal. The MOSFET Q13 through which the sense current formed by the MOSFET Q11 flows is constituted by the LD-MOSFET. Bias current sources Ib corresponding to the bias current sources Ib1 and Ib2 shown in FIG. 25 are provided on the source side and the drain side of the MOSFET Q13. The drain of the MOSFET Q13 is connected to the terminal CS via the blanking circuit BK and the diode D, and a resistor Rs for converting it into a voltage signal is connected thereto.

  The voltage signal generated at the terminal CS is used as the feedback signal CS. Further, the reference voltage VR corresponding to the limiter current and the voltage at which the resistor Rs is formed are detected by the voltage comparison circuit VC2, the flip-flop circuit FF is set through the OR gate circuit G1, and the PWM signal is set to the low level to set the high level. The potential side switch MOSFETs Q10 and Q11 are turned off. Since the sense current generates noise during switching, the blanking circuit BK of about several tens of ns is provided for detecting the sense current in order to prevent malfunction.

  In this embodiment, although not particularly limited, a slope compensation circuit SC is provided. The slope compensation circuit SC forms a current signal corresponding to the ramp waveform and supplies it to a resistance element that converts it into a voltage signal via the terminal RAMP. The voltage signal generated at the terminal RAMP is supplied to the emitter of the transistor T1. A voltage signal corresponding to the sense current IL / 5000 (= N) formed by the resistor Rs is level-shifted by the diode D and supplied to the base of the transistor T1. As a result, the voltage signal formed by the resistor Rs and the voltage signal corresponding to the ramp waveform of the slope compensation circuit SC are added to the emitter of the transistor T1 and transmitted to the voltage comparison circuit VC1.

  The output voltage Vout is divided by a voltage dividing circuit including resistors R1 and R2 and input to the terminal FB. The divided voltage input to the terminal FB is input to the error amplifier EA as the feedback signal VF. The error amplifier EA extracts a difference from the reference voltage Vref. The output signal of the error amplifier EA is transmitted to the voltage comparison circuit VC1 after the noise component is removed by a compensation circuit including a resistor and a capacitor provided at the terminal EO. The resistor and the capacitor provided at the terminal TRK form a soft start signal and transmit it to the error amplifier EA. That is, control is performed so that the output voltage Vout immediately after power-on rises gently in response to the soft start signal. The oscillation circuit OSC sets the frequency of the PWM signal by setting the frequency by the capacitor connected to the terminal CT and the constant currents I1 and I2 as shown in FIG. The pulse formed by the oscillation circuit OSC is supplied to the pulse generation circuit PG to form a reset signal RES of the flip-flop circuit FF and a maximum duty signal MXD as a forced set signal.

  In the peak current control system, the flip-flop circuit FF is reset by the reset signal RES formed by the oscillation circuit OSC, and the PWM signal obtained from the inverted output / Q is raised. As a result, the high potential side switch MOSFET Q10 is turned on, and the sense current IL / N is detected by the MOSFET Q11 to be a voltage signal. The voltage comparison circuit VC1 compares the divided voltage of the output voltage Vout formed by the error amplifier EA with the differential output EO of the reference voltage Vref, and the voltage corresponding to the IL / N reaches the voltage EO. Thus, the flip-flop circuit FF is set to change the PWM signal to a low level. As a result, the high potential side switch MOSFETs Q10 and Q11 are turned off, and the low potential side MOSFET Q12 is switched to the on state instead.

  MOSFETs Q14 and Q13 provided on the emitter side of the transistor T1 perform a switching operation in response to the output signal Q of the flip-flop circuit FF, and operate so that the voltage comparison circuit VC1 has a hysteresis characteristic. That is, when the flip-flop circuit FF is set as described above, the MOSFETs Q14 and Q15 are turned on to forcibly turn off the transistor T1 and lower the input potential of the voltage comparison circuit VC1, and thus the reset signal. The set state is maintained until the flip-flop circuit FF is reset by RES.

  The logic circuit LGC corresponds to a circuit that sets a dead time so that the high-potential side MOSFET Q10 and the low-potential side MOSFET Q12 are not turned on at the same time, and a control voltage transmitted to the high-potential side MOSFETs Q10 and Q11. There is provided a level shift circuit for converting to the signal level.

  In this embodiment, when the switching power supply devices according to the present invention are connected in parallel, the outputs of the error amplifier EA can be connected to each other for high-accuracy current sharing. In the current share, the output of the error amplifier EA is connected to the external terminal ISH through a diode (base and emitter of the transistor T2). For example, the external terminals ISH of two switching power supply devices are connected to each other. By connecting the external terminals ISH to each other in this way, the output voltage of the error amplifier EA in the two switching power supply devices is made common to operate so as to form a similar output voltage Vout, so that sharing is possible. The output current supply capability can be doubled. That is, as will be described later, when a plurality of switching power supply devices are operated in parallel, the current IL flowing through each switching power supply device is distributed to be equal, and the thermal runaway due to the specific switching power supply device bearing a large current It is considered as an important condition for preventing the above.

  Due to the noise current, the ripple current deviates from the steady ripple current and oscillates. However, by providing the slope compensation circuit, even if a noise current is input, the slope waveform is added to converge to a steady ripple current waveform. Such slope compensation is described in detail in Non-Patent Document 1.

  In this embodiment, although not particularly limited, the following monitoring circuit is provided. Although the signal path of the monitoring circuit is omitted, a circuit VLCOC that monitors that the input voltage VIN has dropped below a predetermined voltage and an overcurrent whose output current exceeds a predetermined current are monitored using the feedback signal CS. It consists of a circuit OCLC. These detection signals UVLO and OCL are input to the logic circuit LGC to turn off the output MOSFETs Q10 and Q11 regardless of the PWM signal. Further, these signals UVLO, OCL and the operation control signal ON / OFF of the switching power supply are supplied to the OR gate circuit G2, the MOSFET Q15 is turned on, and the terminal TRK is set to the low level. Thereby, the output of the error amplifier EA is stopped.

  FIG. 27 is a block diagram showing an embodiment of a semiconductor integrated circuit device used in the switching power supply device according to the present invention. In the same figure, pin arrangement and internal configuration are exemplarily shown corresponding to an actual semiconductor integrated circuit device. In this embodiment, a multichip module integrated circuit is provided in which three semiconductor chips are mounted in one package. The semiconductor chip is composed of the high potential side switch MOSFETs Q10 and Q11 (GH), the low potential side switch MOSFET Q12 (GL) and the control circuit DRVC shown in FIG. As shown by the dotted line in FIG. 26, the control circuit DRVC is configured by a semiconductor chip including the drivers DV1 and DV2, the logic circuit LGC, the differential amplifier circuit AMP, the MOSFET Q13, the power supply circuit REG, and the like. Therefore, in the case of configuring the switching power supply device as shown in FIG. 26, the control part circuit that forms the PWM signal in the control circuit is configured in a semiconductor integrated circuit device of another chip provided outside, for a total of four A semiconductor chip is configured as one module.

  In the semiconductor integrated circuit device of this embodiment, 1 to 56 external terminals are provided in the peripheral portion of the chip, and signals or voltages as shown in the figure are supplied to each, or external components are connected. A tab pad (TAB PAD) such as an input terminal VIN, an output terminal SW, and CGND is provided on the back side of the semiconductor integrated circuit device. The entire control circuit shown in FIG. 26 may be incorporated in the control circuit DRVC and mounted in one package.

  In general, when the sense MOS system as described above is adopted, the sense MOSFET Q11 and the main MOSFET Q10 have the same structure because the pair ratio is important. Therefore, the power MOSFET is built in the control IC. The device must be a one-chip device, and the sense current cannot be obtained if the controller and the power MOSFET are separated from each other. Further, when the power MOSFET is built in the control IC with a one-chip configuration, the power MOSFET is greatly deteriorated in characteristics as compared with the discrete power MOSFET, so that it cannot be used in a large current application and the current capacity is limited.

  When a vertical MOSFET as in this embodiment is used and a sense MOSFET Q11 of 1 / N times the same structure as the main MOSFET Q10 on the high potential side is provided on one semiconductor chip CP1 as shown in FIG. Variations in the threshold voltage Vth and on-resistance pair ratio of the MOSFETs Q10 and Q11 caused by the process can be minimized. Further, the change in the on-resistance due to the temperature rise also increases / decreases in the same way in the main MOSFET Q10 and the sense MOSFET Q11, so that the sense current has less temperature dependence. Therefore, by combining these MOSFETs Q10 and Q11 with a high-precision differential amplifier circuit as shown in FIG. 2, high-precision sense current detection that can be used for peak current control becomes possible. As the vertical power MOSFETs Q10 to Q12, those shown in the element structure sectional view of FIG. 9 are used.

  FIG. 28 is a block diagram showing an embodiment of a power supply device according to the present invention. In this embodiment, the terminals SYNC and ISH of the switching power supply devices SWREG1 to SWREGn as shown in FIG. 26 are connected to each other. A capacitor C is connected to a terminal CT of the switching power supply device SWREG1. Thereby, the operation of the oscillation circuit OSC and the voltage determination circuit VD as shown in FIG. 18 makes the synchronization terminal SYNC in the output mode in the switching power supply SWREG1, and the pulse formed by the oscillation circuit OSC of the switching power supply SWREG1. Is output.

  The terminal CT of the switching power supply devices SWREG2 to SWREGn is supplied with the circuit ground potential VSS. As a result, the synchronization terminals SYNC of the switching power supply devices SWREG2 to SWREGn are set to the input mode by the operations of the oscillation circuit OSC and the voltage determination circuit VD as shown in FIG. 18, and are formed by the oscillation circuit OSC of the switching power supply device SWREG1. The received pulse is input to perform a synchronous operation with the switching power supply device SWREG1. Since the terminals ISH shown in FIG. 26 are connected to each other, the switching power supply devices SWREG1 to SWREGn operate so as to distribute the same current. Thereby, the problem that load current concentrates on a specific switching power supply device at the time of parallel operation and output MOSFET is destroyed can be avoided.

  In the power supply device of FIG. 28, synchronous operation can be performed by simply connecting the synchronization terminals SYNC of the switching power supply devices SWREG1 to SWREGn. Thereby, the current supply capability can be increased n times. By performing the synchronous operation as described above, the frequency of noise generated from each of the switching power supply devices SWREG1 to SWREGn becomes the same, so that there is an advantage that measures can be taken toward a specific frequency in order to reduce such noise. .

  FIG. 29 is a block diagram showing another embodiment of the power supply device according to the present invention. In this embodiment, the terminals SYNC and ISH of the switching power supply devices SWREG1 to SWREG2 as shown in FIG. 26 are connected to each other. Similarly to the above, the capacitor C is connected to the terminal CT of the switching power supply device SWREG1. Thereby, the operation of the oscillation circuit OSC and the voltage determination circuit VD as shown in FIG. 18 makes the synchronization terminal SYNC in the output mode in the switching power supply SWREG1, and the pulse formed by the oscillation circuit OSC of the switching power supply SWREG1. Is output.

  The terminal CT of the switching power supply device SWREG2 is supplied with the power supply voltage REG5. As a result, the synchronization terminal SYNC of the switching power supply device SWREG2 is set to the input mode by the operation of the oscillation circuit OSC and the voltage determination circuit VD as shown in FIG. 18, and is formed by the oscillation circuit OSC of the switching power supply device SWREG1. A pulse is input, inverted and supplied to the pulse generation circuit PG to perform a synchronous operation with a phase difference of 180 ° with respect to the switching power supply device SWREG1. In the two switching power supply devices SWREG1 and SWREG2, the clocks are 180 ° out of phase with each other, so a two-phase operation is performed.

  Such a two-phase operation reduces the ripple currents of the load currents IL1 and IL2 flowing through the inductors L1 and L2 provided in the switching power supply devices SWREG1 and SWREG1 as shown in the waveform diagram of FIG. Thus, the ripple voltage of the output voltage Vout and the ripple current of the output smoothing capacitor CO can be reduced. In addition, the apparent operating frequency of the power supply device is doubled, and the power supply response (response to load current) is improved. When the responsiveness is left unchanged with the apparent operating frequency of the power supply device, the operating frequency of each of the switching power supply devices SWREG1 and SWREG2 can be reduced by half. As a result, since the switching loss in each of the switching power supply devices SWREG1 and SWREG2 can be reduced to ½, the efficiency of the power supply device can be improved. Further, since the terminals ISH shown in FIG. 26 are connected to each other, the switching power supply devices SWREG1 and SWREG2 operate so as to distribute the same current. Further, a plurality of units may be operated in two phases in combination with the embodiment of FIG.

  In a power supply apparatus operated in parallel as described above, if a switching power supply apparatus having a relatively small current supply capability is designed as a general-purpose switching power supply apparatus, the above-described power supply apparatus can be used in accordance with the load current of the system in which it is mounted. This can be handled simply by determining the number of parallel operations of the general-purpose switching power supply. As a result, it is possible to standardize the switch power supply, and it is possible to obtain an effect of enabling mass production of the power supply device.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, the power MOSFET may be composed of a lateral MOSFET. By using such a lateral MOSFET, a part of the control circuit may be mounted on one semiconductor chip. The high potential side switch MOSFETGH may be a P-channel MOSFET. In that case, the main MOSFET QM and the sense MOSFET QS are respectively P-channel MOSFETs, which are configured as vertical MOSFETs, and have a common gate and source on the same semiconductor substrate.

  Further, the main MOSFET QM and the drain terminal of the sense MOSFET QS are connected to the respective inputs of the differential amplifier circuit AMP, and the MOSFET receiving the output voltage Vo of the differential amplifier circuit AMP is assumed that the high-potential side switch MOSFET GH is a P-channel MOSFET. Is also a P-channel type. When this is an N-channel type, the high potential side switch MOSFETGH is connected to the input voltage Vin, and the output voltage Vo needs to be driven at a high voltage. This is because the differential amplifier circuit AMP and the MOSFET Q3 need to be formed on the semiconductor substrate on which the high-potential side switch MOSFETGH is formed to increase the breakdown voltage.

  In FIG. 18, there are three ways of setting the synchronization terminal SYNC to the output mode using the terminal CT constituting the oscillation circuit, the input mode, and the pulse phase in the input mode to the in-phase mode and the inversion mode. If there is a margin in the external terminal in addition to the operation switching, an equivalent function can be easily realized by providing a control terminal.

  For example, a ¼ frequency divider is provided at the output part of the oscillation circuit PSC to form four pulses whose phases are different from each other by 90 °, and output or input the four pulses from the four synchronization terminals. It may be added. In this case, one switching power supply is operated as a master, three switching power supplies are operated as a slave operation, and pulses having phases different from each other by 90 ° from the three synchronization terminals are input to the master side. It is also possible to operate in parallel with different pulses at different degrees. In this way, the apparent operating frequency can be quadrupled, or the switching loss can be reduced to ¼.

  The power MOSFET of the switching power supply may be a lateral MOSFET. By using such a lateral MOSFET, a part of the control circuit may be mounted on one semiconductor chip. Further, the high-potential side switch MOSFETs Q10 and Q11 may be P-channel MOSFETs, which are configured as vertical MOSFETs, for example, and have a common gate and source on the same semiconductor substrate.

  The present invention can be widely used in a current sensing step-down switching power supply device, a semiconductor integrated circuit device used therefor, and a power supply device in which it is operated in parallel.

  OSC: oscillation circuit, CP: hysteresis comparator, VD: voltage determination circuit, PG: pulse generation circuit, S1 to S4 ... switch, IN1 to IN4 ... inverter circuit, Q1 to Q15 ... MOSFET, Ib1 to Ib4 ... bias current source, GH ... High-potential side switch MOSFET, GL ... Low-potential side switch MOSFET, DV1, DV2 ... Driver, L ... Inductor, C, CO ... Capacitor, CB ... Bootstrap capacitance, AMP ... Differential amplifier circuit, REG ... Power supply circuit, OSC ... oscillation circuit, DV ... voltage determination circuit, PG ... pulse generation circuit, SC ... slope compensation circuit, FF ... flip-flop circuit, VC1,2 ... voltage comparison circuit, BK ... blanking circuit, G1, G2 ... gate circuit, EA ... error amplifier, LGC ... logic circuit. SWREG1 to SWREGn: Switching power supply device.

Claims (7)

An oscillation circuit;
A first signal transmission path for transmitting a periodic signal corresponding to the output signal of the oscillation circuit to the pulse generation circuit;
A second signal transmission path for transmitting a periodic signal corresponding to the output signal of the oscillation circuit to the first external terminal;
A third signal transmission path for transmitting a periodic signal input from the first external terminal to the pulse generation circuit;
A switching power supply circuit in which a PWM cycle is set by a timing signal formed by the pulse generation circuit,
A first mode for transmitting a periodic signal corresponding to the output signal of the oscillation circuit through the first signal transmission path and the second signal transmission path by an operation control signal; and from the first external terminal through the third signal transmission path A second mode for transmitting the input periodic signal ,
The third signal transmission path includes an operation for transmitting the periodic signal input from the first external terminal in the same phase in the second mode corresponding to the operation control signal, and an operation for transmitting the signal after being inverted. I have a,
The oscillation circuit receives a potential of a first capacitor connected to a second external terminal, and receives an output signal of a voltage comparison circuit having a hysteresis characteristic including a first threshold voltage and a second threshold voltage higher than the first threshold voltage. The charge / discharge operation is switched so that the potential of the first capacitor changes between the first threshold voltage and the second threshold voltage,
A voltage determination circuit;
The voltage determination circuit is
Forming the operation control signal for setting the first mode when the potential of the first capacitor is within the range of the first threshold voltage and the second threshold voltage;
When the potential of the first capacitor is lower than the first threshold voltage, the operation control signal for transmitting the periodic signal input from the first external terminal in the second mode in the same phase is formed in the second mode,
A power supply apparatus for forming the operation control signal for inverting and transmitting a periodic signal input from the first external terminal in the second mode when the potential of the first capacitor is higher than the second threshold voltage. In claim 1 ,
A first power supply device and a second power supply device comprising the oscillation circuit, the first, second and third signal transmission paths and the switching power supply circuit;
The first power supply device operates in a first mode,
The second power supply device operates in a second mode;
A power supply device in which the first external terminal of the first power supply device and the first external terminals of the second power supply device are connected to each other. In claim 2 ,
The switching power supply circuits of the first power supply device and the second power supply device are:
An inductor;
A second capacitor provided between the output side of the inductor and a ground potential;
A first power MOSFET for supplying current from an input voltage to the input side of the inductor;
A second power MOSFET that is turned on when the first power MOSFET is turned off to bring the input side of the inductor to a predetermined potential;
Using the first feedback signal corresponding to the output voltage obtained from the output side of the inductor and the second feedback signal corresponding to the current flowing in the first power MOSFET, the PWM signal is formed, and the output voltage is A control circuit for forming a control signal to be supplied to the gates of the first and second power MOSFETs so as to obtain a desired voltage,
The first power MOSFET is composed of a plurality of cells having a vertical MOS structure,
Consists of cells of the vertical MOS structure, the number of cells is 1 / N relative to the first power MOSFET, and the first power MOSFET and the gate and drain or source are made common on the same semiconductor substrate. A power supply device provided with a detection MOSFET and forming the second feedback signal based on a current flowing through the detection MOSFET. In claim 3 ,
The control circuit is
An error amplifier receiving the first feedback signal and the reference voltage;
A third external terminal corresponding to the output terminal of the error amplifier,
The PWM signal is generated by comparing the output signal of the error amplifier and the second feedback signal,
A power supply apparatus in which the third external terminals are connected to each other and the third external terminal of the error amplifier of the second power supply apparatus becomes an output signal of the error amplifier of the first power supply apparatus. In claim 4 ,
The first power MOSFET and the detection MOSFET have a common gate and drain on the same semiconductor substrate,
A differential amplifier circuit;
A source connected to the source of the detection MOSFET, further comprising a first MOSFET of the opposite conductivity type to the detection MOSFET;
The source of the first power MOSFET and the source of the detection MOSFET are respectively input to the differential amplifier circuit,
The output signal of the differential amplifier circuit is supplied to the gate of the first MOSFET,
A detection current flowing through the detection MOSFET flows on the source side and the drain side of the first MOSFET, and first and second bias current sources for supplying a bias current are provided, respectively.
A power supply apparatus in which a resistance means for converting a sense current into a voltage signal to form the second feedback signal is provided at a drain of the first MOSFET. In claim 5 ,
The differential amplifier circuit is
A first conductivity type first and second differential MOSFET each having a gate connected to the first input and the second input;
A second-conductivity-type input-side MOSFET and an output-side MOSFET that are provided at the drains of the first and second differential MOSFETs and constitute a current mirror load circuit;
A second MOSFET of a first conductivity type provided between the source of the input side and output side MOSFETs and a first operating voltage terminal;
A third MOSFET of the second conductivity type having a gate connected to the drain of the output-side MOSFET connected to the output terminal;
A fourth MOSFET of the first conductivity type having a source connected to the source of the third MOSFET and in the form of a diode;
A first current source provided between a common source of the first and second differential MOSFETs and a second operating voltage terminal;
A second current source for supplying a bias current to the third MOSFET and the fourth MOSFET,
A power supply device in which the second MOSFET and the fourth MOSFET are in the form of a current mirror. In claim 6 ,
The first input receives an output from the source of the first power MOSFET,
The second input receives an output from the source of the detection MOSFET,
The second feedback signal is also used to form an overcurrent detection signal compared with a predetermined voltage,
The overcurrent detection signal is a power supply device that turns off the first power MOSFET and the second power MOSFET.

Images