JP5214014B2 - Signal detection device and imaging system using signal detection device - Google Patents

Description

  The present invention relates to a signal detection device.

A signal detection device that detects a magnetic signal or the like includes a photoelectric conversion device that detects light. Representative types of this photoelectric conversion device include a CCD type and a MOS type photoelectric conversion device. The MOS type photoelectric conversion device includes a pixel portion in which basic cells (pixels) including a photoelectric conversion element such as a photodiode are two-dimensionally arranged, a capacitor portion that holds a signal from the pixel portion, and a signal from the capacitor portion. And a common signal line for outputting to the outside.
Patent Document 1 discloses a configuration in which a plurality of common signal lines are provided and multiplexed. Further, Patent Document 2 discloses a structure in which a capacitor portion is blocked and read out.

JP-A-2005-020484 Japanese Patent Laying-Open No. 2005-086260

By providing a plurality of common signal lines as in Patent Document 1, the data reading speed is improved. However, there may be an offset due to a difference in the common signal line. Further, when a plurality of common signal lines are provided, the number of amplifiers in the output unit is increased, resulting in an increase in power consumption. Further, the number of output terminals required for the photoelectric conversion device may be limited depending on the relationship with the outside of the photoelectric conversion device.
Therefore, the present invention provides a signal detection device in which the number of output terminals can be changed and a reading method thereof. Furthermore, an imaging system using a signal detection device is provided.

The present invention includes a signal generation unit that generates a signal, a plurality of common signal lines from which a signal is output from the signal generation unit and having at least a first common signal line and a second common signal line, and at least a first A plurality of signal lines having a plurality of signal lines and a second signal line; a first switch for controlling conduction between the first common signal line and the first signal line; A plurality of switches including at least a second switch for controlling conduction between the common signal line and the second signal line;
A plurality of amplifier circuit units each including at least a first amplifier circuit to which a signal from the first signal line is input and a second amplifier circuit to which a signal from the second signal line is input; A signal detection device having a circuit unit, wherein the signal detection device includes a switch for controlling conduction between the first common signal line and the second common signal line.

  A signal detection device capable of changing the number of output terminals and a signal reading method thereof are provided.

Schematic circuit diagram of the reading unit of the first embodiment Schematic diagram of photoelectric conversion device for detecting light (A) Equivalent circuit of reading unit, (b) Equivalent circuit of reading unit (A) Driving method in case of parallel reading, (b) Driving method in case of multiplexing Schematic circuit diagram of a reading unit in the second embodiment Example of drive circuit Example of drive circuit Block diagram explaining the imaging system

  The signal reading method of the signal detection apparatus according to the present invention is as follows. First, the signal detection device includes a signal generation unit, a plurality of common signal lines from which the signal is output, and a drive circuit unit. Furthermore, an amplifier circuit unit that amplifies the signal from each common signal line is provided. The amplifier circuit unit has a plurality of amplifier circuits arranged corresponding to the respective common signal lines. At least two common signal lines are connected by a switch. Then, the signal readout method is to amplify and read out signals of the corresponding common signal lines from a plurality of amplifier circuits. Furthermore, this is a signal readout method in which a signal from the connected common signal line is amplified and read from the amplifier circuit corresponding to one common signal line among the common signal lines connected by the switch. Note that an amplifier circuit corresponding to another common signal line connected by a switch may not operate.

  By having such two signal readout methods, the number of output terminals after the amplifier circuit can be changed. In addition, power consumption can be reduced by performing a signal reading method that does not operate the amplifier circuit.

(First embodiment)
In the present embodiment, a photoelectric conversion device using a photoelectric conversion element that detects light will be described as an example. FIG. 1 is a schematic circuit diagram of a reading unit and the like of the signal detection device for explaining the first embodiment. FIG. 2 is an overall schematic diagram of the signal detection apparatus including the reading unit and the like of FIG.

  First, the overall configuration will be described. In FIG. 2, reference numeral 101 denotes a signal generator. The signal generation unit 101 includes a plurality of basic cells (pixels) including photoelectric conversion elements (for example, photodiodes). The pixel includes, for example, a photoelectric conversion element, a transfer transistor that transfers a charge as a signal thereof to a charge holding portion that is an active region, and a reset transistor that sets the potential of the charge holding portion to a reference potential. Furthermore, it has an amplification transistor that constitutes a part of the source follower circuit and outputs a signal based on the potential of the charge holding portion. From such a pixel, a reset signal based on the potential of the charge holding portion that has been set to the reference potential by the reset transistor, and an optical signal based on the charge transferred from the photoelectric conversion element (an optical signal superimposed on the reset signal). Is output.

  Reference numeral 102 denotes a capacitor having a switch for outputting a signal to the line memory and the common signal line. Since it is also a part which reads the signal of a line memory with a switch, it is hereafter called a reading part. The reading unit 102 may include a signal amplification unit such as an amplifier and an AD converter. Reference numeral 103 denotes a drive circuit unit including a horizontal scanning circuit. The symbols “a” and “b” are used for the sake of simplicity in the description and mean the same configuration. That is, in the present embodiment, the signal from the signal detection unit 101 is arbitrarily distributed to the reading unit 102a and the reading unit 102b and read. Reference numeral 104 denotes a drive circuit unit (vertical scanning circuit), 105 denotes an amplifier circuit unit, and 107 denotes an output terminal. Here, 106 is a common signal line portion. In this embodiment, two sets of common signal lines are arranged on 106a. The set of common signal lines refers to a set of a common signal line that outputs a signal for forming an image and a common signal line that outputs a reference signal. That is, four common signal lines are arranged in 102a and 102b.

  A detailed configuration will be described with reference to FIG. FIG. 1 shows the reading unit 102a, the common signal line unit 106a, the amplifier circuit unit 105a, and the output terminal 107a in FIG. Hereinafter, the symbol a is omitted. The amplifier circuit unit 105 has two amplifier circuits. Hereinafter, one amplifier circuit is also indicated as 105. The reading unit 102 includes a line memory 108 that holds a signal read from the signal detection unit 101. Reference numeral 109 denotes a switch for outputting a signal held in the line memory 108 to the common signal line unit 106. The common signal line unit 106 includes four common signal lines 112S, 112N, 113S, and 113N. 112S and 112N are a first set of common signal lines, and 113S and 113N are a second set of common signal lines. Reference numerals S1 and N1 of the line memory indicate that signals are output to the first set of common signal lines 112S and 112N, respectively, and S2 and N2 indicate signals to the second set of common signal lines 113S and 113N, respectively. It shows that it outputs.

  Further, the codes N1 and N2 of the line memory indicate that the reference signal is held. The reference signal is a reset signal (so-called noise signal) output from the signal detection unit 101 or a reference signal (so-called offset) of the amplifier when the reading unit 102 has an amplifier or the like. S1 and S2 are line memories for storing an optical signal (a signal obtained by superimposing the optical signal on the previous reset signal). FIG. 3A shows an equivalent circuit of this line memory configuration.

  An equivalent circuit will be briefly described with reference to FIG. FIG. 3A shows a pixel surrounded by a dotted line, a readout unit 102 surrounded by a dotted line, common signal lines 112S and 112N, and an amplifier circuit unit 105. The signal detection unit 101 in FIG. 1 has a plurality of such pixels arranged side by side. The pixel includes a photodiode PD, a transfer transistor Tx, a reset transistor RES, and a power supply SVDD that provides a reference voltage. Furthermore, an amplification transistor SF and a selection transistor SEL, which are part of the source follower circuit, are included. A signal is read from such a pixel to the reading unit 102. In the reading unit 102 in FIG. 3A, a signal is input from the clamp capacitor CO to the amplifier and is further held in the line memory 108. Then, a signal is read out to the common signal lines 112S and 112N by the switch 109. Here, CHS and CHN indicate the capacity of the common signal line. One memory configuration of the line memory 108 is a switch PTS and a capacitor CTS.

  In such a photoelectric conversion device, a switch 110 that connects the common signal lines 112S and 113S and a switch 111 that connects the common signal lines 112N and 113N are arranged. With the configuration having the switches 110 and 111, four signals S1, N1, S2, and N2 can be read in parallel. In addition, after the signals held by S1 and N1 are read, the signals held by S2 and N2 are read, and the signals can be read alternately. At this time, the number of output terminals 107 to be used can be reduced from two to one. Further, it becomes possible to stop the driving of the amplifier circuit 105 corresponding to the unused output terminal 107, and it is possible to measure low power consumption. In other words, the number of output terminals can be easily changed, and the power consumption can be reduced. A specific driving method is shown in FIGS. 4 (a) and 4 (b). FIG. 4 is a pulse diagram of the switches M1 to M10 of the switch 109. When the pulse is high, the switch is turned on, and a signal is read from the line memory 108. In the first signal reading method, four signals held by S1 and N1, and S2 and N2 are read in parallel. The switches 110 and 111 in FIG. 1 are turned off, and the switch 109 is opened and closed at the timing shown in FIG. At this time, the signals from the common signal lines 112S, 112N, 113S, and 113N are differentially and amplified by the amplifier circuit 105 that is arranged corresponding to each common signal line. Outputs corresponding to the common signal lines 112 and 113 are output in parallel from the two output terminals 117. In the second signal reading method, the switches 110 and 111 in FIG. 1 are turned off, and the switch 109 is opened and closed at the timing shown in FIG. In this operation, for example, signals held in the line memories S1-1 and N1-1 are read out to the common signal lines 112S and 112N. Then, the signal is amplified by one amplifier circuit 105 arranged corresponding to the common signal lines 112S and 112N. Thereafter, the signals held in the line memories S2-1 and N2-1 are read from the common signal line 113S to the common signal line 112S. At the same time, data is read from the common signal line 113N to the common signal line 112N. Then, the signal is amplified by the amplifier circuit 105 arranged corresponding to the common signal lines 112S and 112N. That is, this method makes it possible to multiplex and output signals.

  An example of the configuration of the drive circuit unit 103 that switches these signal readout methods will be described with reference to FIG. A common signal line unit 106 is disposed between the switch 109 and the drive circuit unit 103, but is omitted. The drive circuit unit 103 includes two horizontal scanning circuits. A part of the switches 109 is turned on by the output from the horizontal scanning circuit 1, and all the switches 109 are turned on for the output from the horizontal scanning circuit 2. In the first signal reading method, the switch 109 is driven by the output of the horizontal scanning circuit 1, and in the second signal reading method, the switch 109 is driven by the output from the horizontal scanning circuit 2. These switching operations are performed by an arbitrary method. According to this second signal reading method, compared with the method of switching and multiplexing the switching unit at high speed as in Patent Document 1, the high-speed operation is less, so that the waveform distortion and the output signal are offset. Multiplexing is possible.

  As described above, since the two signal reading methods can be easily switched, it is possible to easily change the number of output terminals and to reduce power consumption. In addition, it is possible to provide a photoelectric conversion device that can arbitrarily switch between low-speed and low-power consumption driving and high-speed driving. Since the number of output terminals can be arbitrarily changed, connection with an external device can be facilitated.

(Second Embodiment)
In the first embodiment, the number of switches 110 and 111 that connect the common signal lines 112S and 113S and 112N and 113N is one. However, in the present embodiment, a plurality of common signal lines are arranged. With this configuration, when a waveform shift (shading) occurs due to the position of the line memory, the amount of waveform shift can be reduced. Specifically, four switches 110 and 111 are provided, and the intervals are arranged at equal intervals including both ends.

(Third embodiment)
When switching a plurality of signal readout methods as in the first embodiment, the gain of the signal read out may be changed by the method. Therefore, in this embodiment, a method for giving an appropriate gain will be considered.

The capacitance value of the line memory 108 is CT, and the capacitance value of the common signal line is CH. CH is composed of a parasitic capacitance of the wiring and the switch 109 for reading. The common signal line is reset to the reset voltage Vres in advance before reading. When the switch 109 is turned on and the signal held in the line memory 108 is a voltage signal Vs, the voltage of the common signal line after the signal is read is
(CT · Vs + CH · Vres) / (CT + CH) (Formula 1)
It becomes. In the first embodiment, since the amplifier circuit 105 also performs difference processing, the following signal is output from the amplifier circuit 105.

{(CT · Vs + CH · Vres) / (CT + CH) − (CT · Vn + CH · Vres) / (CT + CH)} · Gamp + Vref = (Vs−Vn) · CT / (CT + CH) · Gamp + Vref (Formula 2)
Here, Vs is an optical signal, and Vn is a reset signal. Gamp is a read gain of the amplifier circuit 105, and Vref is a reference output voltage. When the signal readout method is changed and multiplexed, the capacity of the common signal line is doubled, so the output voltage of the amplifier circuit 105 is as follows.

(Vs−Vn) · CT · Gamp / (CT + 2CH) + Vref (Formula 3)
By giving an appropriate gain shown in the equation in accordance with the signal readout method, it is possible to make the final readout signal gain uniform.

(Fourth embodiment)
FIG. 6 is a schematic diagram of the drive circuit unit 103 of the present embodiment. The difference between the present embodiment and the first embodiment is that the configuration of the drive circuit unit 103 described with reference to FIG. 5 is different. According to the drive circuit unit 103 of the present embodiment, the number of horizontal scanning circuits can be reduced as compared with the configuration of FIG. 5, and the size of the signal detection device can be reduced. Specifically, it is possible to change the signal reading method by using a data transfer unit constituting a horizontal scanning unit and a logic operation unit indicated by a logic circuit. Further, a mechanism for arbitrarily selecting and switching between a drive pulse and a divided pulse is provided as a reference clock to be supplied to the data transfer unit.

  A driving operation in the driving circuit unit 103 will be described. In FIG. 6, SW is a control switch, and the control switch SW is turned on when a high level is input to one of two input terminals. Of the two signal lines that transmit signals from the logic circuit, the signal line that supplies signals to SW1, SW3, etc. is the first control line, and the signal line that supplies signals to SW2, SW4, etc. is the second control line. To do.

  In the case of the first signal readout method in which signals are read out in parallel from each of the two amplifier circuits in the amplifier circuit unit 105 shown in FIG. 1, high-level inputs are given to the two input terminals of the control switch SW. At the same time, a drive pulse is input as a reference clock. At this time, the output of SR1_O1 simultaneously turns on M1 to M4 which are part of the switch 109. Then, the outputs of SR1_02 and SR1_03 sequentially operate the switch 109.

  On the other hand, the case of the second signal reading method for reading a signal from only one of the amplifier circuits in the amplifier circuit unit 105 shown in FIG. 1 will be described. A drive pulse is applied to the logic circuit, and a high level is output from the logic circuit to the first control line in synchronization with the odd-numbered high level of the drive pulse. Then, a high level is output to the second control line in synchronization with the even-numbered high level of the drive pulse. A frequency-divided pulse obtained by dividing the drive pulse by 1/2 is input as the reference clock. As a result, the reference clock is driven at half the frequency of the drive pulse.

  That is, SR1_O1 outputs a high level for a time that is twice that of parallel reading (driving synchronized with the driving pulse). Among the periods in which SR1_O1 is at a high level, SW1 is turned on by the first control line pulse in the first half period, and SW2 is turned on by the first control line pulse in the second half period.

  In the present embodiment, driving in the configuration of the first embodiment has been described, but the configuration is not limited to that. Corresponding to the configuration of the common signal line and the like, the number of drive and control lines in the frequency divider circuit may be changed.

(Fifth embodiment)
In the present embodiment, the configuration of the common output line in the first embodiment is changed. This embodiment will be described with reference to FIG. FIG. 7 is a schematic circuit diagram of a reading unit and the like of the signal detection device. The description of the reference numerals corresponding to FIG. 1 is omitted. In FIG. 7, for example, 40 lines from S1-1 to N2-10 in the line memory 108 are defined as first blocks, and S1-11 to N2-20 are defined as second blocks. In the first block, signals are read out to the common signal lines 112S, 112N, 113S, and 113N. In the second block, signals are read out to the common signal lines 116S, 116N, 117S, and 117N. These common signal lines are provided with switches 110, 111, 114, and 115. The signal reading method may be the same as in the first embodiment.

  Switches 120 and 121 are provided on the common signal line of each block. Each switch is four switches. When reading a signal from the first block, the switch 120 is turned on, and the switches of other blocks, for example, the switch 121 are turned off. Then, signals are output from the first block to the first signal line pair 118S and 118N and the second signal line pair 119S and 119N.

  By such an operation, the number of switches connected to each signal line can be reduced. And the capacity | capacitance CH of each signal line can be restrained small. That is, the gain CT / (CT + CH) of the signal read from the line memory 108 can be increased, and the Gamp in the amplifier circuit unit 105 can be lowered. Therefore, it becomes possible to read at high speed. In addition, it is possible to provide a high-speed and low-noise amplifier circuit.

  Here, the gain of the read signal at this time is expressed as follows. The capacitance values of the common signal lines 112 and 113 and the like are CHa, and the capacitance values of the signal lines 118 and 119 and the like are CHb. The case where signals are read out in parallel from each common signal line is shown in Equation 4, and the case where the switch 110 is turned on and signals from two common signal lines are read out from one common signal line is shown in Equation 5.

CT · Gamp / (CT + CHa + CHb) (Formula 4)
CT · Gamp / (CT + 2CHa + CHb) (Formula 5)
Here, compared with the capacitance CH of the common signal line of the first embodiment, the capacitance CHa of the common signal line and the capacitance CHb of the signal line of this embodiment are CH >> CHa + CHb. Further, by adjusting the block unit, CHa << CHb. Since CHa << CHb, the amount of increase in Equation 5 is not large compared to Equation 4. For example, it becomes a little less than 10%. This makes it possible to further reduce the capacity compared to the first embodiment in which the capacity is doubled.

  Here, a plurality of switches 110, 111, 114, and 115 that connect the common signal line may be arranged, or may be arranged at an arbitrary position with respect to the common signal line. For example, when the switch 110 is turned on, the signal of S2-1 is read to the common signal line 112S via the switch 110. Therefore, in order to reduce the offset of the signals S1-1 and S2-1, it is desirable that the resistance value of the switch 110 is smaller than the resistance value of the switch 120.

  Further, a configuration in which a switch or the like for connecting the signal lines 118S and 119S is further provided in the configuration of the present embodiment. In that case, a configuration without the switches 110 and 111 may be used.

  In the present embodiment, the capacity of the common signal line can be reduced, so that the signal reading speed can be improved. In addition, since it is not necessary to increase the gain of the amplifier circuit unit, it is possible to reduce the possibility of noise.

(Sixth embodiment)
A case where the present invention is applied to an imaging system will be described as an example using the signal detection device of the present invention. The signal detection device is a photoelectric conversion device having a photoelectric conversion element for detecting light, and a case where the signal detection device is used in a digital still camera as an example of an imaging system will be described with reference to FIG. Other imaging systems include digital camcorders and the like.

  FIG. 8 is a block diagram of a digital still camera system. Includes a solid-state imaging device 804 which is a photoelectric conversion device.

  The optical image of the subject is formed on the imaging surface of the solid-state imaging device 804 by an optical system including the lens 802 and the like. On the outside of the lens 802, a barrier 801 serving both as a protection function of the lens 802 and a main switch can be provided. The lens 802 can be provided with a stop 803 for adjusting the amount of light emitted therefrom. The imaging signal output from the solid-state imaging device 804 through a plurality of channels is subjected to various corrections, clamping, and other processing by the imaging signal processing circuit 805. Imaging signals output from the imaging signal processing circuit 805 through a plurality of channels are analog-digital converted by an A / D converter 806. The image data output from the A / D converter 806 is subjected to various corrections, data compression, and the like by a signal processing unit (image processing unit) 807. The solid-state imaging device 804, the imaging signal processing circuit 805, the A / D converter 806, and the signal processing unit 807 operate according to the timing signal generated by the timing generation unit 808.

  Blocks 805 to 808 may be formed on the same chip as the solid-state imaging device 804. Each block is controlled by the overall control / arithmetic unit 809. In addition, a memory unit 810 for temporarily storing image data and a recording medium control interface unit 811 for recording or reading an image on a recording medium are provided. The recording medium 812 includes a semiconductor memory or the like and can be attached and detached. Furthermore, an external interface (I / F) unit 813 for communicating with an external computer or the like may be provided.

  Next, the operation of FIG. 8 will be described. When the barrier 801 is opened, the main power supply, the control system power supply, and the image pickup system circuit such as the A / D converter 806 are sequentially turned on. Thereafter, the overall control / arithmetic unit 809 opens the aperture 803 to control the exposure amount. The signal output from the solid-state imaging device 804 passes through the imaging signal processing circuit 805 and is provided to the A / D converter 806. The A / D converter 806 A / D converts the signal and outputs it to the signal processing unit 807. The signal processing unit 807 processes the data and provides it to the overall control / calculation unit 809, and the overall control / calculation unit 809 performs computation to determine the exposure amount. The overall control / calculation unit 809 controls the aperture based on the determined exposure amount.

  Next, the overall control / calculation unit 809 extracts a high frequency component from the signal output from the solid-state imaging device 804 and processed by the signal processing unit 807, and calculates the distance to the subject based on the high frequency component. Thereafter, the lens 802 is driven to determine whether or not it is in focus. If it is determined that the subject is not in focus, the lens 802 is driven again to calculate the distance.

  Then, after the in-focus state is confirmed, the main exposure starts. When the exposure is completed, the imaging signal output from the solid-state imaging device 804 is corrected in the imaging signal processing circuit 805, A / D converted by the A / D converter 806, and processed by the signal processing unit 807. The image data processed by the signal processing unit 807 is accumulated in the memory unit 810 by the overall control / calculation 809.

  Thereafter, the image data stored in the memory unit 810 is recorded on the recording medium 812 via the recording medium control I / F unit under the control of the overall control / arithmetic unit 809. The image data can be provided to a computer or the like through the external I / F unit 813 and processed.

  When performing still image shooting with such a digital still camera, driving is performed to read signals in parallel from the four output terminals of the photoelectric conversion device. In addition, when moving image shooting is performed with a digital still camera, for example, thinning driving and multiplexing driving are performed, and driving for reading signals in parallel from two output terminals of the photoelectric conversion device is performed. In addition, there is a drive that cuts out and reads out a part of the screen regardless of a still image or a moving image. By applying the signal readout method for reducing the number of output terminals as in the present invention at the time of such driving, the current consumption can be reduced to about 60% as compared with still image shooting. This is because by reducing the number of output terminals, the number of read amplifiers to be operated can be reduced and current consumption can be reduced. In addition, the AD converter to which a signal is input from the output terminal can be stopped at the same time. Therefore, the power consumption can be further reduced as the imaging system.

  Therefore, since the number of output terminals can be switched by a simple method, it is possible to provide an imaging system capable of easily switching between high speed driving and low power consumption driving.

  Although the photoelectric conversion device has been described in the above embodiment, the present invention relates to the configuration of the common signal line, and the detected signal may be a magnetic signal. Also in the configuration, the common signal line may not be a pair for the optical signal and the reset signal.

101 Signal generation unit 102 Capacitance unit (reading unit)
DESCRIPTION OF SYMBOLS 103 Drive circuit part 104 Drive circuit part 105 Amplification circuit part 106 Common signal line part 107 Output terminal 108 Line memory 109 Read switch 110, 111 switch 112S, 112N, 113S, 113N Common signal line

Claims (10)

A signal generator for generating a signal;
A plurality of common signal lines, each of which has a signal output from the signal generation unit and includes at least a first common signal line and a second common signal line;
A plurality of signal lines having at least a first signal line and a second signal line;
A first switch that controls conduction between the first common signal line and the first signal line; and controls conduction between the second common signal line and the second signal line. A plurality of switches including at least a second switch;
A plurality of amplifier circuit units including at least a first amplifier circuit to which a signal from the first signal line is input and a second amplifier circuit to which a signal from the second signal line is input;
A drive circuit section;
A signal detection device comprising:
The signal detection device includes a switch that controls conduction between the first common signal line and the second common signal line. The plurality of common signal lines include a third common signal line and a fourth common signal line,
The plurality of signal lines include a third signal line and a fourth signal line,
The plurality of switches include: a third switch that controls conduction between the third common signal line and the third signal line; and the fourth common signal line and the fourth signal line. And a fourth switch for controlling conduction between them,
The first amplifier circuit receives a signal from the third signal line in addition to the first signal line,
The second amplifier circuit receives a signal from the fourth signal line in addition to the second signal line,
The signal detection device according to claim 1, wherein the signal detection device includes a switch that controls conduction between the third common signal line and the fourth common signal line. The plurality of common signal lines include a fifth common signal line and a sixth common signal line,
The plurality of switches include a fifth switch that controls conduction between the fifth common signal line and the first signal line, and the sixth common signal line and the second signal line. The signal detection apparatus according to claim 1, further comprising a sixth switch that controls conduction between the first switch and the sixth switch. The drive circuit unit includes a scanning unit,
4. The signal detection apparatus according to claim 1, wherein the scanning unit includes a logical operation unit and is capable of outputting at least two types of drive signals. 5.   The signal detection apparatus according to claim 4, wherein the scanning unit includes a frequency dividing circuit.   The signal detection device according to claim 1, wherein the first amplifier circuit and the second amplifier circuit are amplifier circuits capable of switching gains.   7. The signal detection apparatus according to claim 1, wherein a plurality of switches for controlling conduction between the first common signal line and the second common signal line are provided. 8.   The signal generation unit includes a plurality of photoelectric conversion elements, a transfer transistor that transfers a signal of the photoelectric conversion element to a signal holding unit, and a reset transistor that applies a reference voltage to the signal holding unit. Item 8. The signal detection device according to any one of Items 1 to 7. A signal based on the potential of the signal holding unit when the reset transistor gives the reference voltage is transferred to the first signal line and the second signal line,
The signal based on the potential of the signal holding unit when the transfer transistor transfers the signal is transferred to the third signal line and the fourth signal line. Signal detector. A signal detection device according to claim 8 or 9,
An image processing unit for processing a signal output from the signal detection device;
An imaging system comprising:

Images