JP5269112B2 - Semiconductor device provided with amorphous film, and method for manufacturing semiconductor device - Google Patents

Description

  The present invention includes an amorphous film that may contain N as an optional component in addition to Ti and Al used as an oxygen permeation preventive film in a semiconductor device including a ferroelectric metal oxide as a capacitor insulating film. The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

As a ferroelectric material used as a capacitor insulating film in a so-called ferroelectric memory, lead zirconate titanate (Pb (Zr _{1 -x} Ti _x ) O ₃ ) (hereinafter also referred to as PZT), barium titanate. strontium _{(Ba 1 - x Sr x TiO} 3) ( hereinafter, BS
Also referred to as T. ), And strontium bismuth tantalate niobate (SrBa ₂ (N
_{b 1 -. x Ta x)} 2 O 9) ( hereinafter, also referred to as SBT), etc. are known. Here, X represents a composition ratio having a value between 0 and 1.

  In general, a ferroelectric memory is provided with a capacitor insulating film made of a ferroelectric material provided on the first main surface side of a substrate, an upper electrode provided above the capacitor insulating film, and provided below the capacitor insulating film. A lower barrier electrode, a conductive barrier layer provided below the lower electrode, and a contact plug electrically connected to the conductive barrier layer. The contact plug is provided through an interlayer insulating film that covers the entire surface on the first main surface side of the substrate.

  As a problem of such a ferroelectric memory, diffusion of oxygen from a capacitor insulating film is known. That is, oxygen diffuses from the capacitor insulating film through the lower electrode and the conductive barrier layer by heat treatment or the like when sintering the capacitor insulating film, and oxidizes the surface of the contact plug made of W or the like. As a result, the conductivity of the contact plug is impaired.

  The problem of contact plug surface oxidation is particularly noticeable when the contact plug is formed by a CMP (chemical mechanical polishing) method.

  More specifically, when a contact plug is formed using the CMP method, a step of about 20 to 50 nm occurs at the boundary between the contact plug and the interlayer insulating film due to a difference in polishing rate between the contact plug and the interlayer insulating film. To do. Then, large grain boundaries (hereinafter referred to as seams) derived from the steps are generated in the lower electrode and the conductive barrier layer.

  As a result, oxygen easily diffuses to the contact plug through the seam and oxidizes the contact plug surface.

Various measures have been taken to prevent the diffusion of oxygen. For example, it is known that the lower electrode is a Pt / IrO ₂ / Ir laminate. In this technology, oxygen diffused through the Pt film and IrO ₂ film is consumed by oxidation of the Ir film, so that the oxygen diffusion is stopped in the Ir film, and as a result, the diffusion of oxygen to the contact plug surface is prevented. To do.

  For the same purpose, a technique is disclosed in which a conductive barrier layer having electrical conductivity such as a crystalline TiAlN film containing Ti, Al, and N is interposed between the lower electrode and the contact plug. (For example, see Patent Document 1).

These techniques can suppress the diffusion of oxygen to the contact plug to some extent, but have not been sufficient. The reason is that the IrO ₂ film, the Ir film, and the TiAlN film are all crystalline, and the grain boundaries are oriented in a direction perpendicular to the main surface of the substrate. As a result, oxygen diffuses using this grain boundary, particularly the seam, as a diffusion path, and oxidizes the surface of the contact plug.

Therefore, in order to suppress the diffusion of oxygen through the grain boundary, an amorphous TiAlN film having no orientation is used as the conductive barrier layer, so that the Ir film and the IrO ₂ film deposited on the TiAlN film can be reduced. A technique for weakening the orientation of the lower electrode is disclosed (for example, see Patent Document 2).

In this technology, the orientation of the Ir film and the IrO ₂ film is weakened, that is, the crystal grains in the Ir film and the IrO ₂ film are made small and dense, thereby increasing the oxygen diffusion path length. As described above, the diffusion amount of oxygen reaching the contact plug surface is reduced.
JP-A-8-64786 JP 2005-150688 A

Summarizing the technology disclosed in Patent Document 2, by making the Ir film and IrO ₂ film dense, the total length of the grain boundary where oxygen diffuses is lengthened, and as a result, the diffusion of oxygen reaching the contact plug surface It can be said to reduce the amount.

In other words, the technology of Patent Document 2 focuses on improving the film quality of the Ir film and the IrO ₂ film, and only describes that the TiAlN film as the base may be amorphous. .

Under such a technical background, the inventor of this application has intensively studied the problem of oxidation of the contact plug surface caused by oxygen diffusion. As a result, it was found that the film quality of the TiAlN film, which is a conductive barrier layer, has a greater influence on the oxygen diffusion than the film quality of the Ir film and the IrO ₂ film.

More specifically, the inventor of this application, if the film quality of the TiAlN film that is the conductive barrier layer is amorphous, the film quality of the film (Ir film, IrO ₂ film, etc.) deposited on the conductive barrier layer It has been found that oxygen diffusion can be suppressed regardless of whether or not there is a step at the boundary between the contact plug and the interlayer insulating film.

  The inventors of this application have also found that this amorphous TiAlN film is formed only under specific film formation conditions.

  Furthermore, the inventor has found that even a TiAl film not containing N can suppress the diffusion of oxygen in the same manner as the amorphous TiAlN film described above.

  Another object of the present invention is to provide a semiconductor capable of suppressing oxygen diffusion by using, as a conductive barrier layer, an amorphous film that may contain N as an optional component in addition to containing Ti and Al. It is to provide an apparatus and a manufacturing method thereof.

To solve the problems described above, a semi-conductor device of this invention, the upper side of the first main surface of the substrate, and the conductive barrier layer, a lower electrode formed above the conductive barrier layer, the lower electrode A capacitor insulating film made of a ferroelectric metal oxide formed on the upper side, and the conductive barrier layer contains Ti and Al, in addition to Ti and Al, an amorphous film that may contain N as an optional component, and amorphous It has a laminated structure with a crystalline film containing Ti, Al, and N provided one layer above and below with a film interposed therebetween.

  In the semiconductor device described above, the thickness of the amorphous film is preferably 20 nm to 150 nm.

In order to solve the above-described problems, a method for manufacturing a semiconductor device according to the present invention provides: (1) a sputtering target in which a crystalline film existing under an amorphous film is stacked in a stacked structure; (2) the atmospheric pressure in the film forming chamber, (3) the substrate temperature, and (4) the volume ratio of N ₂ gas in the mixed sputtering gas of N ₂ gas and Ar gas, respectively, with a predetermined value as a reactive value. (A) Sputtering condition changing operation for increasing the DC power of (1), and (B) Sputtering condition for reducing the atmospheric pressure in the filming chamber of (2). change operation, (C) the (3) sputtering conditions change operation for increasing the substrate temperature, and, varying sputtering conditions to reduce the volume ratio of the N ₂ gas (D) wherein (4) By performing one or more sputtering conditions change operation selected from the group consisting of operation, characterized by depositing.

According to the present invention, an amorphous TiAlN film containing N as an optional component having an electric resistivity of 6 × 10 ² μΩ · cm or less can be obtained. Since this TiAlN film is amorphous, there is no grain boundary inside the film. Therefore, by using this TiAlN film as the conductive barrier layer of the ferroelectric memory, oxygen diffusion through the grain boundary of the conductive barrier layer can be effectively blocked.

  In particular, even if the above-described seam exists in the lower electrode, the seam cannot penetrate the amorphous TiAlN film. Therefore, oxygen that diffuses through the seam is effectively blocked by the amorphous TiAlN film.

  Further, since the amorphous TiAlN film containing N as an optional component has a lower electrical resistivity than the crystalline TiAlN film, the electrical resistance between the contact plug and the lower electrode can be reduced as compared with the conventional case.

  Here, Table 1 shows definitions of terms used in the following description.

  As shown in Table 1, the technical scope of the present invention includes an amorphous TiAl alloy film (No. 1) made of Ti and Al not containing N, and an amorphous material containing N, Ti, and Al. Both TiAlN films (No. 2) are included. And these No. 1 and no. 2 is referred to as the first phase.

  The technical scope of the present invention does not include a crystalline TiAlN film (No. 3) containing N, Ti and Al. In addition, No. 3 TiAlN film is referred to as the second phase.

  In the following description, No. 1-No. The film 3 is collectively referred to as a “TiAlN film”.

  Since the present invention has the above-described configuration, the first phase, that is, an amorphous TiAlN film can be formed with high reproducibility. Further, by using this amorphous TiAlN film as a conductive barrier layer of a ferroelectric memory as a semiconductor device, oxidation of the contact plug surface due to oxygen diffusion can be suppressed.

Hereinafter, reference examples and embodiments of the present invention will be described with reference to the drawings. Each figure is only a schematic illustration of the shape, size, and arrangement relationship of each component to the extent that the present invention can be understood. Moreover, although the preferable structural example of this invention is demonstrated below, the material, numerical condition, etc. of each component are only a preferable example. Therefore, the present invention is not limited to the following embodiments.

(Reference Example 1 )
With reference to FIGS. 1 to 3, a method for forming an amorphous film and properties of the formed amorphous film will be described. FIG. 1 is a diagram showing the relationship between the electrical resistivity and N ₂ fraction of an amorphous film formed under six different film forming conditions. FIGS. 2A and 2B are diagrams showing XRD (X-ray diffractometer) analysis results of the first and second phase TiAlN films, respectively. 3A and 3B are cross-sectional SEM (scanning electron microscope) photographs of the first and second phase TiAlN films, respectively.

Hereinafter, a TiAlN film forming method will be described with reference to FIG. In FIG. 1, the vertical axis represents the electrical resistivity (μΩ · cm), and the horizontal axis represents the N ₂ fraction, that is, the volume ratio of N ₂ gas in the sputter gas in which N ₂ gas and Ar gas are mixed (N ₂ / (N ₂ + Ar)) as a percentage. Further, in the drawing, the DC power (kW) and the atmospheric pressure (mTorr) in the film forming chamber are shown in each film forming condition.

The various TiAlN films shown in FIG. 1 are formed by simple sputtering (N ₂ fraction = 0%) or reactive sputtering (N ₂ fraction> 0%). That is, a sputtering gas having an N ₂ fraction shown on the horizontal axis in FIG. 1 is introduced into the film forming chamber of the sputter film forming apparatus.

  Then, the sputtering gas is turned into plasma by applying a voltage between the substrate as the anode and the sputtering target as the cathode. In this reference example, a TiAl alloy target having a ratio of Al to Ti (ratio of the number of atoms) of 50:50 is used as the sputtering target. Further, a Si substrate is used as the substrate (base).

  The positive ions in the plasma are accelerated by the electric field between the substrate and the sputtering target, and collide with the surface of the sputtering target that is a cathode. Due to this collision, atoms of the sputtering target are knocked out, and the knocked-out atoms are deposited on the surface of the substrate arranged to face the sputtering target.

When the N ₂ fraction in the sputtering gas is greater than 0%, the atoms constituting the sputtering target react with N ₂ in the sputtering gas during the above-described deposition, and TiAlN containing N is present on the substrate. A film is formed. In this case, film formation proceeds by so-called reactive sputtering.

In contrast, when the N ₂ fraction in the sputtering gas is 0%, the film formation proceeds by so-called simple sputtering, and a so-called TiAl alloy film that does not contain N is deposited on the substrate.

In general, the film quality of a film formed on a substrate by reactive sputtering is as follows: (i) substrate temperature, (ii) DC power related to the sputtering target, (iii) pressure in the film forming chamber, and (iv) in the sputtering gas. Varies with N ₂ fraction. Here, the DC power is an amount given by the product of the voltage applied to the sputtering target, that is, the cathode, and the current flowing through the sputtering target.

  In FIG. 1, after the substrate temperature of (i) is kept constant at 200 ° C., the conditions (ii) to (iv) are variously changed to form a TiAlN film having a thickness of about 100 nm on the substrate. Filmed. As a result, it has been clarified that the obtained TiAlN films are roughly classified into two types.

That is, a film having an electrical resistivity of 2 × 10 ^{2 to} 6 × 10 ² μΩ · cm (first phase) and a film having an electrical resistivity of 1 × 10 ⁴ to 1 × 10 ⁵ μΩ · cm (second Phase).

As will be described in detail later, the first-phase TiAlN film may contain N as an optional component in addition to Ti and Al, and an amorphous film having an electrical resistivity of 6 × 10 ² Ω · cm or less. Is equivalent to.

  The electrical resistivity was obtained by multiplying the sheet resistance obtained by the conventionally known four-terminal method by the thickness of the TiAlN film (about 100 nm).

  The electrical resistivity was measured for a TiAlN film as it was formed, that is, without any treatment (for example, heat treatment, etc.) after film formation.

  The inventor of this application performed XRD analysis and cross-sectional SEM observation for each of the first-phase and second-phase TiAlN films. An example is shown in FIGS.

  FIGS. 2A and 2B are diagrams showing XRD analysis results of the first and second phase TiAlN films, respectively. In the drawing, the horizontal axis represents the diffraction angle 2θ (degrees), and the vertical axis represents the diffraction intensity (arbitrary unit).

  According to FIG. 2A, in the first phase TiAlN film, a peak derived from the Si substrate is observed at a diffraction angle of about 33 °. However, no peaks other than those derived from the Si substrate have been observed. This suggests that the first phase TiAlN film is not crystalline.

  On the other hand, in FIG. 2B, in addition to the peak derived from the Si substrate observed in FIG. 2A, peaks derived from TiN are observed at diffraction angles of about 37 ° and about 43 °. .

  3A and 3B are cross-sectional SEM photographs of the first and second phase TiAlN films, respectively. The SEM observation was performed at a magnification of 100,000 times.

  According to FIG. 3A, no crystal grains are observed in the first phase TiAlN film. In other words, as long as the magnification is observed, it can be said that the first phase TiAlN film is uniform and has no grain boundary.

  On the other hand, according to FIG. 3B, in the second phase TiAlN film, a large number of columnar crystal grains oriented perpendicular to the main surface of the Si substrate are observed. That is, the second phase TiAlN film has a number of grain boundaries extending in the thickness direction of the film.

  2 and 3, it can be seen that the first phase TiAlN film is not crystalline but amorphous. In contrast, the second phase TiAlN film is found to be crystalline.

  Referring to FIG. 1 again, the first phase, that is, the amorphous phase of the present invention, will be described while touching the behavior of the transition from the first phase (amorphous) to the second phase (crystalline) of the TiAlN film and the inferring mechanism of the transition. Deposition conditions (sputtering conditions) for obtaining a film will be described.

  FIG. 1 shows the electrical resistivity of the TiAlN film formed under the six film forming conditions shown in Table 2 below.

  First, the behavior of the change in film quality of the TiAlN film, which is commonly seen in the film formation conditions 1 to 5, will be described.

As is apparent from FIG. 1, when the N ₂ fraction is increased under each film forming condition, the electrical resistivity of the obtained TiAlN film is in the range of 2 × 10 ^{2 to} 6 × 10 ² μΩ · cm. Increase slightly. The TiAlN film whose electric resistivity falls within this range is the first phase.

The TiAlN film produced in the first phase is a TiAl alloy film not containing N (N ₂ fraction = 0%) or a TiAl alloy film containing a relatively small amount of N (N ₂ fraction> 0%). It is estimated that. That is, in the first phase, the amount of N is small with respect to the amounts of Ti and Al, and it is presumed that most of Ti and Al are alloyed without being bonded to N. Therefore, it is presumed that in the first phase, the TiAlN film remains amorphous.

Further, in the first phase, it is presumed that TiN in an amount not detected by XRD analysis is gradually generated as the N ₂ fraction increases. TiN is conductive, but its electrical resistivity is higher than that of TiAl alloy (N ₂ fraction = 0%). Therefore, in the first phase, it is estimated that TiN increases as the N ₂ fraction increases, and as a result, the electrical resistivity of the TiAlN film slightly increases.

When the N ₂ fraction is further increased and the electrical resistivity of the TiAlN film reaches 4 × 10 ^{2 to} 5 × 10 ² μΩ · cm, the electrical resistivity of the TiAlN film increases with the increase of the N ₂ fraction. It starts to increase rapidly. Hereinafter, the region where the electrical resistivity rapidly increases is referred to as a transition region.

In the transition region, the electrical resistivity increases by about two orders of magnitude while the N ₂ fraction increases by about 10%.

  This is considered to be because Al in the transition region is nitrided abruptly, which has been kept in a metal state until then. That is, it is estimated that AlN is rapidly generated in the transition region.

  As is well known, since AlN is electrically insulative, it is presumed that the electrical resistivity of the TiAlN film increases rapidly when the proportion of AlN in the TiAlN film increases.

When the N ₂ fraction is further increased and the electrical resistivity becomes 1 × 10 ⁴ to 4 × 10 ⁴ μΩ · cm, the increase rate of the electrical resistivity of the TiAlN film becomes moderate. Thereafter, as the N ₂ fraction increases, the electrical resistivity of the TiAlN film slightly increases in the range of 1 × 10 ⁴ to 1 × 10 ⁵ μΩ · cm. A TiAlN film whose electric resistivity falls within this range is the second phase.

Since the electrical resistivity also increases in the second phase, it is presumed that AlN is newly generated in the second phase as the N ₂ fraction increases.

Since the electrical resistivity of the TiAlN film in the second phase is on the order of 1 × 10 ⁴ μΩ · cm, it is shown whether TiN having an electrical resistivity of about 1/100 is generated in the second phase. It cannot be judged from 1. However, since a peak derived from TiN is observed in the XRD analysis result (FIG. 2B) of the second phase TiAlN film, TiN is generated in the second phase as the N ₂ fraction increases. Presumed to be.

Note that, under the deposition condition 6, only the second phase TiAlN film is observed. This is presumably because the change range (40 to 60%) of the N ₂ fraction in the film formation condition 6 is narrower than other conditions. Therefore, it is presumed that the first phase exists in the region where the N ₂ fraction is less than 40% even under the film forming condition 6.

Further, film forming conditions 1 to 4 is not subjected to measurement by N ₂ parts per range of less than 40%, in this range is assumed that shows the same tendency as the film formation conditions 5.

  From the results obtained from the film forming conditions 1 to 5, it has been clarified that the following trends are observed with respect to the transition from the first phase to the second phase.

(Trend 1): When the DC power is equal, the TiAlN film is kept in the first phase in a wider range of N ₂ fraction when the pressure in the film forming chamber is lower. That is, the transition from the first phase to the second phase is difficult.

(Trend 2): When the atmospheric pressures in the film forming chambers are equal, the TiAlN film maintains the first phase state in a wider range of N ₂ fraction when the DC power is larger. That is, the transition from the first phase to the second phase is difficult.

  Moreover, the following (trend 3) became clear from the experimental result which changed the substrate temperature which the inventor of this application performed.

(Trend 3): When other conditions (DC power and film formation chamber pressure) are equal, the TiAlN film maintains the first phase state in a wider range of N ₂ fraction when the substrate temperature is higher. . That is, the transition from the first phase to the second phase is difficult.

From the above, in order to obtain a first phase, that is, an amorphous TiAlN film in a wider N ₂ fraction range, the DC power is increased, the pressure in the deposition chamber is decreased, and the substrate temperature is decreased. It became clear that it should be higher.

From the viewpoint of obtaining a first phase TiAlN film in a wider range of N ₂ fraction, the deposition conditions 1 to 6 are ranked most preferable, and the deposition conditions 2, The preferable degree decreases in the order of the film forming condition 3, the film forming condition 4, the film forming condition 5, and the film forming condition 6. However, the film formation conditions 4 and 5 are substantially the same.

More specifically, under the deposition condition 1, the first phase TiAlN film is obtained when the N ₂ fraction is in the range of 0% or more and 70% or less.

Under the deposition condition 2, the first phase TiAlN film is obtained when the N ₂ fraction is in the range of 0% or more and 60% or less.

Under the deposition condition 3, the first phase TiAlN film is obtained when the N ₂ fraction is in the range of 0% or more and 50% or less.

Under the deposition conditions 4 and 5, the first phase TiAlN film is obtained when the N ₂ fraction is in the range of 0% or more and 40% or less.

Under the deposition condition 6, it is presumed that the first phase TiAlN film can be obtained when the N ₂ fraction is less than 40%.

In FIG. 1, the change width of the N ₂ fraction is 10% intervals in each film forming condition. Therefore, the upper limit value (40%, 50%, 60% and 70%) of the N ₂ fraction at which the first phase TiAlN film is obtained includes an error of 10%. That is, the true upper limit value of the N ₂ fraction is greater than or equal to the upper limit value and less than (upper limit value + 10%), and the electrical resistivity of the TiAlN film is 6 × 10 ² μΩ · cm or less. It can be said to be a _two- minute rate. More specifically, in the case of the film forming condition 1, the true upper limit value of the N ₂ fraction is in the range of 70% or more and less than 80%.

Further, according to the evaluation of the inventors of this application, the first phase TiAlN film has a substrate temperature of 100 to 300 ° C., a DC power of 0.5 to 10 kW, and a film forming chamber pressure of 3 to 15 mTorr. In the range, it became clear that the N ₂ fraction was obtained by making it a desired value.

Further, it is presumed that the oxygen diffusion preventing ability (oxygen barrier property) of the first phase TiAlN film is improved with an increase in the N content in the TiAlN film. As described above, the increase in the electrical resistivity of the TiAlN film in the first phase is assumed to reflect the increase in TiN in the TiAlN film, that is, the increase in N contained in the TiAlN film. Therefore, from the viewpoint of oxygen barrier properties, the TiAlN film has a relatively high electrical resistivity (4 × 10 ^{2 to} 5 × 10 ² μΩ ···) just before the transition from the first phase to the second phase. It is preferable to form the TiAlN film under film formation conditions such as (about cm).

For example, in the case of the film formation condition 1, the N ₂ fraction is set to 70%, more strictly, a predetermined value just before the transition from the first phase to the second phase of 70% or more and less than 80%. It is preferable. In the case of the film formation condition 2, it is preferable to set the N ₂ fraction to a predetermined value just before the transition from the first phase to the second phase, which is 60%, more strictly, less than 70%. In the case of the film formation condition 3, it is preferable to set the N ₂ fraction to a predetermined value immediately before the transition from the first phase to the second phase, which is 50%, more strictly 50% or less and less than 60%. In the case of the film forming conditions 4 and 5, the N ₂ fraction is set to a predetermined value immediately before the transition from the first phase to the second phase of 40%, more strictly 40% or more and less than 50%. preferable.

  Further, according to the evaluation of the inventor of this application, the first phase TiAlN film is stable against heat treatment, and even at a temperature of about 800 ° C. (sintering temperature of the capacitor insulating film 18 described later), It became clear that the state of the 1st phase was maintained, without changing to 2 phases.

Further, according to the evaluation of the inventors of this application, even if an amorphous film (N ₂ fraction = 0%) made of only Ti and Al is heat-treated in an N ₂ atmosphere, the amorphous film containing Ti, Al, and N (N ₂ fraction> 0%) was not obtained. That is, among the first-phase TiAlN films, an amorphous film containing Ti, Al, and N (N ₂ fraction> 0%) can be formed only by reactive sputtering.

Thus, according to the SEM observation, the first phase TiAlN film of this reference example has no grain boundary inside the film. Therefore, if this film is used as a conductive barrier layer of a ferroelectric memory, there is no grain boundary that becomes an oxygen diffusion path in the TiAlN film, so that oxygen cannot permeate the TiAlN film. As a result, the oxidation of the surface of the contact plug provided under the conductive barrier layer can be suppressed. This point will be described in detail in Reference Example 2 .

  In addition, since the first phase TiAlN film has a lower electrical resistivity than the second phase TiAlN film, the electrical resistance between the contact plug and the lower electrode can be reduced as compared with the prior art.

( Reference Example 2 )
A semiconductor device of Reference Example 2 will be described with reference to FIG. FIG. 4 is a schematic diagram illustrating a cross-sectional cut surface of an example of a semiconductor device.

  A configuration of the semiconductor device will be described with reference to FIG.

  The semiconductor device 10 shown as an example in FIG. 4 is a ferroelectric memory formed on the main surface 22 a side of the substrate 22. The cross-sectional shape of the memory mounting portion of the semiconductor device 10 is substantially trapezoidal. The semiconductor device 10 includes a contact plug 12, a conductive barrier layer 14, a lower electrode 16, a capacitor insulating film 18, an upper electrode 20, and the like.

  The contact plug 12 is provided through the interlayer insulating film 24 laminated on the main surface 22 a of the substrate 22. The upper surface 12 a of the contact plug 12 is electrically connected to the lower surface 14 a of the conductive barrier layer 14. The lower end portion of the contact plug 12 is electrically connected to an element such as a transistor (not shown) formed on the main surface 22 a side of the substrate 22.

Here, the interlayer insulating film 24 is, for example, a SiO ₂ film. In addition, the thickness of the interlayer insulating film 24 is, for example, 800 nm. The contact plug 12 is, for example, a W film formed by a CVD method.

  The contact plug 12 forms a contact hole in the interlayer insulating film 24 by a known method after forming the interlayer insulating film 24, fills the contact hole, and forms a W film on the entire surface of the interlayer insulating film 24. Thereafter, the W film is polished to the surface of the interlayer insulating film 24 by CMP.

  As described in the section “Problems to be Solved by the Invention”, a step 26 having a height of about 20 to 50 nm exists between the contact plug 12 and the interlayer insulating film 24. A seam (not shown) exists in the lower electrode 16 along an extension line (indicated by a broken line in the figure) of the step 26.

The conductive barrier layer 14 is an electrically conductive film formed on the upper surface 24 a of the interlayer insulating film 24. The lower surface 14a of the conductive barrier layer 14 is electrically connected to the contact plug 12 described above. The conductive barrier layer 14 is made of the first phase described in Reference Example 1 , that is, an amorphous TiAlN film. The thickness of the conductive barrier layer 14 is about 100 nm, for example.

The lower electrode 16 includes an Ir film 16a, an IrO ₂ film 16b, and a Pt electrode 16c, and is electrically connected to the conductive barrier layer. The Ir film 16a, the IrO ₂ film 16b, and the Pt electrode 16c are formed on the conductive barrier layer 14 in this order.

The Ir film 16a is made of metal Ir and is formed by sputtering. The Ir film 16a is crystalline and has a grain boundary extending in a direction perpendicular to the main surface 22a of the substrate. The thickness of the Ir film 16a is, for example, 100 nm. The Ir film 16a has a function as a sacrificial film. That is, the Ir film 16a is oxidized by oxygen diffused from the capacitor insulating film 18 through the Pt electrode 16c and the IrO ₂ film 16b, thereby suppressing the diffusion of oxygen into the conductive barrier layer.

The IrO ₂ film 16b is made of Ir oxide and is formed by reactive sputtering. The IrO ₂ film 16b is crystalline and has a grain boundary extending in a direction perpendicular to the main surface 22a of the substrate. The thickness of the IrO ₂ film 16b is about 100 nm, for example. Here, the IrO ₂ film 16b spatially separates the Pt electrode 16c and the Ir film 16a and prevents a solid solution reaction caused by direct contact between the two 16a and 16c.

  The Pt electrode 16c is made of metal Pt and is formed by sputtering. The Pt electrode 16c is crystalline and has a grain boundary extending in a direction perpendicular to the main surface 22a of the substrate. The thickness of the Pt electrode 16c is about 200 nm, for example.

  The capacitor insulating film 18 is provided on the lower electrode 16. The capacitor insulating film 18 is made of, for example, SBT, and is formed by a known sol-gel method. The sintering temperature of the capacitor insulating film 18 is about 800 ° C., for example. The thickness of the capacitor insulating film 18 is about 120 nm, for example.

  The upper electrode 20 is formed on the capacitor insulating film 18. The upper electrode 20 is made of metal Pt and is formed by sputtering. The thickness of the upper electrode 20 is about 200 nm, for example.

As described above, the semiconductor device 10 of this reference example includes the conductive barrier layer 14 made of the first phase, that is, the amorphous TiAlN film. Therefore, oxygen diffused from the capacitor insulating film 18 through grain boundaries such as seams existing in the lower electrode 16 is effectively blocked by the conductive barrier layer 14 in which no grain boundaries exist. As a result, oxidation near the upper surface 12a of the contact plug 12 is prevented.

In this reference example , the thickness of the conductive barrier layer 14 was about 100 nm. However, the conductive barrier layer 14 may have a thickness that can suppress oxygen diffusion. More specifically, the conductive barrier layer 14 is preferably 20 nm or more and 150 nm or less in thickness. If the thickness of the conductive barrier layer 14 is 20 nm or more, oxygen diffusion can be suppressed within a practically acceptable range. More preferably, the conductive barrier layer 14 is preferably 50 nm or more. If the thickness of the conductive barrier layer 14 is 50 nm or more, oxygen diffusion can be suppressed at a practically sufficient level. If the thickness of the conductive barrier layer 14 is 150 nm or less, the etching process can be easily performed while maintaining the barrier property against oxygen at a necessary and sufficient level.

Further, according to the evaluation of the inventors of this application, it has been clarified that the film formation conditions for forming the first phase TiAlN film do not depend on the type of the base on which the TiAlN film is formed. That is, also in Reference Example 2 in which the base is the interlayer insulating film 24 (SiO ₂ film), the first phase TiAlN film is obtained under the same film formation conditions as in Reference Example 1 in which the base is the Si substrate.

In this reference example , SBT is used as the capacitor insulating film 18, but the capacitor insulating film 18 is not limited to SBT, and a known ferroelectric metal oxide such as PZT and BST can be used.

(In the form state of implementation)
Referring to FIG 5, it will be described a semiconductor device in the form status of implementation. Figure 5 is a cross-sectional view of a conductive barrier layer 32 in the semiconductor device in the form status of implementation. The semiconductor device in the form status of implementation, except the conductive barrier layer 32 is a three-layer structure has a structure similar to the semiconductor device 10 of Example 2. Therefore, in the semiconductor device in the form status of implementation, the description of the structure common to shown and the semiconductor device 10 of the entire structure will be omitted.

The conductive barrier layer 32 of the semiconductor device of this embodiment has a stacked structure in which a lower layer 32a, an intermediate layer 32b, and an upper layer 32c are deposited in this order. Here, the lower layer 32a and the upper layer 32c are made of the second phase, that is, the crystalline TiAlN film described in Reference Example 1 . The intermediate layer 32b is made of the first phase described in Reference Example 1 , that is, an amorphous TiAlN film.

  That is, the conductive barrier layer 32 has a structure in which the first-phase TiAlN film (intermediate layer 32b) is sandwiched between the second-phase TiAlN films (lower layer 32a and upper layer 32c) that are provided one layer above and below.

  Here, the thickness of the lower layer 32a, the intermediate layer 32b, and the upper layer 32c is about 50 nm, for example.

  Next, a method for manufacturing the conductive barrier layer 32 will be briefly described.

First, the lower layer 32a existing below the intermediate layer 32b is formed. The lower layer 32a is formed by a reactive sputtering method. As the sputtering target, the same target as in Reference Example 1 is used. Then, in FIG. 1, film formation is performed under the sputtering conditions for obtaining the second phase TiAlN film.

That is, in film formation condition 1, the N ₂ fraction is 80% or more, in film formation condition 2, the N ₂ fraction is 70% or more, and in film formation condition 3, N ₂ minutes. In the film formation conditions 4 and 5, the N ₂ fraction is 50% or more in the film formation conditions 4 and 5, and in the film formation condition 6, the N ₂ fraction is 40% or more. Film formation is performed.

Then, when the film thickness of the lower layer 32a reaches about 50 nm, the film formation is temporarily stopped. Thereafter, in order to form the intermediate layer 32b, which is the first phase TiAlN film, a sputtering condition changing operation is performed. Specifically, the operations listed below are performed singly or in combination. (A) Increase DC power, (B) Decrease air pressure in the deposition chamber, (C) Increase substrate temperature, and (D) Decrease N ₂ fraction.

For example, it is assumed that the lower layer 32a is formed under the film formation condition 4 (N ₂ fraction: 50%). In this case, according to FIG. 1, in order to form the intermediate layer 32b which is the first phase TiAlN film, (i) the DC power is increased from 2 kW to 3 kW (deposition condition 2). ) Decrease the pressure in the deposition chamber from 12 mTorr to 10 mTorr (deposition condition 3), (iii) Increase the substrate temperature from 200 ° C. to 300 ° C. (not shown), and (iv) N ₂ fraction These operations (i) to (iv) may be performed singly or in combination.

  In this manner, the intermediate layer 32b is formed by changing the sputtering conditions. Then, when the thickness of the intermediate layer 32b reaches about 50 nm, the film formation is stopped again. Thereafter, the sputtering condition changing operation is performed again to return the sputtering conditions to the conditions for forming the lower layer 32a. Under these conditions, the upper layer 32c having a film thickness of about 50 nm is formed.

  Thus, in the conductive barrier layer 32 of this embodiment, the intermediate layer 32b keeps a good barrier property against oxygen. Furthermore, an intermediate layer 32b that is likely to undergo a solid solution reaction with another metal film is sandwiched between a lower layer 32a and an upper layer 32c that are more stable than the intermediate layer 32b. As a result, direct contact between the intermediate layer 32b and the other metal film is prevented, so that it is better between the other metal film than when the conductive barrier layer 32 is made of the first phase TiAlN film alone. A good interface can be maintained.

More specifically, as described in Reference Example 1 , it can be said that the first phase (amorphous) TiAlN film is an AlTi alloy lacking N atoms. Therefore, the first-phase TiAlN film has a large number of unreacted Al atoms and Ti atoms inside. As a result, when the first phase TiAlN film comes into contact with another metal film (for example, the contact plug 12 or the Ir film 16a), a solid solution reaction may occur. When a solid solution reaction occurs, a good interface may not be maintained between the first phase TiAlN film and another metal film.

  On the other hand, in the second phase (crystalline) TiAlN, since Al atoms and Ti atoms are sufficiently nitrided, no solid solution reaction occurs even when they come into contact with other metal films. As a result, the second phase (crystalline) TiAlN can maintain a good interface with other metal films.

  In this embodiment, the laminated structure in which the first-phase TiAlN film (intermediate layer 32b) is sandwiched between two second-phase TiAlN films (lower layer 32a and upper layer 32c) is used as a conductive barrier layer. Although the example used as 32 was shown, this laminated structure can be used also as wiring which electrically connects between elements, for example.

  In this case, the electric resistivity of the first phase TiAlN film is smaller than that of the second phase TiAlN film. Therefore, when viewed as the entire laminated structure, the current flows through the first phase TiAlN film having a low electric resistivity. Selective flow. Therefore, a laminated structure in which the first-phase TiAlN film and the second-phase TiAlN film are stacked is more likely to pass current than a wiring composed of only the second-phase TiAlN film.

  Moreover, since the TiAlN films of the first phase and the second phase have a hydrogen barrier property, they can be suitably used as a wiring for connecting the above-described laminated structure to the upper electrode 20. By doing so, the laminated structure suppresses the diffusion of hydrogen from the upper electrode 20 side toward the capacitor insulating film 18, so that the deterioration of the capacitor insulating film 18 can be prevented.

  In addition, when the laminated structure is used as the wiring, it is not necessary to make the cross-sectional structure a three-layer structure. A second-phase TiAlN film is provided between the first-phase TiAlN film and another metal film, thereby preventing direct contact between the first-phase TiAlN film and the other metal film. In this case, a two-layer structure may be used.

  In the laminated structure, the film that prevents direct contact between the first phase TiAlN film and the other metal film is not limited to the second phase TiAlN film. For example, a TiN film or a TaN film can be used.

  In the formation of the conductive barrier layer 32, when changing the sputtering conditions from the lower layer 32a to the intermediate layer 32b and from the intermediate layer 32b to the upper layer 32c, the sputtering target and the substrate A shutter is preferably interposed between the two. By doing so, it becomes possible to prevent deposition of atoms sputtered on the substrate during a period when the surface of the sputtering target is unstable, and the interface between the lower layer 32a and the intermediate layer 32b and the intermediate layer 32b and the upper layer 32c. The interface becomes clear.

In six different film forming conditions is a view showing the relationship between the electrical resistivity of the deposited TiAlN film and the N ₂ partial rate. (A) And (B) is a figure which shows the analysis result of the XRD of the TiAlN film | membrane of a 1st phase and a 2nd phase, respectively. (A) And (B) is the cross-sectional SEM photograph of the TiAlN film | membrane of a 1st phase and a 2nd phase, respectively. It is a figure which shows the cross section cut of a semiconductor device. It is sectional drawing of the electroconductive barrier layer in a semiconductor device.

10 semiconductor device 12 contact plugs 12a, 24a upper surface 14, 32 conductive barrier layer 14a lower surface 16 the lower electrode 16a Ir film 16b IrO ₂ film 16c Pt electrode 18 the capacitor insulating film 20 upper electrode 22 substrate 22a main surface 24 interlayer insulating film 26 step 32a Lower layer 32b Intermediate layer 32c Upper layer

Claims (3)

A capacitor comprising a conductive barrier layer above the first main surface of the substrate, a lower electrode formed above the conductive barrier layer, and a ferroelectric metal oxide formed above the lower electrode In addition to Ti and Al, the conductive barrier layer includes an amorphous film that may contain N as an optional component, and Ti that is provided one layer above and below across the amorphous film, A semiconductor device having a stacked structure with a crystalline film containing Al and N. The semiconductor device according to claim 1, wherein the amorphous film has a thickness of 20 nm to 150 nm. In manufacturing the semiconductor device according to claim 1 , in the stacked structure, the crystalline film existing below the amorphous film is
(1) DC power related to the sputtering target, (2) atmospheric pressure in the film forming chamber, (3) substrate temperature, and (4) volume ratio of N ₂ gas in the mixed sputtering gas of N ₂ gas and Ar gas, respectively. As a value, the film was formed by reactive sputtering,
Subsequently, the amorphous film is
(A) Sputter condition changing operation for increasing the DC power in (1),
(B) Sputter condition changing operation for reducing the atmospheric pressure in the film forming chamber of (2),
(C) Sputtering condition changing operation for increasing the substrate temperature in (3), and
(D) The film is formed by performing one or more sputtering condition changing operations selected from the group consisting of a sputtering condition changing operation for reducing the volume ratio of the N ₂ gas of (4). A method for manufacturing a semiconductor device.