JP5262865B2 - Double integral type analog-digital converter, digital temperature sensor and digital multimeter using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a double integration type analog/digital converter which is capable of performing accurate A/D conversion without incurring any digital value conversion error. <P>SOLUTION: A double integration type analog/digital converter includes: a constant current source (amplifier 11, transistor M3, M4, M5) capable of generating two kinds of current values; a diode-connected N-channel transistor M1; a second N-channel transistor M2 of which the gate is connected to a gate of the N-channel transistor M1; an integrator 12 including a capacitor C1 connected in parallel; switches S1-S4 as illustrated; an oscillator 14; a counter 16 which is counted up by the oscillator 14; a control circuit 15 for alternatively selecting voltage values generated by the switches S1-S4 and the constant current source; a comparator 13; a register 17; and a means (delay circuit using a counter or a capacitor) for conducting the switch S4 after the lapse of a fixed time from conduction of the switch S1. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to an analog-digital converter, and more particularly, to a double integration type analog-digital converter suitable for converting an analog signal that does not change rapidly into a digital signal. The double integral type analog-digital converter according to the present invention can be applied to, for example, a digital temperature sensor or a digital multimeter capable of measuring DC voltage, AC voltage, DC current, AC current, resistance, and the like with one unit.

  In an analog-digital mixed semiconductor device, an electronic circuit that converts a continuous analog signal such as a voltage into a digital signal that is a discrete signal is generally called an analog-digital converter (AD converter). As for the AD converter, for example, Japanese Patent Laid-Open No. 3-2901033 (Patent Document 1) discloses “AD conversion method and AD converter” capable of high-speed conversion with high accuracy while suppressing cost and power consumption. .

  There are various types of AD converters such as a ΔΣ type, a parallel comparison type, a successive approximation type, and a double integration type. The ΔΣ type is used for applications that convert high-frequency analog signals to digital signals, such as audio, and is typically used for applications that convert analog signals that do not change much in a short time, such as temperature, to digital signals. An integral type is used. The present invention relates to the latter double integration type AD converter.

First, the outline of the double integration AD converter technology will be described with reference to the drawings.
FIG. 9 is a diagram showing an outline of a double integration type AD converter.
As shown in the figure, the double integration AD converter (ADC) 10 receives an analog voltage Vin as an input and outputs a digital value OUT as an output.

  A reference voltage Vref is supplied to the double integration AD converter (ADC) 10. The reference voltage Vref is a voltage that does not depend on the input voltage Vin or the temperature of the semiconductor integrated circuit on which the double integration AD converter is mounted.

  FIG. 10 is a diagram showing details of an internal circuit of the double integration AD converter (ADC) 10 shown in FIG.

  In the double integration type AD converter, as shown in the figure, the voltage applied to the + input terminal can be alternatively changed to one of two voltages Vin or Vref by complementary switches S5 and S6, respectively. A voltage-current conversion circuit including an amplifier 111 having a resistor R connected between the ground and the input terminal and an output connected to the gate of the N-channel transistor M3, and a diode-connected P-channel transistor M4 An integration having a current mirror circuit for copying the flowing current to the P-channel transistor M5, and a switch C4 connected to the bias voltage Vr having a + input terminal and connected in parallel to the capacitor C1 as a negative feedback capacitor and the capacitor C1. And a switch for connecting the drain of the P-channel transistor M5 and the negative input terminal of the integrator. H3, a switch S1 connecting the P-channel transistor M5 and the N-channel transistor M1, a switch S2 connecting the negative input terminal of the integrator and the N-channel transistor M2, an oscillator (OSC) 14, and an oscillator (OSC ) Counter 1 16 that is counted up by 14, register 17 that holds the result of the AD conversion value, ON / OFF control of switches S 1 to S 6, control circuit 15 that controls the counter 116, and + input terminal Is connected to the output of the integrator 12, the negative input voltage is applied to the negative input terminal of the integrator 12, and the output of the comparator 13 is input to the control circuit 15. Has been.

  The switches S1 and S2 are connected to the control circuit 15 via the control line A, the switch S3 is connected to the control circuit 15 via the control line B, and the switch S4 is connected via the control line C. The complementary switches S5 and S6 are connected to the control circuit 15 via the control line D, and the counter 1 is connected to the control circuit 15 via the control lines E and F.

  Now, each of the switches S1, S2, S3, and S4 is turned on when the H signal is given from the control circuit 15, and is turned off when the L signal is given from the control circuit 15. For the complementary switches S5 and S6, when the H signal is inputted from the control circuit 15, the switch S5 is turned on and the switch S6 is turned off. Conversely, when the L signal is inputted from the control circuit 15, the switch S5 is turned on. Is turned off and the switch S6 is turned on.

  When the L signal is input from the control circuit 15, the switch S5 is turned off and the switch S6 is turned on.

  Further, when the L signal is input from the control circuit 15 to the R terminal of the counter 116 via the control line E, the counter 116 is reset, and when the H signal is input, the counter 116 is reset from the reset state. Opened.

  When the H signal is input to the counter 116 via the control line F, the value held by the counter 116 is sent to the register 17. The N channel transistor M1 and the N channel transistor M2 have a current mirror configuration. The double integration AD converter converts the analog voltage Vin input through three phases into a digital value OUT and outputs the digital value OUT.

(First phase)
FIG. 10 shows a circuit state immediately after the start of the first phase.
Immediately after the start of the first phase, the switches S1 and S2 are ON, and the switches S3 and S4 are OFF. Further, Vin is applied to the + input terminal of the amplifier 1 existing in the voltage-current conversion circuit by turning on the switch S5 and turning off the switch S6.

  Therefore, the constant current (Vin / R) generated by the voltage-current conversion circuit is current-mirrored by the P-channel transistors M4 and M5, and the current flowing into the N-channel transistor M1 is current-mirrored by the N-channel transistor M2. Is subtracted from the integrator. As a result, the capacitor C1 is charged with the current (Vin / R) generated by the constant current source. At the start of charging the capacitor C1, the value of the counter 1 is 0, and is counted up by the oscillator immediately after the start of charging.

  When the value of the counter 116 reaches Δc determined at the time of design, the switches S1 and S2 are turned OFF, and charging of the capacitor C1 is completed, and the first phase is completed. If the output waveform period of the oscillator is T and the capacitor C1 in the integrator has no capacitance-voltage dependency, the integrator output voltage at the end of the first phase is expressed by the following (Equation 1).

第１フェーズ終了直後より、第２フェーズに遷移する。

Transition to the second phase immediately after the end of the first phase.

(Second phase)
The state of the circuit in the second phase is shown in FIG. In the second phase, first, the counter 1 is reset when the control line E changes from the H state to the L state, and at the same time, the control line D transitions from the H state to the L state. When the switch S3 is turned on after the voltage Vref is applied to the positive input terminal of the amplifier 1 in the voltage-current conversion circuit and turned on, the constant current (Vref / R) generated by the voltage-current conversion circuit is changed to the P-channel transistor. Since the current flows into the capacitor C1 in the integrator circuit through M5, the charge charged in the capacitor C1 starts to be discharged in the first phase.

  At the same time as the discharge of the charge charged in the capacitor C1 is started, the control line E changes from the L state to the H state, so that the counter 1 is released from the reset state and counted up again.

  When all the electric charge accumulated in the capacitor C1 is discharged, that is, at the moment when the output of the integrator becomes Vr, the output of the comparator changes from H to L, which is input to the control circuit 15. At the same time, the counter 1 counts up, and when the control line F becomes H, the value of the counter 1 is sent to the register.

  After the value of the counter 116 is taken into the register, the control line F becomes the L state again. Here, the second phase ends. The state transitions to the third phase immediately after the end of the second phase.

(Third phase)
FIG. 12 shows the circuit state of the third phase. In the third phase, the switches S1, S2, and S3 are turned off, and the switch S4 is turned on for a time necessary to completely set the charge of the capacitor C1 to zero. At the same time, the counter 1 is reset, the switch S6 is turned off, and the switch S5 is turned on.

  Immediately after that, the state transits again to the state of the first phase. 13A and 13B show the state of each element of the double integration AD converter circuit through the first phase, the second phase, and the third phase.

  In the second phase, the counter 1 measures the time from the start to the end of the charge discharge from the integrator capacitor C1. When the value held in the counter 1 when the discharge from the capacitor C1 ends is Δx, the following (Equation 2) is established.

（数２）より下記（数３）が導かれる。

The following (Equation 3) is derived from (Equation 2).

この（数３）は、該ＡＤコンバータに入力された電圧Ｖｉｎ が下記（数４）に示す数値に変換されることを示している。

This (Equation 3) indicates that the voltage Vin input to the AD converter is converted into the numerical value shown in the following (Equation 4).

  Here, unmatching such as a Vth manufacturing error and a finished dimension error of the N-channel transistor M1 and the N-channel transistor M2 constituting the current mirror pair necessarily occurs. As a result, the current I (M1) flowing through the N-channel transistor M1 and the current I (M2) flowing through the N-channel transistor M2 do not completely coincide with each other, and some error occurs.

  When the channel width of the N-channel transistor M1 is W1 and the channel length is L1, the drain voltage of the N-channel transistor M1 is equal to the following (Equation 5), but the drain voltage of the N-channel transistor M2 is approximately integrated. It is equal to the bias voltage Vr applied to the + input terminal in the device.

  Therefore, the N-channel transistor M1 and the N-channel transistor M2 have different drain-source voltages, and the current I (M1) and the current I (M2) do not match due to the channel length modulation effect. When I (M1) ≠ I (M2), an error occurs in the digital output value of the AD converter.

  Now, when an error of k% occurs between I (M2) and I (M1), that is, when expressed as I (M2) = (0.01k + 1) I (M1), I (M2) = I ( Compared to the case of M1), an error occurs in the digital output value of the AD converter by the following (Equation 6). FIG. 14 is a diagram illustrating a conversion error of the AD converter caused by an error of k% occurring in I (M2) and I (M1).

  By making the areas of the N-channel transistor M1 and the N-channel transistor M2 as large as possible, unmatching caused by Vth manufacturing errors, finished dimensional errors, etc. of the N-channel transistors M1 and M2 constituting the current mirror can be reduced. it can.

  Further, for the error of the currents I (M1) and I (M2) due to the channel length modulation effect of the N channel transistor M1 and the N channel transistor M2, the L length of the N channel transistor M1 and the N channel transistor M2 is increased. Thus, the difference between I (M1) and I (M2) can be reduced.

  Alternatively, as shown in FIG. 3, an N-channel transistor M6 is inserted between the N-channel transistor M1 and the switch S1, and an N-channel transistor M7 is inserted between the N-channel transistor M2 and the switch S2. When an appropriate bias voltage is applied to the gate of the channel transistor M7, the N-channel transistor M2 and the N-channel transistor M7 form a low voltage cascode. This low voltage cascode can eliminate the channel length modulation effect generated in the N-channel transistor M1 and the N-channel transistor M2.

  However, the larger the areas of the N-channel transistor M1 and the N-channel transistor M2 of the current mirror transistor, the larger the gate-drain capacitance and the drain-substrate capacitance of the N-channel transistor M1. In general, the gate-drain capacitance and the drain-substrate capacitance of a MOS transistor can be expressed by the following (Equation 7) and (Equation 8).

ただし、
Ｃｏｘ：単位面積あたりのゲート−チャネル間容量
Ｃｏｖ：単位面積あたりのゲート−ドレイン間容量
Ｅ：ドレイン領域のチャネル方向の長さ
Ｃｊｓｗ：ドレインと基板間の接合においてドレイン周囲長−基板間の単位側壁容量
Ｃｊ：ドレインと基板間の接合においてドレイン底面−基板間に関する単位容量
Ｃｊｏ：ドレインと基板間の接合において逆バイアス電圧が０のときのドレイン底面−基板間の単位容量。
である。

However,
Cox: gate-channel capacitance per unit area Cov: gate-drain capacitance per unit area E: length of drain region in channel direction
Cjsw: drain peripheral length at the junction between the drain and the substrate-unit side wall capacitance between the substrates Cj: unit capacitance between the drain bottom surface and the substrate at the junction between the drain and the substrate Cjo: zero reverse bias voltage at the junction between the drain and the substrate The unit capacitance between the drain bottom surface and the substrate when.
It is.

  Cj can be generally expressed by the following (Equation 9).

  As the gate-source capacitance Cgs and the drain-substrate capacitance Cdb of the N-channel transistor M1 increase, the settling of the drain voltage of the N-channel transistor M1 ends after the switch S1 is turned on at the start of the first phase. Will be longer. When the settling time of the drain voltage of the N-channel transistor M1 is Tset, the following relational expression is established.

  Here, in the conventional example configured by the circuit shown in FIG. 10 (or FIGS. 11 and 12), the capacitor C1 of the integrator immediately after the start of the first phase, that is, while the drain voltage of the N-channel transistor M1 is settling. In this case, charging is started, and this causes a digital value conversion error. FIG. 15 is a diagram showing this.

  Therefore, the present invention provides a double integration type analog-digital converter capable of performing accurate AD conversion without causing the above-described digital value conversion error, a digital temperature sensor using the double integration type analog-digital converter, and a digital multimeter. For the purpose.

The present invention employs the following configuration in order to achieve the above object.
a) A double integration type analog-digital converter according to the present invention includes a constant current source capable of generating two kinds of current values, a first N-channel transistor whose gate and drain are diode-connected, A second N-channel transistor connected to the gate of the first N-channel transistor, a positive input terminal connected to a bias voltage, a first capacitor as a negative feedback capacitor, and in parallel with the first capacitor An integrator composed of a first switch connected to, a second switch connecting between the constant current source and the negative input terminal of the integrator, and connecting between the constant current source and the drain of the first N-channel transistor. A third switch, a fourth switch for connecting the negative input terminal of the integrator and the second N-channel transistor, and an output for outputting a clock signal having a predetermined frequency. , A first counter counted up by the oscillator, and a control circuit having a function of selecting one of a voltage value generated by each of the first switch to the fourth switch and the constant current source. And the output of the integrator is connected to the + input terminal, the same voltage as the bias voltage applied to the integrator is applied to the-input terminal, and held in the first counter and the comparator whose control circuit is connected to the output And a register for storing the result of analog-digital conversion, and means for turning on the fourth switch after a certain time after the third switch is turned on.

b) The means for conducting the fourth switch after a certain time after the third switch is conducted is the time from the input of the signal for conducting the third switch to the output of the signal for conducting the fourth switch. The delay time is controlled by the second counter, or the time from when the signal for turning on the third switch is input until the signal for turning on the fourth switch is output to the second capacitor is predetermined. It is characterized by being constituted by a delay circuit that is controlled according to the charge time.

c) a third N-channel transistor whose source terminal is grounded, whose gate and drain are diode-connected, and whose shape is the same as that of the first N-channel transistor, and the same current as that generated by the constant current source flows. , The + input terminal is connected to the third capacitor, the − input terminal is short-circuited to its output, and the fifth switch that connects between the gate of the third N-channel transistor and the + input terminal of the amplifier And a sixth switch for connecting between the output of the amplifier and the gates of the first and second N-channel transistors, and when no current flows through the first and second N-channel transistors, the first and second The N-channel transistor has a gate potential of a sample hole constituted by an amplifier, a third capacitor, a fifth switch, and a sixth switch. It is characterized by being held by the circuit.

d) Further, the digital temperature sensor and the digital multimeter according to the present invention are characterized by using the double integral type analog-digital converter as described above.

  According to the present invention, a delay circuit configured by a counter circuit or a delay circuit configured by a capacitor, a current source, and other peripheral circuits is used. The analog-to-digital conversion error can be reduced by turning ON the.

  Further, by using the sample and hold circuit, the N channel transistor M1 drain voltage at the start of the first phase is maintained by keeping the drain voltage of the N channel transistor M1 at the second phase the same as the drain voltage at the first phase. In any case, the problems of the conventional example can be solved and AD conversion can be accurately performed.

It is a figure which shows the example of a delay circuit which produces delay time with an asynchronous counter. It is a figure which shows the structural example which incorporated the delay circuit in the prior art example. It is a figure which shows the example which eliminated the channel length modulation effect by the low voltage cascode structure. It is a figure which shows the state of each device at the time of operation | movement of the circuit in FIG. 2 (waveform diagram). It is a figure which shows the state of each device at the time of operation | movement of the circuit in FIG. 2 (meaning of a waveform diagram). It is a figure which shows the implementation example of the 2nd delay circuit by capacitor | condenser charge. It is a figure which shows the Example which uses a sample hold circuit (1st phase). It is a figure which shows the Example using a sample hold circuit (2nd phase). It is the block diagram which incorporated the 2nd delay circuit in the double integration circuit of a prior art example. It is a figure which shows the outline | summary of a double integral type AD converter. It is a figure which shows the detail of the internal circuit of a double integral type AD converter (just after the 1st phase start). It is a figure which shows the detail of the internal circuit of a double integral type AD converter (2nd phase). It is a figure which shows the detail of the internal circuit of a double integral type AD converter (3rd phase). It is a figure which shows the state of each element of the double integral type AD converter circuit through a 1st phase, a 2nd phase, and a 3rd phase (waveform diagram). It is a figure which shows the state of each element of the double integral type AD converter circuit through a 1st phase, a 2nd phase, and a 3rd phase (meaning of a waveform diagram). It is a figure which shows the conversion error of AD converter caused when the error of k% has arisen in the electric current I (M1) and the electric current I (M2) in the N channel transistor M1 and the N channel transistor M2. FIG. 5 is a diagram showing that a digital value conversion error is generated by starting charging the capacitor C1 of the integrator immediately after the start of the first phase, that is, while the drain voltage of the N-channel transistor M1 is settling.

  In the present invention, in order to perform accurate AD conversion without causing a digital value conversion error, the fourth switch is turned on after a predetermined time after the third switch is turned on by a delay circuit using a counter or a capacitor. Is. Further, the settling is eliminated by using a sample hold.

  Hereinafter, (1) as an embodiment using a delay circuit to turn on the fourth switch after a certain time after the third switch is turned on, the first embodiment using the delay circuit by the counter and the delay circuit by the capacitor are used. Example 2 and Example (2) Example 3 using a sample hold as an example in which the gate voltages of the current mirror transistors M1 and M2 are given from the outside in the second phase will be described with reference to the drawings.

(1) <Embodiment using a delay circuit to turn on the fourth switch after a certain period of time after turning on the third switch>
In the conventional example, the switches S1 and S2 are simultaneously changed from the OFF state to the ON state in the first phase. However, in this embodiment, after the switch S1 is turned on, the switch S2 is turned on after a predetermined time has elapsed. The problem of the conventional example is solved by adding a delay time generation circuit (hereinafter referred to as a delay circuit).

(1a) <Embodiment 1 using delay circuit with counter>
FIG. 1 is a diagram illustrating an example of a delay circuit that generates a delay time by an asynchronous counter. FIG. 2 is a diagram showing a configuration example in which the delay circuit is incorporated in a conventional example. The delay circuit 1 has an input IN for receiving an input from the control circuit 15, an input CLK for receiving a clock from an oscillator (OSC) 14, and an output OUT.

  The output OUT of the delay circuit 1 is connected to the R terminal of the counter via the switch S8, and the control line E is connected to the R terminal of the counter via the switch S7.

  The switches S7 and S8 constitute complementary switches. When the control line A is in the H state, the switch S8 is in the ON state, and when the control line A is in the L state, the switch S7 is in the ON state.

  As shown in FIG. 1, the delay circuit includes an asynchronous counter 2 composed of n delay flip-flops, and a delay flip-flop DFF having the input CLK of the delay circuit as an input and corresponding to the first bit of the counter. The buffer BUF1 driving the C terminal of (1) and the C terminal and Q terminal driven by the terminal of the delay flip-flop DFF (n) indicating the most significant bit of the asynchronous counter with the D terminal connected to the power supply The (N + 1) th flip-flop DFF (n + 1) connected to the output OUT of the delay circuit, the negative logic reset terminal connected to the input IN of the delay circuit, and the / Q terminal of the (D + 1) -th flip-flop C terminal driven by the output of BUF1 driven by (inverting terminal of Q) The n + 2th flip-flop DFF (n + 2) whose delay circuit input IN is connected to the negative logic reset terminal, the input IN of the delay circuit is connected to the first input, and the n + 2th flip-flop The AND circuit AND1 has a Q terminal connected to the second input and an output connected to the negative logic reset terminals of n delay flip-flops constituting an asynchronous counter.

  The delay flip-flop DFF constituting the asynchronous counter takes in data at the rising clock, and the delay flip-flop is reset when an L signal is input to the reset terminal. It is assumed that the period of the clock input from the CLK terminal is T.

  Immediately after the start of the first phase, an H signal is sent from the control circuit 15 to the input IN of the delay circuit 1 through the control line A, so that the reset of DFF (n + 1) and DFF (n + 2) is released at the same time as the switch S1 is turned on.

  After resetting DFF (n + 1) and DFF (n + 2), the Q terminal of DFF (n + 2) changes from L to H after one clock cycle of the oscillator (OSC) 14, and the output OUT of AND1 changes from L to H. The reset of DFF (n) from the DFF (1) constituting the counter 2 is released.

The count-up starts immediately after that. The Q terminal of DFF (n + 1), that is, the output of the delay circuit 1 transitions from L to H after 2 ⁿ T-T after the count-up start. Therefore, since the switch S2 is turned on and the H signal is input from the output OUT of the delay circuit 1 to the R terminal of the counter 1 through the control line G, the counter 1 is released from the reset state. Therefore, the capacitor C1 of the integrator starts to be charged and starts counting up at the same time.

  The Q terminal of DFF (n + 2) transitions from H to L one cycle after the output of the delay circuit transitions from L to H, and at the same time, the output of AND1 transitions from H to L so that the counter in the delay circuit All the n DFFs constituting 2 are reset. The state of each device during the above operation is shown in FIGS.

The counter 2 in the delay circuit does not operate until the first phase is completed, and the counter 2 in the delay circuit is always in the reset state because the switch S1 is OFF in the second and third phases. Does not work. Therefore, after the switch S1 is turned on, that is, the H signal is input to the delay circuit, and the T signal is output from the output of the delay circuit after T−T ⁿ T−T = 2 ⁿ T. I was able to.

Note that it takes about T ⁿ T−T from the time when the reset of the DFF constituting the counter 2 is released to the transition of the output of the delay circuit 1 from the L signal to the H signal, which is based on the settling time Tset of the gate potential of the transistor M1. Therefore, the number n of DFFs constituting the counter 2 must satisfy the following (Equation 11).

ただし遅延回路内のカウンター２のレイアウト面積を最小にするためｎは（数１１）を満たす最小のｎにする。

However, in order to minimize the layout area of the counter 2 in the delay circuit, n is set to the minimum n satisfying (Equation 11).

(1b) <Embodiment 2 using delay circuit by capacitor charging>
FIG. 5 is a diagram showing an embodiment of a second delay circuit using capacitor charging.
The delay circuit 2 has two terminals, an input IN and an output OUT. The delay circuit includes an inverter INV1 whose input is connected to the input IN, an N-channel transistor M9 whose source is grounded, whose gate is connected to the output of INV1, whose drain is connected to the drain of the P-channel transistor M8, and whose gate is A P-channel transistor M8 connected to the output of INV1, an inverter INV2 whose input is connected to the drain of the grounded capacitor C2, P-channel transistor M8 and N-channel transistor M9, and a first input connected to the output of INV1 The second input is connected to the output of INV2, the output is the NOR circuit NOR that becomes the output terminal OUT of the delay circuit, the gate is connected to the output of INV2, the source is connected to the power supply, and the drain is the P channel A P-channel transistor M10 connected to the source of transistor M8; Flow is composed of a constant current source that is by i.

  When the switch S1 is turned on, that is, when an H signal is input to the input IN of the delay circuit, a current flows from the constant current source to the capacitor C2 via the P-channel transistor M8.

  When the drain voltage of the P-channel transistor M8 (or the drain voltage of the N-channel transistor M9) exceeds the threshold voltage of the inverter INV2, the OUT terminal of the delay circuit changes from L to H. At the same time, the P-channel transistor M10 is fully turned on, and the capacitor C2 is charged all at once by the current flowing through the P-channel transistor M10, not from the constant current source.

  Therefore, the delay circuit has a function of outputting an H signal from the OUT terminal of the delay circuit after being delayed by an amount of time until the input voltage of INV2 becomes the threshold voltage of INV2 after the H signal is input to IN. The delay time Tdelay by the delay circuit is expressed by the following (Equation 12) when the current value of the constant current source is i and the threshold voltage of INV2 is Vdd / 2, and can be written as (Equation 13).

当然Ｔｓｅｔ≦Ｔｄｅｌａｙとなるように定電流源ｉとコンデンサＣ２は設計される。

Naturally, the constant current source i and the capacitor C2 are designed so that Tset ≦ Tdelay.

  FIG. 8 is a configuration diagram in which the second delay circuit is incorporated in a conventional double integration circuit. In order to eliminate the influence of the channel length modulation effect, the circuit of FIG. 3 to which the low voltage cascode circuit is added also needs to add a delay circuit. Also in the case of the low-voltage cascode circuit shown in FIG. 3, the first delay circuit 1 or the second delay circuit 2 is inserted between the switch S1 and the switch S2 as in the case of FIG. 2 or FIG.

(2) <Example in which the gate voltage of the current mirror transistors M1 and M2 is applied from the outside in the second phase>
In the conventional double integration AD converter shown in FIG. 11, the drain voltages of the current mirror transistors M1 and M2 are in a floating state during the second phase, and the drain of the N-channel transistor M1 immediately after the first phase starts. It took a certain time Tset until the voltage settling was completed. Here, during phase 2, by applying the same voltage as the voltage generated in the first phase to the gates of the N-channel transistor M1 and the N-channel transistor M2, the gate voltage of the N-channel transistor M1 immediately after the start of the first phase Prevent settling.

(2a) <Embodiment 3 using sample hold circuit>
FIG. 6 is a diagram showing an embodiment using a sample and hold circuit.
Compared with the circuit of the conventional example, the P-channel transistor M11 for turning back the current generated in the constant current source circuit, the source terminal is grounded and diode-connected, and the drain of the P-channel transistor M11 is connected. An N-channel transistor M12 whose N is the same as the N-channel transistor M1, an amplifier whose + input terminal is connected in parallel to the grounding capacitor C2 and the switch S9, and whose −input terminal is short-circuited to the output; A switch S9 connecting the gate of M12 and the positive input terminal of the amplifier, and a switch S10 connecting the output of the amplifier and the gates of the N-channel transistor M1 and the N-channel transistor M2 are added.

  The amplifier connected to the switch S9, the switch S9, the capacitor C2, and the switch S10 function as a sample and hold circuit. FIG. 6 shows the state of the first phase.

  In the first phase, the switch S9 is ON and the switch S10 is OFF. The same current as that flowing into the N-channel transistor M1 is current mirrored by the P-channel transistor M11 and flowing into the N-channel transistor M12. Therefore, a charge corresponding to the same voltage as the drain voltage of the N-channel transistor M1 is stored in the capacitor C2.

  In the phase 2 state, as shown in FIG. 7, the switch S9 is turned off and the switch S10 is turned on, so that the drain voltage of the N-channel transistor M1 is the drain voltage of the N-channel transistor M1 in the first phase. Is retained. In the third phase, the switch S9 is turned on and the switch S10 is turned off. Therefore, the drain voltage of the N-channel transistor M1 does not settle at the start of the first phase.

  To summarize the effects of this embodiment, in the double integration AD converter shown in FIG. 10, when the N-channel transistor M1 and the N-channel transistor M2 constituting the current mirror have a large area, the N-channel transistor M1 Due to the parasitic capacitance of the N-channel transistor M2, it takes a certain amount of time for the drain voltage settling of the N-channel transistor M1 to end at the start of the first phase. Therefore, since the capacitor C1 of the integrator is charged during the settling of the drain voltage of the N-channel transistor M1, there is a problem that an error is caused in the digital conversion value.

  Therefore, as a first embodiment, the switch S2 is turned on after a predetermined time from the time when the switch S1 is turned on by a delay time generation circuit constituted by a counter circuit. As the second embodiment, a delay circuit constituted by a capacitor, a current source, and other peripheral circuits realizes the same thing as the first embodiment. In the third embodiment, the N-channel transistor M1 drain voltage at the second phase is kept the same as the drain voltage at the first phase by the sample and hold circuit, so that the N-channel transistor M1 at the start of the first phase is maintained. Eliminates drain voltage settling. Each of the first to third embodiments solves the problems of the conventional example and makes it possible to accurately perform AD conversion.

  As described above, the double integration type analog-digital converter according to the present invention can accurately perform AD conversion, so that it can be applied to various technical fields that require AD conversion that requires high accuracy. it can.

  For example, it is particularly suitable when applied to a digital temperature sensor that requires high accuracy and a digital multimeter that can measure DC voltage, AC voltage, DC current, AC current, resistance, etc. with a single unit.

10: Double integral AD converter (ADC)
11: Amplifier 1
12: Integrator 13: Comparator 14: Oscillator (OSC)
15: Control circuit 16: Counter 1
17: Register 18: Delay circuit (Ikezumi time generation circuit)
19: Amplifier 2
Vin: input voltage Vref: reference voltage OUT: output M1, M2, M3, M6, M7, M9, M12: N-channel transistors M4, M5, M8, M10, M11: P-channel transistors S1 to S10: switch R: resistor INV1 , INV2: Inverter C1, C2: Capacitor

JP-A-3-2901033

Claims (6)

  A constant current source capable of generating two kinds of current values, a first N-channel transistor whose gate and drain are diode-connected, and a second whose gate is connected to the gate of the first N-channel transistor An N channel transistor, an integrator having a first input connected to a bias voltage, a first capacitor as a negative feedback capacitor, and a first switch connected in parallel to the first capacitor; A second switch that connects between the constant current source and the -input terminal of the integrator; a third switch that connects between the constant current source and the drain of the first N-channel transistor; and- A fourth switch for connecting between the input terminal and the second N-channel transistor, an oscillator for outputting a clock signal having a predetermined frequency, and the oscillator A first counter to be counted up, a control circuit having a function of selecting each of the fourth switch to the voltage value generated by the constant current source from the first switch, and + The output of the integrator is connected to the input terminal, the same voltage as the bias voltage applied to the integrator is applied to the − input terminal, the comparator is connected to the output, and the first counter A double integral type analog digital comprising: a register for storing a held analog-digital conversion result; and a means for conducting the fourth switch after a predetermined time after the third switch is conducted. converter. The double integration type analog-digital converter according to claim 1,
The means for turning on the fourth switch after a certain time after the third switch is turned on is the time from when the signal for turning on the third switch is inputted until the signal for turning on the fourth switch is outputted. A double integration type analog-digital converter characterized by comprising a delay circuit that controls the delay time by a second counter. The double integration type analog-digital converter according to claim 1,
The means for turning on the fourth switch after a certain time after the third switch is turned on is the time from when the signal for turning on the third switch is inputted until the signal for turning on the fourth switch is outputted. A double integration type analog-digital converter characterized by comprising a delay circuit that controls the time according to the time when a predetermined charge is charged in the second capacitor. The double integration type analog-digital converter according to claim 1,
A third N-channel transistor whose source terminal is grounded, whose gate and drain are diode-connected, has the same shape as the first N-channel transistor, and flows the same current as that generated by the constant current source; An amplifier whose input terminal is connected to the third capacitor and whose negative input terminal is short-circuited to its own output, and a fifth switch for connecting between the gate of the third N-channel transistor and the positive input terminal of the amplifier And a sixth switch for connecting between the output of the amplifier and the gates of the first and second N-channel transistors, and when no current flows through the first and second N-channel transistors, the first switch The gate potentials of the first and second N-channel transistors are the amplifier, the third capacitor, the fifth switch, and the sixth switch. Double integration type analog-to-digital converter, characterized in that it is held by the configured sample and hold circuit by pitch.   A digital temperature sensor using the double integral type analog-digital converter according to claim 1.   A digital multimeter using the double integral type analog-digital converter according to any one of claims 1 to 4.

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