JP5246748B2 - Display device and electronic device including the same - Google Patents

Description

  The present invention relates to, for example, a display device and an electronic apparatus including the display device.

  2. Description of the Related Art In recent years, a technology for mounting a photosensor function on a display device, particularly in a liquid crystal display device using a thin film transistor, has been developed (for example, Patent Document 1). The purpose of mounting the optical sensor is (1) to reduce power consumption and improve image quality by measuring external light and adjusting brightness, etc. (2) measuring backlight and adjusting brightness or chromaticity, (3 3) The position of the finger or light pen is recognized and used as a touch key. Examples of the optical sensor include a thin film transistor, a PIN (p-intrinsic-n) diode, and a PN diode. In any case, the light receiving portion is a silicon thin film and does not increase the manufacturing cost. Therefore, it is desirable that the light receiving portion is manufactured in the same manufacturing process as the silicon thin film constituting the display switching element.

JP 2006-118965 A

  From the viewpoint of light illumination measurement accuracy and design, it is preferable to place the photosensor close to the display area of the display device. However, in the liquid crystal display device with a built-in drive circuit, the photosensor is placed inside the drive circuit. Difficult to do. Also, when arranged in this way, the optical sensor is easily affected by the electrical noise of the display area drive, and the influence of stray light from the display area cannot be ignored, so the accuracy of the optical sensor is reduced, In particular, this problem becomes prominent when common potential inversion driving is performed in a liquid crystal display device.

  According to one aspect of the present invention for solving the above-described problems, an active matrix circuit for display, a plurality of bus lines connected to the active matrix circuit and transmitting a driving signal, and driving signals are output to the plurality of bus lines A display device including a driving circuit on a substrate, the optical sensor being provided on the substrate, the optical sensor being arranged in a plurality of sub-regions divided by a plurality of bus lines, wherein the plurality of sub-regions are active matrix The display device is disposed between the circuit and the drive circuit, and is driven to be inverted between the plurality of pixel electrodes connected to the active matrix circuit and the first potential and the second potential lower than the first potential. A common electrode, a liquid crystal element whose alignment state is changed by an electric field applied between the plurality of pixel electrodes and the common electrode, a sensor wiring connected to the photosensor, and an active matrix A plurality of detection circuits for detecting the potentials or currents of the photosensors in a plurality of sub-regions arranged on different sides of the outer periphery of the circuit, and at least two detection results among the detection results of the plurality of detection circuits A plurality of majority circuits that change the output when changed, and the plurality of detection circuits have the same timing and the common electrode has a timing of either the first potential or the second potential. A display device for detecting potential or current is provided.
With such a configuration, even in a display with a built-in drive circuit, the optical sensor can be arranged in the vicinity of the display area, so that the illuminance of outside light can be measured accurately and the degree of design freedom of the mounted electronic device is improved. In addition, while reducing the power consumption of the liquid crystal display device by so-called common AC drive, which reversely drives the common electrode, it prevents electromagnetic noise due to inversion of the common electrode and accuracy degradation due to fluctuations in sensor wiring potential due to coupling capacitance with the common electrode. it can. In addition, since the majority of the results is taken in units of sides, it is possible to detect outside light with higher accuracy without causing malfunction even when a specific side is shaded or when light is applied.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a perspective configuration diagram (partially sectional view) of a liquid crystal display device 910 according to the present embodiment. The liquid crystal display device 910 includes an active matrix substrate 101 and a counter substrate 912 that are bonded to each other with a sealant 923 at a predetermined interval, and a nematic liquid crystal material 922 is sandwiched therebetween. Although not shown, an alignment material made of polyimide or the like is applied onto the active matrix substrate 101 and rubbed to form an alignment film. The counter substrate 912 includes a color filter corresponding to a pixel (not shown), a black matrix 940 made of a low-reflection / low-transmittance resin for preventing light leakage and improving contrast, and an active matrix substrate 101. A counter electrode 930 is formed as a common electrode made of an ITO film that is short-circuited with the counter conductive portion 330 (330-1, 330-2). An alignment material made of polyimide or the like is applied to the surface in contact with the nematic phase liquid crystal material 922, and is rubbed in a direction orthogonal to the direction of the rubbing treatment of the alignment film of the active matrix substrate 101.

  Further, an upper polarizing plate 924 is disposed outside the counter substrate 912, and a lower polarizing plate 925 is disposed outside the active matrix substrate 101, so that the polarization directions thereof are orthogonal to each other (crossed Nicols). Further, a backlight unit 926 and a light guide plate 927 are disposed below the lower polarizing plate 925, and light is emitted from the backlight unit 926 toward the light guide plate 927. The light guide plate 927 activates light from the backlight unit 926. It functions as a light source of the liquid crystal display device 910 by reflecting and refracting light so that it becomes a vertical and uniform surface light source toward the matrix substrate 101. The backlight unit 926 is an LED unit in this embodiment, but may be between cold cathodes (CCFL). The backlight unit 926 is connected to the electronic device main body through the connector 929 and supplied with power. In this embodiment, the amount of light from the backlight unit 926 is adjusted by appropriately adjusting the power source to an appropriate current and voltage. It has a function.

  Although not shown, if necessary, the periphery may be covered with an outer shell, or a protective glass or acrylic plate may be attached further above the upper polarizing plate 924, and optical for improving the viewing angle. A compensation film may be attached.

  In addition, the active matrix substrate 101 is provided with a projecting portion 921 that projects from the counter substrate 912, and an FPC 928 as a flexible substrate is mounted and electrically connected to the signal input terminal 320 in the projecting portion 921. Yes. An FPC 928 as a flexible substrate is connected to the electronic device main body and supplied with necessary power, control signals, and the like.

  Further, on the liquid crystal display device 910, the first first side light receiving opening 991-1 to the third first side light receiving opening 991-3 and the first second side light receiving opening 992-1 to fourth. Second side light receiving opening 992-4, first third side light receiving opening 993-3 to third third side light receiving opening 993-3, first fourth side light receiving opening 994-1 to first. Four fourth side light receiving openings 994-4 are formed by partially removing the black matrix 940 on the counter substrate 912, and external light passes through these openings to form the active matrix substrate 101. It is supposed to reach the top.

  FIG. 2 is a block diagram of the active matrix substrate 101. In the display area 310 on the active matrix substrate 101, 480 scanning lines 201 (201-1 to 201-480) and 1920 data lines 202 (202-1 to 202-1920) are orthogonal to each other as an active matrix circuit. The 480 capacitor lines 203 (203-1 to 203-480) are arranged in parallel with the scanning lines 201 (201-1 to 201-480). The capacitor lines 203 (203-1 to 203-480) are short-circuited to each other, connected to the common potential wiring 335, and further connected to the two opposing conductive portions 330 (330-1 to 330-2) to be signal input terminals. From 320, an inverted signal of 0V-5V and a common potential of 35 μsec are applied. The scanning lines 201 (201-1 to 201-480) are connected to the scanning line driving circuit 301, and the data lines 202 (202-1 to 202-1920) are connected to the data line driving circuit 302 and the precharge circuit 303. Each is driven appropriately. The scanning line driver circuit 301, the data line driver circuit 302, and the precharge circuit 303 are supplied with signals necessary for driving from a signal input terminal 320. The signal input terminal 320 is disposed on the overhang portion 921. The scanning line driving circuit 301, the data line driving circuit 302, and the precharge circuit 303 are formed by integrating polysilicon thin film transistors on the active matrix substrate 101, and will be described later as a pixel switching element 401 (401-nm). Is a liquid crystal display device with a built-in drive circuit manufactured in the same process.

  In addition, in a region sandwiched between the scanning line driving circuit 301 and the display region 310, first edge light sensors 351-1 to 351-480 as 480 light sensors are arranged as light sensors 351. The n-th n-th first side light sensor 351-n is disposed in a region (an example of a sub-region) between the scanning line 201-n and the scanning line 201-n + 1. Here, the 81st first side light sensor 351-81 to the 160th first side light sensor 351-160 include the first first side light receiving opening 991-1 and the 241st first side light sensor 351. The -241 to 320th first side light sensors 351-320 include the second first side light receiving opening 991-2 and the 401st first side light sensors 351-401 to 480th first side light sensors 351. -480 is arranged so as to overlap the third first side light receiving opening 991-3 in plan view. The n-th first side light sensor 351-n that planarly overlaps any one of the first first-side light receiving opening 991-1 to the third first-side light receiving opening 991-3 is collectively referred to as a first. This is called a side light receiving sensor group. In addition, the first side light receiving opening 991-1 to the third first side light receiving opening 991-3 are collectively referred to as the first side light sensor 351-n that does not overlap any of the first side light receiving opening 991-1 to the third first side light receiving opening 991-3. This is called a light shielding sensor group.

  Similarly, in a region sandwiched between the precharge circuit 303 and the display region 310, second side light sensors 352-1 to 352-1920 as 1920 light sensors are arranged as the light sensor 352. The nth second side light sensor 352-n is disposed in a region (an example of a sub region) between the data line 202-n and the data line 202-n + 1. Here, the first second side light sensor 352-1 to the 240th second side light sensor 352-240 include the first second side light receiving opening 992-1 and the 481st second side light sensor 352. The second side light sensor 352-720 of −481 to 720 includes the second second side light receiving opening 992-2 and the 961 second side light sensor 352-961 to the first second side light sensor 352. -1200 is a third second side light receiving opening 992-3, and 1441nd second side light sensor 352-1441 to 1680 second side light sensors 352-1680 are fourth second side light receiving openings. 992-4 and each overlap with each other in a plane. The n-th second side light sensor 352-n that planarly overlaps any one of the first second-side light receiving opening 992-1 to the fourth second-side light receiving opening 992-4 is collectively referred to as a second. This is called a side light receiving sensor group. The n-th second side light sensor 352-n that does not overlap any of the first second-side light receiving opening 992-1 to the fourth second-side light receiving opening 992-4 is collectively referred to as the second side. This is called a light shielding sensor group.

  Similarly, 480 third side light sensors 353-1 to 353-480 as light sensors are arranged as light sensors 353 at the peripheral portion facing the scanning line driving circuit 301 and the display area 310. The nth third side light sensor 353-n is disposed in a region between the capacitor line 203-n and the capacitor line 203-n-1. Here, the first third side light sensor 353-1 to the 80th third side light sensor 353-80 include the first third side light receiving opening 993-1 and the 161st third side light sensor 353. The 161-240th third side light sensor 353-240 includes the second third side light receiving opening 993-2 and the 321st third side light sensor 353-321 to the 400th third side light sensor 353. −400 is arranged so as to overlap the third third side light receiving opening 993-3 in plan view. The n-th third side light sensor 353-n that planarly overlaps one of the first third-side light receiving opening 993-1 to the third third-side light receiving opening 993-3 is collectively referred to as a third. This is called a side light receiving sensor group. Also, the third side light sensor 353-n that is not overlapped with any of the first third side light receiving opening 993-1 to the third third side light receiving opening 993-3 is collectively referred to as the third side. This is called a light shielding sensor group.

  Similarly, 1920 fourth side light sensors 354-1 to 354-1920 as light sensors are arranged as light sensors 354 in a region between the data line driving circuit 302 and the display region 310. The nth fourth edge light sensor 354-n is disposed in a region between the data line 202-n and the data line 202-n + 1, respectively. Here, the 241st fourth side light sensor 354-241 to the 480th fourth side light sensor 354-480 include the first fourth side light receiving opening 994-1 and the 721 fourth side light sensor 354. The fourth side light sensor 354-960 of −721 to 960 includes the second fourth side light receiving opening 994-2 and the fourth side light sensor 354-1201 to the first side light sensor 354 of the 1201. -1440 is the third fourth side light receiving opening 994-3, and the 1681th fourth side light sensor 354-1681 to the 1920th fourth side light sensor 354-1920 is the fourth fourth side light receiving opening. 994-4 and each overlap with each other in a plane. The nth fourth side light sensor 354-n that overlaps with any one of the first fourth side light receiving opening 994-1 to the fourth fourth side light receiving opening 994-4 in a plan view is collectively referred to as a fourth. This is called a side light receiving sensor group. Further, the fourth side light sensor 354-n that is not overlapped with any of the first fourth side light receiving opening 994-1 to the fourth fourth side light receiving opening 994-4 is collectively referred to as the fourth side. This is called a light shielding sensor group.

  Here, the first side light receiving sensor group is connected to the wiring SENSE (SENSE1) and the wiring VSH (VSH1). The first side light shielding sensor group is connected to the wiring SENSE1, the wiring VSL (VSL1), and the wiring VDBT (VDBT1). The second side light receiving sensor group is connected to the wiring SENSE (SENSE2) and the wiring VSH (VSH2). The second side light shielding sensor group is connected to the wiring SENSE2, the wiring VSL (VSL2), and the wiring VDBT (VDBT2). The third side light receiving sensor group is connected to the wiring SENSE (SENSE3) and the wiring VSH (VSH3). The third side light shielding sensor group is connected to the wiring SENSE3, the wiring VSL (VSL3), and the wiring VDBT (VDBT3). The fourth side light receiving sensor group is connected to the wiring SENSE (SENSE4) and the wiring VSH (VSH4). The fourth side light shielding sensor group is connected to the wiring SENSE4, the wiring VSL (VSL4), and the wiring VDBT (VDBT4).

  The wiring SENSE1, the wiring VSH1, the wiring VSL1, and the wiring VDBT1 are connected to the first detection circuit 360-1 as the detection circuit 360. The wiring SENSE2, the wiring VSH2, the wiring VSL2, and the wiring VDBT2 are connected to the second detection circuit 360-2 as the detection circuit 360. The wiring SENSE3, the wiring VSH3, the wiring VSL3, and the wiring VDBT3 are connected to the third detection circuit 360-3 as the detection circuit 360. The wiring SENSE4, the wiring VSH4, the wiring VSL4, and the wiring VDBT4 are connected to the fourth detection circuit 360-4 as the detection circuit 360.

Output wiring OUT1 from the first detection circuit 360-1, output wiring OUT2 from the second detection circuit 360-2, output wiring OUT3 from the third detection circuit 360-3, and fourth detection circuit 360-4 Is connected to the majority circuit 370, and the output wiring OUT from the majority circuit 370 is connected to an external circuit through one of the signal input terminals 320.

  FIG. 3 is a circuit diagram in the vicinity of the intersection of the mth data line 202-m and the nth scanning line 201-n in the display area 310. A pixel switching element 401-nm including an N-channel field effect polysilicon thin film transistor is formed at each intersection of the scanning line 201-n and the data line 202-m, and the gate electrode thereof is the scanning line 201-n. The source / drain electrodes are connected to the data line 202-m and the pixel electrode 402 (402-nm), respectively. The pixel electrode 402-nm and the electrode short-circuited to the same potential form a capacitance line 203-n and an auxiliary capacitance capacitor 403 (403-nm), and when assembled as a liquid crystal display device, a liquid crystal element After that, a capacitor is formed with the counter electrode 930 as well.

  FIG. 4 is a block diagram showing a specific configuration of the electronic apparatus in this embodiment. The liquid crystal display device 910 is the liquid crystal display device described in FIG. 1, and the external power supply circuit 784 and the video processing circuit 780 supply necessary signals and power to the liquid crystal display device 910 through the FPC 928 and the connector 929 as flexible substrates. To do. The central processing circuit 781 acquires input data from the input / output device 783 via the external I / F circuit 782. Here, the input / output device 783 is, for example, a keyboard, a mouse, a trackball, an LED, a speaker, an antenna, or the like. The central processing circuit 781 performs various arithmetic processing based on data from the outside, and transfers the result to the video processing circuit 780 or the external I / F circuit 782 as a command. The video processing circuit 780 updates the video information based on the command from the central processing circuit 781 and changes the signal to the liquid crystal display device 910, whereby the display video of the liquid crystal display device 910 changes. The output wiring OUT from the majority circuit 370 on the liquid crystal display device 910 is input to the central arithmetic circuit 781 through the FPC 928 as a flexible substrate, and the central arithmetic circuit 781 corresponds to the pulse length of the binary output signal (OUT). To discrete values. Next, the central processing circuit 781 accesses a reference table 785 comprising an EEPROM (Electronically Erasable and Programmable Read Only Memory), reconverts the converted discrete value into a value corresponding to an appropriate voltage of the backlight unit 926, and external power supply. Transmit to circuit 784. The external power supply circuit 784 supplies a potential power supply having a voltage corresponding to the transmitted value to the backlight unit 926 in the liquid crystal display device 910 through the connector 929. Since the luminance of the backlight unit 926 varies depending on the voltage supplied from the external power supply circuit 784, the luminance of the liquid crystal display device 910 when displaying all white also varies. Here, the electronic devices are specifically monitors, TVs, notebook computers, PDAs (Personal Digital (Data) Assistants), digital cameras, video cameras, mobile phones, mobile photo viewers, mobile video players, mobile DVD players, and mobile audio. Such as a player.

  In this embodiment, the luminance of the backlight unit 926 is controlled by the central processing circuit 781 on the electronic device. For example, the liquid crystal display device 910 includes a driver IC and an EEPROM, and the driver IC has a binary value. A conversion function from the output signal (OUT) to a discrete value, a re-conversion function with reference to the EEPROM, and a function for adjusting the output voltage to the backlight unit 926 may be provided. Further, a configuration may be adopted in which a discrete value is converted into a value corresponding to the voltage of the backlight unit 926 by numerical calculation without using a reference table.

  FIG. 5 is a plan view showing an actual configuration of the circuit diagram of the pixel display region shown in FIG. As shown in the legend of FIG. 5, different shaded parts indicate different material wirings, and the same shaded parts indicate the same material wiring. It is composed of a five-layer thin film of chromium thin film (Cr), polysilicon thin film (Poly-Si), molybdenum thin film (Mo), aluminum-neodymium alloy thin film (AlNd), and indium tin oxide thin film (Indium tin Oxiced = ITO). Thus, an insulating film formed by laminating any one of silicon oxide, silicon nitride, and an organic insulating film is formed between the respective layers. Specifically, the chromium thin film (Cr) has a thickness of 100 nm, the polysilicon thin film (Poly-Si) has a thickness of 50 nm, the molybdenum thin film (Mo) has a thickness of 200 nm, the aluminum-neodymium alloy thin film (AlNd) has a thickness of 500 nm, The indium oxide / tin thin film (ITO) has a thickness of 100 nm. In addition, a base insulating film in which a 100 nm silicon nitride film and a 100 nm silicon oxide film are stacked is formed between the chromium thin film (Cr) and the polysilicon thin film (Poly-Si), and the polysilicon thin film (Poly-Si) and Between the molybdenum thin film (Mo), a gate insulating film made of a 100 nm silicon oxide film is formed. Between the molybdenum thin film (Mo) and the aluminum-neodymium alloy thin film (AlNd), a 200 nm silicon nitride film and a 500 nm oxide film are formed. An interlayer insulating film formed by laminating a silicon film is formed, and a 200 nm silicon nitride film and an average 1 μm organic planarizing film are laminated between an aluminum / neodymium alloy thin film (AlNd) and an indium oxide / tin thin film (ITO). A protective insulating film is formed to insulate the wires from each other, and contact holes are opened at appropriate positions. It is connected to the stomach. In FIG. 5, there is no chromium thin film (Cr) pattern.

  As shown in FIG. 5, the data line 202-m is formed of an aluminum-neodymium alloy thin film (AlNd) and is connected to the source electrode of the pixel switching element 401-nm through a contact hole. The scanning line 201-n is composed of a molybdenum thin film (Mo) and also serves as the gate electrode of the pixel switching element 401-nm. The capacitor line 203-n is made of the same wiring material as the scanning line 201-n, the pixel electrode 402-nm is made of an indium oxide / tin thin film, and a contact hole is formed in the drain electrode of the pixel switching element 401-nm. Connected through. Further, the drain electrode of the pixel switching element 401-nm is also connected to a capacitor electrode 605 made of an n + type polysilicon thin film heavily doped with phosphorus, and overlaps the capacitor line 203-n in plan view to form an auxiliary capacitor. Condenser 403-nm is formed.

  FIG. 6 is a diagram showing a partial cross-sectional structure of the liquid crystal display device 910 corresponding to the AA ′ line portion of FIG. 5 for explaining the structure of the pixel switching element 401 -nm. Note that the scale is not constant in order to make the drawing easier to see. The active matrix substrate 101 is an insulating substrate made of alkali-free glass and having a thickness of 0.6 mm, and is made of a polysilicon thin film through a base insulating film in which a 200 nm silicon nitride film and a 300 nm silicon oxide film are stacked on the substrate. A silicon island 602 is arranged, and the scanning line 201-n is arranged above the silicon island 602 and the gate insulating film. In the region overlapping with the scanning line 201-n, the silicon island 602 is an intrinsic semiconductor region 602I in which phosphorus ions are not doped at all or only in a very low concentration, and a sheet resistance of about 20 kΩ in which phosphorus ions are lightly doped on the left and right sides thereof. This is an LDD (Lightly Doped Drain) structure in which n-regions 602L exist and n + regions 602N having a sheet resistance of about 1 kΩ doped with phosphorus ions at a high concentration are present on the left and right sides thereof. The left and right n + regions 602N are connected to the source electrode 603 and the drain electrode 604 through contact holes, the source electrode 603 is connected to the data line 202-m, and the drain electrode 604 is connected to the pixel electrode 402-nm. ing. A nematic phase liquid crystal material 922 exists between the pixel electrode 402-nm and the counter electrode 930 as a common electrode on the counter substrate 912. In addition, a black matrix 940 is formed over the counter substrate 912 so as to partially overlap with the pixel electrodes 402-nm. In the case where the light leakage current of the pixel switching element 401-nm becomes a problem, a light shielding layer made of a Cr film may be formed under the silicon island 602. In this embodiment, the light leakage current is hardly a problem, and if such a structure is adopted, the mobility of the pixel switching element 401-nm is lowered, and therefore a configuration in which the Cr film under the silicon island 602 is removed is selected. did.

  FIG. 7 is a diagram showing a partial cross-sectional structure of the liquid crystal display device 910 with respect to the line BB ′ in FIG. 5 for explaining the structure of the auxiliary capacitor 403-nm, and the capacitance connected to the drain electrode 604. The storage electrode is formed by overlapping the partial electrode 605 and the capacitor line 203-n with the gate insulating film interposed therebetween.

  FIG. 8 is an enlarged plan view of an nth first side light sensor 351-n which is one of the first side light receiving sensor groups. The legend is the same as in FIG. 9 is a diagram showing a partial cross-sectional structure of the liquid crystal display device 910 corresponding to the line CC ′ line portion of FIG. The n-th first side light sensor 351-n is formed by an anode region 610P (610P-n), an intrinsic region 610I (610I-n), and a cathode region 610N (610N-n). The anode region 610P-n, the intrinsic region 610I-n, and the cathode region 610N-n are all suitable for the same island pattern made of the same polysilicon thin film (Poly-Si) that forms the pixel switching element 401-nm. Each is formed by performing a simple impurity implantation. Specifically, boron ions are implanted into the anode region 610P-n at a high concentration to adjust the sheet resistance to about 2 kΩ, and phosphorus ions are implanted into the cathode region 610N-n at a high concentration to reduce the sheet resistance to about 1 kΩ. It is adjusted to become. In the intrinsic region 610I-n, only a very small amount of boron ions or phosphorus ions are implanted, or not implanted at all, and is formed as an intrinsic semiconductor. In this way, the nth first side light sensor 351-n is formed as a lateral PIN junction diode. The size of the intrinsic region 610I-n is 100 μm in the direction parallel to the bonding surface and 10 μm in the direction perpendicular to the bonding surface.

  The n-th first side light sensor 351-n has the same indium / tin oxide as the light-shielding electrode 611 (611-n) and the pixel electrode 402-n-m made of a chromium thin film (Cr). The transparent shield electrode 612 made of a thin film (ITO) is formed so as to overlap the transparent shield electrode 612-n. The light shielding electrode 611-n functions as a light shielding film that prevents light from the backlight unit 926 from entering the nth first side light sensor 351-n. Further, the transparent shield electrode 612-n prevents a decrease in illuminance detection accuracy due to electromagnetic noise. The nth first side light sensor 351-n overlaps the kth first side light receiving opening 991-k. Since the black matrix 940 on the counter substrate 912 is removed from the kth first side light receiving opening 991-k, external light passes through the kth first side light receiving opening 991-k and the nth first side. It is formed so as to reach the optical sensor 351-n. k is a number corresponding to n, n = 81 to 160 corresponds to k = 1, n = 241 to 320 corresponds to k = 2, and n = 401 to 80 corresponds to k = 3.

  Here, the anode region 610P-n is connected to the anode electrode 615 (615-n) through a contact hole. The cathode region 610N-n is connected to the cathode electrode 616 (616-n) through a contact hole. The light shielding electrode 611-n and the transparent shield electrode 612-n are connected to the BT electrode 617 (617-n) through a contact hole. Although not shown, the anode electrode 615-n is connected to the wiring SENSE1, the cathode electrode 616-n is connected to the wiring VSH1, and the BT electrode 617-n is also connected to the wiring VSH1.

  Note that the n′th first side light sensor 351-n ′, which is one of the first side light shielding sensor groups, does not overlap with the kth first side light receiving opening 991-k, and the anode electrode 615 ( 615-n ′) is connected to the wiring VSL1, the cathode electrode 616 (616-n ′) is connected to the wiring SENSE1, and the BT electrode 617 (617-n ′) is connected to the wiring VDBT1. Since this is the same as the n-th first side light sensor 351-n that is one of the above, the description thereof is omitted.

  In this embodiment, the light shielding electrode 611-n and the transparent shield electrode 612-n are individually islanded and formed so that a gap is formed between them. However, the first side light receiving sensor group and the first side light shielding sensor group are Adjacent locations, i.e., between n = 80 and n = 81, n = 160 and n = 161, n = 240 and n = 241, n = 320 and n = 321, n = 400 And n = 401, since they are the same potential, they may be short-circuited. In any case, stray light from the gap can be prevented by covering the gap between the light shielding electrodes with some metal electrode as in this embodiment, and more preferably, the circuit area can be reduced by using a bus line as the metal electrode.

  FIG. 10 is an enlarged plan view of the m-th second side light sensor 352-m which is one of the second side light receiving sensor groups. The legend is the same as in FIG. The m-th second side light sensor 352-m is formed by an anode region 620P (620P-m), an intrinsic region 620I (620I-m), and a cathode region 620N (620N-m), and the data line 202-m. And the data line 202-m + 1, and overlaps with the jth second side light receiving opening 992-j. j is a number corresponding to m, m = 1 to 240 is j = 1, m = 481 to 720 is j = 2, m = 961 to 1200 is j = 3, m = 1441 to 1680 is This corresponds to j = 4, respectively.

  Anode region 620P-m, intrinsic region 620I-m, and cathode region 620N-m are each an anode region 610P-n, intrinsic region 610I-n, and cathode region of FIG. Since it is the same structure as 610N-n, description is abbreviate | omitted. The m-th second side light sensor 352-m is formed so as to overlap the entire area with the light shielding electrode 621 (621-m) and the transparent shield electrode 622 (622-m). Since it is the same structure as 611-n and the transparent shield electrode 612-n, description is abbreviate | omitted. The anode region 620P-m is an anode electrode 625 (625-m), the cathode region 620N-m is a cathode electrode 626 (626-m), the light shielding electrode 621-m and the transparent shield electrode 622-m are BT electrodes 627. (627-m) are connected to each other through contact holes, which are also the same as the anode electrode 615-n, cathode electrode 616-n, and BT electrode 617-n in FIG. Omitted. The sectional view taken along the line DD ′ in FIG. 10 is not different from the sectional view taken along the line CC ′ in FIG.

  The m′th second side light sensor 352-m ′, which is one of the second side light shielding sensor groups, does not overlap the jth second side light receiving opening 992-j, and the anode electrode 625 ( 625-m ′) is connected to the wiring VSL2, the cathode electrode 626 (626-m ′) is connected to the wiring SENSE2, and the BT electrode 627 (627-m ′) is connected to the wiring VDBT2. This is the same as the m-th second side light sensor 352-m.

  The n-th third side light sensor 353-n is located between the capacitor line 203-n-1 and the capacitor line 203-n, as shown in FIG. 8, as compared with the n-th first side light sensor 351-n. The layout is rotated by 180 degrees, and the portions connected to the wiring SENSE1, the wiring VSH1, the wiring VSL1, and the wiring VDBT1 are the same except that the wiring SENSE3, the wiring VSH3, the wiring VSL3, and the wiring VDBT3 are connected. To do. Similarly, the mth fourth side light sensor 354-m is rotated 180 degrees compared to the mth second side light sensor 352-m, and the wiring SENSE2, the wiring VSH2, Since the portions connected to the wiring VSL2 and the wiring VDBT2 are the same except that the portions connected to the wiring SENSE4, the wiring VSH4, the wiring VSL4, and the wiring VDBT4 are the same, description thereof is omitted.

  FIG. 11 is a circuit diagram showing an nth detection circuit 360-n (n = 1 to 4) as the detection circuit 360. The wiring SMP, the wiring VCHG, the wiring RST, the wiring VSL, and the wiring VSH are connected to the signal input terminal 320, and appropriate potentials and signals are supplied from the external power supply circuit 784. Here, the wiring VCHG is supplied with the potential VVCHG (= 2.0 V), the wiring VSL is supplied with the potential VVSL (= 0.0 V), and the wiring VSH is supplied with the potential VVSH (= 5.0 V). Note that here, the potential VVSL of the wiring VSL is GND of the liquid crystal display device 910. The output wiring OUTn is connected to the majority circuit 370.

  The wiring VDBT (VDBTn) is connected to one end of the first switch SW1, the wiring VSL (VSLn) is connected to one end of the second switch SW2, the wiring VSH (VSHn) is connected to one end of the third switch SW3, and the wiring SENSE ( SENSEn) is connected to one end of the fourth switch SW4. Here, the first switch SW1 to the fourth switch SW4 are constituted by CMOS transmission gates. The other end of the first switch SW1 is connected to the wiring VCHG, the other end of the second switch SW2 is connected to the wiring VSL, the other end of the third switch SW3 is connected to the wiring CSH, and the other end of the fourth switch SW4 is connected to the node SIN. Are connected to each other. The gate electrodes of all the n-channel transistors constituting the first switch SW1 to the fourth switch SW4 are connected to the wiring SMP, and the gate electrodes of all the p-channel transistors are connected to the output terminal of the inverter circuit INV1. . The input terminal of the inverter circuit INV1 is connected to the wiring SMP.

  The node SIN is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the node A. The source electrode of the initialization transistor NC is connected to the wiring VCHG and is supplied with a potential VVCH (= 2.0 V) power source. The gate electrode of the initialization transistor NC is connected to the wiring RST, and the drain electrode is connected to the wiring SENSEn. The node A is further connected to the gate electrode of the first N-type transistor N1, the gate electrode of the first P-type transistor P1, and the drain electrode of the reset transistor NR, and further connected to one end of the second capacitor C2. The other end of the second capacitor C2 is connected to the wiring RST. The drain electrode of the first N-type transistor N1, the drain electrode of the first P-type transistor P1, and the source electrode of the reset transistor NR are connected to the node B, and the node B is further connected to the gate electrode of the second N-type transistor N2. Connected to the gate electrode of the second P-type transistor P2. The drain electrode of the second N-type transistor N2 and the drain electrode of the second P-type transistor P2 are connected to the node C. The node C is further connected to the gate electrode of the third N-type transistor N3 and the third P-type transistor P3. To the gate electrode. The drain electrode of the third N-type transistor N3 and the drain electrode of the third P-type transistor P3 are connected to the node D. The node D is further connected to the gate electrode of the fourth N-type transistor N4 and the fourth P-type transistor P4. To the gate electrode. The drain electrode of the fourth N-type transistor N4 and the drain electrode of the fourth P-type transistor P4 are connected to the output wiring OUTn, and the output wiring OUTn is further connected to the drain electrode of the fifth N-type transistor N5. The gate electrode of the fifth N-type transistor N5 and the gate electrode of the fifth P-type transistor P5 are connected to the wiring RST, and the drain electrode of the fifth P-type transistor P5 is connected to the source electrode of the fourth P-type transistor P4. Connected. The source electrodes of the first N-type transistor N1 to the fifth N-type transistor N5 are connected to the wiring VSL and supplied with a potential VVSL (= 0 V). The source electrodes of the first P-type transistor P1 to the third P-type transistor P3 and the fifth P-type transistor P5 are connected to the wiring VSH and supplied with the potential VVSH (= + 5 V). Further, + 9V and -4V power is supplied to the inverter circuit INV1.

In this embodiment, the channel width of the first N-type transistor N1 is 10 μm, the channel width of the second N-type transistor N2 is 35 μm, and the channel width of the third N-type transistor N3 is 100 μm. The channel width of the fourth N-type transistor N4 is 150 μm, the channel width of the fifth N-type transistor N5 is 150 μm, the channel width of the sixth N-type transistor N11 is 4 μm, and the seventh N-type transistor N5 The channel width of the N-type transistor N21 is 200 μm, the channel width of the first P-type transistor P1 is 10 μm, the channel width of the second P-type transistor P2 is 35 μm, and the channel width of the third P-type transistor P3 The width is 100 μm, the channel width of the fourth P-type transistor P4 is 300 μm, and the fifth The channel width of the P-type transistor P5 is 300 μm, the channel width of the sixth P-type transistor P11 is 200 μm, the channel width of the seventh P-type transistor P21 is 4 μm, and the channel width of the reset transistor NR is The channel width of the initialization transistor NC is 50 μm, the channel widths of the N-type transistor and the P-type transistor constituting the first switch SW1 to the fourth switch SW4 are 100 μm, and the inverter circuit INV1 and the inverter The channel width of the N-type transistor and the P-type transistor constituting the circuit INV2 is 50 μm, the channel length of all these N-type transistors is 8 μm, the channel length of all these P-type transistors is 6 μm, N-type Tran Mobility star is 80 cm ² / Vsec, mobility of all P-type transistor is 60cm ² / Vsec, the threshold voltages of all the N-type transistor (Vth) is + 1.0 V, all the P-type The threshold voltage (Vth) of the transistor is −1.0 V, the capacitance of the first capacitor C1 is 1 pF, and the capacitance of the second capacitor C2 is 38 fF.

  FIG. 12 is a timing chart of signals applied to the wiring RST, the wiring SMP, the common potential wiring 335, the scanning line 201-1 and the scanning line 201-2. Note that the scale of the vertical and horizontal axes is not constant in order to prioritize the visibility of the figure. The scanning line 201-1 and the scanning line 201-2 are driven by the scanning line driving circuit 301, and are selected every 16.7 milliseconds for 31.2 microseconds. The scanning line 201-2 is selected 34.6 microseconds after the scanning line 201-1 is selected, and is subsequently selected at intervals of 34.6 microseconds as scanning lines 201-3, 201-4,. The common potential wiring 335 is inverted between the High potential (= 5 V) and the Low potential (= 0 V) every 34.6 μsec, but the phase is shifted by a half cycle every 16.7 msec. Therefore, every time the scanning line 201-n is selected, so-called 1H common inversion driving is performed in which the polarity applied to the common potential wiring 335 is inverted. The RST signal is selected for 27.7 μs before the scanning line 201-1 is selected for 32.9 μs. At this time, the potential of the common potential wiring 335 is always the Low potential (= 0 V), and all the scanning lines 201-1 to 201-480 are not selected. The SMP signal is selected for 27.7 μsec after 3.5 μsec from the inversion timing of the common potential wiring 335 during the period when the common potential wiring 335 is Low. During the period when the RST signal is ON, the SMP signal is also always ON. Here, the RST signal, the SMP signal, and the scanning line 201-n are selected, that is, the High potential is + 9V, and when not selected, that is, the Low potential is −4V.

  With this configuration, at the timing when the wiring RST is High (= + 9 V), the potential VVCHG (= 2.0 V) is charged in the wiring SENSEn and the node SIN. The wiring VDBTn is charged with the potential VVCHG, the wiring VSLn is charged with the potential VVSL, and the wiring VSH is charged with the potential VVSH. Further, since the reset transistor NR is turned ON, the node A and the node B are short-circuited, and both nodes are charged to 2.5 V in this embodiment. Note that while the wiring RST is High (= 9V), the fifth N-type transistor N5 is ON and the fifth P-type transistor P5 is OFF, so the output wiring OUTn is 0V.

  When the wiring RST becomes Low (= −4 V) after 27.7 μsec, the reset transistor NR is turned OFF, the node A and the node B are electrically disconnected, and the node A is coupled to the wiring RST by the coupling of the second capacitor C2. At the same time, the potential drops by 0.5V to 2.0V. At the moment when the wiring RST becomes Low (= −4 V) after 27.7 μsec, the wiring SENSEn is at the potential VVCHG (= 2.0 V), the wiring VSLn is at the potential VVSL (= 0.0 V), and the wiring VSHn is The potential is VVSH (= 5.0 V). Accordingly, a reverse bias of 3.0 V is applied from the first side of the light receiving sensor group to the fourth side of the light receiving sensor group, and a reverse bias of 2.0 V is applied from the first side light shielding sensor to the fourth side light shielding sensor group. Applied. Further, the potential VVSL is output from the output wiring OUTn. At this time, the thermal currents flowing from the light-receiving sensor group on the first side to the light-receiving sensor group on the fourth side and the light-shielding sensor group on the first side to the light-shielding sensor group on the fourth side are approximately equal, and the wiring SENSEn has the first side A photocurrent Iphoto proportional to the illuminance of external light applied to the light-receiving sensor group on the fourth side flows from the light-receiving sensor group, and the potential of the wiring SENSEn rises at a rate proportional to the photocurrent Iphoto. A current also flows through the wiring VSHn and the wiring VSLn, both of which are slightly closer to the potential of the wiring SENSEn, but at the timing when the wiring SMP becomes High (= 9V) every 69.2 μs, the second switch SW2 and the third switch SW3. Turns on and returns to its original potential with little change.

  The relationship between the speed at which the potential of the wiring SENSEn changes and the amount of light applied to the light receiving sensor group on the nth side is expressed by a linear expression, and the coefficient indicating the inclination is the light receiving on the wiring SENSEn and the nth side connected thereto. Although it is determined by the sum of the load capacities of the anode electrode of the sensor group and the cathode electrode of the light shielding sensor group of the nth side, in this embodiment, the coefficient indicating this inclination is from the first side to the fourth side (n = 1 to 4). There is no difference, that is, the capacitance of “photocurrent Iphoto” ÷ “wiring SENSEn” at a constant light amount from the light receiving sensor group on the first side to the light receiving sensor group on the fourth side is adjusted to be equal on each side.

  As described above, since the node A is in a floating state while the wiring RST is Low (= −4 V), the potential is simultaneously increased due to the coupling with the node SIN due to the capacitive coupling with the first capacitor C1. When the node A and the node SIN become 2.5V, the potential of the output wiring OUTn is inverted to High (= 5V).

  In the present embodiment, the first side light receiving sensor group to the fourth side light receiving sensor group are arranged close to the display region 310, and the anode electrode 615-n, the cathode electrode 616-n, and the BT electrode 617-n are common potentials. Crosses the wiring 335. In addition, there is a capacitance via the light-shielding electrode and any of the scanning line 201-n, the data line 202-m, and the capacitance line 203-n, and electromagnetic noise easily enters through these capacitances. In particular, the common potential wiring 335 and the wiring SENSEn are coupled by a capacitance that cannot be ignored, and the potential of the wiring SENSEn is increased or decreased depending on the polarity of the common potential wiring 335. An example is shown in FIG. 12 as a timing chart of the wiring SENSEn. As described above, the wiring SENSEn increases the ΔV potential by capacitive coupling when the common potential wiring 335 is inverted from Low (= 0V) to High (= 5 V), and ΔV when the potential is inverted from High (= 5 V) to Low (= 0 V). The potential drops. However, in this embodiment, since the node SIN and the wiring SENSEn are brought into conduction only when the SMP signal is ON, as shown in FIG. 12, the node SIN does not change when the polarity is inverted. Accordingly, malfunction due to inversion of the common potential wiring 335 does not occur.

  Similarly, in this embodiment, the wiring VDBTn, the wiring VSLn, and the wiring VSHn (n = 1 to 4) are electrically connected to the wiring VCHG, the wiring VSL, and the wiring VSH only when the SMP signal is ON, and the SMP signal is OFF. It is in a floating state at the timing. With this configuration, the potential of the wiring VDBTn, the wiring VSLn, and the wiring VSHn (n = 1 to 4) also varies by about ΔV due to capacitive coupling when the polarity of the common potential wiring 335 is reversed. Therefore, even if the polarity of the common potential wiring 335 is reversed, the bias applied from the first side light receiving sensor group to the fourth side light receiving sensor group and from the first side light shielding sensor group to the fourth side light shielding sensor group changes. Therefore, the photocurrent Iphoto and thermal current flowing from the first side light-receiving sensor group to the fourth side light-receiving sensor group and the thermal current flowing from the first side light-shielding sensor group to the fourth side light-shielding sensor group are the common potential. It is constant regardless of the polarity of the wiring 335.

  In this embodiment, since ΔV is relatively large, such a configuration is adopted. However, when ΔV is relatively small and less than 1V, the first switch SW1, the second switch SW2, and the fourth switch SW4 are removed. Is also possible. FIG. 13 shows a circuit diagram of an nth detection circuit 360′-n as a detection circuit 360 ′ which is another configuration example of the detection circuit in such a case. In the second embodiment, the first switch SW1 to the fourth switch SW4 are removed as compared with the nth detection circuit 360-n shown in FIG. 11, the wiring VDBTn is the wiring VCHG, the wiring VSLn is the wiring VSL, The wiring VSHn is short-circuited with the wiring VSH, and the wiring SENSEn and the node SIN are each short-circuited. With such a configuration, the node SIN has an amplitude corresponding to the polarity of the common potential wiring 335 (just like the chart shown by the wiring SENSEn in FIG. 12). Therefore, if the detection operation is performed for the entire period as it is, a malfunction occurs when the common potential wiring 335 is inverted to High (= 5 V). Therefore, the third N-type transistor N3 to the fifth N-type transistor N5 and the third P-type transistor P3 to the fifth P-type transistor P5 are removed, and instead the second N-type transistor N2 and the second N-type transistor N2 The drain electrode of the P-type transistor P2 is connected to one of the input terminals of the first NAND circuit NAND1, the other input terminal of the first NAND circuit NAND1 is connected to the SMP signal, and the output of the first NAND circuit NAND1. The terminal is connected to one input terminal of the second NAND circuit NAND2, the other input terminal of the second NAND circuit NAND2 is connected to the output terminal of the third NAND circuit NAND3, and the input of the third NAND circuit NAND3. One of the terminals is connected to the output terminal of the second NAND circuit NAND2, and the other input terminal of the third NAND circuit NAND3. Connected to the output terminal of the inverter circuit INV3, connects the input terminal of the inverter circuit INV3 to the wiring RST. The power sources of the first NAND circuit NAND1 to the third NAND circuit NAND3 and the inverter circuit INV3 are connected to the wiring VSH and the wiring VSL. The configuration and operation of the other circuits are the same as those in FIG. With this configuration, the output of the first NAND circuit NAND1 is Low only when the potential of the node SIN is 2.5 V or more and the SMP signal is High. The second NAND circuit NAND2 and the third NAND circuit NAND3 are RS flip-flops, and the output of the first NAND circuit NAND1 is a negative polarity set signal, and the output of the inverter circuit INV3 is a negative polarity reset signal. Yes. That is, when the RESET signal becomes High (= 9V), the output to the output wiring OUTn is latched Low, and at the first timing when the potential of the node SIN is 2.5V or more and the SMP signal becomes High. The output to the output wiring OUTn is latched High. Accordingly, the detection result of the common potential wiring 335 during the period of High (= 5 V) is invalidated, so that no malfunction occurs.

  FIG. 14 is a circuit diagram of the majority circuit 370. The input terminals of the fourth NAND circuit NAND11, the fifth NAND circuit NAND12, the sixth NAND circuit NAND13, the seventh NAND circuit NAND14, the eighth NAND circuit NAND15, and the ninth NAND circuit NAND16 are connected to the output wiring OUT1. Any one of ˜OUT4 is connected in a permutation combination. The output terminals of the fourth NAND circuit NAND11, the fifth NAND circuit NAND12, and the sixth NAND circuit NAND13 are connected to the input terminal of the tenth NAND circuit NAND21, and the seventh NAND circuit NAND14 and the eighth NAND circuit NAND15. The output terminal of the ninth NAND circuit NAND16 is connected to the input terminal of the eleventh NAND circuit NAND22, and the output terminals of the tenth NAND circuit NAND21 and the eleventh NAND circuit NAND22 are input terminals of the first NOR circuit 30. The output terminal of the first NOR circuit 30 is connected to the input terminal of the inverter circuit INV4, and the output terminal of the inverter circuit INV4 is connected to the output wiring OUT. Fourth NAND circuit NAND11, fifth NAND circuit NAND12, sixth NAND circuit NAND13, seventh NAND circuit NAND14, eighth NAND circuit NAND15, ninth NAND circuit NAND16, tenth NAND circuit NAND21, The power sources of the eleventh NAND circuit NAND22 and the first NOR circuit 30 are connected to the wiring VSH and the wiring VSL. This circuit outputs High (= 5V) to the output wiring OUT when any two or more of the output wirings OUT1 to OUT4 are High (= 5V), and all of the output wirings OUT1 to OUT4 are output. This circuit outputs Low (= 0 V) to the output wiring OUT when Low (= 0 V) or only one of them is High (= 5 V). With this configuration, the time from when the wiring RST becomes Low (= −4 V) until the output wiring OUT is inverted to High (= 5 V) is from the first side light receiving sensor group to the fourth side light receiving sensor group. Of these, the second light irradiation amount is inversely proportional to the light irradiation amount of the side having the largest light irradiation amount. In the present embodiment, such a majority circuit 370 is mounted, and when a spot light stronger than the external environment light hits the side by excluding the result with the highest illuminance among the illuminance detection results of each side, malfunction occurs. Is preventing. Further, the result with the lowest illuminance and the result with the second lowest illuminance are also excluded, so that a correct result can be obtained even if a shadow such as a finger falls on two of the four sides.

  FIG. 15 is a setting example of the detection illuminance of external light and the backlight luminance based on the output from the output wiring OUT in this embodiment. When the external illuminance is very low, the backlight brightness is changed slowly, and the change is set to a s-curve that gradually changes suddenly to maximize the luminance change at external illuminance of 500 lux and then gradually changes to 1500 lux. In the above, the maximum brightness is set. This curve may be set freely according to the characteristics of the electronic device, or it may be gradually changed with an average value for a certain period to prevent the blinking of the luminance, and a hysteresis is given to the relationship between the luminance and the illuminance. Also good. Further, the curve may be changed according to the operation state of the electronic device, such as during standby and during operation.

  As described above, in this embodiment, although the light receiving opening is very close to the display area, even if the common inversion driving method is used, malfunction does not occur and the light detection accuracy is high, so that the brightness is always optimum. A display device can be set, which improves visibility and contributes to power consumption reduction. Further, even if one or two sides are covered with a finger or a spot light hits one place, the ambient light can be accurately measured, and the backlight luminance can always be kept optimal.

[Second Embodiment]
FIG. 16 is an enlarged plan view of an nth first side light sensor 351-n which is one of the first side light receiving sensor groups according to the second embodiment, and corresponds to FIG. 8 of the first embodiment. It is a figure to do. The legend is the same as in FIG. Hereinafter, FIG. 16 will be described focusing on differences from FIG.

  In FIG. 16, unlike FIG. 8, the scanning line 201-n is composed of wiring formed of an aluminum-neodymium alloy thin film (AlNd) through a contact hole in a region overlapping the light shielding electrode 611-n in a plane. A common potential branch line 618-n made of a molybdenum thin film (Mo) is formed between the scanning line 201-n and the light shielding electrode 611-n. The common potential branch wiring 618-n is connected to the common potential wiring 335 through a contact hole, and is given a common potential (COM). In other respects, FIG. 16 is not different from FIG.

  FIG. 17 is an enlarged plan view of an nth second side light sensor 352-n which is one of the second side light receiving sensor groups according to the second embodiment, and corresponds to FIG. 10 of the first embodiment. It is a figure to do. The legend is the same as in FIG. Hereinafter, FIG. 17 will be described focusing on the differences from FIG.

  17, unlike FIG. 10, a common potential branch wiring 628-n configured by a molybdenum thin film (Mo) is provided between regions where the data line 202-n and the light shielding electrode 621 (621-n) overlap in a plane. Is formed. The common potential branch wiring 628-n is connected to the common potential wiring 335 via a contact hole, and is given a common potential (COM). In other respects, FIG. 17 is not different from FIG.

  The configurations of the active matrix substrate 101 and the liquid crystal display device 910 in the present embodiment are the same as those in the first embodiment, and the configuration of the electronic device, the setting of the external light illuminance and the brightness, etc. are also the first embodiment, and the description is omitted. To do.

  In this embodiment, as compared with the first embodiment, the scanning line 201-n and the light shielding electrode 611-n overlap in a plane, and the data line 202-n and the light shielding electrode 621-n overlap in a plane. Since the common potential branch wirings 618-n and 628-n connected to the common potential wiring 335 are arranged between them, there is no direct cross capacitance. For this reason, when the potentials of the scanning line 201-n and the data line 202-n change, that is, the timing when the scanning line 201-n is selected by the scanning line driving circuit 301 or the data line 202-n. Alternatively, even when different potentials (images) are written by the precharge circuit 303, the potentials of the light shielding electrode 611-n and the light shielding electrode 621-n are unlikely to fluctuate. When the potentials of the light shielding electrode 611-n and the light shielding electrode 621-n vary, the potentials of the wiring SENSE1 and the wiring SENSE2 also vary due to capacitive coupling. Therefore, the present embodiment can measure the illuminance with higher accuracy than the first embodiment. It becomes possible. In addition, by connecting the wiring for shielding sandwiched between them to the common potential wiring 335, it is not necessary to newly provide a power supply for shielding. Since the common potential wiring 335 is originally arranged with a low impedance for maintaining image quality, it is extremely effective for use as a shield potential. Since the common potential wiring 335 is driven in an inverted manner, there is a problem that noise is generated to the light shielding electrode. However, in this embodiment, since the same driving as described in the first embodiment is performed, the common potential wiring 335 is driven. There is no decrease in accuracy due to potential fluctuations due to capacitive coupling. On the other hand, since the capacity of the common potential wiring 335 increases in this embodiment, there is a problem that power consumption increases. Whether to select the configuration of the first embodiment or the configuration of the second embodiment may be selected in accordance with the use application of the electronic device in consideration of the above advantages and disadvantages.

  In the present embodiment, measures are taken only with respect to the light shielding electrodes overlapping the nth first side light sensor 351-n and the nth second side light sensor 352-n. The third side light sensor 353-n and the nth fourth side light sensor 354-n may be used.

[Second Embodiment]
FIG. 18 is a block diagram of the active matrix substrate 102 according to the third embodiment. Hereinafter, the differences of the first embodiment from the active matrix substrate 101 shown in FIG. 2 will be described. Components having the same configuration as in FIG. 2 are given the same symbols, and description thereof is omitted. In this embodiment, instead of the first edge light sensors 351-1 to 351-480 in the first embodiment, first edge light sensors 351′-1 to 351′-480 as light sensors are replaced by second edge light sensors. The second side light sensors 352′-1 to 352′-1920 as photosensors instead of 352-1 to 352-1920 replace the third side light sensors 353-1 to 353-480 as the photosensors. The three side light sensors 353′-1 to 353′-480 are replaced by the fourth side light sensors 354′-1 to 354′-1920 instead of the fourth side light sensors 354-1 to 354-1920. The optical sensors 351 ′, 352 ′, 353 ′, and 354 ′ are arranged, respectively. Further, a detection circuit 361 is arranged in place of the first detection circuit 360-1 to the fourth detection circuit 360-4.

  Among the first side light sensors 351′-1 to 351′-480, the first side light receiving openings 991-1 to 991-3 that overlap with the third first side light receiving openings 991-3 (first side light receiving The sensor group is connected to the wiring SENSE (SENSEP), and the non-overlapping sensor (first side light shielding sensor group) is connected to the wiring SENSE (SENSED). Similarly, among the second side light sensors 352′-1 to 352′-1920, one that overlaps the first second side light receiving opening 992-1 to the fourth second side light receiving opening 992-4 (second The side light receiving sensor group) does not overlap the wiring SENSEP (the second side light shielding sensor group) is the wiring SENSED, and the first third of the third side light sensors 353′-1 to 353′-480. The ones that overlap the side light receiving openings 993-1 to the third third side light receiving openings 993-3 (third side light receiving sensor group) are not overlapped with the wiring SENSEP (the third side light shielding sensor group). Of the wiring SENSED and the fourth side light sensors 354′-1 to 354′-1920, overlapping the first fourth side light receiving opening 994-1 to the fourth fourth side light receiving opening 994-4 ( 4th side light receiving sensor group) is wiring SEN And EP, one shall not to overlap (fourth side shielding sensor groups) is a wiring SENSED, are connected. The wiring SENSED and the wiring SENSEP are connected to the detection circuit 361, and the output wiring OUT of the detection circuit 361 is connected to the outside through the signal input terminal 320.

  FIG. 19 is an enlarged plan view of an nth first side light sensor 351′-n which is one of the first side light receiving sensor groups according to the third embodiment, and is similar to FIG. 8 of the first embodiment. It is a corresponding figure. The legend is the same as in FIG. Hereinafter, FIG. 19 will be described focusing on the differences from FIG.

  The n-th first side light sensor 351′-n in FIG. 19 includes an anode region 610P ′ (610P′-n), an intrinsic region 610I ′ (610I′-n), and a cathode region 610N ′ (610N′-n). The lateral PIN diodes are the same as the anode region 610P-n, intrinsic region 610I-n, and cathode region 610N-n described in FIG. 8 of the first embodiment, and the description thereof is omitted. To do. The anode region 610P′-n is connected to the anode electrode 615 ′ (615′-n) through the contact hole, and the anode electrode 615′-n is connected to the wiring SENSEP. As the cathode region 610N′-n, the light shielding electrode 611 ′ (611′-n), and the transparent shield electrode 612 ′, the transparent shield electrode 612′-n is connected to the common potential wiring 335 through the contact holes, respectively. ). In other respects, FIG. 19 is not different from FIG.

  For the n′th first side light sensor 351′-n ′, which is one of the first side light shielding sensor groups, the first first side light receiving opening 991-1 to the third first side light receiving opening. 991-3 is not overlapped, and the anode electrode 615 ′ (615′-n ′) is the same as in the description of FIG. 19 except that it is connected to the wiring SENSED.

  FIG. 20 is an enlarged plan view of an mth second side light sensor 352′-m, which is one of the second side light receiving sensor groups according to the third embodiment, and is similar to FIG. 10 of the first embodiment. It is a corresponding figure. The legend is the same as in FIG. Hereinafter, FIG. 20 will be described focusing on differences from FIG.

  The m-th second side light sensor 352′-m in FIG. 20 includes an anode region 620P ′ (620P′-m), an intrinsic region 620I ′ (620I′-m), and a cathode region 620N ′ (620N′-m). Lateral type PIN diodes, which have the same configuration as the anode region 620P-m, intrinsic region 620I-m, and cathode region 620N-m described in FIG. To do. The anode region 620P′-m is connected to the anode electrode 625 ′ (625′-m) through the contact hole, and the anode electrode 625′-m is connected to the wiring SENSEP. The cathode region 620N′-m, the transparent shield electrode 622 ′ (622′-n), and the light shielding electrode 621 ′ (621′-n) are connected to the common potential wiring 335 through the contact holes, respectively, and the common potential (COM) is set. Given. In other respects, FIG. 20 is not different from FIG.

  For the n'th second side light sensor 352'-n ', which is one of the second side light shielding sensor groups, the first second side light receiving opening 992-1 to the fourth second side light receiving opening. 992-4 is not overlapped, and the anode electrode 625 ′ (625′-n ′) is the same as in the description of FIG. 19 except that it is connected to the wiring SENSED.

  The n-th third side light sensor 353′-n is located between the capacitor line 203-n−1 and the capacitor line 203-n as compared with the n-th first side light sensor 351′-n, and FIG. The layout is the same except that the layout shown in FIG. The nth fourth side light sensor 354′-n is similar to the nth second side light sensor 352′-n except that the layout shown in FIG. 20 is rotated by 180 degrees. Description is omitted.

  FIG. 21 is a circuit diagram of the detection circuit 361. The wiring SMP1, the wiring SMP2, the wiring RST, the wiring VCHG, the wiring VSL, and the wiring VSH are connected to the signal input terminal 320, and appropriate potentials and signals are supplied from the external power supply circuit 784. Here, the wiring VCHG is supplied with the potential VVCHG (= −2.0 V), the wiring VSL is supplied with the potential VVSL (= 0.0 V), and the wiring VSH is supplied with the potential VVSH (= 5.0 V). Note that here, the potential VVSL of the wiring VSL is GND of the liquid crystal display device 910. The output wiring OUTn is connected to the signal input terminal 320 and output to an external circuit.

  The wiring SENSED is connected to one end of the fifth switch SW5, and the wiring SENSEP is connected to one end of the sixth switch SW6. The other ends of the fifth switch SW5 and the sixth switch SW6 are both connected to the node SIN ′. Here, the fifth switch SW5 to the sixth switch SW6 are composed of CMOS transmission gates. The gate electrode of the n-channel transistor constituting the fifth switch SW5 is connected to the wiring SMP1, and the gate electrode of the p-channel transistor is connected to the output terminal of the inverter circuit INV5. The input terminal of the inverter circuit INV5 is connected to the wiring SMP1. Further, the gate electrode of the n-channel transistor constituting the sixth switch SW6 is connected to the wiring SMP2, and the gate electrode of the p-channel transistor is connected to the output terminal of the inverter circuit INV6. The input terminal of the inverter circuit INV6 is connected to the wiring SMP2.

  The node SIN ′ is connected to one end of the third capacitor C3 and the drain electrode of the initialization transistor NC ′, and the other end of the third capacitor C3 is connected to the node A ′. The source electrode of the initialization transistor NC ′ is connected to the wiring VCHG and supplied with a potential VVCHG (= −2.0 V) power source. The gate electrode of the initialization transistor NC ′ is connected to the wiring RST. The node A ′ is further connected to the gate electrode of the sixth N-type transistor N′1, the gate electrode of the sixth P-type transistor P′1, and the drain electrode of the reset transistor NR ′, and one end of the fourth capacitor C4. Connected to. The other end of the fourth capacitor C4 is connected to the wiring RST.

  The drain electrode of the sixth N-type transistor N′1, the drain electrode of the sixth P-type transistor P′1, and the source electrode of the reset transistor NR ′ are connected to the node B ′, and the node B ′ is further connected to the seventh N-type transistor. Connected to the gate electrode of the N-type transistor N′2 and the gate electrode of the seventh P-type transistor P′2. The drain electrode of the seventh N-type transistor N′2 and the drain electrode of the seventh P-type transistor P′2 are connected to the node C ′, and the node C ′ is further the gate electrode of the eighth N-type transistor N′3. And the gate electrode of the eighth P-type transistor P′3. The drain electrode of the eighth N-type transistor N′3 and the drain electrode of the eighth P-type transistor P′3 are connected to the node D ′, and the node D ′ is further the gate electrode of the ninth N-type transistor N′4. And the gate electrode of the ninth P-type transistor P′4. The drain electrode of the ninth N-type transistor N′4 and the drain electrode of the ninth P-type transistor P′4 are connected to the output wiring OUT, and the output wiring OUT is further the drain electrode of the tenth N-type transistor N′5. Also connected to. The gate electrode of the tenth N-type transistor N′5 and the gate electrode of the tenth P-type transistor P′5 are connected to the wiring RST, and the drain electrode of the tenth P-type transistor P′5 is the ninth P-type. Connected to the source electrode of transistor P′4. The source electrodes of the sixth N-type transistor N′1 to the tenth N-type transistor N′5 are connected to the wiring VSL and supplied with the potential VVSL (= 0 V). The source electrodes of the sixth P-type transistor P′1 to the eighth P-type transistor P′3 and the tenth P-type transistor P′5 are connected to the wiring VSH and supplied with the potential VVSH (= + 5 V). Become. Further, + 9V and -4V power is supplied to the inverter circuit INV5 and the inverter circuit INV6.

In this embodiment, the channel width of the sixth N-type transistor N′1 is 10 μm, the channel width of the seventh N-type transistor N′2 is 35 μm, and the channel width of the eighth N-type transistor N′3 is The channel width is 100 μm, the channel width of the ninth N-type transistor N′4 is 150 μm, the channel width of the tenth N-type transistor N′5 is 150 μm, and the sixth P-type transistor P′1 Has a channel width of 10 μm, a seventh P-type transistor P ′ 2 has a channel width of 35 μm, an eighth P-type transistor P ′ 3 has a channel width of 100 μm, and a ninth P-type transistor P ′. 4 has a channel width of 300 μm, the tenth P-type transistor P′5 has a channel width of 300 μm, and the reset transistor NR ′ has a channel width of 10 μm. The channel width of the initialization transistor NC ′ is 150 μm, the channel widths of the N-type transistor and the P-type transistor constituting the fifth switch SW5 to the sixth switch SW6 are 100 μm, and the inverter circuit INV5 and the inverter circuit INV6 The channel width of the N-type transistor and the P-type transistor constituting the channel is 50 μm, the channel length of all these N-type transistors is 8 μm, the channel length of all these P-type transistors is 6 μm, and all the N-type transistors The mobility of the transistors is 80 cm ² / Vsec, the mobility of all P-type transistors is 60 cm ² / Vsec, the threshold voltage (Vth) of all N-type transistors is +1.0 V, and all the P-type transistors The threshold voltage (Vth) of the transistor is -1. 0.0V, the capacitance of the third capacitor C3 is 1 pF, and the capacitance of the fourth capacitor C4 is 38 fF.

  Next, FIG. 22 is a timing chart of the present embodiment. The scales of the vertical and horizontal axes are not constant in order to prioritize the visibility of the figure. Since the common potential wiring 335, the scanning line 201-1, the scanning line 201-2, and the wiring RST are the same as those described in the first embodiment with reference to FIG. The wiring SMP1 is selected for 13.8 μsec when the common potential wiring 335 is Low (= 0 V) and has a period of 69.2 μsec. Similarly, the wiring SMP2 is selected for 13.8 μs after the wiring SMP1 when the common potential wiring 335 is Low. The wiring SMP1 and the wiring SMP2 are signals that are + 9V when selected, that is, when the potential is High, and are −4V when not selected, that is, when the potential is Low.

  When the circuit is configured in this way, the wiring SMP1 is first selected during the period when the common potential wiring 335 is Low (= 0V), the wiring SENSED is connected to the node SIN ′, and at the same time, the nodes A ′ and B ′ are connected to the reset transistor NR. Shorted by 'and charged to 2.5V. During this time, the output to the output wiring OUT is always Low (= 0 V). Next, after 13.8 μsec, the wiring SMP1 is deselected and simultaneously the wiring SMP2 is selected, the wiring SENSEP is connected to the node SIN ′, and the node A ′ and the node B ′ are electrically separated, and the fourth The potential of the node A ′ is lowered to 2.0 V by the capacitor C4. After that, the potential of the node SIN ′ changes from the potential of the wiring SENSED to the wiring SENSEP through the fifth switch SW5, and the potential of the node A ′ also changes due to capacitive coupling. That is, immediately before the wiring SMP2 is deselected, the potential of the node A is “2.0 V” + “potential of the wiring SENSEP” − “potential of the wiring SENSED”. When this exceeds 2.5 V, the detection circuit 361 outputs High is output to the wiring OUT. The potential of the wiring SENSED changes with a slope proportional to the thermal current flowing from the first side light shielding sensor group to the fourth side light shielding sensor group, and the wiring SENSEP potential is received from the first side light receiving sensor group by the fourth side light receiving. The potential difference between the wiring SENSEP and the wiring SENSED changes with a slope proportional to the photocurrent Iphoto because the slope changes in proportion to “thermal current” + “photocurrent Iphoto” flowing through the sensor group. From this point, as in the first embodiment, the period from when the wiring RST is deselected to when the output wiring OUT first becomes High is proportional to the reciprocal of the external light illuminance.

  Next, before the common potential wiring 335 is inverted to High (= 5V), the wiring SMP1 and the wiring SMP2 are both unselected, and the period during which the common potential wiring 335 is High (= 5V) is not selected. As shown in the chart of FIG. 12, as shown in the wiring SENSED and the wiring SENSEP, when the common potential wiring 335 is inverted to High (= 5V), the potential of the wiring SENSED and the wiring SENSEP rises by about 5V due to capacitive coupling. However, as shown in FIG. 12, since the fifth switch SW5 and the sixth switch SW6 are closed during this period, the potential of the node SIN ′ is not affected. Therefore, high-precision detection is possible without being affected by the inversion of the common potential wiring 335 as in the first embodiment.

  The configuration of the detection circuit 361 of this embodiment has an advantage that it is relatively resistant to noise because the period during which the node A in the circuit is floating is shorter than the configuration of the detection circuit 360 of the first embodiment. On the other hand, it may be easily affected by the switching noise of the fifth switch SW5 and the sixth switch SW6, and may be inferior in accuracy. Which configuration should be adopted may be selected in consideration of the advantages of both. In any configuration, the common potential (COM) at the timing when the reset operation is finished (in the embodiment, the potential of the wiring RST returns to Low) and the detection circuit 361 operates (in the embodiment, the wiring SMP, the wiring It is important that the common potential (COM) in the period in which SMP1 and wiring SMP2 become High) is the same, and any circuit having such a configuration is given as an example in this specification. The detection circuit 361 may be configured by any known circuit other than the circuit.

  The liquid crystal display device in this embodiment is the same as the liquid crystal display device 910 and active matrix substrate 101 in the first embodiment shown in FIG. In addition, the configuration of the electronic device, the setting of the illuminance and luminance of the external light, and the like are also the first embodiment, and the description thereof is omitted.

  In this embodiment, the power source connected to the photosensor uses the common potential (COM) of the common potential wiring 335. In this embodiment, since the light-shielding electrode and the transparent electrode are also connected to the common potential wiring 335, the optical sensor is almost completely coupled to the common potential (COM) of the common potential wiring 335, and the wiring SENSEP and the wiring SENSED are connected to the common potential wiring 335. Are amplified at approximately the same potential with the same period and phase. For this reason, the bias applied to the diode does not substantially change depending on the polarity of the common potential wiring 335. Further, since the number of wirings can be greatly reduced as compared with the first embodiment, the external dimensions of the liquid crystal display device can be reduced. On the other hand, since the power supply potential of the detection circuit 361 may be a DC potential, it can be shared with the power supply potentials of the scanning line driving circuit 301 and the data line driving circuit 302, and the number of power supplies to be supplied is not increased unnecessarily. Note that when there is a concern about image quality due to potential fluctuation of the common potential wiring 335 or increase in noise, it is a matter of course that another power supply potential may be supplied to the photosensor.

  In this embodiment, the wiring SENSEP and the wiring SENSED on all sides are connected and connected to one detection circuit 361. However, the wiring SENSEP and the wiring SENSED are separated on each side as in the first embodiment. The detection circuits 361-1 to 361-4 may be arranged in the circuit, and the output thereof may be determined by the majority circuit 370 shown in the first embodiment. Conversely, the n-th detection circuit 360-n in the first embodiment may be one and the wirings on each side may be short-circuited. If each side is short-circuited and one detection circuit is provided as in this embodiment, the circuit scale can be greatly reduced, and the outer shape of the liquid crystal display device 910 can be reduced. On the other hand, since the ambient light illuminance that can be detected is the average of the ambient light illuminance on each side, when the ambient light is largely blocked by a finger or the like, the ambient light illuminance is detected to be darker than actual. Which one is selected may be determined by the configuration of the electronic device, the operation method, the size of the liquid crystal display device, and the like.

  In each embodiment of the present specification, the photosensors are arranged on the four sides of the display area 310. However, if there is a limitation on the outer shape or the like, it is needless to say that the number may be three or less.

  The present invention is not limited to the embodiments, and is used for liquid crystal display devices such as a vertical alignment mode (VA mode) instead of the TN mode, an IPS mode using a lateral electric field, and an FFS mode using a fringe electric field. It doesn't matter. Moreover, not only a total transmission type but also a total reflection type and a reflection / transmission combined type may be used. Further, instead of the liquid crystal display device, it may be used for an organic EL display, a field emission type display, or a semiconductor device other than the liquid crystal display device.

  In addition to controlling the display brightness according to the external light as shown in this embodiment, the brightness and chromaticity of the display device are measured and fed back, and used for a display device free from unevenness and aging. It doesn't matter.

The perspective view of the liquid crystal display device 910 which concerns on the Example of this invention. The block diagram of the active-matrix board | substrate 101 which concerns on the 1st and 2nd Example of this invention. 1 is a pixel circuit diagram of an active matrix substrate 101 according to an embodiment of the present invention. 1 is a block diagram illustrating an embodiment of an electronic device of the present invention. The top view of the pixel part of the active matrix substrate 101 which concerns on the Example of this invention. FIG. 5A is a cross-sectional view along AA ′. FIG. 5B is a cross-sectional view taken along the line BB ′. The plane enlarged view of nth 1st edge light sensor 351-n which is one of the 1st edge light-receiving sensor groups which concern on the 1st Example of this invention. FIG. 9 is a cross-sectional view taken along the line CC ′. The plane enlarged view of nth 2nd edge light sensor 352-n which is one of the 2nd edge light-receiving sensor groups which concern on 1st Example of this invention. The circuit diagram of nth detection circuit 360-n based on the Example of this invention. The timing chart which concerns on the Example of this invention. The circuit diagram of nth detection circuit 360'-n which concerns on another Example of this invention. The circuit diagram of the majority circuit 370 which concerns on the Example of this invention. FIG. 3 is a setting diagram of detected illuminance of external light and backlight luminance according to an embodiment of the present invention. The plane enlarged view of the nth 1st edge light sensor 351-n which is one of the 1st edge light receiving sensor groups concerning the 2nd example of the present invention. The plane enlarged view of nth 2nd edge light sensor 352-n which is one of the 2nd edge light-receiving sensor groups which concern on the 2nd Example of this invention. The block diagram of the active matrix substrate 102 which concerns on the 3rd Example of this invention. The plane enlarged view of nth 1st edge light sensor 351'-n which is one of the 1st edge light-receiving sensor groups which concern on the 3rd Example of this invention. The plane enlarged view of nth 2nd edge light sensor 352'-n which is one of the 2nd edge light-receiving sensor groups which concern on the 3rd Example of this invention. The circuit diagram of the detection circuit 361 which concerns on the 3rd Example of this invention. The timing chart which concerns on the 3rd Example of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101,102 ... Active matrix substrate, 201, 201-1 to 201-480 ... Scanning line, 202, 202-1 to 202-1920 ... Data line, 203, 203-1 to 203-480 ... Capacitance line, 301 ... Scanning Line drive circuit 302 ... Data line drive circuit 303 ... Precharge circuit 310 ... Display area 320 ... Signal input terminal 330 ... Opposite conduction part 335 ... Common potential wiring 351, 351 ', 352, 352', 353, 353 ', 354, 354' ... optical sensors, 351-1 to 351-480, 351'-1 to 351'-480 ... first side light sensors as optical sensors, 352-1 to 352-1920, 352 '-1 to 352'-1920 ... second side light sensors as light sensors, 353-1 to 353-480, 353'-1 to 353'-480 ... light sensors Third side light sensors as sensors, 354-1 to 354-1920, 354'-1 to 354'-1920 ... Fourth side light sensors as light sensors, 360, 360 ', 361 ... Detection circuit, 370 ... Majority decision Circuit 401 ... Pixel switching element 402 ... Pixel electrode 403 ... Auxiliary capacitance capacitor 602 ... Silicon island 603 ... Source electrode 604 ... Drain electrode 610P, 610P ', 620P, 620P' ... Anode region, 610N, 610N ', 620N, 620N' ... cathode region, 610I, 610I ', 620I, 620I' ... intrinsic region, 611, 611 ', 621, 621' ... light shielding electrode, 612, 622, 622 '... transparent shield electrode, 615, 615 ', 625,625' ... anode electrode, 616, 626 ... cathode electrode, 617, 27 ... BT electrode, 780 ... Video processing circuit, 781 ... Central processing circuit, 782 ... External I / F circuit, 784 ... External power supply circuit, 785 ... Reference table, 783 ... Input / output device, 910 ... Liquid crystal display device, 912 ... Counter substrate, 921 ... Overhang, 922 ... Nematic phase liquid crystal material, 923 ... Sealing material, 924 ... Upper polarizing plate, 925 ... Lower polarizing plate, 926 ... Backlight unit, 927 ... Light guide plate, 928 ... As flexible substrate FPC, 929... Connector, 930. Counter electrode as common electrode, 940... Black matrix, 991-1 to 991-3... First first side light receiving opening to third first side light receiving opening, 992 −1 to 992-4... First second side light receiving opening to fourth second side light receiving opening, 993-1 to 993-3... First third side light receiving opening to third third. Side light receiving aperture , 994-1 to 994-4... First fourth side light receiving opening to fourth fourth light receiving opening, SENSE, VSH, VSL, VDBT, VCHG.

Claims (11)

An active matrix circuit for display;
A display device comprising a plurality of bus lines connected to the active matrix circuit for transmitting a drive signal, and a drive circuit for outputting the drive signal to the plurality of bus lines on a substrate,
A light sensor on the substrate;
The optical sensor is arranged in a plurality of sub-regions divided by the plurality of bus lines ,
The plurality of sub-regions are disposed between the active matrix circuit and the driving circuit ,
The display device
A plurality of pixel electrodes connected to the active matrix circuit;
A common electrode that is inverted and driven between a first potential and a second potential lower than the first potential;
A liquid crystal element whose alignment state is changed by an electric field applied between the plurality of pixel electrodes and the common electrode;
Sensor wiring connected to the light sensor;
A plurality of detection circuits for detecting the potentials or currents of the photosensors in the plurality of sub-regions arranged on different sides of the outer periphery of the active matrix circuit;
A majority circuit that changes an output when at least two detection results of the detection results of the plurality of detection circuits change; and
Further comprising
The plurality of detection circuits detect the potential or current of the sensor wiring at the same timing and the common electrode at the timing of either the first potential or the second potential.
Display device. A first electrode formed by a plurality of light-shielding electrodes for shielding a backlight and disposed in a region overlapping with the optical sensor in a plane; and a common electrode disposed in a region overlapping with the bus line in a plane. And a second electrode connected to
  The display device according to claim 1. The first electrode is used as a potential fixing destination of the second electrode.
  The display device according to claim 2.
The bus line or the second electrode is disposed in a gap between the plurality of light shielding electrodes.
  The display device according to claim 2 or 3. The plurality of detection circuits repeatedly perform a reset operation for returning the potential of the sensor wiring to an initial state,
  The reset operation is performed at the other timing of the first potential or the second potential of the common electrode.
  The display apparatus of any one of Claims 1-4. The sensor wiring changes in potential at the same timing as the common electrode.
  The display apparatus of any one of Claims 1-5. The sensor wiring is short-circuited with the common electrode.
  The display apparatus of any one of Claims 1-6. The sensor wiring is connected to a power supply wiring to which a potential is supplied from the outside during the period of either the first potential or the second potential, and the sensor wiring is in a floating state during one period
  The display device according to claim 1. The optical sensor is a PIN junction diode or a PN junction diode using thin film polysilicon,
  The drive circuit is composed of a transistor using thin film polysilicon.
  The display apparatus of any one of Claims 1-8. The electronic device provided with the display apparatus of any one of Claims 1-9. A touch panel disposed on the display device;
  The electronic device according to claim 10.