JP5244464B2 - Semiconductor device and manufacturing method thereof, and integrated semiconductor device and nonvolatile semiconductor memory device using the semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a logic circuit element that operates at a low voltage, a semiconductor memory device to which the logic circuit element is applied, and a manufacturing method thereof.

  From the end of the 20th century to the 21st century, semiconductor integrated circuits (chips) with dramatically improved information processing capabilities have been realized by reducing CMOS devices and increasing the degree of integration. In reducing the size of CMOS devices, it can be considered that the structure of MOSFET devices has been extremely simple, and the continuous advancement of planar technology used for processing has played a major role. Since this increase in the degree of integration increases the power consumption of the chip, “scaling” has been performed in which the device size is reduced and the operating voltage is reduced. As the power supply voltage of the so-called “logic CMOS” used in the logic circuit, for example, a voltage setting of 1.2 V in the 90 nm planar technology generation and 1 V in the further 45 nm generation is performed. This state can be seen in, for example, International Technology Roadmap for Semiconductor (ITRS) 2005 edition (Non-patent Document 1). As shown in this, it is considered that the voltage needs to be lowered to 1 V or less in order to further reduce the device size.

  However, switching characteristics are considered to be a major issue in operating a MOSFET with a voltage of 1 V or less. The switching of the MOSFET is turned on and off by applying a gate voltage. This is based on the fact that the channel conductivity of the MOSFET changes abruptly at a certain voltage (threshold). When Subthreshold Swing (hereinafter referred to as S value), which evaluates this change as a change in channel current, is used, it is S to 100 mV / digit. That is, the channel current can be increased by an order of magnitude by applying a gate voltage of about 0.1V. The smaller the S value, the steeper switching characteristics are shown. Since the MOSFET changes by about 10 digits with respect to a voltage of 1V, sufficiently steep switching characteristics can be obtained, which is a basic element for digital circuit operation.

This S value is known to be dominated by channel charge induced by the field effect of the gate. That is, since the channel surface state follows the Boltzmann distribution, when an ideal MOSFET device is realized,
S = 2.3 kT / q
It can be expressed as. Here, k is Boltzmann's constant, T is temperature, and q is electronic charge. For example, 59.5 mV is taken at room temperature (300 ° K). In a MOSFET, the S value cannot be made lower than this, and therefore, a problem known as a 60 mV wall is a problem among MOSFETs.

As described above, in order to reduce the power consumption, the lowering of the power supply voltage is a serious obstacle to the S value having a lower limit. For example, when the voltage is set to 0.3 V, it is indicated that it becomes a limit to obtain an on / off ratio of 5 digits. In an actual device, an effect such as a variation in threshold value is added to this, so that the on / off ratio is further reduced, and a satisfactory circuit operation cannot be obtained.
So far, new structures of low S value devices with improved (reduced) S values have been proposed. For example, in 2002, Plimmer et al. Proposed a structure called I-MOS at International Electron Device Meeting (2002 International Electron Devices Meeting Technical Digest 289-291 (IEEE International Electron Devices Meeting Technical Digest pp. 289-292, 2002) (Non-Patent Document 2) In I-MOS, the avalanche phenomenon is caused by a high electric field to amplify the amount of charge and exceed the charge specified by the Boltzmann distribution. Is getting done.

  However, according to this principle, the controllability by the gate of the charge generated by amplification is deteriorated, and a high voltage is required to generate a high electric field. These are contrary to voltage reduction for power reduction, which is considered as a problem to be solved by the present invention. Therefore, it is considered that the low S value device structure proposed so far cannot be used in the field handled by the present invention. That is, in an element using an amplifying action, a voltage larger than that of a semiconductor bandgap is usually applied. Therefore, it is necessary to develop an element that works effectively in a state of operating under a voltage smaller than that of the bandgap. is there.

JP-A-4-343475 http://www.itrs.net/“International Technology Roadmap for Semiconductor (ITRS) ”, 2005 edition “2002 IEEE, International Electron Device Meeting, Technical Digest”, p. 289-292 S. Sze, “Physics of Semiconductor Devices, 2nd edition”, A Wiley-Interscience publication, p. 190-242

  An object of the present invention is to provide a transistor element having a switching characteristic superior to that of a CMOS while maintaining an integration property equivalent to that of a conventional CMOS, that is, having an S value smaller than 60 mV at room temperature. is there.

  This object can be achieved by forming a diode element and a resistance element in the drain diffusion layer of the conventional MOSFET. As will be described in detail later on the basis of the machining process, there is no problem of integration in this structure. That is, in the planar technology, the diffusion layer of the MOSFET is formed in a self-aligned manner by using an ion implantation method for the gate electrode. Therefore, if the gate electrode is made small, the diffusion layer that determines the device characteristics can be made very small (close to it), and the overall size can be reduced while improving the device performance, and the integration can be improved. It has become. At present, when the spacer technology widely used in the semiconductor industry is used, the diode and the resistance element having the structure of the present invention can be formed in a self-aligned manner with respect to the gate electrode. Therefore, it is clear that the structure of the present invention does not cause the problem of integration.

Next, the decrease in the S value will be described with reference to FIGS. 1A and 1B. FIG. 1A shows an equivalent circuit of the element structure of the present invention. Although the element of the present invention is one element in structure, by incorporating a diode in the diffusion layer, an equivalent circuit includes three elements, a MOSFET, a diode, and a resistance element. In consideration of the substrate electrode, this configuration can be regarded as including three elements, a MOSFET, a bipolar transistor, and a resistance element, as shown in the equivalent circuit diagram of FIG. 1B. Here, description will be made using NMOS for the MOSFET and PNP for the bipolar transistor. FIG. 2 shows the calculated potential (φ _A ) change at the node A when a voltage is applied to the gate electrode. The potential V _D is applied to the D terminal and Yuku raising the gate voltage, phi _A is contrary to the gate potential, it can be seen that rapidly drops from V _D.

This can also be understood from the fact that the connection between the NMOS and the resistor surrounded by a broken line in FIG. 1B can be regarded as forming an inverter. The emitter of this time bipolar device - in diode B to be between the base, a voltage of V _D -.phi _A is applied. FIG. 3 plots the relationship between the gate potential and V _D −φ _A applied to the diode. As is apparent from this figure, when applied to the gate, a voltage that increases extremely rapidly as compared with the boosting of the gate potential is applied to the diode. Therefore, a rapidly increasing current can be obtained at the drain. FIG. 4 shows drain current-gate voltage characteristics obtained by using an element that explains the manufacturing method in detail in Example 1 later. The measurement was performed at a drain voltage of 0.7V. What is indicated by a broken line in the figure is a subthreshold characteristic of the conventional MOSFET shown for comparison. It shows that the slope is steeper than 60 mV / digit. As can be seen from the explanation of the operation described here, the gate potential at which this current rises depends on the threshold value of the MOSFET. Therefore, the rising position can be easily adjusted by a normal method such as ion implantation. According to the present invention, since an S value smaller than 60 mV can be obtained, an element having excellent switching characteristics can be realized.

  As shown in the equivalent circuit of FIG. 1B, the element of the present invention has a configuration in which a MOSFET and a bipolar transistor are connected by a connection method known as Darlington connection. Connecting a MOSFET and a bipolar transistor has been widely used so far. This is because by adopting this configuration, it is possible to combine the good gate input response of the MOSFET with the high current drive capability of the bipolar transistor.

However, since it was not intended to improve the S value of the element, it has so far been considered to be used mainly under a high voltage such as a high voltage MOS. For this reason, the subthreshold region smaller than the operating voltage is not problematic in operation, and it has been assumed that the bipolar transistor is driven with the MOSFET turned on. That is, the present invention is characterized in that the bipolar transistor is set to be driven in the sub-threshold region of the MOSFET. Therefore, for example, in the configuration of FIG. 1B, the resistance value R _N of the resistance element is formed so as to match the channel resistance of the sub-threshold region of the MOSFET. Specifically, the subthreshold region of the enhancement type MOSFET can be regarded as a region where the channel surface is weakly inverted from the flat band state. When the substrate potential is grounded, the surface potential (φ _s ) can be considered as 0 <φ _s <2φ _F. Here, φ _F is the Fermi level of the channel layer. φ _s = 0 corresponds to a flat band state. Therefore, when considering the operation in this region, it is considered appropriate to take 1.5φ _F as the representative surface potential. At this time, _assuming that the channel resistance R _CH is a function of the surface potential and RCH (φ _s ), the resistance may be formed so that R _{N to} R _CH (1.5 φ _F ).

  From the viewpoint of the arrangement of the junction in the structure of the present invention, it can be seen that the PNPN and the PN junction are overlapped from the drain terminal side. This superposed junction can be regarded as having the same configuration as that of a high-voltage device speed-up technique known as a thyristor. As for the thyristor, for example, S.C. M.M. Physics of Semiconductor Devices by Tse, 2nd edition, pages 190-242 of SM It is done. In thyristors, the principle of high-speed operation is to cause potential fluctuations due to injected charges. Due to the potential change caused by the charge injection, the feed forward effect of performing more charge injection works, so that high-speed switching can be performed. Therefore, it is currently used as a high breakdown voltage switching element in a field where a large amount of driving force is required.

  On the other hand, in the structure of the present invention, the potential of each node is given by resistance division rather than being controlled by charge. Therefore, there is no need to inject excess charge, and the feature is that it can operate at high speed even with a low voltage. In addition, in the insulated gate bipolar transistor used in the high breakdown voltage operation, the same approach as that of the thyristor can be seen. For example, the description can be found in JP-A-4-343475 (Patent Document 1). Here, a structure is employed in which an insulated gate type gate electrode is arranged on the overlapping junction structure. In order to extract the injected excess charge, it is considered to add a resistance element. These are formed so as to bypass the charge accumulated in the active element portion and to be extracted outside, so that they are set to a low resistance value and directly connected to the terminal to the outside. On the other hand, the structure of the present invention is not intended to extract charges, and therefore has the feature that it can be effectively operated by connecting to a node formed in the substrate.

  According to the present invention, in an insulated gate field effect transistor for high integration used for configuring a digital logic circuit, an element having a change in channel resistance with respect to voltage application to the gate electrode of less than 60 mV can be obtained.

  Hereinafter, embodiments will be described in detail with reference to the drawings.

Hereinafter, a typical device structure of the present invention will be described including manufacturing steps. First, description will be made using the element of the present invention corresponding to a conventional NMOS. Thereafter, it is shown that an element corresponding to the PMOS can be formed in the same manner, and that a CMOS structure is suitable for reducing power consumption. FIG. 5 shows a planar arrangement of elements corresponding to the equivalent circuit diagram of FIG. 1B, and FIG. 6A shows a schematic cross-sectional view of the element taken along the line AA of FIG. In FIG. 6A, the gate electrode 500 controls the channel potential φ _S on the surface of the substrate 100 through the gate insulating film 900. The substrate 100 is P-type silicon, and the n-type impurity diffusion layers 200 and 300 serve as source and drain electrodes in the MOSFET. In the diffusion layer 300, a P-type diffusion layer region 350 and an N-type region 400 having a higher concentration than that of the 300 are formed. A PNP bipolar transistor is configured by successively arranging the P-type diffusion layer 400, the N-type diffusion layer 300, and the P-type substrate 100. Since the P-type 350 layer formed at a high concentration and the N-type 400 layer are formed close to each other, a low-breakdown-voltage diode, that is, a highly resistive PN junction is formed between 350-400. Therefore, the potential φ _N at the channel end of the drain diffusion layer of the MOSFET is connected to 300 through 400 by the voltage applied to the drain 350.

Therefore, the resistance between 350 and 400 and the internal resistance of the diffusion layer 300 constitute the resistance element shown in the equivalent circuit of FIG. 1B. In order to explain the resistance element formed between 350 and 400, the impurity distribution in the substrate depth direction of the junction of 350 to 400 in FIG. 6A is shown in FIG. 6B. As will be described later in the manufacturing process, a junction in which P-type (350) and N-type (400) impurities are in contact with each other at a high concentration of about 10 ¹⁹ to 10 ²⁰ cm ⁻³ has a sharp peak realized by LSA. Has been. The current-voltage characteristics of this high-concentration junction are shown in FIG. 6C. As can be seen from the figure, the high-concentration PN junction is different from a normal PN junction (indicated by a broken line in the figure), and the current is not turned off even in the reverse bias state, and functions as a resistance element. From this, it can be seen that the equivalent circuit of FIG. 1B is realized by the element structure schematically shown in FIG. 6A.

Hereinafter, the element forming process will be described with reference to FIGS. 7 to 12 using the AA cross section of FIG.
FIG. 7: After forming a 10 nm thermal oxide film on the surface of a P-type silicon substrate, a 100 nm silicon nitride film is deposited using a CVD (Chemical Vapor Deposition) method, and an active region pattern (FIG. 5, 1100), the active region is patterned, and the silicon nitride film and the thermal oxide film are anisotropically etched in a direction perpendicular to the substrate surface by a dry etching method. Then, the silicon substrate is anisotropically etched to form a 300 nm groove. Form. Thereafter, the exposed silicon surface is oxidized to form a 5 nm oxide film, and after depositing a 700 nm silicon oxide film by a CVD method, the silicon nitride film is used as a base mask using a CMP (Chemical Mechanical Polishing) method. The deposited oxide film is polished to remove other deposited oxide films except in the formed grooves, and then the silicon nitride film used as a mask is removed by wet etching using hot phosphoric acid. By doping boron using an ion implantation method and heat treatment, a well region having a P-type concentration set to 8 × 10 ¹⁷ cm ⁻³ is formed in the vicinity of the substrate surface. The threshold value of the MOSFET can be set by setting the impurity concentration profile. Further, the silicon surface is exposed by removing the thermal oxide film formed under the silicon nitride film using hydrofluoric acid. Since this process is an element isolation region forming process known as shallow trench isolation, a drawing is omitted here. Thus, an active region where the silicon surface is exposed and an element isolation region covered with the element isolation insulating film 910 are formed.

FIG. 8: A gate oxide film 900 having a thickness of 3 nm is formed in the active region by thermal oxidation, and crystalline silicon 500 is deposited to a thickness of 100 nm using a CVD method. The polycrystalline silicon layer is doped with phosphorus at a high concentration by using an in-situ doping method or an ion implantation method. The gate electrode 500 is patterned by photolithography using the gate pattern (FIGS. 5 and 1500) and anisotropically etching the polycrystalline silicon layer in the direction perpendicular to the substrate surface using the dry etching method. Form.
FIG. 9: Diffusion layer electrodes 200 and 300 are formed by doping the arsenic with 5 × 10 ¹⁴ cm ⁻² at an acceleration energy of 25 keV by ion implantation using the gate electrode 500 as a mask and activating the impurities by heat treatment. At this time, the photoresist can be patterned using the photolithography method together with the gate 500 to form an ion implantation mask. By using FIGS. 5, 1205, and 1305, diffusion layers having different concentrations can be formed in the source 200 and the drain 300.
FIG. 10: A silicon oxide film 50 nm is deposited by CVD and anisotropically etched to form a spacer 920 on the side surface of the gate 500. Boron is ion-implanted at 2 × 10 ¹⁵ cm ⁻² at 2 keV using the spacers 920, the gate 500 and the resists of the pattern diagrams 5, 1305 formed by photolithography as a mask.
FIG. 11: Furthermore, a silicon oxide film 50 nm is deposited by CVD and anisotropically etched to form a spacer 930 outside the spacer 920. Ions are implanted at 2 × 10 ¹⁵ cm ⁻² at 40 keV using the spacers 920 and 930, the gate 500 and the resists of the pattern diagrams 5 and 1305 formed by photolithography as a mask. Laser activation is performed for a short time using Laser Spike Annealing (LSA) to form a P-type impurity region 350 and a high-concentration N-type region 400. Thereby, 350 and 400 can form a PN junction in contact with the high-concentration diffusion layer region. At this time, the resistance of the PN junction can be changed by adjusting the ion implantation energy of the high concentration diffusion layer 400.
FIG. 12: Hereinafter, an element can be obtained by performing a wiring process used in a normal LSI. Here, an oxide film 940 is deposited to a thickness of 500 nm by the CVD method, planarized by the CMP method, patterned by the photolithography method using the contact pattern shown in FIGS. 5 and 1650, and a hole is formed in the oxide film 940 by dry etching. The contact hole is opened at k. Here, as shown in the AA cross section of FIG. 5, the contact to the gate 500 does not appear, but a contact hole is formed simultaneously with the diffusion layers 200 and 350. After the contact opening, a laminated film of tungsten 50 nm and aluminum 200 nm was deposited and patterned using a photolithography method, and the wiring 600 was obtained by processing the metal laminated film.

In order to form these wiring steps, it is possible to use a resistance reduction process known so far. For example, by performing a salicide process using cobalt, nickel, titanium, or the like before the interlayer film 940 is deposited, the contact resistance can be lowered. In addition, although the wiring 600 uses a laminated film of tungsten and aluminum, copper wiring technology can be used. Multi-layer wiring can be formed as necessary.
According to this formation process, as described above, it is obvious that the structure of the present invention can be formed with the same planar layout as that of a normal MOSFET. Therefore, a high-performance element can be obtained without impairing integration.

So far, the present invention element corresponding to NMOS has been used to describe the element structure. In the element of the present invention, an element corresponding to the PMOS can also be formed, so that a circuit that operates in a complementary manner can be formed as in the conventional MOSFET. Therefore, a manufacturing process in the case of performing a complementary operation is shown. FIG. 20 shows an equivalent circuit in which a CMOS inverter, which is the basis of a digital circuit, is replaced with an element of the present invention. M1 is a device of the present invention corresponding to NMOS, and M2 is a device of the present invention corresponding to PMOS. In the figure, in order to indicate the direction of the electrode corresponding to the diffusion layer in which the diode is formed, that is, the drain, the symbol of the commonly used MOSFET is indicated by an element symbol with a triangular arrow. Node 1 is connected to an input terminal, node 4 is connected to an output terminal, node 2 is connected to power supply potential V _DD , and node 3 is connected to ground potential GND. Thereby, the input terminal and the output terminal can be operated as an inverter. The manufacturing method will be described with reference to FIG. 13 to FIG.

FIG. 13: An active region and an element isolation oxide film 910 are formed using the element isolation region formation process described in FIG. An element corresponding to NMOS is formed on the left side of the cross-sectional structure diagram, and an element corresponding to PMOS is formed on the right side. Therefore, a P-type well 105 is formed on the left side of the substrate using an ion implantation method, and an N-type well 106 is formed on the right side.
FIG. 14: Similar to the gate formation process described in FIG. 8, the surface silicon in the active region is thermally oxidized to form a gate insulating film 900 having a thickness of 3 nm, and polycrystalline silicon is deposited to a thickness of 100 nm by the CVD method. Phosphorus is ion-implanted on the left side and boron is ion-implanted on the right side, and gate electrodes 505 and 506 are formed by using a photolithography method and a dry etching technique.
FIG. 15: Similarly to the diffusion layer formation process of FIG. 9, N-type diffusion layers are formed on 305, 205, and 156 and P-type diffusion layers are formed on 155, 206, and 306 using the gates 505 and 506 and the photoresist pattern as a mask. .
FIG. 16: Similar to the impurity implantation process of FIG. 10, after the spacer 920 is formed, N-type diffusion layers 255 and 356 and P-type diffusion layers 256 and 355 are formed.
FIG. 17: Similar to the diffusion layer forming process of FIG. 11, after the spacer 930 is formed, the N-type high concentration layer 405 and the P-type high concentration layer 406 are formed using LSA.
FIG. 18: A nickel silicide layer 650 is formed on the diffusion layer electrode and the gate electrode using a known salicide process.
FIG. 19: As described in FIG. 12, a wiring layer is formed using a known wiring process. Here, a state in which two metal wiring layers (600, 610) are formed is shown.
Here, an inverter manufacturing method is shown. An inverter is a basic unit of a digital circuit. By combining them, it is possible to construct basic logic gates such as NAND used in digital circuits, and it can be seen that the element of the present invention can be applied to these basic logic gates.

Next, it will be shown that the element of the present invention can be formed (integrated) at the same time as a conventional MOSFET. The manufacturing process to be integrated will be described with reference to FIGS. In these element cross-sectional structure diagrams, the element of the present invention corresponding to the NMOS is formed on the left side, and the conventional NMOS is formed on the right side.
FIG. 21: An active region and an element isolation region 910 are formed by the shallow trench isolation process described above with reference to FIGS.
FIG. 22: A gate insulating film 900 and gate electrodes 505 and 506 are formed in the same manner as the gate formation process described in FIG. However, both 505 and 506 are doped with N-type impurities.
FIG. 23: Similar to the diffusion layer formation process of FIG. 9, the diffusion layer electrode is formed by ion implantation using the gate as a mask. Here, 305, 205, 206, and 306 are N-type, and 155 and 156 that are power supply portions to the P-type well form a P-type diffusion layer.
FIG. 24: Similar to the impurity implantation process of FIG. 10, after the spacer 920 is formed, boron is ion-implanted into the element portion 355 of the present invention.
FIG. 25: Similarly to the diffusion layer forming process of FIG. 11, after forming the spacer 930, phosphorus is ion-implanted into the element portion 405 of the present invention and then activated by LSA.
FIG. 26: A silicide layer 650 is formed on the diffusion layer electrode and the gate.
FIG. 27: As described in FIG. 12, the metal wiring 600 is obtained by using a known back-end process.

  As shown here, the element of the present invention and the conventional MOSFET can be easily integrated. The element of the present invention has extremely excellent switching characteristics, but has an asymmetric structure because the source electrode and the drain electrode have different structures. Therefore, there is a problem that conventional MOSFETs cannot be replaced when used as pass transistors that require symmetry in circuit configuration. However, as shown here, since it has high integration with the conventional MOSFET, excellent characteristics can be obtained by using the conventional MOSFET where symmetry is required and combining with the element of the present invention. As an example, FIGS. 28A and 28B show a case where the SRAM cell is used. FIG. 28A shows an SRAM cell having a total of four elements including two NMOSs and two elements of the present invention corresponding to the NMOSs. FIG. 28B shows a basic structure of a 6-transistor CMOS SRAM cell generally used. Here, the element of the present invention is shown using the same notation as that used in FIG. The pass gate is conventionally composed of NMOS.

  The characteristics of the SRAM cell shown in FIG. 28B are shown in FIG. 29 using a butterfly curve. Since a large static noise margin is obtained at a voltage of 0.3 V, which cannot be operated by a conventional CMOS, it can be seen that extremely good memory characteristics can be obtained by using the element of the present invention.

Next, the case where the element of the present invention is formed on a Silicon On Insulator (SOI) substrate will be described. The manufacturing process using the SOI substrate is shown in the element cross-sectional structure diagram of FIGS. In forming this element, when viewed as a single element, it can be formed in the same arrangement as the planar layout shown in FIG.
FIG. 30: An active region and an element isolation region are formed on a support substrate 100 and a buried oxide film 960 using an SOI substrate having a P-type 10 ¹⁵ cm ⁻³ thin film single crystal silicon 101 having a thickness of 50 nm. By etching the shallow trench for element isolation up to the buried oxide film 960, an element isolation region can be formed as in the case of using a single crystal silicon substrate.
FIG. 31: A gate insulating film 900 is formed, and polycrystalline silicon that has been made conductive by doping impurities at a high concentration is patterned to form a gate electrode 500.
FIG. 32: N-type diffusion layer electrodes 200 and 300 are formed by ion implantation of phosphorus using the gate electrode as a mask. At this time, a shallow junction can be formed by making the implantation energy on the source 200 side lower than that on the drain side.
FIG. 33: A spacer 920 is formed on the side surface of the gate 500, and boron is ion-implanted using the gate 500, the spacer 920 and the patterned photoresist as a mask, thereby implanting impurities into the drain side 350 and the source side 450.
FIG. 34: Similar to the spacer formation process of FIG. 11, a spacer 930 is formed, arsenic is implanted using an ion implantation method, and activated using an LSA method to form a high concentration impurity 400.
FIG. 35: In the following, the metal wiring is provided on each electrode by the wiring process.
In this structure, since the N-type high concentration diffusion layer 200 and the P-type high concentration diffusion layer 450 are in contact with each other on the source side, a PN junction with an extremely low breakdown voltage is formed and operates as a resistor. Therefore, the channel portion 101 can be connected to the source 200 through this resistor. In the conventional SOI-MOSFET, since there is a buried oxide film, it is known that power cannot be supplied to the channel portion, causing an unstable operation called a substrate floating phenomenon, which is a big problem. In contrast, by using the structure on the source side shown in this embodiment, it is possible to connect to the source electrode, so that such a problem can be avoided. This can be applied to a conventional MOSFET as it is. By providing this resistor, the structure of the present invention shown by the equivalent circuit in FIG. 1B can be realized even in an SOI substrate.

So far, examples have been described in which a diode using a silicon PN junction is formed in a drain diffusion layer. Similar diode characteristics can be realized using a metal-semiconductor interface junction (Schottky junction). The manufacturing method shown in Example 1 using LSA can be directly replaced with device formation having a Schottky junction. That is, the activation of the impurities by LSA can be performed after the thin film metal layer is formed. Therefore, instead of performing ion implantation on 350 shown in FIG. 10, after forming a 350 by silicidation, 400 is ion-implanted and activated by LSA to obtain the element of the present invention having a Schottky junction. Can do. Also, it can be formed by the manufacturing method shown in the element cross-sectional structure diagrams of FIGS.
FIG. 36: As in FIG. 7, an active region and an element isolation region are formed.
FIG. 37: As in FIG. 8, a gate insulating film 900 and a gate electrode 500 are formed.
FIG. 38: Similarly to FIG. 9, after a 3 nm oxide film 915 is grown on the surface of the gate 500, diffusion layers 200 and 300 are formed using these as masks.
FIG. 39: Polycrystalline silicon is deposited to a thickness of 100 nm by CVD, and dry etching is performed to form a polycrystalline silicon spacer 515 on the side surface of the gate 500, and a high concentration layer 460 is ion implanted.
FIG. 40: The polycrystalline silicon spacer 515 is removed by a wet etching method, a silicon oxide film 920 is deposited by a CVD method, the diffusion layer 200 side is covered with a photoresist, and a spacer 920 is formed on the diffusion layer 300 side. Silicide is selectively reacted with cobalt on the exposed silicon surface on the diffusion layer 300 to form a silicide layer 360. In this process, the salicide process is applied only to the drain side. As the metal, Pt, Ni, Er, W, Mo, or the like can be used.
Thereby, it can replace with a PN junction and can obtain the element of the present invention which has a Schottky junction. Here, the metal layer 360 is selectively formed using a silicide reaction; however, by applying this process, the metal layer 360 can be formed by deposition. The manufacturing method will be described with reference to FIGS.
FIG. 41: The gate electrode has a laminated structure of 100 nm polycrystalline silicon 500 having conductivity and 100 nm oxide film 916, and a polycrystalline silicon spacer 515 is formed as in FIG. The high concentration layer 460 is formed by ion implantation of this spacer or the like into a mask.
FIG. 42: Similar to FIG. 40, after removing the polysilicon spacer 515, an oxide film spacer layer 920 is deposited and etched to form a spacer 920 on the drain 300 side so that it contacts the exposed silicon surface. A metal layer 360 is deposited. When tungsten is used for the metal layer, it can be deposited only on the opening using a selective growth technique. In addition, this structure can be formed by depositing a metal layer on the entire surface of the substrate and then patterning it using a photolithography technique. Therefore, Pt, Al and Au can be widely used.

In order to improve the PN junction characteristics, the operation characteristics at a lower voltage can be improved by forming a heterostructure using a semiconductor having a narrow band gap instead of the silicon PN junction. A manufacturing method using SiGe crystal will be described with reference to FIGS.
FIG. 43: As in FIG. 7, an active region and an element isolation region are formed.
FIG. 44: As shown in FIG. 41 in the fourth embodiment, a gate electrode is formed by a laminated structure of polycrystalline silicon 500 and oxide film 916.
FIG. 45: Diffusion layer electrodes 200 and 300 are formed by ion implantation using the gate electrode as a mask.
FIG. 46: After an oxide film spacer 920 is formed on the gate side surface, a 10 nm oxide film 921 is deposited, and the drain 300 side is opened by photolithography to expose the silicon surface. A SiGe layer is epitaxially grown on the opening surface and doped to be P-type.
FIG. 47: Further, an oxide film spacer 930 is formed, and the high concentration layer 400 is obtained by ion implantation using the spacer or the like as a mask.
Since the SiGe layer 350 has a narrower band gap than Si, it is possible to improve the on characteristics when a low voltage is applied. On the other hand, leakage current can be reduced because leakage is suppressed by the gate 500 in the off state. This characteristic is extremely effective when used at a high temperature, which is a problem when a narrow band gap semiconductor is used.

In order to form the high-concentration layer in a self-aligned manner, it has been shown that it is formed using a spacer. On the other hand, it can also be formed in a self-aligned manner by performing implantation at an angle during ion implantation. The manufacturing method will be described with reference to FIGS.
FIG. 48: As in FIG. 7, an active region and an element isolation region are formed.
FIG. 49: The gate electrode 500 is formed as in FIG.
FIG. 50: Similar to FIG. 9, diffusion layer electrodes 200 and 300 are formed using gate 500 and the like as a mask.
FIG. 51: As in FIG. 10, a spacer 920 is formed on the side surface of the gate 500, and an impurity layer 350 is implanted using this as a mask.
FIG. 52: Ion implantation is performed obliquely with respect to the gate surface to form the diffusion layer 400. At this time, 400 is also formed on the source side, but it does not cause a problem in operating characteristics because of the same conductivity type. Therefore, a desired diffusion layer can be obtained in a self-aligned manner without forming a double spacer.

  In the process of FIG. 50, the diffusion layer 350 is formed by the spacer. However, as shown in FIG. 53, the diffusion layer 350 can be formed in a self-aligning manner by implanting ions into the gate 500 from an oblique direction. it can. In FIG. 53, reference numeral 820 denotes a photoresist mask.

The element of the present invention improves the switching characteristics of the subthreshold region of the element controlled by the electric field effect of the gate electrode. Therefore, the present invention can be applied to a nonvolatile memory element in which the gate threshold value is changed by holding charge. A case of applying to a so-called MONOS type nonvolatile memory cell using a stacked film of a silicon oxide film, a silicon nitride film and a silicon oxide film as a charge retention film will be described based on the manufacturing process with reference to FIGS. To do.
54: As in FIG. 7, an active region and an element isolation region are formed.
FIG. 55: The silicon surface of the active region is thermally oxidized 971 by 2 nm, a silicon nitride film 972 is deposited by CVD method, and a silicon oxide film 973 of 5 nm is deposited by CVD method. The oxide film 973 may be formed by depositing the nitride film 972 thick and oxidizing the nitride film 972 by using In-Situ Steam Generation (ISSG) oxidation. A gate electrode is formed using polycrystalline silicon 500 doped with phosphorus as an impurity at a high concentration.
FIG. 56: Diffusion layer electrodes 200 and 300 are formed by implanting and activating arsenic ions using gate 500 as a mask.
FIG. 57: An oxide film spacer 920 is formed on the side surface of the gate 500, and boron is implanted into the diffusion layer 350 by ion implantation using this as a mask.
FIG. 58: Further, an oxide film spacer 930 is formed, arsenic is ion-implanted using these as a mask, and activated by LSA to obtain a high concentration layer 400. Hereinafter, although a wiring layer is formed by a normal wiring process, it is omitted here.

In this structure, for example, by applying 10 V to the gate, a strong inversion layer is formed on the surface of the substrate 100, and electrons are injected and trapped in the nitride film 972 by tunneling the oxide film 971 from here. In addition, by applying −10 V to the gate electrode in a state where electrons are trapped, the trapped electrons are tunneled through the oxide film 971 to the substrate side, and more positive from the hole accumulation layer formed on the substrate. When holes are tunneled through the oxide film 971 and injected into the nitride film 972, trapped electrons disappear and a hole is trapped. Due to the trapped charge, the threshold is high when electrons are trapped, and the threshold is low when holes are trapped. By reading out this difference in threshold value as a difference in cell current with respect to a certain voltage, it is possible to operate as a nonvolatile memory. By applying the structure of the present invention to the drain 300, the current can be changed very steeply with respect to the gate voltage, so that a large difference in current value can be obtained with few charge traps. Since the amount of charge to be trapped is small, the stress on the tunnel film is small, and the self electric field is also weak, so that good holding characteristics can be obtained.
Although the MONOS type memory cell has been described here, the same effect can be obtained by applying the present invention to a floating gate type memory cell.

The typical equivalent circuit diagram for demonstrating this invention element | device operation | movement. The typical equivalent circuit diagram for demonstrating this invention element | device operation | movement. FIG. 4 is a relationship diagram between gate voltage and potential change for explaining the operation of the element of the present invention. FIG. 5 is a relationship diagram between a gate voltage and an applied bias for explaining the operation of the element of the present invention. The relationship figure of the gate voltage and drain current which showed the characteristic of this invention element. FIG. 5 is a plan layout view for explaining the element structure of the present invention. The element cross-section figure which showed typically for describing this invention element structure. The impurity distribution diagram in the substrate depth direction for explaining the element structure of the present invention. Resistance element characteristics for explaining the element structure of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an element cross-sectional structure diagram illustrating a method for producing an element of the present invention shown in Example 1. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an element cross-sectional structure diagram illustrating a method for producing an element of the present invention shown in Example 1. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an element cross-sectional structure diagram illustrating a method for producing an element of the present invention shown in Example 1. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an element cross-sectional structure diagram illustrating a method for producing an element of the present invention shown in Example 1. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an element cross-sectional structure diagram illustrating a method for producing an element of the present invention shown in Example 1. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an element cross-sectional structure diagram illustrating a method for producing an element of the present invention shown in Example 1. FIG. 5 is a cross-sectional structure diagram of an element for explaining another method of manufacturing an element of the present invention according to Example 1. FIG. 5 is a cross-sectional structure diagram of an element for explaining another method of manufacturing an element of the present invention according to Example 1. FIG. 5 is a cross-sectional structure diagram of an element for explaining another method of manufacturing an element of the present invention according to Example 1. FIG. 5 is a cross-sectional structure diagram of an element for explaining another method of manufacturing an element of the present invention according to Example 1. FIG. 5 is a cross-sectional structure diagram of an element for explaining another method of manufacturing an element of the present invention according to Example 1. FIG. 5 is a cross-sectional structure diagram of an element for explaining another method of manufacturing an element of the present invention according to Example 1. FIG. 5 is a cross-sectional structure diagram of an element for explaining another method of manufacturing an element of the present invention according to Example 1. FIG. 3 is an equivalent circuit diagram for explaining another element of the present invention according to the first embodiment. The element cross-section figure explaining the manufacturing method of the element of this invention shown in Example 2. FIG. The element cross-section figure explaining the manufacturing method of the element of this invention shown in Example 2. FIG. The element cross-section figure explaining the manufacturing method of the element of this invention shown in Example 2. FIG. The element cross-section figure explaining the manufacturing method of the element of this invention shown in Example 2. FIG. The element cross-section figure explaining the manufacturing method of the element of this invention shown in Example 2. FIG. The element cross-section figure explaining the manufacturing method of the element of this invention shown in Example 2. FIG. The element cross-section figure explaining the manufacturing method of the element of this invention shown in Example 2. FIG. 3 is an equivalent circuit diagram of an SRAM cell for explaining the element of the present invention shown in Embodiment 2. FIG. 3 is an equivalent circuit diagram of an SRAM cell for explaining the element of the present invention shown in Embodiment 2. FIG. FIG. 6 is a characteristic diagram of an SRAM cell for explaining the effect of the element of the present invention shown in Example 2. The element cross-section figure explaining the manufacturing method of this invention element shown in Example 3. FIG. The element cross-section figure explaining the manufacturing method of this invention element shown in Example 3. FIG. The element cross-section figure explaining the manufacturing method of this invention element shown in Example 3. FIG. The element cross-section figure explaining the manufacturing method of this invention element shown in Example 3. FIG. The element cross-section figure explaining the manufacturing method of this invention element shown in Example 3. FIG. The element cross-section figure explaining the manufacturing method of this invention element shown in Example 3. FIG. The element cross-section figure explaining the manufacturing method of this invention element shown in Example 4. FIG. The element cross-section figure explaining the manufacturing method of this invention element shown in Example 4. FIG. The element cross-section figure explaining the manufacturing method of this invention element shown in Example 4. FIG. The element cross-section figure explaining the manufacturing method of this invention element shown in Example 4. FIG. The element cross-section figure explaining the manufacturing method of this invention element shown in Example 4. FIG. The element cross-section figure explaining the manufacturing method of the other this invention element of Example 4. FIG. The element cross-section figure explaining the manufacturing method of the other this invention element of Example 4. FIG. FIG. 10 is a device cross-sectional structure diagram illustrating a method for manufacturing the device of the present invention shown in Example 5. FIG. 10 is a device cross-sectional structure diagram illustrating a method for manufacturing the device of the present invention shown in Example 5. FIG. 10 is a device cross-sectional structure diagram illustrating a method for manufacturing the device of the present invention shown in Example 5. FIG. 10 is a device cross-sectional structure diagram illustrating a method for manufacturing the device of the present invention shown in Example 5. FIG. 10 is a device cross-sectional structure diagram illustrating a method for manufacturing the device of the present invention shown in Example 5. FIG. 11 is a device cross-sectional structure diagram illustrating a method for manufacturing the device of the present invention shown in Example 6. FIG. 11 is a device cross-sectional structure diagram illustrating a method for manufacturing the device of the present invention shown in Example 6. FIG. 11 is a device cross-sectional structure diagram illustrating a method for manufacturing the device of the present invention shown in Example 6. FIG. 11 is a device cross-sectional structure diagram illustrating a method for manufacturing the device of the present invention shown in Example 6. FIG. 11 is a device cross-sectional structure diagram illustrating a method for manufacturing the device of the present invention shown in Example 6. The element cross-section figure explaining the manufacturing method of the other this invention element of Example 6. FIG. The element cross-section figure explaining the manufacturing method of the element of this invention shown in Example 7. FIG. The element cross-section figure explaining the manufacturing method of the element of this invention shown in Example 7. FIG. The element cross-section figure explaining the manufacturing method of the element of this invention shown in Example 7. FIG. The element cross-section figure explaining the manufacturing method of the element of this invention shown in Example 7. FIG. The element cross-section figure explaining the manufacturing method of the element of this invention shown in Example 7. FIG.

Explanation of symbols

100, 101: substrate,
105, 106: Well,
155, 156, 200, 205, 206, 300, 305, 306, 350, 355, 356, 400, 405, 406, 450, 460: diffusion layer electrodes,
360: Silicide,
500, 505, 506: gate,
515: polycrystalline silicon,
600, 610: Metal wiring layer,
650: Silicide,
820: Photoresist,
900: Gate insulating film,
910, 915, 916, 920, 921, 930, 940, 960: insulating film,
971: silicon oxide film,
972: silicon nitride film,
973: Silicon oxide film,
1100: active region pattern,
1200, 1300, 1350, 1400: diffusion layer electrode pattern,
1500: gate pattern,
1205, 1305: ion implantation mask pattern,
1650: Contact hole pattern.

Claims (21)

A first diffusion layer having a first conductivity type provided on a semiconductor substrate and a second diffusion having the first conductivity type provided on the semiconductor substrate so as to face the first diffusion layer A layer region, a channel region having a second conductivity type opposite to the first conductivity type provided between the first diffusion layer and the second diffusion layer, and at least covering the channel region And a gate insulating film provided on the semiconductor substrate,
A third diffusion layer having the second conductivity type is provided in the second diffusion layer;
A semiconductor having a fourth diffusion layer having the first conductivity type so as to include a part of a junction region where the third diffusion layer and the second diffusion layer cross each other. apparatus.   A diode element is constituted by the second diffusion layer and the third diffusion layer, one terminal is in contact with the third diffusion layer, the other terminal is in contact with the second diffusion layer, and the fourth diffusion layer is resisted. 2. The semiconductor device according to claim 1, wherein a resistance element as a body is configured, and the diode element and the resistance element are electrically connected in parallel.   The semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon substrate.   The impurity concentration of the fourth diffusion layer is set to be higher than the impurity concentration of the second diffusion layer, and the fourth diffusion layer and the second diffusion layer have respective impurity concentration distributions. 2. The semiconductor device according to claim 1, further comprising a PN junction that intersects in a high concentration region.   The semiconductor device according to claim 2, wherein a part of the diode element constituted by the second diffusion layer and the third diffusion layer is constituted by a resistance element.   3. The semiconductor according to claim 2, wherein the diode element has a heterostructure including a silicon substrate and a second semiconductor layer having a narrower band gap than silicon provided on the silicon substrate. apparatus.   The semiconductor device according to claim 6, wherein the second semiconductor layer is a silicon germanium single crystal. When the resistance value of the resistance element is R _N , the resistance of the channel region controlled by the gate is R _CH , the Fermi level depending on the impurity concentration of the substrate serving as the channel is φ _F , and the surface potential of the channel region is φ _S , _{R N is, R CH (φ F) <} R N < semiconductor device according to claim 1, characterized in that it is set such that _R CH _{(2φ F).}   The semiconductor device according to claim 1, wherein the semiconductor substrate is a substrate (Silicon On Insulator) formed on an insulating layer. The first diffusion layer electrode provided in the first diffusion layer has a stacked structure of a layer having the first conductivity type and a layer having a conductivity type opposite to the first conductivity type. The semiconductor device according to claim 9 . A plurality of semiconductor devices according to claim 1;
The first diffusion layer electrode includes a first element having an N-type conductivity type, and the first diffusion layer electrode includes a second element having a P-type conductivity type. Semiconductor device. The integrated semiconductor device according to claim 11 , wherein the first element and the second element constitute an inverter. 13. An integrated semiconductor device comprising a flip-flop circuit using two integrated semiconductor devices according to claim 12 . 14. An integrated semiconductor memory device comprising an SRAM cell using the integrated semiconductor device according to claim 13 . A semiconductor device according to claim 1;
A first diffusion layer having a first conductivity type provided on the semiconductor substrate and a second diffusion having the first conductivity type provided on the semiconductor substrate so as to face the first diffusion layer An integrated semiconductor device, wherein a conventional MOSFET having a layer and a gate insulating film provided on the semiconductor substrate so as to cover at least the channel region is integrated on the semiconductor substrate. A first diffusion layer having a first conductivity type provided on a semiconductor substrate and a second diffusion having the first conductivity type provided on the semiconductor substrate so as to face the first diffusion layer A layer region, a channel region having a second conductivity type opposite to the first conductivity type provided between the first diffusion layer and the second diffusion layer, and at least covering the channel region A gate insulating film provided on the semiconductor substrate, and a gate electrode provided on the gate insulating film,
A third diffusion layer having the second conductivity type is provided in the second diffusion layer;
A nonvolatile layer, wherein a fourth diffusion layer having the first conductivity type is provided so as to include a part of a junction region where the third diffusion layer and the second diffusion layer cross each other. Semiconductor memory device. The nonvolatile semiconductor memory device according to claim 16 , wherein the gate electrode provided on the gate insulating film has a charge holding portion. The nonvolatile semiconductor memory device according to claim 17 , wherein the charge holding portion is formed of a floating gate. The nonvolatile semiconductor memory device according to claim 17 , wherein the charge holding portion is formed of a laminated insulating film. Preparing a semiconductor substrate;
Introducing an impurity having a first conductivity type into the semiconductor substrate to form a first diffusion layer and a second diffusion layer;
Introducing a second conductivity type impurity having a conductivity type opposite to the first conductivity type into the second diffusion layer to form a third diffusion layer;
Selectively introducing an impurity having the first conductivity type into a partial region of the third diffusion layer to form a fourth diffusion layer;
Forming a gate insulating film on a channel region formed between the first diffusion layer and the second diffusion layer, and
After the third diffusion layer and the fourth diffusion layer are formed, a high-temperature short-time heat treatment is performed to form a high concentration resistance element between the second diffusion layer and the third diffusion layer. A method of manufacturing a semiconductor device. 21. The method of manufacturing a semiconductor device according to claim 20 , wherein the high-temperature short-time heat treatment is performed by a laser spike annealing (LSA) process.

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