JP5240146B2 - Solid-state image sensor - Google Patents

Description

The present invention relates to a solid-state imaging device used in a video camera or a digital still camera or the like (image sensor).

A solid-state imaging device (image sensor) is a semiconductor device configured to read out pixel signals using a plurality of pixels as photoelectric conversion means and a MOS transistor that selectively reads out the signals of the pixels. For example, a video camera And digital still cameras.
Of these, the so-called CMOS type solid-state imaging device (CMOS image sensor) manufactured by the CMOS (complementary MOS) process is particularly low voltage, low power consumption, multi-function, and peripheral circuits and one-chip integration. It has the merit of being able to perform SOC (system on chip).
Therefore, it is attracting attention and used as an imaging device for a camera for a mobile phone, a digital still camera, and a digital video camera.

FIG. 9 shows a schematic configuration diagram (circuit configuration diagram) of an example of the configuration of a CMOS solid-state imaging device (CMOS image sensor).
This CMOS image sensor includes a pixel formation region 4 in which a plurality of photodiodes 2 that perform photoelectric conversion and a pixel 1 that includes a MOS transistor 3 that selectively reads and reads the photodiodes 2 are two-dimensionally arranged on the same semiconductor substrate. Peripheral circuits 5 and 6 for pixel selection and signal output are provided.
Hereinafter, a region other than the pixel formation region 4, that is, a region including the pixel selection circuit 5 and the output circuit 6 is referred to as a “peripheral circuit formation region”.
In the pixel formation region 4, each pixel 1 is composed of a photodiode 2 and three MOS transistors including a transfer transistor 3, a reset transistor 7, and an amplifier transistor 8. In the peripheral circuit formation region, the pixel selection circuit 5 and the output circuit 6 are configured using CMOS transistors.

In a conventional CMOS image sensor, each circuit in the peripheral circuit formation region is formed by a CMOS transistor.
On the other hand, in the pixel formation region, all MOS transistors constituting each pixel are NMOS transistors.
The NMOS transistor constituting this pixel usually has the same element isolation structure as the NMOS transistor used in the peripheral circuit formation region (see, for example, Patent Document 1).

Here, FIG. 8 shows a cross-sectional view of an element isolation structure used in a peripheral circuit formation region in a conventional CMOS image sensor.
An N-type semiconductor well region 52 and a P-type semiconductor well region 53 are formed in the semiconductor substrate 51. A PMOS transistor 54 is formed in the N-type semiconductor well region 52, and an NMOS transistor 55 is formed in the P-type semiconductor well region 53.
The transistors 54 and 55 are electrically isolated from each other by an element isolation portion 56 made of so-called STI (Shallow Trench Isolation) in which an element isolation layer is embedded in a groove formed in the semiconductor substrate 51. Yes. In the element isolation portion 56, for example, an oxide film is embedded as an element isolation layer.

Further, in the conventional CMOS image sensor, the NMOS transistors constituting the pixels are separated by the element isolation portion 56 having the same structure as the NMOS transistors used in the peripheral circuit formation region. Therefore, in the pixel formation region 4 of FIG. Similarly, the element isolation layer 56 in which the element isolation layer is embedded in the semiconductor substrate 51 shown in FIG. 8 is formed, and is isolated from the adjacent pixel cell 1.
The source / drain diffusion layers of the transistors such as the transfer transistor 3, the amplifier transistor 8, and the reset transistor 7 formed in each pixel cell 1 in the pixel formation region 4 are also similarly configured in the element isolation portions 56. Separated by.

Japanese Patent Laying-Open No. 2003-142673 (FIG. 10)

However, in the conventional CMOS image sensor, since the element isolation layer 56 is formed by embedding the element isolation layer in the groove formed in the semiconductor substrate 51 as described above, the groove is formed in the semiconductor substrate 51. Distortion or crystal defects in the semiconductor substrate 51 due to a damage caused by a difference in thermal expansion coefficient between the semiconductor substrate 51 and the embedded insulating layer (element isolation layer) 56 in a heat treatment process during manufacturing. May occur.
Due to this strain and crystal defects, unnecessary charges (leakage current, dark current) are generated and enter the photodiode 2.
Since the charge accumulated in the photodiode 2 is transferred through the transfer transistor 3, the charge generated due to distortion or crystal defects becomes a noise signal for the pixel signal as it is.

  Further, when a groove is formed in a single crystal substrate such as a silicon substrate, a single crystal terminal portion is formed not only on the surface of the substrate but also on the side wall of the groove. The level is also a factor of a noise signal with respect to the image signal.

Conventionally, the NMOS transistors constituting the pixels are separated by the element isolation part 56 having the same structure as the NMOS transistors used in the peripheral circuit formation region. However, the CMOS transistors used in the peripheral circuit formation region are finely divided. In many cases, the state-of-the-art process is adopted, and the power supply voltage is also low because it is designed mainly for high speed, low power consumption and space saving.
For this reason, when the element isolation portion 56 is optimized in accordance with the design of the CMOS transistor in the peripheral circuit formation region, the element isolation portion 56 in the pixel formation region 4 is likely to generate the above-described unnecessary charges. There is also.

In order to solve the above-described problems, the present invention provides a solid-state imaging device having a structure that can suppress noise with respect to an image signal and can be miniaturized in a peripheral circuit formation region.

The solid-state imaging device of the present invention is a pixel comprising a photoelectric conversion element having a first conductivity type region formed on the surface of a semiconductor substrate and a second conductivity type region formed so as to be in contact with the lower portion of the first conductivity type region. A transistor for reading out signal charges from the photoelectric conversion element, a pixel formation region including the pixel and the transistor, a peripheral circuit formation region formed on the same semiconductor substrate as the pixel formation region, and the peripheral circuit An element isolation region including a first element isolation portion formed by embedding an insulating layer in a semiconductor substrate of a formation region , an impurity diffusion layer of a first conductivity type formed in the semiconductor substrate of a pixel formation region , and a pixel A second element isolation portion made of an insulating layer formed on the semiconductor substrate in the formation region, and the bottom of the insulating layer of the second element isolation portion is the bottom of the insulating layer of the first element isolation portion Shallower than And it is formed.

According to the above-described configuration of the solid-state imaging device of the present invention, in the pixel formation region, the element isolation region formed of the first conductivity type impurity diffusion layer formed in the semiconductor substrate and the insulation formed on the semiconductor substrate. Since the second element isolation portion composed of the layer is formed, the junction isolation can be performed by the element isolation region (impurity region) formed in the semiconductor substrate. And in this 2nd element isolation part , since the insulating layer is not buried deeply in the semiconductor substrate, it is possible to suppress the occurrence of crystal defects, damage, and interface states in the semiconductor substrate around the element isolation layer. Noise due to crystal defects, damage, and interface states can be reduced.

According to the present invention described above, noise caused by crystal defects, damage, and interface states in the element isolation region can be reduced in the pixel formation region. In addition, it is possible to improve characteristics such as resolution of the solid-state imaging device.
Further, in the peripheral circuit formation region, it is possible to simultaneously realize high speed, low power consumption and space saving of the peripheral circuit. In addition, the solid-state image sensor can be miniaturized.

In addition, according to the present invention, at least a part of the steps can be simultaneously performed in the process of manufacturing the element isolation layer in the pixel formation region and the process of manufacturing the element isolation layer in the peripheral circuit formation region. The number of manufacturing processes can be reduced.
Therefore, the time required for manufacturing can be shortened by reducing the number of manufacturing steps.

1 is a schematic configuration diagram (cross-sectional view) of an embodiment of a solid-state imaging device of the present invention. It is a circuit block diagram of the solid-state image sensor of FIG. FIG. 2A is a diagram showing the relationship between the depth in the substrate of the element isolation layer of the solid-state imaging device of FIG. 1 and the number of pixels in which output abnormality has occurred. B is a diagram showing the relationship between the thickness of the element isolation layer of the solid-state imaging element of FIG. 1, the element isolation capability, and the number of occurrences of gate shorts. FIGS. 2A to 2C are process diagrams illustrating a method for manufacturing the solid-state imaging device of FIG. D to F are process diagrams illustrating a method of manufacturing the solid-state imaging device of FIG. GI is process drawing which shows the manufacturing method of the solid-state image sensor of FIG. J to L are process diagrams illustrating a method of manufacturing the solid-state imaging device of FIG. It is sectional drawing of the peripheral circuit formation area of the conventional CMOS sensor. It is a circuit block diagram of the conventional solid-state image sensor.

As an embodiment of the present invention, FIG. 1 shows a schematic configuration diagram (cross-sectional view) of a solid-state imaging device.
Further, FIG. 2 shows a circuit configuration diagram of the solid-state imaging device of the present embodiment. The solid-state imaging device of the present embodiment has a circuit configuration similar to the circuit configuration previously shown in FIG.

  In this solid-state imaging device, a pixel formation region 4 in which a large number of pixel cells 1 having photodiodes 2 are formed and a peripheral circuit formation region 20 are formed on the same semiconductor substrate 10 made of, for example, an N-type silicon substrate. ing.

  As shown in FIG. 1, in the peripheral circuit formation region 20, an element isolation layer 21 such as a silicon oxide film is embedded in the semiconductor substrate 10 in the same manner as the configuration of the conventional element isolation portion 56 shown in FIG. An element isolation portion is formed. In other words, the element isolation portion has a so-called trench element isolation (STI) structure. In the figure, reference numeral 13 denotes a thin insulating film (for example, a silicon oxide film) on the surface of the substrate 10.

In the pixel formation region 4, a sensor unit is formed by an N-type charge accumulation region 14 formed in the semiconductor substrate 10 and a P-type (P ⁺ ) positive charge accumulation region 15 formed near the surface of the semiconductor substrate 10. 16 is configured.

  Although not shown, transistor source / drain regions are formed in the semiconductor substrate 10 in the pixel formation region 4 and the peripheral circuit formation region 20, respectively, and the transistor gate electrode and the like are formed on the semiconductor substrate 10 via the insulating film 13. Is formed. Further, in the pixel formation region 4, a color filter and an on-chip lens are formed further upward as necessary.

As shown in FIG. 2, the CMOS image sensor has a circuit configuration in which a pixel 1 including a plurality of photodiodes 2 that perform photoelectric conversion and a MOS transistor 3 that selectively reads out the photodiodes 2 is two-dimensionally formed on the same semiconductor substrate. The pixel formation region 4 arranged in a shape and peripheral circuits 5 and 6 for pixel selection and signal output are provided.
In the pixel formation region 4, each pixel 1 is composed of a photodiode 2 and three MOS transistors including a transfer transistor 3, a reset transistor 7, and an amplifier transistor 8. In the peripheral circuit formation region, the pixel selection circuit 5 and the output circuit 6 are configured using CMOS transistors.

In the solid-state imaging device of the present embodiment, in particular, in the pixel formation region 4, the transistors 3, 7 and 8 (see the circuit configuration diagram of FIG. 2) are separated between the pixel cells 1 and in each pixel cell 1. The configuration of the element isolation part (second element isolation part) is different from the element isolation part (first element isolation part) in the peripheral circuit formation region 20.
That is, as shown in the cross-sectional view of FIG. 1, in the pixel formation region 4, an element isolation region 11 composed of a P-type (P ⁺ ) impurity diffusion layer is formed in the semiconductor substrate 10, and this P-type A convex element isolation layer (cover layer) 12 protruding from the semiconductor substrate 10 is formed above the element isolation region 11, and the element isolation portion (first layer) is formed by the element isolation region 11 and the element isolation layer (cover layer) 12. 2 element isolation part).

  The P-type element isolation region 11 has a wide portion 11A at the top and a narrow portion 11B at the bottom, and has a substantially T-shaped cross section.

Thus, by forming the P-type element isolation region 11, it is possible to perform element isolation by junction isolation.
Further, since the element isolation layer (cover layer) 12 is formed, leakage current due to the parasitic MOS can be suppressed.

Furthermore, in the solid-state imaging device according to the present embodiment, in particular, an element isolation layer (cover layer) 12 that constitutes an element isolation portion of the pixel formation region 4 and an element isolation layer that constitutes an element isolation portion of the peripheral circuit formation region 20. 21 are formed of the same insulating layer (for example, silicon oxide film) 17, 18, and 19.
That is, the element isolation layer (cover layer) 12 constituting the element isolation portion of the pixel formation region 4 includes a thin silicon oxide film 17 near the interface with the silicon substrate 10, a silicon oxide film 18, and a silicon oxide film at the upper center. 19, the element isolation layer 21 constituting the element isolation part of the peripheral circuit part forming region 20 includes a thin silicon oxide film 17 near the interface with the silicon substrate 10, a silicon oxide film 18, and a central part. Insulating layers (for example, SiO ₂ layers) 17, 18 and 19 are common.

Since the insulating layers 17, 18, and 19 are formed in this manner, the element isolation layer (cover layer) 12 forming the element isolation portion of the pixel formation region 4 and the peripheral circuit formation region 20 are formed. The formation process of the element isolation layer 21 constituting the element isolation part can be made common.
Thereby, the number of manufacturing processes can be reduced.

In this embodiment, the height H2 of the element isolation layer 21 in the peripheral circuit formation region 20 (height on the silicon oxide film 13 on the surface of the silicon substrate 10) H2 is higher than the element isolation layer made of normal STI. It has become.
Therefore, the difference between the height H1 of the element isolation layer (cover layer) 12 in the pixel formation region 4 and the height H2 of the element isolation layer 21 in the peripheral circuit formation region 20 is relatively small.

In the solid-state imaging device of the present embodiment, the P-type positive charge accumulation region 15 on the surface of the sensor unit 16 is formed so as to be connected to the upper portion 11A of the element isolation region 11, and the N of the sensor unit 16 The type charge storage region 14 extends under the element isolation layer (cover layer) 12 and is formed up to a portion in contact with the lower portion 11B of the element isolation region 11.
In the configuration in which the STI is used for the element isolation portion of the conventional pixel formation region, for example, as described in Patent Document 1, a P-type region is provided around the insulating layer having the STI structure for the purpose of noise reduction. Was forming. Due to the presence of the P-type region, the N-type charge accumulation region of the sensor portion cannot be formed widely.
On the other hand, in the present embodiment, in the pixel formation region 4, element isolation is performed by the element isolation region 11 instead of element isolation by STI. Therefore, the width of the element isolation portion in the semiconductor substrate 10 is determined. Can be made narrower than the STI, whereby the N-type charge accumulation region 14 of the sensor unit 16 can be formed wide and extended under the element isolation layer (cover layer) 12. it can.
In this way, the saturation charge amount Qs can be increased by forming the element isolation layer (cover layer) 12 so as to extend below the element isolation layer (cover layer) 12.

The element isolation layer (cover layer) 12 in the pixel formation region 4 preferably has a depth in the semiconductor substrate 10 of 50 nm or less and a thickness in the range of 50 nm to 150 nm.
In FIG. 1, the element isolation layer (cover layer) 12 is partially formed in the semiconductor substrate 10, but the element isolation layer (cover layer) 12 is formed only on the semiconductor substrate 10. It is good also as a structure.

  The element isolation layer 21 in the peripheral circuit formation region 20 preferably has a depth in the semiconductor substrate 10 of 150 nm to 450 nm.

  Here, in the pixel formation region 4, the depth (the amount of digging of the silicon substrate 10) formed in the silicon substrate 10 of the element isolation layer (cover layer) 12 made of a silicon oxide film and an output abnormality (noise) are generated. FIG. 3A shows the relationship with the number of pixels obtained.

As shown in FIG. 3A, when the depth exceeds 50 nm, the number of pixels in which output abnormality has occurred increases. This means that the stress or the stress due to the difference in thermal expansion coefficient generated between the buried element isolation layer (silicon oxide film) 12 and the silicon substrate 10 reaches a level that cannot be ignored. Further, when the depth is further increased, the interface state of the silicon substrate 10 is increased, which means that uncontrollable trap charges are increased.
Note that “normal STI” shown in the drawing indicates a thickness of 350 nm of the element isolation layer having a normal STI structure. With the configuration of this embodiment, it can be seen that the number of pixels in which output abnormality has occurred can be significantly reduced as compared with an element isolation layer having a normal STI structure.

Further, FIG. 3B shows the relationship between the thickness of the element isolation layer (silicon oxide film) 12 in the pixel formation region 4, the element isolation capability (critical value of leakage current), and the number of occurrences of gate shorts. A solid line indicates the element isolation capability, and a broken line indicates the number of gate shorts.
As shown in FIG. 3B, when the thickness of the element isolation layer 12 is less than 50 nm, the leakage current of the parasitic MOS transistor showing the element isolation capability increases. On the other hand, when the thickness exceeds 150 nm, the gate electrode is significantly short-circuited. It becomes easier and the yield is significantly reduced. This is because when the element isolation layer 12 is thickened, it becomes difficult to process the gate electrode formed on the element isolation layer 12, and the number of gate shorts increases.

  Therefore, it is desirable that the element isolation layer (cover layer) 12 formed in the pixel formation region 4 has a depth in the semiconductor substrate 10 of 50 nm or less and a thickness in the range of 50 nm to 150 nm.

Preferably, the minimum isolation width of the element isolation portion in the peripheral circuit formation region 20 is smaller than the minimum isolation width of the element isolation portion in the pixel formation region 4.
With this configuration, since the minimum isolation width of the element isolation portion is small in the peripheral circuit formation region 20, further miniaturization of the solid-state imaging device is achieved, and high speed, low power consumption, and space saving are achieved. Can do. Further, in the pixel formation region 4, since the minimum isolation width of the element isolation portion is large, noise generation and leakage current can be sufficiently suppressed.

The solid-state imaging device of the present embodiment can be manufactured as follows, for example.
First, the surface of the semiconductor substrate 10, for example, a silicon substrate is oxidized to form a silicon oxide film 31. The thickness of the silicon oxide film 31 is, for example, 5 nm to 20 nm.
Next, a silicon nitride film 32 is formed with a film thickness of, for example, 100 nm to 200 nm on the silicon oxide film 31 by a CVD (chemical vapor deposition) method (see FIG. 4A above). The silicon nitride film 32 serves as a polishing stopper in a step of polishing a silicon oxide film to be formed later by a CMP (Chemical Mechanical Polishing) method.

  Next, as shown in FIG. 4B, the silicon nitride film 32 where the element isolation layers 12 and 21 are formed in the pixel formation region 4 and the peripheral circuit formation region 20 is selectively removed. When the silicon nitride film 32 is selectively removed, the digging amount of the silicon substrate 10 in the pixel formation region 4 is desirably as small as possible, and the depth is suppressed to 50 nm or less.

Next, after a resist is formed so as to cover the surface, a resist pattern 33 that covers the pixel formation region 4 is formed by exposure and development.
Then, in the peripheral circuit formation region 20, a trench 34 is formed in the silicon substrate 10 by a normal method using the silicon nitride film 32 as a hard mask (see FIG. 4C above). At this time, the silicon nitride film 32 is removed by etching for forming the groove 34, and the silicon nitride film 32 in the peripheral circuit formation region 20 is slightly thinner than the silicon nitride film 32 in the pixel formation region 4. .

  Subsequently, the resist pattern 33 is removed, and then the surface of the silicon substrate 10 exposed through the opening is oxidized, and a thickness of 5 nm is formed in each of the pixel formation region 4 and the peripheral circuit formation region 20 as shown in FIG. 5D. A silicon oxide film 17 of ˜20 nm is formed.

Next, a resist is formed to cover the surface, and then a resist pattern 35 that covers the peripheral circuit formation region 20 is formed by exposure and development.
Further, a P-type impurity such as boron is ion-implanted at a concentration of 1 × 10 ^{12 to} 5 × 10 ¹³ atoms / cm ² , so that the upper portion 11 A of the element isolation region (channel stop layer) 11 is formed in the pixel formation region 4. (See FIG. 5E).

Subsequently, after removing the resist pattern 35, the silicon oxide film 18 is formed by a CVD method so as to cover the surface. This silicon oxide film 18 is formed thinner than the silicon nitride film 32. As a result, in the pixel formation region 4, the silicon oxide film 18 is formed along the inner wall of the opening of the silicon nitride film 32, leaving a space at the center of the opening. Further, a space remains in the central portion of the groove 34 in the peripheral circuit formation region 20.
The silicon oxide film 18 is preferably HTO (High Temperature Oxide) (see FIG. 5F above).

Next, a resist is formed to cover the surface, and then a resist pattern 36 that covers the peripheral circuit formation region 20 is formed by exposure and development.
Further, P-type impurities such as boron are ion-implanted into the silicon substrate 10 at a concentration of 5 × 10 ¹² to 1 × 10 ¹⁴ atoms / cm ² , so that the lower portion 11B of the element isolation region 11 is formed in the pixel formation region 4. Form. Here, the silicon oxide film 18 in the opening of the silicon nitride film 32 acts as a mask for ion implantation, and the width of the lower portion 11B of the element isolation region 11 becomes a narrow width corresponding to the space at the center of the opening. Thereby, the lower part 11B of the element isolation region 11 is formed to have a narrower width than the upper part 11A, and the element isolation region 11 having a T-shaped cross section is formed (see FIG. 6G above).

  Next, after removing the resist pattern 36, as shown in FIG. 6H, a silicon oxide film 37 is formed to a thickness of, for example, 100 nm to 200 nm by the HDP method. As a result, the space in the center of the opening in the pixel formation region 4 and the space in the center in the groove 34 in the peripheral circuit formation region 20 are filled with the silicon oxide film 37.

  Next, as shown in FIG. 6I, the silicon oxide film 37 in a portion on the relatively thick element formation region is selectively removed by etching using the resist mask 38. This is to match the polishing rate in the CMP process within the wafer surface.

  Subsequently, the silicon oxide film 37 on the silicon nitride film 32 is removed by planarizing the surface using a CMP (Chemical Mechanical Polishing) method or an etch back method. At this time, the silicon nitride film 32 functions as a stopper layer for CMP or etching. As a result, only the silicon oxide film 37 in the opening of the silicon nitride film 32 remains in each of the pixel formation region 4 and the peripheral circuit formation region 20, and becomes the silicon oxide film 19 shown in FIG. 1 (see FIG. 7J above). .

Next, the silicon nitride film 32 is removed using a hot phosphoric acid solution.
As a result, as shown in FIG. 7K, in the pixel formation region 4, an element isolation layer (cover layer) is formed by a convex insulating film (silicon oxide film 17, silicon oxide film 18, and silicon oxide film 19) on the semiconductor substrate 10. ) 12 is formed, and an element isolation region (channel stop diffusion layer) 11 is formed under the element isolation layer (cover layer) 12.
On the other hand, in the peripheral circuit forming region 20 of the same silicon substrate 10, an element isolation layer 21 made of an insulating layer (silicon oxide film 17, silicon oxide film 18, and silicon oxide film 19) is formed as STI.

Thereafter, as shown in FIG. 7L, the N-type charge accumulation region 14, the positive charge accumulation region 15, the source / drain region of the transistor, and the like of the sensor unit 16 are sequentially formed by ion implantation into the semiconductor substrate 10.
And after forming a gate electrode etc. on the silicon oxide film 31 of the surface of the semiconductor substrate 10, a color filter, an on-chip lens, etc. are formed in the pixel formation area 4 as needed, and a solid-state image sensor is manufactured. can do.

  According to the above-described manufacturing method, the element isolation layer 21 is formed as the STI in the peripheral circuit formation region 20 by adding the minimum necessary steps to the conventional STI formation step, and the pixel formation region 4 is formed. Can form an element isolation layer (cover layer) 12 and an element isolation region 11 for junction isolation.

In the cross-sectional view of FIG. 1 and the manufacturing method described above, the element isolation layer (cover layer) 12 in the pixel formation region 4 and the element isolation layer 21 in the peripheral circuit formation region 20 are formed to have substantially the same width. .
On the other hand, as described above, when the minimum isolation width of the element isolation portion in the peripheral circuit formation region 20 is smaller than the minimum isolation width of the element isolation portion in the pixel formation region 4, FIG. In the illustrated process, the width of the opening formed in the silicon nitride film 32 may be narrower in the peripheral circuit formation region 20.

In the cross-sectional view of FIG. 1 and the manufacturing method described above, the height H1 of the element isolation layer (cover layer) 12 in the pixel formation region 4 and the height H2 of the element isolation layer 21 in the peripheral circuit formation region 20 are: Slightly different.
On the other hand, for example, in the process of forming the groove 34 in the silicon substrate 10, if the silicon nitride film 32 can be substantially prevented from being scraped, the element isolation layers 12 and 21 can be set to substantially the same height. become.

According to the solid-state imaging device of the present embodiment described above, the element isolation layer (cover layer) 12 that forms the element isolation portion of the pixel formation region 4 and the element isolation layer 21 that forms the element isolation portion of the peripheral circuit formation region 20. Are formed of the same insulating layers 17, 18, 19, so that a process for forming the element isolation layer (cover layer) 12 in the pixel formation region 4 and a process for forming the element isolation layer 21 in the peripheral circuit formation region 20 are performed. And can be made common.
Thereby, the number of manufacturing processes can be reduced.

Further, the N-type charge accumulation region 14 of the sensor unit 16 is formed so as to extend below the element isolation layer (cover layer) 12, so that the sensor unit 16, that is, the photoelectric conversion element can be connected to the element isolation layer (cover). Layer) 12, and the saturation charge amount can be maximized.
This makes it possible to improve characteristics such as resolution of the solid-state imaging device.

In the pixel formation region 4, an element isolation portion is configured by the element isolation region 11 and the element isolation layer (cover layer) 12 in the semiconductor substrate 10.
As a result, it is possible to reduce noise caused by crystal defects, damage, and interface states in the vicinity of the element isolation portion as compared with the case where the element isolation portion having the STI structure is configured.

  Further, in the peripheral circuit formation region 20, since the element isolation layer 21 having the STI structure is formed as in the element isolation portion of the conventional CMOS sensor, the peripheral circuit is increased in speed, power consumption is reduced, and space is saved. Can be realized simultaneously.

In the above-described embodiment, the element isolation layer (cover layer) 12 in the pixel formation region 4 and the element isolation layer 21 in the peripheral circuit formation region 20 have the same insulating layers 17, 18, and 19. However, in the present invention, these element isolation layers are not limited to the configuration comprising the same insulating layer.
That is, in the present invention, the element isolation layer in the pixel formation region and the element isolation layer in the peripheral circuit formation region include at least the same insulating layer, and the same insulating layer is made common and partially different insulating layers. It does not matter even if it is the composition containing. Even in this case, at least a part of the process of manufacturing the element isolation layer in the pixel formation region and the process of manufacturing the element isolation layer in the peripheral circuit formation region (the same insulating layer forming process) can be performed simultaneously. Therefore, the number of manufacturing processes can be reduced.

  In the above-described embodiment, the case where the semiconductor substrate 10 such as a silicon substrate is used as the semiconductor substrate has been described. Good.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

  1 pixel, 2 photodiode, 4 pixel formation region, 10 silicon substrate, 11 element isolation region, 12 element isolation layer (cover layer), 14 charge storage region, 15 positive charge storage region, 16 sensor unit, 17, 18, 19 Silicon oxide film, 20 peripheral circuit formation region, 21 element isolation layer, 32 silicon nitride film

Claims (1)

A pixel comprising a photoelectric conversion element having a first conductivity type region formed on a surface of a semiconductor substrate and a second conductivity type region formed so as to be in contact with a lower portion of the first conductivity type region;
A transistor for reading a signal charge from the photoelectric conversion element;
A pixel formation region configured to include the pixel and the transistor;
A peripheral circuit formation region formed on the same semiconductor substrate as the pixel formation region;
A first element isolation portion formed by embedding an insulating layer in the semiconductor substrate in the peripheral circuit formation region ;
An element isolation region comprising an impurity diffusion layer of a first conductivity type formed in the semiconductor substrate in the pixel formation region, and a second element comprising an insulating layer formed on the semiconductor substrate in the pixel formation region. Including a separation part ,
The bottom of the insulating layer of the second element isolation part is formed shallower than the bottom of the insulating layer of the first element isolation part .

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